[deliverable/linux.git] / drivers / phy / phy-ti-pipe3.c

/*
 * phy-ti-pipe3 - PIPE3 PHY driver.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/phy/phy.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>

#define	PLL_STATUS		0x00000004
#define	PLL_GO			0x00000008
#define	PLL_CONFIGURATION1	0x0000000C
#define	PLL_CONFIGURATION2	0x00000010
#define	PLL_CONFIGURATION3	0x00000014
#define	PLL_CONFIGURATION4	0x00000020

#define	PLL_REGM_MASK		0x001FFE00
#define	PLL_REGM_SHIFT		0x9
#define	PLL_REGM_F_MASK		0x0003FFFF
#define	PLL_REGM_F_SHIFT	0x0
#define	PLL_REGN_MASK		0x000001FE
#define	PLL_REGN_SHIFT		0x1
#define	PLL_SELFREQDCO_MASK	0x0000000E
#define	PLL_SELFREQDCO_SHIFT	0x1
#define	PLL_SD_MASK		0x0003FC00
#define	PLL_SD_SHIFT		10
#define	SET_PLL_GO		0x1
#define PLL_LDOPWDN		BIT(15)
#define PLL_TICOPWDN		BIT(16)
#define	PLL_LOCK		0x2
#define	PLL_IDLE		0x1

/*
 * This is an Empirical value that works, need to confirm the actual
 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 */
#define PLL_IDLE_TIME	100	/* in milliseconds */
#define PLL_LOCK_TIME	100	/* in milliseconds */

struct pipe3_dpll_params {
	u16	m;
	u8	n;
	u8	freq:3;
	u8	sd;
	u32	mf;
};

struct pipe3_dpll_map {
	unsigned long rate;
	struct pipe3_dpll_params params;
};

struct ti_pipe3 {
	void __iomem		*pll_ctrl_base;
	struct device		*dev;
	struct device		*control_dev;
	struct clk		*wkupclk;
	struct clk		*sys_clk;
	struct clk		*refclk;
	struct clk		*div_clk;
	struct pipe3_dpll_map	*dpll_map;
};

static struct pipe3_dpll_map dpll_map_usb[] = {
	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
	{ },					/* Terminator */
};

static struct pipe3_dpll_map dpll_map_sata[] = {
	{12000000, {1000, 7, 4, 6, 0} },	/* 12 MHz */
	{16800000, {714, 7, 4, 6, 0} },		/* 16.8 MHz */
	{19200000, {625, 7, 4, 6, 0} },		/* 19.2 MHz */
	{20000000, {600, 7, 4, 6, 0} },		/* 20 MHz */
	{26000000, {461, 7, 4, 6, 0} },		/* 26 MHz */
	{38400000, {312, 7, 4, 6, 0} },		/* 38.4 MHz */
	{ },					/* Terminator */
};

static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
{
	return __raw_readl(addr + offset);
}

static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	u32 data)
{
	__raw_writel(data, addr + offset);
}

static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
	unsigned long rate;
	struct pipe3_dpll_map *dpll_map = phy->dpll_map;

	rate = clk_get_rate(phy->sys_clk);

	for (; dpll_map->rate; dpll_map++) {
		if (rate == dpll_map->rate)
			return &dpll_map->params;
	}

	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);

	return NULL;
}

static int ti_pipe3_power_off(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 0);

	return 0;
}

static int ti_pipe3_power_on(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 1);

	return 0;
}

static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
	u32		val;
	unsigned long	timeout;

	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if (val & PLL_LOCK)
			break;
	} while (!time_after(jiffies, timeout));

	if (!(val & PLL_LOCK)) {
		dev_err(phy->dev, "DPLL failed to lock\n");
		return -EBUSY;
	}

	return 0;
}

static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
	u32			val;
	struct pipe3_dpll_params *dpll_params;

	dpll_params = ti_pipe3_get_dpll_params(phy);
	if (!dpll_params)
		return -EINVAL;

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGN_MASK;
	val |= dpll_params->n << PLL_REGN_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val &= ~PLL_SELFREQDCO_MASK;
	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGM_MASK;
	val |= dpll_params->m << PLL_REGM_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
	val &= ~PLL_REGM_F_MASK;
	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
	val &= ~PLL_SD_MASK;
	val |= dpll_params->sd << PLL_SD_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);

	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);

	return ti_pipe3_dpll_wait_lock(phy);
}

static int ti_pipe3_init(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	int ret = 0;

	/*
	 * Set pcie_pcs register to 0x96 for proper functioning of phy
	 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	 * 18-1804.
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
		omap_control_pcie_pcs(phy->control_dev, 0x96);
		return 0;
	}

	/* Bring it out of IDLE if it is IDLE */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	if (val & PLL_IDLE) {
		val &= ~PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
		ret = ti_pipe3_dpll_wait_lock(phy);
	}

	/* Program the DPLL only if not locked */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	if (!(val & PLL_LOCK))
		if (ti_pipe3_dpll_program(phy))
			return -EINVAL;

	return ret;
}

static int ti_pipe3_exit(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	unsigned long timeout;

	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
	 * does not have internal DPLL
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
	    of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
		return 0;

	/* Put DPLL in IDLE mode */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val |= PLL_IDLE;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	/* wait for LDO and Oscillator to power down */
	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
			break;
	} while (!time_after(jiffies, timeout));

	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
		dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
			val);
		return -EBUSY;
	}

	return 0;
}
static struct phy_ops ops = {
	.init		= ti_pipe3_init,
	.exit		= ti_pipe3_exit,
	.power_on	= ti_pipe3_power_on,
	.power_off	= ti_pipe3_power_off,
	.owner		= THIS_MODULE,
};

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[];
#endif

static int ti_pipe3_probe(struct platform_device *pdev)
{
	struct ti_pipe3 *phy;
	struct phy *generic_phy;
	struct phy_provider *phy_provider;
	struct resource *res;
	struct device_node *node = pdev->dev.of_node;
	struct device_node *control_node;
	struct platform_device *control_pdev;
	const struct of_device_id *match;
	struct clk *clk;

	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	phy->dev		= &pdev->dev;

	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
		match = of_match_device(of_match_ptr(ti_pipe3_id_table),
					&pdev->dev);
		if (!match)
			return -EINVAL;

		phy->dpll_map = (struct pipe3_dpll_map *)match->data;
		if (!phy->dpll_map) {
			dev_err(&pdev->dev, "no DPLL data\n");
			return -EINVAL;
		}

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						   "pll_ctrl");
		phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(phy->pll_ctrl_base))
			return PTR_ERR(phy->pll_ctrl_base);

		phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
		if (IS_ERR(phy->sys_clk)) {
			dev_err(&pdev->dev, "unable to get sysclk\n");
			return -EINVAL;
		}
	}

	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
		phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
		if (IS_ERR(phy->wkupclk)) {
			dev_err(&pdev->dev, "unable to get wkupclk\n");
			return PTR_ERR(phy->wkupclk);
		}

		phy->refclk = devm_clk_get(phy->dev, "refclk");
		if (IS_ERR(phy->refclk)) {
			dev_err(&pdev->dev, "unable to get refclk\n");
			return PTR_ERR(phy->refclk);
		}
	} else {
		phy->wkupclk = ERR_PTR(-ENODEV);
		phy->refclk = ERR_PTR(-ENODEV);
	}

	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {

		clk = devm_clk_get(phy->dev, "dpll_ref");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get dpll ref clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 1500000000);

		clk = devm_clk_get(phy->dev, "dpll_ref_m2");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		clk = devm_clk_get(phy->dev, "phy-div");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get phy-div clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		phy->div_clk = devm_clk_get(phy->dev, "div-clk");
		if (IS_ERR(phy->div_clk)) {
			dev_err(&pdev->dev, "unable to get div-clk\n");
			return PTR_ERR(phy->div_clk);
		}
	} else {
		phy->div_clk = ERR_PTR(-ENODEV);
	}

	control_node = of_parse_phandle(node, "ctrl-module", 0);
	if (!control_node) {
		dev_err(&pdev->dev, "Failed to get control device phandle\n");
		return -EINVAL;
	}

	control_pdev = of_find_device_by_node(control_node);
	if (!control_pdev) {
		dev_err(&pdev->dev, "Failed to get control device\n");
		return -EINVAL;
	}

	phy->control_dev = &control_pdev->dev;

	omap_control_phy_power(phy->control_dev, 0);

	platform_set_drvdata(pdev, phy);
	pm_runtime_enable(phy->dev);

	generic_phy = devm_phy_create(phy->dev, NULL, &ops);
	if (IS_ERR(generic_phy))
		return PTR_ERR(generic_phy);

	phy_set_drvdata(generic_phy, phy);
	phy_provider = devm_of_phy_provider_register(phy->dev,
			of_phy_simple_xlate);
	if (IS_ERR(phy_provider))
		return PTR_ERR(phy_provider);

	pm_runtime_get(&pdev->dev);

	return 0;
}

static int ti_pipe3_remove(struct platform_device *pdev)
{
	if (!pm_runtime_suspended(&pdev->dev))
		pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM

static int ti_pipe3_runtime_suspend(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);
	if (!IS_ERR(phy->div_clk))
		clk_disable_unprepare(phy->div_clk);

	return 0;
}

static int ti_pipe3_runtime_resume(struct device *dev)
{
	u32 ret = 0;
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	if (!IS_ERR(phy->refclk)) {
		ret = clk_prepare_enable(phy->refclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
			goto err1;
		}
	}

	if (!IS_ERR(phy->wkupclk)) {
		ret = clk_prepare_enable(phy->wkupclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
			goto err2;
		}
	}

	if (!IS_ERR(phy->div_clk)) {
		ret = clk_prepare_enable(phy->div_clk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
			goto err3;
		}
	}
	return 0;

err3:
	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);

err2:
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

err1:
	return ret;
}

static const struct dev_pm_ops ti_pipe3_pm_ops = {
	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
			   ti_pipe3_runtime_resume, NULL)
};

#define DEV_PM_OPS     (&ti_pipe3_pm_ops)
#else
#define DEV_PM_OPS     NULL
#endif

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[] = {
	{
		.compatible = "ti,phy-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,omap-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,phy-pipe3-sata",
		.data = dpll_map_sata,
	},
	{
		.compatible = "ti,phy-pipe3-pcie",
	},
	{}
};
MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
#endif

static struct platform_driver ti_pipe3_driver = {
	.probe		= ti_pipe3_probe,
	.remove		= ti_pipe3_remove,
	.driver		= {
		.name	= "ti-pipe3",
		.pm	= DEV_PM_OPS,
		.of_match_table = of_match_ptr(ti_pipe3_id_table),
	},
};

module_platform_driver(ti_pipe3_driver);

MODULE_ALIAS("platform: ti_pipe3");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("TI PIPE3 phy driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
57f6ce07	1	/*
a70143bb	2	* phy-ti-pipe3 - PIPE3 PHY driver.
57f6ce07 KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
a70143bb	22	#include <linux/phy/phy.h>
57f6ce07 KVA	23	#include <linux/of.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
a70143bb	26	#include <linux/io.h>
57f6ce07 KVA	27	#include <linux/pm_runtime.h>
57f6ce07 KVA	28	#include <linux/delay.h>
14da699b	29	#include <linux/phy/omap_control_phy.h>
918ee0d2	30	#include <linux/of_platform.h>
57f6ce07	31
57f6ce07 KVA	32	#define PLL_STATUS 0x00000004
	33	#define PLL_GO 0x00000008
	34	#define PLL_CONFIGURATION1 0x0000000C
	35	#define PLL_CONFIGURATION2 0x00000010
	36	#define PLL_CONFIGURATION3 0x00000014
	37	#define PLL_CONFIGURATION4 0x00000020
	38
	39	#define PLL_REGM_MASK 0x001FFE00
	40	#define PLL_REGM_SHIFT 0x9
	41	#define PLL_REGM_F_MASK 0x0003FFFF
	42	#define PLL_REGM_F_SHIFT 0x0
	43	#define PLL_REGN_MASK 0x000001FE
	44	#define PLL_REGN_SHIFT 0x1
	45	#define PLL_SELFREQDCO_MASK 0x0000000E
	46	#define PLL_SELFREQDCO_SHIFT 0x1
	47	#define PLL_SD_MASK 0x0003FC00
1562864f	48	#define PLL_SD_SHIFT 10
57f6ce07	49	#define SET_PLL_GO 0x1
629138db RQ	50	#define PLL_LDOPWDN BIT(15)
629138db RQ	51	#define PLL_TICOPWDN BIT(16)
57f6ce07 KVA	52	#define PLL_LOCK 0x2
	53	#define PLL_IDLE 0x1
	54
	55	/*
	56	* This is an Empirical value that works, need to confirm the actual
a70143bb KVA	57	* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
a70143bb KVA	58	* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
57f6ce07	59	*/
629138db RQ	60	#define PLL_IDLE_TIME 100 /* in milliseconds */
629138db RQ	61	#define PLL_LOCK_TIME 100 /* in milliseconds */
57f6ce07	62
a70143bb KVA	63	struct pipe3_dpll_params {
	64	u16 m;
	65	u8 n;
	66	u8 freq:3;
	67	u8 sd;
	68	u32 mf;
	69	};
	70
61f54674 RQ	71	struct pipe3_dpll_map {
	72	unsigned long rate;
	73	struct pipe3_dpll_params params;
	74	};
	75
a70143bb KVA	76	struct ti_pipe3 {
	77	void __iomem *pll_ctrl_base;
	78	struct device *dev;
	79	struct device *control_dev;
	80	struct clk *wkupclk;
	81	struct clk *sys_clk;
1562864f	82	struct clk *refclk;
99bbd48c	83	struct clk *div_clk;
61f54674	84	struct pipe3_dpll_map *dpll_map;
a70143bb KVA	85	};
a70143bb KVA	86
61f54674	87	static struct pipe3_dpll_map dpll_map_usb[] = {
519c6013 RQ	88	{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
	89	{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
	90	{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
	91	{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
	92	{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
	93	{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
61f54674 RQ	94	{ }, /* Terminator */
	95	};
	96
	97	static struct pipe3_dpll_map dpll_map_sata[] = {
	98	{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
	99	{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
	100	{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
	101	{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
	102	{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
	103	{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
	104	{ }, /* Terminator */
57f6ce07 KVA	105	};
57f6ce07 KVA	106
a70143bb KVA	107	static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
	108	{
	109	return __raw_readl(addr + offset);
	110	}
	111
	112	static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	113	u32 data)
	114	{
	115	__raw_writel(data, addr + offset);
	116	}
	117
61f54674	118	static struct pipe3_dpll_params ti_pipe3_get_dpll_params(struct ti_pipe3 phy)
519c6013	119	{
61f54674 RQ	120	unsigned long rate;
61f54674 RQ	121	struct pipe3_dpll_map *dpll_map = phy->dpll_map;
519c6013	122
61f54674 RQ	123	rate = clk_get_rate(phy->sys_clk);
	124
	125	for (; dpll_map->rate; dpll_map++) {
	126	if (rate == dpll_map->rate)
	127	return &dpll_map->params;
519c6013 RQ	128	}
519c6013 RQ	129
61f54674 RQ	130	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
61f54674 RQ	131
1b97be8c	132	return NULL;
519c6013 RQ	133	}
519c6013 RQ	134
a70143bb KVA	135	static int ti_pipe3_power_off(struct phy *x)
	136	{
	137	struct ti_pipe3 *phy = phy_get_drvdata(x);
a70143bb	138
14da699b	139	omap_control_phy_power(phy->control_dev, 0);
a70143bb KVA	140
	141	return 0;
	142	}
	143
	144	static int ti_pipe3_power_on(struct phy *x)
57f6ce07	145	{
a70143bb	146	struct ti_pipe3 *phy = phy_get_drvdata(x);
57f6ce07	147
629138db	148	omap_control_phy_power(phy->control_dev, 1);
57f6ce07 KVA	149
	150	return 0;
	151	}
	152
629138db	153	static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
57f6ce07 KVA	154	{
	155	u32 val;
	156	unsigned long timeout;
	157
629138db	158	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
57f6ce07	159	do {
629138db	160	cpu_relax();
a70143bb	161	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
57f6ce07 KVA	162	if (val & PLL_LOCK)
57f6ce07 KVA	163	break;
629138db RQ	164	} while (!time_after(jiffies, timeout));
	165
	166	if (!(val & PLL_LOCK)) {
	167	dev_err(phy->dev, "DPLL failed to lock\n");
	168	return -EBUSY;
	169	}
	170
	171	return 0;
57f6ce07 KVA	172	}
57f6ce07 KVA	173
629138db	174	static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
57f6ce07 KVA	175	{
57f6ce07 KVA	176	u32 val;
a70143bb	177	struct pipe3_dpll_params *dpll_params;
57f6ce07	178
61f54674 RQ	179	dpll_params = ti_pipe3_get_dpll_params(phy);
61f54674 RQ	180	if (!dpll_params)
57f6ce07	181	return -EINVAL;
57f6ce07	182
a70143bb	183	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	184	val &= ~PLL_REGN_MASK;
519c6013	185	val \|= dpll_params->n << PLL_REGN_SHIFT;
a70143bb	186	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	187
a70143bb	188	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
57f6ce07	189	val &= ~PLL_SELFREQDCO_MASK;
519c6013	190	val \|= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
a70143bb	191	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
57f6ce07	192
a70143bb	193	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	194	val &= ~PLL_REGM_MASK;
519c6013	195	val \|= dpll_params->m << PLL_REGM_SHIFT;
a70143bb	196	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	197
a70143bb	198	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
57f6ce07	199	val &= ~PLL_REGM_F_MASK;
519c6013	200	val \|= dpll_params->mf << PLL_REGM_F_SHIFT;
a70143bb	201	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
57f6ce07	202
a70143bb	203	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
57f6ce07	204	val &= ~PLL_SD_MASK;
519c6013	205	val \|= dpll_params->sd << PLL_SD_SHIFT;
a70143bb	206	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
57f6ce07	207
629138db	208	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
57f6ce07	209
629138db	210	return ti_pipe3_dpll_wait_lock(phy);
57f6ce07 KVA	211	}
57f6ce07 KVA	212
a70143bb	213	static int ti_pipe3_init(struct phy *x)
57f6ce07	214	{
a70143bb	215	struct ti_pipe3 *phy = phy_get_drvdata(x);
629138db RQ	216	u32 val;
629138db RQ	217	int ret = 0;
519c6013	218
0bc09f9c V	219	/*
	220	* Set pcie_pcs register to 0x96 for proper functioning of phy
	221	* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	222	* 18-1804.
	223	*/
f0e2cf7b	224	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
0bc09f9c	225	omap_control_pcie_pcs(phy->control_dev, 0x96);
99bbd48c	226	return 0;
f0e2cf7b	227	}
99bbd48c	228
629138db RQ	229	/* Bring it out of IDLE if it is IDLE */
	230	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	231	if (val & PLL_IDLE) {
	232	val &= ~PLL_IDLE;
	233	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	234	ret = ti_pipe3_dpll_wait_lock(phy);
	235	}
57f6ce07	236
629138db RQ	237	/* Program the DPLL only if not locked */
	238	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	239	if (!(val & PLL_LOCK))
	240	if (ti_pipe3_dpll_program(phy))
	241	return -EINVAL;
57f6ce07	242
629138db	243	return ret;
57f6ce07 KVA	244	}
57f6ce07 KVA	245
629138db RQ	246	static int ti_pipe3_exit(struct phy *x)
	247	{
	248	struct ti_pipe3 *phy = phy_get_drvdata(x);
	249	u32 val;
	250	unsigned long timeout;
	251
99bbd48c KVA	252	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
	253	* does not have internal DPLL
	254	*/
	255	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") \|\|
	256	of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
56042e4e RQ	257	return 0;
56042e4e RQ	258
629138db RQ	259	/* Put DPLL in IDLE mode */
	260	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	261	val \|= PLL_IDLE;
	262	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	263
	264	/* wait for LDO and Oscillator to power down */
	265	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	266	do {
	267	cpu_relax();
	268	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	269	if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
	270	break;
	271	} while (!time_after(jiffies, timeout));
	272
	273	if (!(val & PLL_TICOPWDN) \|\| !(val & PLL_LDOPWDN)) {
	274	dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
	275	val);
	276	return -EBUSY;
	277	}
	278
	279	return 0;
	280	}
a70143bb KVA	281	static struct phy_ops ops = {
a70143bb KVA	282	.init = ti_pipe3_init,
629138db	283	.exit = ti_pipe3_exit,
a70143bb KVA	284	.power_on = ti_pipe3_power_on,
	285	.power_off = ti_pipe3_power_off,
	286	.owner = THIS_MODULE,
	287	};
	288
61f54674 RQ	289	#ifdef CONFIG_OF
	290	static const struct of_device_id ti_pipe3_id_table[];
	291	#endif
	292
a70143bb	293	static int ti_pipe3_probe(struct platform_device *pdev)
57f6ce07	294	{
a70143bb KVA	295	struct ti_pipe3 *phy;
	296	struct phy *generic_phy;
	297	struct phy_provider *phy_provider;
918ee0d2 RQ	298	struct resource *res;
	299	struct device_node *node = pdev->dev.of_node;
	300	struct device_node *control_node;
	301	struct platform_device *control_pdev;
61f54674	302	const struct of_device_id *match;
99bbd48c	303	struct clk *clk;
57f6ce07 KVA	304
57f6ce07 KVA	305	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
3a4cfcbb	306	if (!phy)
57f6ce07	307	return -ENOMEM;
3a4cfcbb	308
99bbd48c	309	phy->dev = &pdev->dev;
57f6ce07	310
99bbd48c KVA	311	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
	312	match = of_match_device(of_match_ptr(ti_pipe3_id_table),
	313	&pdev->dev);
	314	if (!match)
	315	return -EINVAL;
61f54674	316
99bbd48c KVA	317	phy->dpll_map = (struct pipe3_dpll_map *)match->data;
	318	if (!phy->dpll_map) {
	319	dev_err(&pdev->dev, "no DPLL data\n");
	320	return -EINVAL;
	321	}
57f6ce07	322
99bbd48c KVA	323	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	324	"pll_ctrl");
	325	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	326	if (IS_ERR(phy->pll_ctrl_base))
	327	return PTR_ERR(phy->pll_ctrl_base);
57f6ce07	328
99bbd48c KVA	329	phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
	330	if (IS_ERR(phy->sys_clk)) {
	331	dev_err(&pdev->dev, "unable to get sysclk\n");
	332	return -EINVAL;
	333	}
	334	}
9c7f0443	335
99bbd48c	336	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
9c7f0443 RQ	337	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
	338	if (IS_ERR(phy->wkupclk)) {
	339	dev_err(&pdev->dev, "unable to get wkupclk\n");
	340	return PTR_ERR(phy->wkupclk);
	341	}
	342
	343	phy->refclk = devm_clk_get(phy->dev, "refclk");
	344	if (IS_ERR(phy->refclk)) {
	345	dev_err(&pdev->dev, "unable to get refclk\n");
	346	return PTR_ERR(phy->refclk);
	347	}
	348	} else {
	349	phy->wkupclk = ERR_PTR(-ENODEV);
	350	phy->refclk = ERR_PTR(-ENODEV);
57f6ce07	351	}
57f6ce07	352
99bbd48c	353	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
99bbd48c KVA	354
	355	clk = devm_clk_get(phy->dev, "dpll_ref");
	356	if (IS_ERR(clk)) {
	357	dev_err(&pdev->dev, "unable to get dpll ref clk\n");
	358	return PTR_ERR(clk);
	359	}
	360	clk_set_rate(clk, 1500000000);
	361
	362	clk = devm_clk_get(phy->dev, "dpll_ref_m2");
	363	if (IS_ERR(clk)) {
	364	dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
	365	return PTR_ERR(clk);
	366	}
	367	clk_set_rate(clk, 100000000);
	368
	369	clk = devm_clk_get(phy->dev, "phy-div");
	370	if (IS_ERR(clk)) {
	371	dev_err(&pdev->dev, "unable to get phy-div clk\n");
	372	return PTR_ERR(clk);
	373	}
	374	clk_set_rate(clk, 100000000);
	375
	376	phy->div_clk = devm_clk_get(phy->dev, "div-clk");
	377	if (IS_ERR(phy->div_clk)) {
	378	dev_err(&pdev->dev, "unable to get div-clk\n");
	379	return PTR_ERR(phy->div_clk);
	380	}
	381	} else {
	382	phy->div_clk = ERR_PTR(-ENODEV);
57f6ce07 KVA	383	}
57f6ce07 KVA	384
918ee0d2 RQ	385	control_node = of_parse_phandle(node, "ctrl-module", 0);
	386	if (!control_node) {
	387	dev_err(&pdev->dev, "Failed to get control device phandle\n");
	388	return -EINVAL;
57f6ce07	389	}
a70143bb	390
918ee0d2 RQ	391	control_pdev = of_find_device_by_node(control_node);
	392	if (!control_pdev) {
	393	dev_err(&pdev->dev, "Failed to get control device\n");
	394	return -EINVAL;
	395	}
	396
	397	phy->control_dev = &control_pdev->dev;
57f6ce07	398
14da699b	399	omap_control_phy_power(phy->control_dev, 0);
57f6ce07 KVA	400
57f6ce07 KVA	401	platform_set_drvdata(pdev, phy);
57f6ce07	402	pm_runtime_enable(phy->dev);
a70143bb	403
dbc98635	404	generic_phy = devm_phy_create(phy->dev, NULL, &ops);
a70143bb KVA	405	if (IS_ERR(generic_phy))
	406	return PTR_ERR(generic_phy);
	407
	408	phy_set_drvdata(generic_phy, phy);
	409	phy_provider = devm_of_phy_provider_register(phy->dev,
	410	of_phy_simple_xlate);
	411	if (IS_ERR(phy_provider))
	412	return PTR_ERR(phy_provider);
	413
57f6ce07 KVA	414	pm_runtime_get(&pdev->dev);
	415
	416	return 0;
	417	}
	418
a70143bb	419	static int ti_pipe3_remove(struct platform_device *pdev)
57f6ce07	420	{
57f6ce07 KVA	421	if (!pm_runtime_suspended(&pdev->dev))
	422	pm_runtime_put(&pdev->dev);
	423	pm_runtime_disable(&pdev->dev);
	424
	425	return 0;
	426	}
	427
7ba37053	428	#ifdef CONFIG_PM
57f6ce07	429
a70143bb	430	static int ti_pipe3_runtime_suspend(struct device *dev)
57f6ce07	431	{
a70143bb	432	struct ti_pipe3 *phy = dev_get_drvdata(dev);
57f6ce07	433
1562864f RQ	434	if (!IS_ERR(phy->wkupclk))
	435	clk_disable_unprepare(phy->wkupclk);
	436	if (!IS_ERR(phy->refclk))
	437	clk_disable_unprepare(phy->refclk);
99bbd48c KVA	438	if (!IS_ERR(phy->div_clk))
99bbd48c KVA	439	clk_disable_unprepare(phy->div_clk);
57f6ce07 KVA	440
	441	return 0;
	442	}
	443
a70143bb	444	static int ti_pipe3_runtime_resume(struct device *dev)
57f6ce07 KVA	445	{
57f6ce07 KVA	446	u32 ret = 0;
a70143bb	447	struct ti_pipe3 *phy = dev_get_drvdata(dev);
57f6ce07	448
1562864f RQ	449	if (!IS_ERR(phy->refclk)) {
	450	ret = clk_prepare_enable(phy->refclk);
	451	if (ret) {
	452	dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
	453	goto err1;
	454	}
57f6ce07 KVA	455	}
57f6ce07 KVA	456
1562864f RQ	457	if (!IS_ERR(phy->wkupclk)) {
	458	ret = clk_prepare_enable(phy->wkupclk);
	459	if (ret) {
	460	dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
	461	goto err2;
	462	}
57f6ce07 KVA	463	}
57f6ce07 KVA	464
99bbd48c KVA	465	if (!IS_ERR(phy->div_clk)) {
	466	ret = clk_prepare_enable(phy->div_clk);
	467	if (ret) {
	468	dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
	469	goto err3;
	470	}
	471	}
57f6ce07 KVA	472	return 0;
57f6ce07 KVA	473
99bbd48c KVA	474	err3:
	475	if (!IS_ERR(phy->wkupclk))
	476	clk_disable_unprepare(phy->wkupclk);
	477
57f6ce07	478	err2:
1562864f RQ	479	if (!IS_ERR(phy->refclk))
1562864f RQ	480	clk_disable_unprepare(phy->refclk);
57f6ce07 KVA	481
	482	err1:
	483	return ret;
	484	}
	485
a70143bb KVA	486	static const struct dev_pm_ops ti_pipe3_pm_ops = {
	487	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
	488	ti_pipe3_runtime_resume, NULL)
57f6ce07 KVA	489	};
57f6ce07 KVA	490
a70143bb	491	#define DEV_PM_OPS (&ti_pipe3_pm_ops)
57f6ce07 KVA	492	#else
	493	#define DEV_PM_OPS NULL
	494	#endif
	495
	496	#ifdef CONFIG_OF
a70143bb	497	static const struct of_device_id ti_pipe3_id_table[] = {
61f54674 RQ	498	{
	499	.compatible = "ti,phy-usb3",
	500	.data = dpll_map_usb,
	501	},
	502	{
	503	.compatible = "ti,omap-usb3",
	504	.data = dpll_map_usb,
	505	},
	506	{
	507	.compatible = "ti,phy-pipe3-sata",
	508	.data = dpll_map_sata,
	509	},
99bbd48c KVA	510	{
	511	.compatible = "ti,phy-pipe3-pcie",
	512	},
57f6ce07 KVA	513	{}
57f6ce07 KVA	514	};
a70143bb	515	MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
57f6ce07 KVA	516	#endif
57f6ce07 KVA	517
a70143bb KVA	518	static struct platform_driver ti_pipe3_driver = {
	519	.probe = ti_pipe3_probe,
	520	.remove = ti_pipe3_remove,
57f6ce07	521	.driver = {
a70143bb	522	.name = "ti-pipe3",
57f6ce07	523	.pm = DEV_PM_OPS,
a70143bb	524	.of_match_table = of_match_ptr(ti_pipe3_id_table),
57f6ce07 KVA	525	},
	526	};
	527
a70143bb	528	module_platform_driver(ti_pipe3_driver);
57f6ce07	529
a70143bb	530	MODULE_ALIAS("platform: ti_pipe3");
57f6ce07	531	MODULE_AUTHOR("Texas Instruments Inc.");
a70143bb	532	MODULE_DESCRIPTION("TI PIPE3 phy driver");
57f6ce07	533	MODULE_LICENSE("GPL v2");