[deliverable/linux.git] / drivers / phy / phy-ti-pipe3.c

/*
 * phy-ti-pipe3 - PIPE3 PHY driver.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/phy/phy.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>

#define	PLL_STATUS		0x00000004
#define	PLL_GO			0x00000008
#define	PLL_CONFIGURATION1	0x0000000C
#define	PLL_CONFIGURATION2	0x00000010
#define	PLL_CONFIGURATION3	0x00000014
#define	PLL_CONFIGURATION4	0x00000020

#define	PLL_REGM_MASK		0x001FFE00
#define	PLL_REGM_SHIFT		0x9
#define	PLL_REGM_F_MASK		0x0003FFFF
#define	PLL_REGM_F_SHIFT	0x0
#define	PLL_REGN_MASK		0x000001FE
#define	PLL_REGN_SHIFT		0x1
#define	PLL_SELFREQDCO_MASK	0x0000000E
#define	PLL_SELFREQDCO_SHIFT	0x1
#define	PLL_SD_MASK		0x0003FC00
#define	PLL_SD_SHIFT		10
#define	SET_PLL_GO		0x1
#define PLL_LDOPWDN		BIT(15)
#define PLL_TICOPWDN		BIT(16)
#define	PLL_LOCK		0x2
#define	PLL_IDLE		0x1

/*
 * This is an Empirical value that works, need to confirm the actual
 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 */
#define PLL_IDLE_TIME	100	/* in milliseconds */
#define PLL_LOCK_TIME	100	/* in milliseconds */

struct pipe3_dpll_params {
	u16	m;
	u8	n;
	u8	freq:3;
	u8	sd;
	u32	mf;
};

struct pipe3_dpll_map {
	unsigned long rate;
	struct pipe3_dpll_params params;
};

struct ti_pipe3 {
	void __iomem		*pll_ctrl_base;
	struct device		*dev;
	struct device		*control_dev;
	struct clk		*wkupclk;
	struct clk		*sys_clk;
	struct clk		*refclk;
	struct pipe3_dpll_map	*dpll_map;
};

static struct pipe3_dpll_map dpll_map_usb[] = {
	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
	{ },					/* Terminator */
};

static struct pipe3_dpll_map dpll_map_sata[] = {
	{12000000, {1000, 7, 4, 6, 0} },	/* 12 MHz */
	{16800000, {714, 7, 4, 6, 0} },		/* 16.8 MHz */
	{19200000, {625, 7, 4, 6, 0} },		/* 19.2 MHz */
	{20000000, {600, 7, 4, 6, 0} },		/* 20 MHz */
	{26000000, {461, 7, 4, 6, 0} },		/* 26 MHz */
	{38400000, {312, 7, 4, 6, 0} },		/* 38.4 MHz */
	{ },					/* Terminator */
};

static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
{
	return __raw_readl(addr + offset);
}

static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	u32 data)
{
	__raw_writel(data, addr + offset);
}

static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
	unsigned long rate;
	struct pipe3_dpll_map *dpll_map = phy->dpll_map;

	rate = clk_get_rate(phy->sys_clk);

	for (; dpll_map->rate; dpll_map++) {
		if (rate == dpll_map->rate)
			return &dpll_map->params;
	}

	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);

	return NULL;
}

static int ti_pipe3_power_off(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 0);

	return 0;
}

static int ti_pipe3_power_on(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 1);

	return 0;
}

static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
	u32		val;
	unsigned long	timeout;

	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if (val & PLL_LOCK)
			break;
	} while (!time_after(jiffies, timeout));

	if (!(val & PLL_LOCK)) {
		dev_err(phy->dev, "DPLL failed to lock\n");
		return -EBUSY;
	}

	return 0;
}

static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
	u32			val;
	struct pipe3_dpll_params *dpll_params;

	dpll_params = ti_pipe3_get_dpll_params(phy);
	if (!dpll_params)
		return -EINVAL;

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGN_MASK;
	val |= dpll_params->n << PLL_REGN_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val &= ~PLL_SELFREQDCO_MASK;
	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGM_MASK;
	val |= dpll_params->m << PLL_REGM_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
	val &= ~PLL_REGM_F_MASK;
	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
	val &= ~PLL_SD_MASK;
	val |= dpll_params->sd << PLL_SD_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);

	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);

	return ti_pipe3_dpll_wait_lock(phy);
}

static int ti_pipe3_init(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	int ret = 0;

	/* Bring it out of IDLE if it is IDLE */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	if (val & PLL_IDLE) {
		val &= ~PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
		ret = ti_pipe3_dpll_wait_lock(phy);
	}

	/* Program the DPLL only if not locked */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	if (!(val & PLL_LOCK))
		if (ti_pipe3_dpll_program(phy))
			return -EINVAL;

	return ret;
}

static int ti_pipe3_exit(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	unsigned long timeout;

	/* SATA DPLL can't be powered down due to Errata i783 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
		return 0;

	/* Put DPLL in IDLE mode */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val |= PLL_IDLE;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	/* wait for LDO and Oscillator to power down */
	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
			break;
	} while (!time_after(jiffies, timeout));

	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
		dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
			val);
		return -EBUSY;
	}

	return 0;
}
static struct phy_ops ops = {
	.init		= ti_pipe3_init,
	.exit		= ti_pipe3_exit,
	.power_on	= ti_pipe3_power_on,
	.power_off	= ti_pipe3_power_off,
	.owner		= THIS_MODULE,
};

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[];
#endif

static int ti_pipe3_probe(struct platform_device *pdev)
{
	struct ti_pipe3 *phy;
	struct phy *generic_phy;
	struct phy_provider *phy_provider;
	struct resource *res;
	struct device_node *node = pdev->dev.of_node;
	struct device_node *control_node;
	struct platform_device *control_pdev;
	const struct of_device_id *match;

	match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
	if (!match)
		return -EINVAL;

	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
	if (!phy) {
		dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
		return -ENOMEM;
	}

	phy->dpll_map = (struct pipe3_dpll_map *)match->data;
	if (!phy->dpll_map) {
		dev_err(&pdev->dev, "no DPLL data\n");
		return -EINVAL;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(phy->pll_ctrl_base))
		return PTR_ERR(phy->pll_ctrl_base);

	phy->dev		= &pdev->dev;

	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {

		phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
		if (IS_ERR(phy->wkupclk)) {
			dev_err(&pdev->dev, "unable to get wkupclk\n");
			return PTR_ERR(phy->wkupclk);
		}

		phy->refclk = devm_clk_get(phy->dev, "refclk");
		if (IS_ERR(phy->refclk)) {
			dev_err(&pdev->dev, "unable to get refclk\n");
			return PTR_ERR(phy->refclk);
		}
	} else {
		phy->wkupclk = ERR_PTR(-ENODEV);
		phy->refclk = ERR_PTR(-ENODEV);
	}

	phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
	if (IS_ERR(phy->sys_clk)) {
		dev_err(&pdev->dev, "unable to get sysclk\n");
		return -EINVAL;
	}

	control_node = of_parse_phandle(node, "ctrl-module", 0);
	if (!control_node) {
		dev_err(&pdev->dev, "Failed to get control device phandle\n");
		return -EINVAL;
	}

	control_pdev = of_find_device_by_node(control_node);
	if (!control_pdev) {
		dev_err(&pdev->dev, "Failed to get control device\n");
		return -EINVAL;
	}

	phy->control_dev = &control_pdev->dev;

	omap_control_phy_power(phy->control_dev, 0);

	platform_set_drvdata(pdev, phy);
	pm_runtime_enable(phy->dev);

	generic_phy = devm_phy_create(phy->dev, &ops, NULL);
	if (IS_ERR(generic_phy))
		return PTR_ERR(generic_phy);

	phy_set_drvdata(generic_phy, phy);
	phy_provider = devm_of_phy_provider_register(phy->dev,
			of_phy_simple_xlate);
	if (IS_ERR(phy_provider))
		return PTR_ERR(phy_provider);

	pm_runtime_get(&pdev->dev);

	return 0;
}

static int ti_pipe3_remove(struct platform_device *pdev)
{
	if (!pm_runtime_suspended(&pdev->dev))
		pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM_RUNTIME

static int ti_pipe3_runtime_suspend(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

	return 0;
}

static int ti_pipe3_runtime_resume(struct device *dev)
{
	u32 ret = 0;
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	if (!IS_ERR(phy->refclk)) {
		ret = clk_prepare_enable(phy->refclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
			goto err1;
		}
	}

	if (!IS_ERR(phy->wkupclk)) {
		ret = clk_prepare_enable(phy->wkupclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
			goto err2;
		}
	}

	return 0;

err2:
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

err1:
	return ret;
}

static const struct dev_pm_ops ti_pipe3_pm_ops = {
	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
			   ti_pipe3_runtime_resume, NULL)
};

#define DEV_PM_OPS     (&ti_pipe3_pm_ops)
#else
#define DEV_PM_OPS     NULL
#endif

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[] = {
	{
		.compatible = "ti,phy-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,omap-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,phy-pipe3-sata",
		.data = dpll_map_sata,
	},
	{}
};
MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
#endif

static struct platform_driver ti_pipe3_driver = {
	.probe		= ti_pipe3_probe,
	.remove		= ti_pipe3_remove,
	.driver		= {
		.name	= "ti-pipe3",
		.owner	= THIS_MODULE,
		.pm	= DEV_PM_OPS,
		.of_match_table = of_match_ptr(ti_pipe3_id_table),
	},
};

module_platform_driver(ti_pipe3_driver);

MODULE_ALIAS("platform: ti_pipe3");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("TI PIPE3 phy driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
57f6ce07	1	/*
a70143bb	2	* phy-ti-pipe3 - PIPE3 PHY driver.
57f6ce07 KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
a70143bb	22	#include <linux/phy/phy.h>
57f6ce07 KVA	23	#include <linux/of.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
a70143bb	26	#include <linux/io.h>
57f6ce07 KVA	27	#include <linux/pm_runtime.h>
57f6ce07 KVA	28	#include <linux/delay.h>
14da699b	29	#include <linux/phy/omap_control_phy.h>
918ee0d2	30	#include <linux/of_platform.h>
57f6ce07	31
57f6ce07 KVA	32	#define PLL_STATUS 0x00000004
	33	#define PLL_GO 0x00000008
	34	#define PLL_CONFIGURATION1 0x0000000C
	35	#define PLL_CONFIGURATION2 0x00000010
	36	#define PLL_CONFIGURATION3 0x00000014
	37	#define PLL_CONFIGURATION4 0x00000020
	38
	39	#define PLL_REGM_MASK 0x001FFE00
	40	#define PLL_REGM_SHIFT 0x9
	41	#define PLL_REGM_F_MASK 0x0003FFFF
	42	#define PLL_REGM_F_SHIFT 0x0
	43	#define PLL_REGN_MASK 0x000001FE
	44	#define PLL_REGN_SHIFT 0x1
	45	#define PLL_SELFREQDCO_MASK 0x0000000E
	46	#define PLL_SELFREQDCO_SHIFT 0x1
	47	#define PLL_SD_MASK 0x0003FC00
1562864f	48	#define PLL_SD_SHIFT 10
57f6ce07	49	#define SET_PLL_GO 0x1
629138db RQ	50	#define PLL_LDOPWDN BIT(15)
629138db RQ	51	#define PLL_TICOPWDN BIT(16)
57f6ce07 KVA	52	#define PLL_LOCK 0x2
	53	#define PLL_IDLE 0x1
	54
	55	/*
	56	* This is an Empirical value that works, need to confirm the actual
a70143bb KVA	57	* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
a70143bb KVA	58	* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
57f6ce07	59	*/
629138db RQ	60	#define PLL_IDLE_TIME 100 /* in milliseconds */
629138db RQ	61	#define PLL_LOCK_TIME 100 /* in milliseconds */
57f6ce07	62
a70143bb KVA	63	struct pipe3_dpll_params {
	64	u16 m;
	65	u8 n;
	66	u8 freq:3;
	67	u8 sd;
	68	u32 mf;
	69	};
	70
61f54674 RQ	71	struct pipe3_dpll_map {
	72	unsigned long rate;
	73	struct pipe3_dpll_params params;
	74	};
	75
a70143bb KVA	76	struct ti_pipe3 {
	77	void __iomem *pll_ctrl_base;
	78	struct device *dev;
	79	struct device *control_dev;
	80	struct clk *wkupclk;
	81	struct clk *sys_clk;
1562864f	82	struct clk *refclk;
61f54674	83	struct pipe3_dpll_map *dpll_map;
a70143bb KVA	84	};
a70143bb KVA	85
61f54674	86	static struct pipe3_dpll_map dpll_map_usb[] = {
519c6013 RQ	87	{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
	88	{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
	89	{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
	90	{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
	91	{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
	92	{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
61f54674 RQ	93	{ }, /* Terminator */
	94	};
	95
	96	static struct pipe3_dpll_map dpll_map_sata[] = {
	97	{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
	98	{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
	99	{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
	100	{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
	101	{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
	102	{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
	103	{ }, /* Terminator */
57f6ce07 KVA	104	};
57f6ce07 KVA	105
a70143bb KVA	106	static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
	107	{
	108	return __raw_readl(addr + offset);
	109	}
	110
	111	static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	112	u32 data)
	113	{
	114	__raw_writel(data, addr + offset);
	115	}
	116
61f54674	117	static struct pipe3_dpll_params ti_pipe3_get_dpll_params(struct ti_pipe3 phy)
519c6013	118	{
61f54674 RQ	119	unsigned long rate;
61f54674 RQ	120	struct pipe3_dpll_map *dpll_map = phy->dpll_map;
519c6013	121
61f54674 RQ	122	rate = clk_get_rate(phy->sys_clk);
	123
	124	for (; dpll_map->rate; dpll_map++) {
	125	if (rate == dpll_map->rate)
	126	return &dpll_map->params;
519c6013 RQ	127	}
519c6013 RQ	128
61f54674 RQ	129	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
61f54674 RQ	130
1b97be8c	131	return NULL;
519c6013 RQ	132	}
519c6013 RQ	133
a70143bb KVA	134	static int ti_pipe3_power_off(struct phy *x)
	135	{
	136	struct ti_pipe3 *phy = phy_get_drvdata(x);
a70143bb	137
14da699b	138	omap_control_phy_power(phy->control_dev, 0);
a70143bb KVA	139
	140	return 0;
	141	}
	142
	143	static int ti_pipe3_power_on(struct phy *x)
57f6ce07	144	{
a70143bb	145	struct ti_pipe3 *phy = phy_get_drvdata(x);
57f6ce07	146
629138db	147	omap_control_phy_power(phy->control_dev, 1);
57f6ce07 KVA	148
	149	return 0;
	150	}
	151
629138db	152	static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
57f6ce07 KVA	153	{
	154	u32 val;
	155	unsigned long timeout;
	156
629138db	157	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
57f6ce07	158	do {
629138db	159	cpu_relax();
a70143bb	160	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
57f6ce07 KVA	161	if (val & PLL_LOCK)
57f6ce07 KVA	162	break;
629138db RQ	163	} while (!time_after(jiffies, timeout));
	164
	165	if (!(val & PLL_LOCK)) {
	166	dev_err(phy->dev, "DPLL failed to lock\n");
	167	return -EBUSY;
	168	}
	169
	170	return 0;
57f6ce07 KVA	171	}
57f6ce07 KVA	172
629138db	173	static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
57f6ce07 KVA	174	{
57f6ce07 KVA	175	u32 val;
a70143bb	176	struct pipe3_dpll_params *dpll_params;
57f6ce07	177
61f54674 RQ	178	dpll_params = ti_pipe3_get_dpll_params(phy);
61f54674 RQ	179	if (!dpll_params)
57f6ce07	180	return -EINVAL;
57f6ce07	181
a70143bb	182	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	183	val &= ~PLL_REGN_MASK;
519c6013	184	val \|= dpll_params->n << PLL_REGN_SHIFT;
a70143bb	185	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	186
a70143bb	187	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
57f6ce07	188	val &= ~PLL_SELFREQDCO_MASK;
519c6013	189	val \|= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
a70143bb	190	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
57f6ce07	191
a70143bb	192	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	193	val &= ~PLL_REGM_MASK;
519c6013	194	val \|= dpll_params->m << PLL_REGM_SHIFT;
a70143bb	195	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	196
a70143bb	197	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
57f6ce07	198	val &= ~PLL_REGM_F_MASK;
519c6013	199	val \|= dpll_params->mf << PLL_REGM_F_SHIFT;
a70143bb	200	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
57f6ce07	201
a70143bb	202	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
57f6ce07	203	val &= ~PLL_SD_MASK;
519c6013	204	val \|= dpll_params->sd << PLL_SD_SHIFT;
a70143bb	205	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
57f6ce07	206
629138db	207	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
57f6ce07	208
629138db	209	return ti_pipe3_dpll_wait_lock(phy);
57f6ce07 KVA	210	}
57f6ce07 KVA	211
a70143bb	212	static int ti_pipe3_init(struct phy *x)
57f6ce07	213	{
a70143bb	214	struct ti_pipe3 *phy = phy_get_drvdata(x);
629138db RQ	215	u32 val;
629138db RQ	216	int ret = 0;
519c6013	217
629138db RQ	218	/* Bring it out of IDLE if it is IDLE */
	219	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	220	if (val & PLL_IDLE) {
	221	val &= ~PLL_IDLE;
	222	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	223	ret = ti_pipe3_dpll_wait_lock(phy);
	224	}
57f6ce07	225
629138db RQ	226	/* Program the DPLL only if not locked */
	227	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	228	if (!(val & PLL_LOCK))
	229	if (ti_pipe3_dpll_program(phy))
	230	return -EINVAL;
57f6ce07	231
629138db	232	return ret;
57f6ce07 KVA	233	}
57f6ce07 KVA	234
629138db RQ	235	static int ti_pipe3_exit(struct phy *x)
	236	{
	237	struct ti_pipe3 *phy = phy_get_drvdata(x);
	238	u32 val;
	239	unsigned long timeout;
	240
56042e4e RQ	241	/* SATA DPLL can't be powered down due to Errata i783 */
	242	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
	243	return 0;
	244
629138db RQ	245	/* Put DPLL in IDLE mode */
	246	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	247	val \|= PLL_IDLE;
	248	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	249
	250	/* wait for LDO and Oscillator to power down */
	251	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	252	do {
	253	cpu_relax();
	254	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	255	if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
	256	break;
	257	} while (!time_after(jiffies, timeout));
	258
	259	if (!(val & PLL_TICOPWDN) \|\| !(val & PLL_LDOPWDN)) {
	260	dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
	261	val);
	262	return -EBUSY;
	263	}
	264
	265	return 0;
	266	}
a70143bb KVA	267	static struct phy_ops ops = {
a70143bb KVA	268	.init = ti_pipe3_init,
629138db	269	.exit = ti_pipe3_exit,
a70143bb KVA	270	.power_on = ti_pipe3_power_on,
	271	.power_off = ti_pipe3_power_off,
	272	.owner = THIS_MODULE,
	273	};
	274
61f54674 RQ	275	#ifdef CONFIG_OF
	276	static const struct of_device_id ti_pipe3_id_table[];
	277	#endif
	278
a70143bb	279	static int ti_pipe3_probe(struct platform_device *pdev)
57f6ce07	280	{
a70143bb KVA	281	struct ti_pipe3 *phy;
	282	struct phy *generic_phy;
	283	struct phy_provider *phy_provider;
918ee0d2 RQ	284	struct resource *res;
	285	struct device_node *node = pdev->dev.of_node;
	286	struct device_node *control_node;
	287	struct platform_device *control_pdev;
61f54674	288	const struct of_device_id *match;
918ee0d2	289
61f54674 RQ	290	match = of_match_device(of_match_ptr(ti_pipe3_id_table), &pdev->dev);
61f54674 RQ	291	if (!match)
918ee0d2	292	return -EINVAL;
57f6ce07 KVA	293
	294	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
	295	if (!phy) {
a70143bb	296	dev_err(&pdev->dev, "unable to alloc mem for TI PIPE3 PHY\n");
57f6ce07 KVA	297	return -ENOMEM;
	298	}
	299
61f54674 RQ	300	phy->dpll_map = (struct pipe3_dpll_map *)match->data;
	301	if (!phy->dpll_map) {
	302	dev_err(&pdev->dev, "no DPLL data\n");
	303	return -EINVAL;
	304	}
	305
57f6ce07	306	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
862421da SK	307	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	308	if (IS_ERR(phy->pll_ctrl_base))
	309	return PTR_ERR(phy->pll_ctrl_base);
57f6ce07 KVA	310
	311	phy->dev = &pdev->dev;
	312
9c7f0443 RQ	313	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
	314
	315	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
	316	if (IS_ERR(phy->wkupclk)) {
	317	dev_err(&pdev->dev, "unable to get wkupclk\n");
	318	return PTR_ERR(phy->wkupclk);
	319	}
	320
	321	phy->refclk = devm_clk_get(phy->dev, "refclk");
	322	if (IS_ERR(phy->refclk)) {
	323	dev_err(&pdev->dev, "unable to get refclk\n");
	324	return PTR_ERR(phy->refclk);
	325	}
	326	} else {
	327	phy->wkupclk = ERR_PTR(-ENODEV);
	328	phy->refclk = ERR_PTR(-ENODEV);
57f6ce07	329	}
57f6ce07	330
1562864f	331	phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
57f6ce07	332	if (IS_ERR(phy->sys_clk)) {
1562864f	333	dev_err(&pdev->dev, "unable to get sysclk\n");
57f6ce07 KVA	334	return -EINVAL;
	335	}
	336
918ee0d2 RQ	337	control_node = of_parse_phandle(node, "ctrl-module", 0);
	338	if (!control_node) {
	339	dev_err(&pdev->dev, "Failed to get control device phandle\n");
	340	return -EINVAL;
57f6ce07	341	}
a70143bb	342
918ee0d2 RQ	343	control_pdev = of_find_device_by_node(control_node);
	344	if (!control_pdev) {
	345	dev_err(&pdev->dev, "Failed to get control device\n");
	346	return -EINVAL;
	347	}
	348
	349	phy->control_dev = &control_pdev->dev;
57f6ce07	350
14da699b	351	omap_control_phy_power(phy->control_dev, 0);
57f6ce07 KVA	352
57f6ce07 KVA	353	platform_set_drvdata(pdev, phy);
57f6ce07	354	pm_runtime_enable(phy->dev);
a70143bb KVA	355
	356	generic_phy = devm_phy_create(phy->dev, &ops, NULL);
	357	if (IS_ERR(generic_phy))
	358	return PTR_ERR(generic_phy);
	359
	360	phy_set_drvdata(generic_phy, phy);
	361	phy_provider = devm_of_phy_provider_register(phy->dev,
	362	of_phy_simple_xlate);
	363	if (IS_ERR(phy_provider))
	364	return PTR_ERR(phy_provider);
	365
57f6ce07 KVA	366	pm_runtime_get(&pdev->dev);
	367
	368	return 0;
	369	}
	370
a70143bb	371	static int ti_pipe3_remove(struct platform_device *pdev)
57f6ce07	372	{
57f6ce07 KVA	373	if (!pm_runtime_suspended(&pdev->dev))
	374	pm_runtime_put(&pdev->dev);
	375	pm_runtime_disable(&pdev->dev);
	376
	377	return 0;
	378	}
	379
	380	#ifdef CONFIG_PM_RUNTIME
	381
a70143bb	382	static int ti_pipe3_runtime_suspend(struct device *dev)
57f6ce07	383	{
a70143bb	384	struct ti_pipe3 *phy = dev_get_drvdata(dev);
57f6ce07	385
1562864f RQ	386	if (!IS_ERR(phy->wkupclk))
	387	clk_disable_unprepare(phy->wkupclk);
	388	if (!IS_ERR(phy->refclk))
	389	clk_disable_unprepare(phy->refclk);
57f6ce07 KVA	390
	391	return 0;
	392	}
	393
a70143bb	394	static int ti_pipe3_runtime_resume(struct device *dev)
57f6ce07 KVA	395	{
57f6ce07 KVA	396	u32 ret = 0;
a70143bb	397	struct ti_pipe3 *phy = dev_get_drvdata(dev);
57f6ce07	398
1562864f RQ	399	if (!IS_ERR(phy->refclk)) {
	400	ret = clk_prepare_enable(phy->refclk);
	401	if (ret) {
	402	dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
	403	goto err1;
	404	}
57f6ce07 KVA	405	}
57f6ce07 KVA	406
1562864f RQ	407	if (!IS_ERR(phy->wkupclk)) {
	408	ret = clk_prepare_enable(phy->wkupclk);
	409	if (ret) {
	410	dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
	411	goto err2;
	412	}
57f6ce07 KVA	413	}
	414
	415	return 0;
	416
	417	err2:
1562864f RQ	418	if (!IS_ERR(phy->refclk))
1562864f RQ	419	clk_disable_unprepare(phy->refclk);
57f6ce07 KVA	420
	421	err1:
	422	return ret;
	423	}
	424
a70143bb KVA	425	static const struct dev_pm_ops ti_pipe3_pm_ops = {
	426	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
	427	ti_pipe3_runtime_resume, NULL)
57f6ce07 KVA	428	};
57f6ce07 KVA	429
a70143bb	430	#define DEV_PM_OPS (&ti_pipe3_pm_ops)
57f6ce07 KVA	431	#else
	432	#define DEV_PM_OPS NULL
	433	#endif
	434
	435	#ifdef CONFIG_OF
a70143bb	436	static const struct of_device_id ti_pipe3_id_table[] = {
61f54674 RQ	437	{
	438	.compatible = "ti,phy-usb3",
	439	.data = dpll_map_usb,
	440	},
	441	{
	442	.compatible = "ti,omap-usb3",
	443	.data = dpll_map_usb,
	444	},
	445	{
	446	.compatible = "ti,phy-pipe3-sata",
	447	.data = dpll_map_sata,
	448	},
57f6ce07 KVA	449	{}
57f6ce07 KVA	450	};
a70143bb	451	MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
57f6ce07 KVA	452	#endif
57f6ce07 KVA	453
a70143bb KVA	454	static struct platform_driver ti_pipe3_driver = {
	455	.probe = ti_pipe3_probe,
	456	.remove = ti_pipe3_remove,
57f6ce07	457	.driver = {
a70143bb	458	.name = "ti-pipe3",
57f6ce07 KVA	459	.owner = THIS_MODULE,
57f6ce07 KVA	460	.pm = DEV_PM_OPS,
a70143bb	461	.of_match_table = of_match_ptr(ti_pipe3_id_table),
57f6ce07 KVA	462	},
	463	};
	464
a70143bb	465	module_platform_driver(ti_pipe3_driver);
57f6ce07	466
a70143bb	467	MODULE_ALIAS("platform: ti_pipe3");
57f6ce07	468	MODULE_AUTHOR("Texas Instruments Inc.");
a70143bb	469	MODULE_DESCRIPTION("TI PIPE3 phy driver");
57f6ce07	470	MODULE_LICENSE("GPL v2");