[deliverable/linux.git] / drivers / phy / phy-ti-pipe3.c

/*
 * phy-ti-pipe3 - PIPE3 PHY driver.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/phy/phy.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#define	PLL_STATUS		0x00000004
#define	PLL_GO			0x00000008
#define	PLL_CONFIGURATION1	0x0000000C
#define	PLL_CONFIGURATION2	0x00000010
#define	PLL_CONFIGURATION3	0x00000014
#define	PLL_CONFIGURATION4	0x00000020

#define	PLL_REGM_MASK		0x001FFE00
#define	PLL_REGM_SHIFT		0x9
#define	PLL_REGM_F_MASK		0x0003FFFF
#define	PLL_REGM_F_SHIFT	0x0
#define	PLL_REGN_MASK		0x000001FE
#define	PLL_REGN_SHIFT		0x1
#define	PLL_SELFREQDCO_MASK	0x0000000E
#define	PLL_SELFREQDCO_SHIFT	0x1
#define	PLL_SD_MASK		0x0003FC00
#define	PLL_SD_SHIFT		10
#define	SET_PLL_GO		0x1
#define PLL_LDOPWDN		BIT(15)
#define PLL_TICOPWDN		BIT(16)
#define	PLL_LOCK		0x2
#define	PLL_IDLE		0x1

#define SATA_PLL_SOFT_RESET	BIT(18)

/*
 * This is an Empirical value that works, need to confirm the actual
 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 */
#define PLL_IDLE_TIME	100	/* in milliseconds */
#define PLL_LOCK_TIME	100	/* in milliseconds */

struct pipe3_dpll_params {
	u16	m;
	u8	n;
	u8	freq:3;
	u8	sd;
	u32	mf;
};

struct pipe3_dpll_map {
	unsigned long rate;
	struct pipe3_dpll_params params;
};

struct ti_pipe3 {
	void __iomem		*pll_ctrl_base;
	struct device		*dev;
	struct device		*control_dev;
	struct clk		*wkupclk;
	struct clk		*sys_clk;
	struct clk		*refclk;
	struct clk		*div_clk;
	struct pipe3_dpll_map	*dpll_map;
	struct regmap		*dpll_reset_syscon; /* ctrl. reg. acces */
	unsigned int		dpll_reset_reg; /* reg. index within syscon */
	bool			sata_refclk_enabled;
};

static struct pipe3_dpll_map dpll_map_usb[] = {
	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
	{ },					/* Terminator */
};

static struct pipe3_dpll_map dpll_map_sata[] = {
	{12000000, {1000, 7, 4, 6, 0} },	/* 12 MHz */
	{16800000, {714, 7, 4, 6, 0} },		/* 16.8 MHz */
	{19200000, {625, 7, 4, 6, 0} },		/* 19.2 MHz */
	{20000000, {600, 7, 4, 6, 0} },		/* 20 MHz */
	{26000000, {461, 7, 4, 6, 0} },		/* 26 MHz */
	{38400000, {312, 7, 4, 6, 0} },		/* 38.4 MHz */
	{ },					/* Terminator */
};

static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
{
	return __raw_readl(addr + offset);
}

static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	u32 data)
{
	__raw_writel(data, addr + offset);
}

static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
	unsigned long rate;
	struct pipe3_dpll_map *dpll_map = phy->dpll_map;

	rate = clk_get_rate(phy->sys_clk);

	for (; dpll_map->rate; dpll_map++) {
		if (rate == dpll_map->rate)
			return &dpll_map->params;
	}

	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);

	return NULL;
}

static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);

static int ti_pipe3_power_off(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 0);

	return 0;
}

static int ti_pipe3_power_on(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 1);

	return 0;
}

static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
	u32		val;
	unsigned long	timeout;

	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if (val & PLL_LOCK)
			return 0;
	} while (!time_after(jiffies, timeout));

	dev_err(phy->dev, "DPLL failed to lock\n");
	return -EBUSY;
}

static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
	u32			val;
	struct pipe3_dpll_params *dpll_params;

	dpll_params = ti_pipe3_get_dpll_params(phy);
	if (!dpll_params)
		return -EINVAL;

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGN_MASK;
	val |= dpll_params->n << PLL_REGN_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val &= ~PLL_SELFREQDCO_MASK;
	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGM_MASK;
	val |= dpll_params->m << PLL_REGM_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
	val &= ~PLL_REGM_F_MASK;
	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
	val &= ~PLL_SD_MASK;
	val |= dpll_params->sd << PLL_SD_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);

	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);

	return ti_pipe3_dpll_wait_lock(phy);
}

static int ti_pipe3_init(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	int ret = 0;

	ti_pipe3_enable_clocks(phy);
	/*
	 * Set pcie_pcs register to 0x96 for proper functioning of phy
	 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	 * 18-1804.
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
		omap_control_pcie_pcs(phy->control_dev, 0x96);
		return 0;
	}

	/* Bring it out of IDLE if it is IDLE */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	if (val & PLL_IDLE) {
		val &= ~PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
		ret = ti_pipe3_dpll_wait_lock(phy);
	}

	/* Program the DPLL only if not locked */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	if (!(val & PLL_LOCK))
		if (ti_pipe3_dpll_program(phy))
			return -EINVAL;

	return ret;
}

static int ti_pipe3_exit(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	unsigned long timeout;

	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
	 * due to Errata i783
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
	    !phy->dpll_reset_syscon)
		return 0;

	/* PCIe doesn't have internal DPLL */
	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
		/* Put DPLL in IDLE mode */
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
		val |= PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

		/* wait for LDO and Oscillator to power down */
		timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
		do {
			cpu_relax();
			val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
			if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
				break;
		} while (!time_after(jiffies, timeout));

		if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
			dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
				val);
			return -EBUSY;
		}
	}

	/* i783: SATA needs control bit toggle after PLL unlock */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
				   SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
		regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
				   SATA_PLL_SOFT_RESET, 0);
	}

	ti_pipe3_disable_clocks(phy);

	return 0;
}
static const struct phy_ops ops = {
	.init		= ti_pipe3_init,
	.exit		= ti_pipe3_exit,
	.power_on	= ti_pipe3_power_on,
	.power_off	= ti_pipe3_power_off,
	.owner		= THIS_MODULE,
};

static const struct of_device_id ti_pipe3_id_table[];

static int ti_pipe3_probe(struct platform_device *pdev)
{
	struct ti_pipe3 *phy;
	struct phy *generic_phy;
	struct phy_provider *phy_provider;
	struct resource *res;
	struct device_node *node = pdev->dev.of_node;
	struct device_node *control_node;
	struct platform_device *control_pdev;
	const struct of_device_id *match;
	struct clk *clk;
	struct device *dev = &pdev->dev;

	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	phy->dev		= dev;

	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
		match = of_match_device(ti_pipe3_id_table, dev);
		if (!match)
			return -EINVAL;

		phy->dpll_map = (struct pipe3_dpll_map *)match->data;
		if (!phy->dpll_map) {
			dev_err(dev, "no DPLL data\n");
			return -EINVAL;
		}

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						   "pll_ctrl");
		phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
		if (IS_ERR(phy->pll_ctrl_base))
			return PTR_ERR(phy->pll_ctrl_base);

		phy->sys_clk = devm_clk_get(dev, "sysclk");
		if (IS_ERR(phy->sys_clk)) {
			dev_err(dev, "unable to get sysclk\n");
			return -EINVAL;
		}
	}

	phy->refclk = devm_clk_get(dev, "refclk");
	if (IS_ERR(phy->refclk)) {
		dev_err(dev, "unable to get refclk\n");
		/* older DTBs have missing refclk in SATA PHY
		 * so don't bail out in case of SATA PHY.
		 */
		if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
			return PTR_ERR(phy->refclk);
	}

	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
		phy->wkupclk = devm_clk_get(dev, "wkupclk");
		if (IS_ERR(phy->wkupclk)) {
			dev_err(dev, "unable to get wkupclk\n");
			return PTR_ERR(phy->wkupclk);
		}
	} else {
		phy->wkupclk = ERR_PTR(-ENODEV);
		phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
							"syscon-pllreset");
		if (IS_ERR(phy->dpll_reset_syscon)) {
			dev_info(dev,
				 "can't get syscon-pllreset, sata dpll won't idle\n");
			phy->dpll_reset_syscon = NULL;
		} else {
			if (of_property_read_u32_index(node,
						       "syscon-pllreset", 1,
						       &phy->dpll_reset_reg)) {
				dev_err(dev,
					"couldn't get pllreset reg. offset\n");
				return -EINVAL;
			}
		}
	}

	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {

		clk = devm_clk_get(dev, "dpll_ref");
		if (IS_ERR(clk)) {
			dev_err(dev, "unable to get dpll ref clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 1500000000);

		clk = devm_clk_get(dev, "dpll_ref_m2");
		if (IS_ERR(clk)) {
			dev_err(dev, "unable to get dpll ref m2 clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		clk = devm_clk_get(dev, "phy-div");
		if (IS_ERR(clk)) {
			dev_err(dev, "unable to get phy-div clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		phy->div_clk = devm_clk_get(dev, "div-clk");
		if (IS_ERR(phy->div_clk)) {
			dev_err(dev, "unable to get div-clk\n");
			return PTR_ERR(phy->div_clk);
		}
	} else {
		phy->div_clk = ERR_PTR(-ENODEV);
	}

	control_node = of_parse_phandle(node, "ctrl-module", 0);
	if (!control_node) {
		dev_err(dev, "Failed to get control device phandle\n");
		return -EINVAL;
	}

	control_pdev = of_find_device_by_node(control_node);
	if (!control_pdev) {
		dev_err(dev, "Failed to get control device\n");
		return -EINVAL;
	}

	phy->control_dev = &control_pdev->dev;

	omap_control_phy_power(phy->control_dev, 0);

	platform_set_drvdata(pdev, phy);
	pm_runtime_enable(dev);

	/*
	 * Prevent auto-disable of refclk for SATA PHY due to Errata i783
	 */
	if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
		if (!IS_ERR(phy->refclk)) {
			clk_prepare_enable(phy->refclk);
			phy->sata_refclk_enabled = true;
		}
	}

	generic_phy = devm_phy_create(dev, NULL, &ops);
	if (IS_ERR(generic_phy))
		return PTR_ERR(generic_phy);

	phy_set_drvdata(generic_phy, phy);
	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(phy_provider))
		return PTR_ERR(phy_provider);

	return 0;
}

static int ti_pipe3_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);

	return 0;
}

static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
{
	int ret = 0;

	if (!IS_ERR(phy->refclk)) {
		ret = clk_prepare_enable(phy->refclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
			return ret;
		}
	}

	if (!IS_ERR(phy->wkupclk)) {
		ret = clk_prepare_enable(phy->wkupclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
			goto disable_refclk;
		}
	}

	if (!IS_ERR(phy->div_clk)) {
		ret = clk_prepare_enable(phy->div_clk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
			goto disable_wkupclk;
		}
	}

	return 0;

disable_wkupclk:
	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);

disable_refclk:
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

	return ret;
}

static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
{
	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);
	if (!IS_ERR(phy->refclk)) {
		clk_disable_unprepare(phy->refclk);
		/*
		 * SATA refclk needs an additional disable as we left it
		 * on in probe to avoid Errata i783
		 */
		if (phy->sata_refclk_enabled) {
			clk_disable_unprepare(phy->refclk);
			phy->sata_refclk_enabled = false;
		}
	}

	if (!IS_ERR(phy->div_clk))
		clk_disable_unprepare(phy->div_clk);
}

static const struct of_device_id ti_pipe3_id_table[] = {
	{
		.compatible = "ti,phy-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,omap-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,phy-pipe3-sata",
		.data = dpll_map_sata,
	},
	{
		.compatible = "ti,phy-pipe3-pcie",
	},
	{}
};
MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);

static struct platform_driver ti_pipe3_driver = {
	.probe		= ti_pipe3_probe,
	.remove		= ti_pipe3_remove,
	.driver		= {
		.name	= "ti-pipe3",
		.of_match_table = ti_pipe3_id_table,
	},
};

module_platform_driver(ti_pipe3_driver);

MODULE_ALIAS("platform:ti_pipe3");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("TI PIPE3 phy driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
57f6ce07	1	/*
a70143bb	2	* phy-ti-pipe3 - PIPE3 PHY driver.
57f6ce07 KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
a70143bb	22	#include <linux/phy/phy.h>
57f6ce07 KVA	23	#include <linux/of.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
a70143bb	26	#include <linux/io.h>
57f6ce07 KVA	27	#include <linux/pm_runtime.h>
57f6ce07 KVA	28	#include <linux/delay.h>
14da699b	29	#include <linux/phy/omap_control_phy.h>
918ee0d2	30	#include <linux/of_platform.h>
c934b361 RQ	31	#include <linux/mfd/syscon.h>
c934b361 RQ	32	#include <linux/regmap.h>
57f6ce07	33
57f6ce07 KVA	34	#define PLL_STATUS 0x00000004
	35	#define PLL_GO 0x00000008
	36	#define PLL_CONFIGURATION1 0x0000000C
	37	#define PLL_CONFIGURATION2 0x00000010
	38	#define PLL_CONFIGURATION3 0x00000014
	39	#define PLL_CONFIGURATION4 0x00000020
	40
	41	#define PLL_REGM_MASK 0x001FFE00
	42	#define PLL_REGM_SHIFT 0x9
	43	#define PLL_REGM_F_MASK 0x0003FFFF
	44	#define PLL_REGM_F_SHIFT 0x0
	45	#define PLL_REGN_MASK 0x000001FE
	46	#define PLL_REGN_SHIFT 0x1
	47	#define PLL_SELFREQDCO_MASK 0x0000000E
	48	#define PLL_SELFREQDCO_SHIFT 0x1
	49	#define PLL_SD_MASK 0x0003FC00
1562864f	50	#define PLL_SD_SHIFT 10
57f6ce07	51	#define SET_PLL_GO 0x1
629138db RQ	52	#define PLL_LDOPWDN BIT(15)
629138db RQ	53	#define PLL_TICOPWDN BIT(16)
57f6ce07 KVA	54	#define PLL_LOCK 0x2
	55	#define PLL_IDLE 0x1
	56
c934b361 RQ	57	#define SATA_PLL_SOFT_RESET BIT(18)
c934b361 RQ	58
57f6ce07 KVA	59	/*
57f6ce07 KVA	60	* This is an Empirical value that works, need to confirm the actual
a70143bb KVA	61	* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
a70143bb KVA	62	* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
57f6ce07	63	*/
629138db RQ	64	#define PLL_IDLE_TIME 100 /* in milliseconds */
629138db RQ	65	#define PLL_LOCK_TIME 100 /* in milliseconds */
57f6ce07	66
a70143bb KVA	67	struct pipe3_dpll_params {
	68	u16 m;
	69	u8 n;
	70	u8 freq:3;
	71	u8 sd;
	72	u32 mf;
	73	};
	74
61f54674 RQ	75	struct pipe3_dpll_map {
	76	unsigned long rate;
	77	struct pipe3_dpll_params params;
	78	};
	79
a70143bb KVA	80	struct ti_pipe3 {
	81	void __iomem *pll_ctrl_base;
	82	struct device *dev;
	83	struct device *control_dev;
	84	struct clk *wkupclk;
	85	struct clk *sys_clk;
1562864f	86	struct clk *refclk;
99bbd48c	87	struct clk *div_clk;
61f54674	88	struct pipe3_dpll_map *dpll_map;
c934b361 RQ	89	struct regmap dpll_reset_syscon; / ctrl. reg. acces */
	90	unsigned int dpll_reset_reg; /* reg. index within syscon */
	91	bool sata_refclk_enabled;
a70143bb KVA	92	};
a70143bb KVA	93
61f54674	94	static struct pipe3_dpll_map dpll_map_usb[] = {
519c6013 RQ	95	{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
	96	{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
	97	{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
	98	{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
	99	{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
	100	{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
61f54674 RQ	101	{ }, /* Terminator */
	102	};
	103
	104	static struct pipe3_dpll_map dpll_map_sata[] = {
	105	{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
	106	{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
	107	{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
	108	{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
	109	{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
	110	{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
	111	{ }, /* Terminator */
57f6ce07 KVA	112	};
57f6ce07 KVA	113
a70143bb KVA	114	static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
	115	{
	116	return __raw_readl(addr + offset);
	117	}
	118
	119	static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	120	u32 data)
	121	{
	122	__raw_writel(data, addr + offset);
	123	}
	124
61f54674	125	static struct pipe3_dpll_params ti_pipe3_get_dpll_params(struct ti_pipe3 phy)
519c6013	126	{
61f54674 RQ	127	unsigned long rate;
61f54674 RQ	128	struct pipe3_dpll_map *dpll_map = phy->dpll_map;
519c6013	129
61f54674 RQ	130	rate = clk_get_rate(phy->sys_clk);
	131
	132	for (; dpll_map->rate; dpll_map++) {
	133	if (rate == dpll_map->rate)
	134	return &dpll_map->params;
519c6013 RQ	135	}
519c6013 RQ	136
61f54674 RQ	137	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
61f54674 RQ	138
1b97be8c	139	return NULL;
519c6013 RQ	140	}
519c6013 RQ	141
0a0830fe RQ	142	static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
	143	static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
	144
a70143bb KVA	145	static int ti_pipe3_power_off(struct phy *x)
	146	{
	147	struct ti_pipe3 *phy = phy_get_drvdata(x);
a70143bb	148
14da699b	149	omap_control_phy_power(phy->control_dev, 0);
a70143bb KVA	150
	151	return 0;
	152	}
	153
	154	static int ti_pipe3_power_on(struct phy *x)
57f6ce07	155	{
a70143bb	156	struct ti_pipe3 *phy = phy_get_drvdata(x);
57f6ce07	157
629138db	158	omap_control_phy_power(phy->control_dev, 1);
57f6ce07 KVA	159
	160	return 0;
	161	}
	162
629138db	163	static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
57f6ce07 KVA	164	{
	165	u32 val;
	166	unsigned long timeout;
	167
629138db	168	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
57f6ce07	169	do {
629138db	170	cpu_relax();
a70143bb	171	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
57f6ce07	172	if (val & PLL_LOCK)
a5e5d3c0	173	return 0;
629138db RQ	174	} while (!time_after(jiffies, timeout));
629138db RQ	175
a5e5d3c0 AL	176	dev_err(phy->dev, "DPLL failed to lock\n");
a5e5d3c0 AL	177	return -EBUSY;
57f6ce07 KVA	178	}
57f6ce07 KVA	179
629138db	180	static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
57f6ce07 KVA	181	{
57f6ce07 KVA	182	u32 val;
a70143bb	183	struct pipe3_dpll_params *dpll_params;
57f6ce07	184
61f54674 RQ	185	dpll_params = ti_pipe3_get_dpll_params(phy);
61f54674 RQ	186	if (!dpll_params)
57f6ce07	187	return -EINVAL;
57f6ce07	188
a70143bb	189	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	190	val &= ~PLL_REGN_MASK;
519c6013	191	val \|= dpll_params->n << PLL_REGN_SHIFT;
a70143bb	192	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	193
a70143bb	194	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
57f6ce07	195	val &= ~PLL_SELFREQDCO_MASK;
519c6013	196	val \|= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
a70143bb	197	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
57f6ce07	198
a70143bb	199	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	200	val &= ~PLL_REGM_MASK;
519c6013	201	val \|= dpll_params->m << PLL_REGM_SHIFT;
a70143bb	202	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	203
a70143bb	204	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
57f6ce07	205	val &= ~PLL_REGM_F_MASK;
519c6013	206	val \|= dpll_params->mf << PLL_REGM_F_SHIFT;
a70143bb	207	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
57f6ce07	208
a70143bb	209	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
57f6ce07	210	val &= ~PLL_SD_MASK;
519c6013	211	val \|= dpll_params->sd << PLL_SD_SHIFT;
a70143bb	212	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
57f6ce07	213
629138db	214	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
57f6ce07	215
629138db	216	return ti_pipe3_dpll_wait_lock(phy);
57f6ce07 KVA	217	}
57f6ce07 KVA	218
a70143bb	219	static int ti_pipe3_init(struct phy *x)
57f6ce07	220	{
a70143bb	221	struct ti_pipe3 *phy = phy_get_drvdata(x);
629138db RQ	222	u32 val;
629138db RQ	223	int ret = 0;
519c6013	224
0a0830fe	225	ti_pipe3_enable_clocks(phy);
0bc09f9c V	226	/*
	227	* Set pcie_pcs register to 0x96 for proper functioning of phy
	228	* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	229	* 18-1804.
	230	*/
f0e2cf7b	231	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
0bc09f9c	232	omap_control_pcie_pcs(phy->control_dev, 0x96);
99bbd48c	233	return 0;
f0e2cf7b	234	}
99bbd48c	235
629138db RQ	236	/* Bring it out of IDLE if it is IDLE */
	237	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	238	if (val & PLL_IDLE) {
	239	val &= ~PLL_IDLE;
	240	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	241	ret = ti_pipe3_dpll_wait_lock(phy);
	242	}
57f6ce07	243
629138db RQ	244	/* Program the DPLL only if not locked */
	245	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	246	if (!(val & PLL_LOCK))
	247	if (ti_pipe3_dpll_program(phy))
	248	return -EINVAL;
57f6ce07	249
629138db	250	return ret;
57f6ce07 KVA	251	}
57f6ce07 KVA	252
629138db RQ	253	static int ti_pipe3_exit(struct phy *x)
	254	{
	255	struct ti_pipe3 *phy = phy_get_drvdata(x);
	256	u32 val;
	257	unsigned long timeout;
	258
c934b361 RQ	259	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
	260	* due to Errata i783
	261	*/
	262	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
	263	!phy->dpll_reset_syscon)
56042e4e RQ	264	return 0;
56042e4e RQ	265
0a0830fe RQ	266	/* PCIe doesn't have internal DPLL */
	267	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
	268	/* Put DPLL in IDLE mode */
	269	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	270	val \|= PLL_IDLE;
	271	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
629138db	272
0a0830fe RQ	273	/* wait for LDO and Oscillator to power down */
	274	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	275	do {
	276	cpu_relax();
	277	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	278	if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
	279	break;
	280	} while (!time_after(jiffies, timeout));
	281
	282	if (!(val & PLL_TICOPWDN) \|\| !(val & PLL_LDOPWDN)) {
	283	dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
	284	val);
	285	return -EBUSY;
	286	}
629138db RQ	287	}
629138db RQ	288
c934b361 RQ	289	/* i783: SATA needs control bit toggle after PLL unlock */
	290	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
	291	regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
	292	SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
	293	regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
	294	SATA_PLL_SOFT_RESET, 0);
	295	}
	296
0a0830fe RQ	297	ti_pipe3_disable_clocks(phy);
0a0830fe RQ	298
629138db RQ	299	return 0;
629138db RQ	300	}
4a9e5ca1	301	static const struct phy_ops ops = {
a70143bb	302	.init = ti_pipe3_init,
629138db	303	.exit = ti_pipe3_exit,
a70143bb KVA	304	.power_on = ti_pipe3_power_on,
	305	.power_off = ti_pipe3_power_off,
	306	.owner = THIS_MODULE,
	307	};
	308
61f54674	309	static const struct of_device_id ti_pipe3_id_table[];
61f54674	310
a70143bb	311	static int ti_pipe3_probe(struct platform_device *pdev)
57f6ce07	312	{
a70143bb KVA	313	struct ti_pipe3 *phy;
	314	struct phy *generic_phy;
	315	struct phy_provider *phy_provider;
918ee0d2 RQ	316	struct resource *res;
	317	struct device_node *node = pdev->dev.of_node;
	318	struct device_node *control_node;
	319	struct platform_device *control_pdev;
61f54674	320	const struct of_device_id *match;
99bbd48c	321	struct clk *clk;
d65ff52e	322	struct device *dev = &pdev->dev;
57f6ce07	323
d65ff52e	324	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
3a4cfcbb	325	if (!phy)
57f6ce07	326	return -ENOMEM;
3a4cfcbb	327
d65ff52e	328	phy->dev = dev;
57f6ce07	329
99bbd48c	330	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
d65ff52e	331	match = of_match_device(ti_pipe3_id_table, dev);
99bbd48c KVA	332	if (!match)
99bbd48c KVA	333	return -EINVAL;
61f54674	334
99bbd48c KVA	335	phy->dpll_map = (struct pipe3_dpll_map *)match->data;
99bbd48c KVA	336	if (!phy->dpll_map) {
d65ff52e	337	dev_err(dev, "no DPLL data\n");
99bbd48c KVA	338	return -EINVAL;
99bbd48c KVA	339	}
57f6ce07	340
99bbd48c KVA	341	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
99bbd48c KVA	342	"pll_ctrl");
d65ff52e	343	phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
99bbd48c KVA	344	if (IS_ERR(phy->pll_ctrl_base))
99bbd48c KVA	345	return PTR_ERR(phy->pll_ctrl_base);
57f6ce07	346
d65ff52e	347	phy->sys_clk = devm_clk_get(dev, "sysclk");
99bbd48c	348	if (IS_ERR(phy->sys_clk)) {
d65ff52e	349	dev_err(dev, "unable to get sysclk\n");
99bbd48c KVA	350	return -EINVAL;
	351	}
	352	}
9c7f0443	353
d65ff52e	354	phy->refclk = devm_clk_get(dev, "refclk");
7f33912d	355	if (IS_ERR(phy->refclk)) {
d65ff52e	356	dev_err(dev, "unable to get refclk\n");
7f33912d RQ	357	/* older DTBs have missing refclk in SATA PHY
	358	* so don't bail out in case of SATA PHY.
	359	*/
	360	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
	361	return PTR_ERR(phy->refclk);
	362	}
	363
99bbd48c	364	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
d65ff52e	365	phy->wkupclk = devm_clk_get(dev, "wkupclk");
9c7f0443	366	if (IS_ERR(phy->wkupclk)) {
d65ff52e	367	dev_err(dev, "unable to get wkupclk\n");
9c7f0443 RQ	368	return PTR_ERR(phy->wkupclk);
9c7f0443 RQ	369	}
9c7f0443 RQ	370	} else {
9c7f0443 RQ	371	phy->wkupclk = ERR_PTR(-ENODEV);
c934b361 RQ	372	phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
	373	"syscon-pllreset");
	374	if (IS_ERR(phy->dpll_reset_syscon)) {
d65ff52e	375	dev_info(dev,
c934b361 RQ	376	"can't get syscon-pllreset, sata dpll won't idle\n");
	377	phy->dpll_reset_syscon = NULL;
	378	} else {
	379	if (of_property_read_u32_index(node,
	380	"syscon-pllreset", 1,
	381	&phy->dpll_reset_reg)) {
d65ff52e	382	dev_err(dev,
c934b361 RQ	383	"couldn't get pllreset reg. offset\n");
	384	return -EINVAL;
	385	}
	386	}
57f6ce07	387	}
57f6ce07	388
99bbd48c	389	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
99bbd48c	390
d65ff52e	391	clk = devm_clk_get(dev, "dpll_ref");
99bbd48c	392	if (IS_ERR(clk)) {
d65ff52e	393	dev_err(dev, "unable to get dpll ref clk\n");
99bbd48c KVA	394	return PTR_ERR(clk);
	395	}
	396	clk_set_rate(clk, 1500000000);
	397
d65ff52e	398	clk = devm_clk_get(dev, "dpll_ref_m2");
99bbd48c	399	if (IS_ERR(clk)) {
d65ff52e	400	dev_err(dev, "unable to get dpll ref m2 clk\n");
99bbd48c KVA	401	return PTR_ERR(clk);
	402	}
	403	clk_set_rate(clk, 100000000);
	404
d65ff52e	405	clk = devm_clk_get(dev, "phy-div");
99bbd48c	406	if (IS_ERR(clk)) {
d65ff52e	407	dev_err(dev, "unable to get phy-div clk\n");
99bbd48c KVA	408	return PTR_ERR(clk);
	409	}
	410	clk_set_rate(clk, 100000000);
	411
d65ff52e	412	phy->div_clk = devm_clk_get(dev, "div-clk");
99bbd48c	413	if (IS_ERR(phy->div_clk)) {
d65ff52e	414	dev_err(dev, "unable to get div-clk\n");
99bbd48c KVA	415	return PTR_ERR(phy->div_clk);
	416	}
	417	} else {
	418	phy->div_clk = ERR_PTR(-ENODEV);
57f6ce07 KVA	419	}
57f6ce07 KVA	420
918ee0d2 RQ	421	control_node = of_parse_phandle(node, "ctrl-module", 0);
918ee0d2 RQ	422	if (!control_node) {
d65ff52e	423	dev_err(dev, "Failed to get control device phandle\n");
918ee0d2	424	return -EINVAL;
57f6ce07	425	}
a70143bb	426
918ee0d2 RQ	427	control_pdev = of_find_device_by_node(control_node);
918ee0d2 RQ	428	if (!control_pdev) {
d65ff52e	429	dev_err(dev, "Failed to get control device\n");
918ee0d2 RQ	430	return -EINVAL;
	431	}
	432
	433	phy->control_dev = &control_pdev->dev;
57f6ce07	434
14da699b	435	omap_control_phy_power(phy->control_dev, 0);
57f6ce07 KVA	436
57f6ce07 KVA	437	platform_set_drvdata(pdev, phy);
d65ff52e	438	pm_runtime_enable(dev);
c934b361 RQ	439
	440	/*
	441	* Prevent auto-disable of refclk for SATA PHY due to Errata i783
	442	*/
	443	if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
	444	if (!IS_ERR(phy->refclk)) {
0a0830fe	445	clk_prepare_enable(phy->refclk);
c934b361 RQ	446	phy->sata_refclk_enabled = true;
	447	}
	448	}
a70143bb	449
d65ff52e	450	generic_phy = devm_phy_create(dev, NULL, &ops);
a70143bb KVA	451	if (IS_ERR(generic_phy))
	452	return PTR_ERR(generic_phy);
	453
	454	phy_set_drvdata(generic_phy, phy);
d65ff52e	455	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
a70143bb KVA	456	if (IS_ERR(phy_provider))
	457	return PTR_ERR(phy_provider);
	458
57f6ce07 KVA	459	return 0;
	460	}
	461
a70143bb	462	static int ti_pipe3_remove(struct platform_device *pdev)
57f6ce07	463	{
57f6ce07 KVA	464	pm_runtime_disable(&pdev->dev);
	465
	466	return 0;
	467	}
	468
0a0830fe	469	static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
7f33912d	470	{
0a0830fe	471	int ret = 0;
7f33912d	472
0a0830fe	473	if (!IS_ERR(phy->refclk)) {
7f33912d RQ	474	ret = clk_prepare_enable(phy->refclk);
	475	if (ret) {
	476	dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
	477	return ret;
	478	}
7f33912d RQ	479	}
7f33912d RQ	480
1562864f RQ	481	if (!IS_ERR(phy->wkupclk)) {
	482	ret = clk_prepare_enable(phy->wkupclk);
	483	if (ret) {
	484	dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
0a0830fe	485	goto disable_refclk;
1562864f	486	}
57f6ce07 KVA	487	}
57f6ce07 KVA	488
99bbd48c KVA	489	if (!IS_ERR(phy->div_clk)) {
	490	ret = clk_prepare_enable(phy->div_clk);
	491	if (ret) {
	492	dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
0a0830fe	493	goto disable_wkupclk;
99bbd48c KVA	494	}
99bbd48c KVA	495	}
6e738432	496
57f6ce07 KVA	497	return 0;
57f6ce07 KVA	498
0a0830fe	499	disable_wkupclk:
99bbd48c KVA	500	if (!IS_ERR(phy->wkupclk))
	501	clk_disable_unprepare(phy->wkupclk);
	502
0a0830fe	503	disable_refclk:
1562864f RQ	504	if (!IS_ERR(phy->refclk))
1562864f RQ	505	clk_disable_unprepare(phy->refclk);
57f6ce07	506
6e738432 RQ	507	return ret;
	508	}
	509
	510	static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
	511	{
6e738432 RQ	512	if (!IS_ERR(phy->wkupclk))
6e738432 RQ	513	clk_disable_unprepare(phy->wkupclk);
c934b361	514	if (!IS_ERR(phy->refclk)) {
0a0830fe	515	clk_disable_unprepare(phy->refclk);
c934b361 RQ	516	/*
	517	* SATA refclk needs an additional disable as we left it
	518	* on in probe to avoid Errata i783
	519	*/
	520	if (phy->sata_refclk_enabled) {
	521	clk_disable_unprepare(phy->refclk);
	522	phy->sata_refclk_enabled = false;
	523	}
	524	}
	525
6e738432 RQ	526	if (!IS_ERR(phy->div_clk))
6e738432 RQ	527	clk_disable_unprepare(phy->div_clk);
6e738432 RQ	528	}
6e738432 RQ	529
a70143bb	530	static const struct of_device_id ti_pipe3_id_table[] = {
61f54674 RQ	531	{
	532	.compatible = "ti,phy-usb3",
	533	.data = dpll_map_usb,
	534	},
	535	{
	536	.compatible = "ti,omap-usb3",
	537	.data = dpll_map_usb,
	538	},
	539	{
	540	.compatible = "ti,phy-pipe3-sata",
	541	.data = dpll_map_sata,
	542	},
99bbd48c KVA	543	{
	544	.compatible = "ti,phy-pipe3-pcie",
	545	},
57f6ce07 KVA	546	{}
57f6ce07 KVA	547	};
a70143bb	548	MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
57f6ce07	549
a70143bb KVA	550	static struct platform_driver ti_pipe3_driver = {
	551	.probe = ti_pipe3_probe,
	552	.remove = ti_pipe3_remove,
57f6ce07	553	.driver = {
a70143bb	554	.name = "ti-pipe3",
298fe56e	555	.of_match_table = ti_pipe3_id_table,
57f6ce07 KVA	556	},
	557	};
	558
a70143bb	559	module_platform_driver(ti_pipe3_driver);
57f6ce07	560
dd64ad38	561	MODULE_ALIAS("platform:ti_pipe3");
57f6ce07	562	MODULE_AUTHOR("Texas Instruments Inc.");
a70143bb	563	MODULE_DESCRIPTION("TI PIPE3 phy driver");
57f6ce07	564	MODULE_LICENSE("GPL v2");