projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9612327c | 1 | /* |
| f23556d3 PG |
2 | * Freescale imx6ul pinctrl driver |
| 3 | * | |
| 4 | * Author: Anson Huang <Anson.Huang@freescale.com> | |
| 9612327c FL |
5 | * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #include <linux/err.h> | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/io.h> | |
| 9612327c FL |
15 | #include <linux/of.h> |
| 16 | #include <linux/of_device.h> | |
| 17 | #include <linux/pinctrl/pinctrl.h> | |
| 18 | ||
| 19 | #include "pinctrl-imx.h" | |
| 20 | ||
| 21 | enum imx6ul_pads { | |
| 22 | MX6UL_PAD_RESERVE0 = 0, | |
| 23 | MX6UL_PAD_RESERVE1 = 1, | |
| 24 | MX6UL_PAD_RESERVE2 = 2, | |
| 25 | MX6UL_PAD_RESERVE3 = 3, | |
| 26 | MX6UL_PAD_RESERVE4 = 4, | |
| 27 | MX6UL_PAD_RESERVE5 = 5, | |
| 28 | MX6UL_PAD_RESERVE6 = 6, | |
| 29 | MX6UL_PAD_RESERVE7 = 7, | |
| 30 | MX6UL_PAD_RESERVE8 = 8, | |
| 31 | MX6UL_PAD_RESERVE9 = 9, | |
| 32 | MX6UL_PAD_RESERVE10 = 10, | |
| 33 | MX6UL_PAD_SNVS_TAMPER4 = 11, | |
| 34 | MX6UL_PAD_RESERVE12 = 12, | |
| 35 | MX6UL_PAD_RESERVE13 = 13, | |
| 36 | MX6UL_PAD_RESERVE14 = 14, | |
| 37 | MX6UL_PAD_RESERVE15 = 15, | |
| 38 | MX6UL_PAD_RESERVE16 = 16, | |
| 39 | MX6UL_PAD_JTAG_MOD = 17, | |
| 40 | MX6UL_PAD_JTAG_TMS = 18, | |
| 41 | MX6UL_PAD_JTAG_TDO = 19, | |
| 42 | MX6UL_PAD_JTAG_TDI = 20, | |
| 43 | MX6UL_PAD_JTAG_TCK = 21, | |
| 44 | MX6UL_PAD_JTAG_TRST_B = 22, | |
| 45 | MX6UL_PAD_GPIO1_IO00 = 23, | |
| 46 | MX6UL_PAD_GPIO1_IO01 = 24, | |
| 47 | MX6UL_PAD_GPIO1_IO02 = 25, | |
| 48 | MX6UL_PAD_GPIO1_IO03 = 26, | |
| 49 | MX6UL_PAD_GPIO1_IO04 = 27, | |
| 50 | MX6UL_PAD_GPIO1_IO05 = 28, | |
| 51 | MX6UL_PAD_GPIO1_IO06 = 29, | |
| 52 | MX6UL_PAD_GPIO1_IO07 = 30, | |
| 53 | MX6UL_PAD_GPIO1_IO08 = 31, | |
| 54 | MX6UL_PAD_GPIO1_IO09 = 32, | |
| 55 | MX6UL_PAD_UART1_TX_DATA = 33, | |
| 56 | MX6UL_PAD_UART1_RX_DATA = 34, | |
| 57 | MX6UL_PAD_UART1_CTS_B = 35, | |
| 58 | MX6UL_PAD_UART1_RTS_B = 36, | |
| 59 | MX6UL_PAD_UART2_TX_DATA = 37, | |
| 60 | MX6UL_PAD_UART2_RX_DATA = 38, | |
| 61 | MX6UL_PAD_UART2_CTS_B = 39, | |
| 62 | MX6UL_PAD_UART2_RTS_B = 40, | |
| 63 | MX6UL_PAD_UART3_TX_DATA = 41, | |
| 64 | MX6UL_PAD_UART3_RX_DATA = 42, | |
| 65 | MX6UL_PAD_UART3_CTS_B = 43, | |
| 66 | MX6UL_PAD_UART3_RTS_B = 44, | |
| 67 | MX6UL_PAD_UART4_TX_DATA = 45, | |
| 68 | MX6UL_PAD_UART4_RX_DATA = 46, | |
| 69 | MX6UL_PAD_UART5_TX_DATA = 47, | |
| 70 | MX6UL_PAD_UART5_RX_DATA = 48, | |
| 71 | MX6UL_PAD_ENET1_RX_DATA0 = 49, | |
| 72 | MX6UL_PAD_ENET1_RX_DATA1 = 50, | |
| 73 | MX6UL_PAD_ENET1_RX_EN = 51, | |
| 74 | MX6UL_PAD_ENET1_TX_DATA0 = 52, | |
| 75 | MX6UL_PAD_ENET1_TX_DATA1 = 53, | |
| 76 | MX6UL_PAD_ENET1_TX_EN = 54, | |
| 77 | MX6UL_PAD_ENET1_TX_CLK = 55, | |
| 78 | MX6UL_PAD_ENET1_RX_ER = 56, | |
| 79 | MX6UL_PAD_ENET2_RX_DATA0 = 57, | |
| 80 | MX6UL_PAD_ENET2_RX_DATA1 = 58, | |
| 81 | MX6UL_PAD_ENET2_RX_EN = 59, | |
| 82 | MX6UL_PAD_ENET2_TX_DATA0 = 60, | |
| 83 | MX6UL_PAD_ENET2_TX_DATA1 = 61, | |
| 84 | MX6UL_PAD_ENET2_TX_EN = 62, | |
| 85 | MX6UL_PAD_ENET2_TX_CLK = 63, | |
| 86 | MX6UL_PAD_ENET2_RX_ER = 64, | |
| 87 | MX6UL_PAD_LCD_CLK = 65, | |
| 88 | MX6UL_PAD_LCD_ENABLE = 66, | |
| 89 | MX6UL_PAD_LCD_HSYNC = 67, | |
| 90 | MX6UL_PAD_LCD_VSYNC = 68, | |
| 91 | MX6UL_PAD_LCD_RESET = 69, | |
| 92 | MX6UL_PAD_LCD_DATA00 = 70, | |
| 93 | MX6UL_PAD_LCD_DATA01 = 71, | |
| 94 | MX6UL_PAD_LCD_DATA02 = 72, | |
| 95 | MX6UL_PAD_LCD_DATA03 = 73, | |
| 96 | MX6UL_PAD_LCD_DATA04 = 74, | |
| 97 | MX6UL_PAD_LCD_DATA05 = 75, | |
| 98 | MX6UL_PAD_LCD_DATA06 = 76, | |
| 99 | MX6UL_PAD_LCD_DATA07 = 77, | |
| 100 | MX6UL_PAD_LCD_DATA08 = 78, | |
| 101 | MX6UL_PAD_LCD_DATA09 = 79, | |
| 102 | MX6UL_PAD_LCD_DATA10 = 80, | |
| 103 | MX6UL_PAD_LCD_DATA11 = 81, | |
| 104 | MX6UL_PAD_LCD_DATA12 = 82, | |
| 105 | MX6UL_PAD_LCD_DATA13 = 83, | |
| 106 | MX6UL_PAD_LCD_DATA14 = 84, | |
| 107 | MX6UL_PAD_LCD_DATA15 = 85, | |
| 108 | MX6UL_PAD_LCD_DATA16 = 86, | |
| 109 | MX6UL_PAD_LCD_DATA17 = 87, | |
| 110 | MX6UL_PAD_LCD_DATA18 = 88, | |
| 111 | MX6UL_PAD_LCD_DATA19 = 89, | |
| 112 | MX6UL_PAD_LCD_DATA20 = 90, | |
| 113 | MX6UL_PAD_LCD_DATA21 = 91, | |
| 114 | MX6UL_PAD_LCD_DATA22 = 92, | |
| 115 | MX6UL_PAD_LCD_DATA23 = 93, | |
| 116 | MX6UL_PAD_NAND_RE_B = 94, | |
| 117 | MX6UL_PAD_NAND_WE_B = 95, | |
| 118 | MX6UL_PAD_NAND_DATA00 = 96, | |
| 119 | MX6UL_PAD_NAND_DATA01 = 97, | |
| 120 | MX6UL_PAD_NAND_DATA02 = 98, | |
| 121 | MX6UL_PAD_NAND_DATA03 = 99, | |
| 122 | MX6UL_PAD_NAND_DATA04 = 100, | |
| 123 | MX6UL_PAD_NAND_DATA05 = 101, | |
| 124 | MX6UL_PAD_NAND_DATA06 = 102, | |
| 125 | MX6UL_PAD_NAND_DATA07 = 103, | |
| 126 | MX6UL_PAD_NAND_ALE = 104, | |
| 127 | MX6UL_PAD_NAND_WP_B = 105, | |
| 128 | MX6UL_PAD_NAND_READY_B = 106, | |
| 129 | MX6UL_PAD_NAND_CE0_B = 107, | |
| 130 | MX6UL_PAD_NAND_CE1_B = 108, | |
| 131 | MX6UL_PAD_NAND_CLE = 109, | |
| 132 | MX6UL_PAD_NAND_DQS = 110, | |
| 133 | MX6UL_PAD_SD1_CMD = 111, | |
| 134 | MX6UL_PAD_SD1_CLK = 112, | |
| 135 | MX6UL_PAD_SD1_DATA0 = 113, | |
| 136 | MX6UL_PAD_SD1_DATA1 = 114, | |
| 137 | MX6UL_PAD_SD1_DATA2 = 115, | |
| 138 | MX6UL_PAD_SD1_DATA3 = 116, | |
| 139 | MX6UL_PAD_CSI_MCLK = 117, | |
| 140 | MX6UL_PAD_CSI_PIXCLK = 118, | |
| 141 | MX6UL_PAD_CSI_VSYNC = 119, | |
| 142 | MX6UL_PAD_CSI_HSYNC = 120, | |
| 143 | MX6UL_PAD_CSI_DATA00 = 121, | |
| 144 | MX6UL_PAD_CSI_DATA01 = 122, | |
| 145 | MX6UL_PAD_CSI_DATA02 = 123, | |
| 146 | MX6UL_PAD_CSI_DATA03 = 124, | |
| 147 | MX6UL_PAD_CSI_DATA04 = 125, | |
| 148 | MX6UL_PAD_CSI_DATA05 = 126, | |
| 149 | MX6UL_PAD_CSI_DATA06 = 127, | |
| 150 | MX6UL_PAD_CSI_DATA07 = 128, | |
| 151 | }; | |
| 152 | ||
| 153 | /* Pad names for the pinmux subsystem */ | |
| 154 | static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { | |
| 155 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), | |
| 156 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1), | |
| 157 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2), | |
| 158 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3), | |
| 159 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4), | |
| 160 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5), | |
| 161 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6), | |
| 162 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7), | |
| 163 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8), | |
| 164 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9), | |
| 165 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10), | |
| 166 | IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4), | |
| 167 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12), | |
| 168 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13), | |
| 169 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14), | |
| 170 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15), | |
| 171 | IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16), | |
| 172 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD), | |
| 173 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS), | |
| 174 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO), | |
| 175 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI), | |
| 176 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK), | |
| 177 | IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B), | |
| 178 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00), | |
| 179 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01), | |
| 180 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02), | |
| 181 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03), | |
| 182 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04), | |
| 183 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05), | |
| 184 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06), | |
| 185 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07), | |
| 186 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08), | |
| 187 | IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09), | |
| 188 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA), | |
| 189 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA), | |
| 190 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B), | |
| 191 | IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B), | |
| 192 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA), | |
| 193 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA), | |
| 194 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B), | |
| 195 | IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B), | |
| 196 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA), | |
| 197 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA), | |
| 198 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B), | |
| 199 | IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B), | |
| 200 | IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA), | |
| 201 | IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA), | |
| 202 | IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA), | |
| 203 | IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA), | |
| 204 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0), | |
| 205 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1), | |
| 206 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN), | |
| 207 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0), | |
| 208 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1), | |
| 209 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN), | |
| 210 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK), | |
| 211 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER), | |
| 212 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0), | |
| 213 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1), | |
| 214 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN), | |
| 215 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0), | |
| 216 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1), | |
| 217 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN), | |
| 218 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK), | |
| 219 | IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER), | |
| 220 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK), | |
| 221 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE), | |
| 222 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC), | |
| 223 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC), | |
| 224 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET), | |
| 225 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00), | |
| 226 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01), | |
| 227 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02), | |
| 228 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03), | |
| 229 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04), | |
| 230 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05), | |
| 231 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06), | |
| 232 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07), | |
| 233 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08), | |
| 234 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09), | |
| 235 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10), | |
| 236 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11), | |
| 237 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12), | |
| 238 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13), | |
| 239 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14), | |
| 240 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15), | |
| 241 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16), | |
| 242 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17), | |
| 243 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18), | |
| 244 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19), | |
| 245 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20), | |
| 246 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21), | |
| 247 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22), | |
| 248 | IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23), | |
| 249 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B), | |
| 250 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B), | |
| 251 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00), | |
| 252 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01), | |
| 253 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02), | |
| 254 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03), | |
| 255 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04), | |
| 256 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05), | |
| 257 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06), | |
| 258 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07), | |
| 259 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE), | |
| 260 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B), | |
| 261 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B), | |
| 262 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B), | |
| 263 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B), | |
| 264 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE), | |
| 265 | IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS), | |
| 266 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD), | |
| 267 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK), | |
| 268 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0), | |
| 269 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1), | |
| 270 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2), | |
| 271 | IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3), | |
| 272 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK), | |
| 273 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK), | |
| 274 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC), | |
| 275 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC), | |
| 276 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00), | |
| 277 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01), | |
| 278 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02), | |
| 279 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03), | |
| 280 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04), | |
| 281 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05), | |
| 282 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06), | |
| 283 | IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), | |
| 284 | }; | |
| 285 | ||
| 286 | static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { | |
| 287 | .pins = imx6ul_pinctrl_pads, | |
| 288 | .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), | |
| 8626ada8 | 289 | .gpr_compatible = "fsl,imx6ul-iomuxc-gpr", |
| 9612327c FL |
290 | }; |
| 291 | ||
| 292 | static struct of_device_id imx6ul_pinctrl_of_match[] = { | |
| 293 | { .compatible = "fsl,imx6ul-iomuxc", }, | |
| 294 | { /* sentinel */ } | |
| 295 | }; | |
| 296 | ||
| 297 | static int imx6ul_pinctrl_probe(struct platform_device *pdev) | |
| 298 | { | |
| 299 | return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); | |
| 300 | } | |
| 301 | ||
| 302 | static struct platform_driver imx6ul_pinctrl_driver = { | |
| 303 | .driver = { | |
| 304 | .name = "imx6ul-pinctrl", | |
| 9612327c FL |
305 | .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), |
| 306 | }, | |
| 307 | .probe = imx6ul_pinctrl_probe, | |
| 9612327c FL |
308 | }; |
| 309 | ||
| 310 | static int __init imx6ul_pinctrl_init(void) | |
| 311 | { | |
| 312 | return platform_driver_register(&imx6ul_pinctrl_driver); | |
| 313 | } | |
| 314 | arch_initcall(imx6ul_pinctrl_init); |