[deliverable/linux.git] / drivers / pinctrl / freescale / pinctrl-imx7d.c

/*
 * Freescale imx7d pinctrl driver
 *
 * Author: Anson Huang <Anson.Huang@freescale.com>
 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-imx.h"

enum imx7d_pads {
	MX7D_PAD_RESERVE0 = 0,
	MX7D_PAD_RESERVE1 = 1,
	MX7D_PAD_RESERVE2 = 2,
	MX7D_PAD_RESERVE3 = 3,
	MX7D_PAD_RESERVE4 = 4,
	MX7D_PAD_GPIO1_IO08 = 5,
	MX7D_PAD_GPIO1_IO09 = 6,
	MX7D_PAD_GPIO1_IO10 = 7,
	MX7D_PAD_GPIO1_IO11 = 8,
	MX7D_PAD_GPIO1_IO12 = 9,
	MX7D_PAD_GPIO1_IO13 = 10,
	MX7D_PAD_GPIO1_IO14 = 11,
	MX7D_PAD_GPIO1_IO15 = 12,
	MX7D_PAD_EPDC_DATA00 = 13,
	MX7D_PAD_EPDC_DATA01 = 14,
	MX7D_PAD_EPDC_DATA02 = 15,
	MX7D_PAD_EPDC_DATA03 = 16,
	MX7D_PAD_EPDC_DATA04 = 17,
	MX7D_PAD_EPDC_DATA05 = 18,
	MX7D_PAD_EPDC_DATA06 = 19,
	MX7D_PAD_EPDC_DATA07 = 20,
	MX7D_PAD_EPDC_DATA08 = 21,
	MX7D_PAD_EPDC_DATA09 = 22,
	MX7D_PAD_EPDC_DATA10 = 23,
	MX7D_PAD_EPDC_DATA11 = 24,
	MX7D_PAD_EPDC_DATA12 = 25,
	MX7D_PAD_EPDC_DATA13 = 26,
	MX7D_PAD_EPDC_DATA14 = 27,
	MX7D_PAD_EPDC_DATA15 = 28,
	MX7D_PAD_EPDC_SDCLK = 29,
	MX7D_PAD_EPDC_SDLE = 30,
	MX7D_PAD_EPDC_SDOE = 31,
	MX7D_PAD_EPDC_SDSHR = 32,
	MX7D_PAD_EPDC_SDCE0 = 33,
	MX7D_PAD_EPDC_SDCE1 = 34,
	MX7D_PAD_EPDC_SDCE2 = 35,
	MX7D_PAD_EPDC_SDCE3 = 36,
	MX7D_PAD_EPDC_GDCLK = 37,
	MX7D_PAD_EPDC_GDOE = 38,
	MX7D_PAD_EPDC_GDRL = 39,
	MX7D_PAD_EPDC_GDSP = 40,
	MX7D_PAD_EPDC_BDR0 = 41,
	MX7D_PAD_EPDC_BDR1 = 42,
	MX7D_PAD_EPDC_PWR_COM = 43,
	MX7D_PAD_EPDC_PWR_STAT = 44,
	MX7D_PAD_LCD_CLK = 45,
	MX7D_PAD_LCD_ENABLE = 46,
	MX7D_PAD_LCD_HSYNC = 47,
	MX7D_PAD_LCD_VSYNC = 48,
	MX7D_PAD_LCD_RESET = 49,
	MX7D_PAD_LCD_DATA00 = 50,
	MX7D_PAD_LCD_DATA01 = 51,
	MX7D_PAD_LCD_DATA02 = 52,
	MX7D_PAD_LCD_DATA03 = 53,
	MX7D_PAD_LCD_DATA04 = 54,
	MX7D_PAD_LCD_DATA05 = 55,
	MX7D_PAD_LCD_DATA06 = 56,
	MX7D_PAD_LCD_DATA07 = 57,
	MX7D_PAD_LCD_DATA08 = 58,
	MX7D_PAD_LCD_DATA09 = 59,
	MX7D_PAD_LCD_DATA10 = 60,
	MX7D_PAD_LCD_DATA11 = 61,
	MX7D_PAD_LCD_DATA12 = 62,
	MX7D_PAD_LCD_DATA13 = 63,
	MX7D_PAD_LCD_DATA14 = 64,
	MX7D_PAD_LCD_DATA15 = 65,
	MX7D_PAD_LCD_DATA16 = 66,
	MX7D_PAD_LCD_DATA17 = 67,
	MX7D_PAD_LCD_DATA18 = 68,
	MX7D_PAD_LCD_DATA19 = 69,
	MX7D_PAD_LCD_DATA20 = 70,
	MX7D_PAD_LCD_DATA21 = 71,
	MX7D_PAD_LCD_DATA22 = 72,
	MX7D_PAD_LCD_DATA23 = 73,
	MX7D_PAD_UART1_RX_DATA = 74,
	MX7D_PAD_UART1_TX_DATA = 75,
	MX7D_PAD_UART2_RX_DATA = 76,
	MX7D_PAD_UART2_TX_DATA = 77,
	MX7D_PAD_UART3_RX_DATA = 78,
	MX7D_PAD_UART3_TX_DATA = 79,
	MX7D_PAD_UART3_RTS_B = 80,
	MX7D_PAD_UART3_CTS_B = 81,
	MX7D_PAD_I2C1_SCL = 82,
	MX7D_PAD_I2C1_SDA = 83,
	MX7D_PAD_I2C2_SCL = 84,
	MX7D_PAD_I2C2_SDA = 85,
	MX7D_PAD_I2C3_SCL = 86,
	MX7D_PAD_I2C3_SDA = 87,
	MX7D_PAD_I2C4_SCL = 88,
	MX7D_PAD_I2C4_SDA = 89,
	MX7D_PAD_ECSPI1_SCLK = 90,
	MX7D_PAD_ECSPI1_MOSI = 91,
	MX7D_PAD_ECSPI1_MISO = 92,
	MX7D_PAD_ECSPI1_SS0 = 93,
	MX7D_PAD_ECSPI2_SCLK = 94,
	MX7D_PAD_ECSPI2_MOSI = 95,
	MX7D_PAD_ECSPI2_MISO = 96,
	MX7D_PAD_ECSPI2_SS0 = 97,
	MX7D_PAD_SD1_CD_B = 98,
	MX7D_PAD_SD1_WP = 99,
	MX7D_PAD_SD1_RESET_B = 100,
	MX7D_PAD_SD1_CLK = 101,
	MX7D_PAD_SD1_CMD = 102,
	MX7D_PAD_SD1_DATA0 = 103,
	MX7D_PAD_SD1_DATA1 = 104,
	MX7D_PAD_SD1_DATA2 = 105,
	MX7D_PAD_SD1_DATA3 = 106,
	MX7D_PAD_SD2_CD_B = 107,
	MX7D_PAD_SD2_WP = 108,
	MX7D_PAD_SD2_RESET_B = 109,
	MX7D_PAD_SD2_CLK = 110,
	MX7D_PAD_SD2_CMD = 111,
	MX7D_PAD_SD2_DATA0 = 112,
	MX7D_PAD_SD2_DATA1 = 113,
	MX7D_PAD_SD2_DATA2 = 114,
	MX7D_PAD_SD2_DATA3 = 115,
	MX7D_PAD_SD3_CLK = 116,
	MX7D_PAD_SD3_CMD = 117,
	MX7D_PAD_SD3_DATA0 = 118,
	MX7D_PAD_SD3_DATA1 = 119,
	MX7D_PAD_SD3_DATA2 = 120,
	MX7D_PAD_SD3_DATA3 = 121,
	MX7D_PAD_SD3_DATA4 = 122,
	MX7D_PAD_SD3_DATA5 = 123,
	MX7D_PAD_SD3_DATA6 = 124,
	MX7D_PAD_SD3_DATA7 = 125,
	MX7D_PAD_SD3_STROBE = 126,
	MX7D_PAD_SD3_RESET_B = 127,
	MX7D_PAD_SAI1_RX_DATA = 128,
	MX7D_PAD_SAI1_TX_BCLK = 129,
	MX7D_PAD_SAI1_TX_SYNC = 130,
	MX7D_PAD_SAI1_TX_DATA = 131,
	MX7D_PAD_SAI1_RX_SYNC = 132,
	MX7D_PAD_SAI1_RX_BCLK = 133,
	MX7D_PAD_SAI1_MCLK = 134,
	MX7D_PAD_SAI2_TX_SYNC = 135,
	MX7D_PAD_SAI2_TX_BCLK = 136,
	MX7D_PAD_SAI2_RX_DATA = 137,
	MX7D_PAD_SAI2_TX_DATA = 138,
	MX7D_PAD_ENET1_RGMII_RD0 = 139,
	MX7D_PAD_ENET1_RGMII_RD1 = 140,
	MX7D_PAD_ENET1_RGMII_RD2 = 141,
	MX7D_PAD_ENET1_RGMII_RD3 = 142,
	MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
	MX7D_PAD_ENET1_RGMII_RXC = 144,
	MX7D_PAD_ENET1_RGMII_TD0 = 145,
	MX7D_PAD_ENET1_RGMII_TD1 = 146,
	MX7D_PAD_ENET1_RGMII_TD2 = 147,
	MX7D_PAD_ENET1_RGMII_TD3 = 148,
	MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
	MX7D_PAD_ENET1_RGMII_TXC = 150,
	MX7D_PAD_ENET1_TX_CLK = 151,
	MX7D_PAD_ENET1_RX_CLK = 152,
	MX7D_PAD_ENET1_CRS = 153,
	MX7D_PAD_ENET1_COL = 154,
};

enum imx7d_lpsr_pads {
	MX7D_PAD_GPIO1_IO00 = 0,
	MX7D_PAD_GPIO1_IO01 = 1,
	MX7D_PAD_GPIO1_IO02 = 2,
	MX7D_PAD_GPIO1_IO03 = 3,
	MX7D_PAD_GPIO1_IO04 = 4,
	MX7D_PAD_GPIO1_IO05 = 5,
	MX7D_PAD_GPIO1_IO06 = 6,
	MX7D_PAD_GPIO1_IO07 = 7,
};

/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
	IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
	IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
	IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
};

/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
};

static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
	.pins = imx7d_pinctrl_pads,
	.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
	.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
};

static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
	.pins = imx7d_lpsr_pinctrl_pads,
	.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
	.flags = ZERO_OFFSET_VALID,
};

static struct of_device_id imx7d_pinctrl_of_match[] = {
	{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
	{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
	{ /* sentinel */ }
};

static int imx7d_pinctrl_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct imx_pinctrl_soc_info *pinctrl_info;

	match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev);

	if (!match)
		return -ENODEV;

	pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;

	return imx_pinctrl_probe(pdev, pinctrl_info);
}

static struct platform_driver imx7d_pinctrl_driver = {
	.driver = {
		.name = "imx7d-pinctrl",
		.of_match_table = of_match_ptr(imx7d_pinctrl_of_match),
	},
	.probe = imx7d_pinctrl_probe,
};

static int __init imx7d_pinctrl_init(void)
{
	return platform_driver_register(&imx7d_pinctrl_driver);
}
arch_initcall(imx7d_pinctrl_init);
Commit	Line	Data
c30024a6	1	/*
bc21f488 PG	2	* Freescale imx7d pinctrl driver
	3	*
	4	* Author: Anson Huang <Anson.Huang@freescale.com>
c30024a6 FL	5	* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/err.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
c30024a6 FL	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/pinctrl/pinctrl.h>
	18
	19	#include "pinctrl-imx.h"
	20
	21	enum imx7d_pads {
	22	MX7D_PAD_RESERVE0 = 0,
	23	MX7D_PAD_RESERVE1 = 1,
	24	MX7D_PAD_RESERVE2 = 2,
	25	MX7D_PAD_RESERVE3 = 3,
	26	MX7D_PAD_RESERVE4 = 4,
	27	MX7D_PAD_GPIO1_IO08 = 5,
	28	MX7D_PAD_GPIO1_IO09 = 6,
	29	MX7D_PAD_GPIO1_IO10 = 7,
	30	MX7D_PAD_GPIO1_IO11 = 8,
	31	MX7D_PAD_GPIO1_IO12 = 9,
	32	MX7D_PAD_GPIO1_IO13 = 10,
	33	MX7D_PAD_GPIO1_IO14 = 11,
	34	MX7D_PAD_GPIO1_IO15 = 12,
	35	MX7D_PAD_EPDC_DATA00 = 13,
	36	MX7D_PAD_EPDC_DATA01 = 14,
	37	MX7D_PAD_EPDC_DATA02 = 15,
	38	MX7D_PAD_EPDC_DATA03 = 16,
	39	MX7D_PAD_EPDC_DATA04 = 17,
	40	MX7D_PAD_EPDC_DATA05 = 18,
	41	MX7D_PAD_EPDC_DATA06 = 19,
	42	MX7D_PAD_EPDC_DATA07 = 20,
	43	MX7D_PAD_EPDC_DATA08 = 21,
	44	MX7D_PAD_EPDC_DATA09 = 22,
	45	MX7D_PAD_EPDC_DATA10 = 23,
	46	MX7D_PAD_EPDC_DATA11 = 24,
	47	MX7D_PAD_EPDC_DATA12 = 25,
	48	MX7D_PAD_EPDC_DATA13 = 26,
	49	MX7D_PAD_EPDC_DATA14 = 27,
	50	MX7D_PAD_EPDC_DATA15 = 28,
	51	MX7D_PAD_EPDC_SDCLK = 29,
	52	MX7D_PAD_EPDC_SDLE = 30,
	53	MX7D_PAD_EPDC_SDOE = 31,
	54	MX7D_PAD_EPDC_SDSHR = 32,
	55	MX7D_PAD_EPDC_SDCE0 = 33,
	56	MX7D_PAD_EPDC_SDCE1 = 34,
	57	MX7D_PAD_EPDC_SDCE2 = 35,
	58	MX7D_PAD_EPDC_SDCE3 = 36,
	59	MX7D_PAD_EPDC_GDCLK = 37,
	60	MX7D_PAD_EPDC_GDOE = 38,
	61	MX7D_PAD_EPDC_GDRL = 39,
	62	MX7D_PAD_EPDC_GDSP = 40,
	63	MX7D_PAD_EPDC_BDR0 = 41,
	64	MX7D_PAD_EPDC_BDR1 = 42,
	65	MX7D_PAD_EPDC_PWR_COM = 43,
	66	MX7D_PAD_EPDC_PWR_STAT = 44,
	67	MX7D_PAD_LCD_CLK = 45,
	68	MX7D_PAD_LCD_ENABLE = 46,
	69	MX7D_PAD_LCD_HSYNC = 47,
	70	MX7D_PAD_LCD_VSYNC = 48,
	71	MX7D_PAD_LCD_RESET = 49,
	72	MX7D_PAD_LCD_DATA00 = 50,
	73	MX7D_PAD_LCD_DATA01 = 51,
	74	MX7D_PAD_LCD_DATA02 = 52,
	75	MX7D_PAD_LCD_DATA03 = 53,
	76	MX7D_PAD_LCD_DATA04 = 54,
	77	MX7D_PAD_LCD_DATA05 = 55,
	78	MX7D_PAD_LCD_DATA06 = 56,
79	MX7D_PAD_LCD_DATA07 = 57,
80	MX7D_PAD_LCD_DATA08 = 58,
81	MX7D_PAD_LCD_DATA09 = 59,
82	MX7D_PAD_LCD_DATA10 = 60,
83	MX7D_PAD_LCD_DATA11 = 61,
84	MX7D_PAD_LCD_DATA12 = 62,
85	MX7D_PAD_LCD_DATA13 = 63,
86	MX7D_PAD_LCD_DATA14 = 64,
87	MX7D_PAD_LCD_DATA15 = 65,
88	MX7D_PAD_LCD_DATA16 = 66,
89	MX7D_PAD_LCD_DATA17 = 67,
90	MX7D_PAD_LCD_DATA18 = 68,
91	MX7D_PAD_LCD_DATA19 = 69,
92	MX7D_PAD_LCD_DATA20 = 70,
93	MX7D_PAD_LCD_DATA21 = 71,
94	MX7D_PAD_LCD_DATA22 = 72,
95	MX7D_PAD_LCD_DATA23 = 73,
96	MX7D_PAD_UART1_RX_DATA = 74,
97	MX7D_PAD_UART1_TX_DATA = 75,
98	MX7D_PAD_UART2_RX_DATA = 76,
99	MX7D_PAD_UART2_TX_DATA = 77,
100	MX7D_PAD_UART3_RX_DATA = 78,
101	MX7D_PAD_UART3_TX_DATA = 79,
102	MX7D_PAD_UART3_RTS_B = 80,
103	MX7D_PAD_UART3_CTS_B = 81,
104	MX7D_PAD_I2C1_SCL = 82,
105	MX7D_PAD_I2C1_SDA = 83,
106	MX7D_PAD_I2C2_SCL = 84,
107	MX7D_PAD_I2C2_SDA = 85,
108	MX7D_PAD_I2C3_SCL = 86,
109	MX7D_PAD_I2C3_SDA = 87,
110	MX7D_PAD_I2C4_SCL = 88,
111	MX7D_PAD_I2C4_SDA = 89,
112	MX7D_PAD_ECSPI1_SCLK = 90,
113	MX7D_PAD_ECSPI1_MOSI = 91,
114	MX7D_PAD_ECSPI1_MISO = 92,
115	MX7D_PAD_ECSPI1_SS0 = 93,
116	MX7D_PAD_ECSPI2_SCLK = 94,
117	MX7D_PAD_ECSPI2_MOSI = 95,
118	MX7D_PAD_ECSPI2_MISO = 96,
119	MX7D_PAD_ECSPI2_SS0 = 97,
120	MX7D_PAD_SD1_CD_B = 98,
121	MX7D_PAD_SD1_WP = 99,
122	MX7D_PAD_SD1_RESET_B = 100,
123	MX7D_PAD_SD1_CLK = 101,
124	MX7D_PAD_SD1_CMD = 102,
125	MX7D_PAD_SD1_DATA0 = 103,
126	MX7D_PAD_SD1_DATA1 = 104,
127	MX7D_PAD_SD1_DATA2 = 105,
128	MX7D_PAD_SD1_DATA3 = 106,
129	MX7D_PAD_SD2_CD_B = 107,
130	MX7D_PAD_SD2_WP = 108,
131	MX7D_PAD_SD2_RESET_B = 109,
132	MX7D_PAD_SD2_CLK = 110,
133	MX7D_PAD_SD2_CMD = 111,
134	MX7D_PAD_SD2_DATA0 = 112,
135	MX7D_PAD_SD2_DATA1 = 113,
136	MX7D_PAD_SD2_DATA2 = 114,
137	MX7D_PAD_SD2_DATA3 = 115,
138	MX7D_PAD_SD3_CLK = 116,
139	MX7D_PAD_SD3_CMD = 117,
140	MX7D_PAD_SD3_DATA0 = 118,
141	MX7D_PAD_SD3_DATA1 = 119,
142	MX7D_PAD_SD3_DATA2 = 120,
143	MX7D_PAD_SD3_DATA3 = 121,
144	MX7D_PAD_SD3_DATA4 = 122,
145	MX7D_PAD_SD3_DATA5 = 123,
146	MX7D_PAD_SD3_DATA6 = 124,
147	MX7D_PAD_SD3_DATA7 = 125,
148	MX7D_PAD_SD3_STROBE = 126,
149	MX7D_PAD_SD3_RESET_B = 127,
150	MX7D_PAD_SAI1_RX_DATA = 128,
151	MX7D_PAD_SAI1_TX_BCLK = 129,
152	MX7D_PAD_SAI1_TX_SYNC = 130,
153	MX7D_PAD_SAI1_TX_DATA = 131,
154	MX7D_PAD_SAI1_RX_SYNC = 132,
155	MX7D_PAD_SAI1_RX_BCLK = 133,
156	MX7D_PAD_SAI1_MCLK = 134,
157	MX7D_PAD_SAI2_TX_SYNC = 135,
158	MX7D_PAD_SAI2_TX_BCLK = 136,
159	MX7D_PAD_SAI2_RX_DATA = 137,
160	MX7D_PAD_SAI2_TX_DATA = 138,
161	MX7D_PAD_ENET1_RGMII_RD0 = 139,
162	MX7D_PAD_ENET1_RGMII_RD1 = 140,
163	MX7D_PAD_ENET1_RGMII_RD2 = 141,
164	MX7D_PAD_ENET1_RGMII_RD3 = 142,
165	MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
166	MX7D_PAD_ENET1_RGMII_RXC = 144,
167	MX7D_PAD_ENET1_RGMII_TD0 = 145,
168	MX7D_PAD_ENET1_RGMII_TD1 = 146,
169	MX7D_PAD_ENET1_RGMII_TD2 = 147,
170	MX7D_PAD_ENET1_RGMII_TD3 = 148,
171	MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
172	MX7D_PAD_ENET1_RGMII_TXC = 150,
173	MX7D_PAD_ENET1_TX_CLK = 151,
174	MX7D_PAD_ENET1_RX_CLK = 152,
175	MX7D_PAD_ENET1_CRS = 153,
176	MX7D_PAD_ENET1_COL = 154,
177	};
178
978fd1d7 AA	179	enum imx7d_lpsr_pads {
	180	MX7D_PAD_GPIO1_IO00 = 0,
	181	MX7D_PAD_GPIO1_IO01 = 1,
	182	MX7D_PAD_GPIO1_IO02 = 2,
	183	MX7D_PAD_GPIO1_IO03 = 3,
	184	MX7D_PAD_GPIO1_IO04 = 4,
	185	MX7D_PAD_GPIO1_IO05 = 5,
	186	MX7D_PAD_GPIO1_IO06 = 6,
	187	MX7D_PAD_GPIO1_IO07 = 7,
	188	};
	189
c30024a6 FL	190	/* Pad names for the pinmux subsystem */
	191	static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
	192	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
	193	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
	194	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
	195	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
	196	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
	197	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
	198	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
	199	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
	200	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
	201	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
	202	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
	203	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
	204	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
	205	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
	206	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
	207	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
	208	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
	209	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
	210	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
	211	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
	212	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
	213	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
	214	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
	215	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
	216	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
	217	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
	218	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
	219	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
	220	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
	221	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
	222	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
	223	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
	224	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
	225	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
	226	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
	227	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
	228	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
	229	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
	230	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
	231	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
	232	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
	233	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
	234	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
	235	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
	236	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
	237	IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
	238	IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
	239	IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
	240	IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
	241	IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
	242	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
	243	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
	244	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
	245	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
	246	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
	247	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
	248	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
	249	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
	250	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
	251	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
	252	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
	253	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
254	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
255	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
256	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
257	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
258	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
259	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
260	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
261	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
262	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
263	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
264	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
265	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
266	IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
267	IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
268	IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
269	IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
270	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
271	IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
272	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
273	IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
274	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
275	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
276	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
277	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
278	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
279	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
280	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
281	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
282	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
283	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
284	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
285	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
286	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
287	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
288	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
289	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
290	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
291	IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
292	IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
293	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
294	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
295	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
296	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
297	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
298	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
299	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
300	IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
301	IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
302	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
303	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
304	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
305	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
306	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
307	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
308	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
309	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
310	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
311	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
312	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
313	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
314	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
315	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
316	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
317	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
318	IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
319	IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
320	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
321	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
322	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
323	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
324	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
325	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
326	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
327	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
328	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
329	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
330	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
331	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
332	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
333	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
334	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
335	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
336	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
337	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
338	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
339	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
340	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
341	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
342	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
343	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
344	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
345	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
346	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
347	};
348
978fd1d7 AA	349	/* Pad names for the pinmux subsystem */
	350	static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
	351	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
	352	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
	353	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
	354	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
	355	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
	356	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
	357	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
	358	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
	359	};
	360
c30024a6 FL	361	static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
	362	.pins = imx7d_pinctrl_pads,
	363	.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
8626ada8	364	.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
c30024a6 FL	365	};
c30024a6 FL	366
978fd1d7 AA	367	static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
	368	.pins = imx7d_lpsr_pinctrl_pads,
	369	.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
	370	.flags = ZERO_OFFSET_VALID,
	371	};
	372
c30024a6 FL	373	static struct of_device_id imx7d_pinctrl_of_match[] = {
c30024a6 FL	374	{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
978fd1d7	375	{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
c30024a6 FL	376	{ /* sentinel */ }
	377	};
	378
	379	static int imx7d_pinctrl_probe(struct platform_device *pdev)
	380	{
	381	const struct of_device_id *match;
	382	struct imx_pinctrl_soc_info *pinctrl_info;
	383
	384	match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev);
	385
	386	if (!match)
	387	return -ENODEV;
	388
	389	pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
	390
	391	return imx_pinctrl_probe(pdev, pinctrl_info);
	392	}
	393
	394	static struct platform_driver imx7d_pinctrl_driver = {
	395	.driver = {
	396	.name = "imx7d-pinctrl",
c30024a6 FL	397	.of_match_table = of_match_ptr(imx7d_pinctrl_of_match),
	398	},
	399	.probe = imx7d_pinctrl_probe,
c30024a6 FL	400	};
	401
	402	static int __init imx7d_pinctrl_init(void)
	403	{
	404	return platform_driver_register(&imx7d_pinctrl_driver);
	405	}
	406	arch_initcall(imx7d_pinctrl_init);