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a6df410d HY |
1 | /* |
2 | * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver. | |
3 | * Copyright (c) 2014 MediaTek Inc. | |
4 | * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/io.h> | |
17 | #include <linux/gpio.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_device.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/pinctrl/consumer.h> | |
24 | #include <linux/pinctrl/machine.h> | |
25 | #include <linux/pinctrl/pinconf.h> | |
26 | #include <linux/pinctrl/pinconf-generic.h> | |
27 | #include <linux/pinctrl/pinctrl.h> | |
28 | #include <linux/pinctrl/pinmux.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/bitops.h> | |
32 | #include <linux/regmap.h> | |
33 | #include <linux/mfd/syscon.h> | |
d9819eb9 | 34 | #include <linux/delay.h> |
30f010f5 | 35 | #include <linux/interrupt.h> |
58a5e1b6 | 36 | #include <linux/pm.h> |
a6df410d HY |
37 | #include <dt-bindings/pinctrl/mt65xx.h> |
38 | ||
39 | #include "../core.h" | |
40 | #include "../pinconf.h" | |
41 | #include "../pinctrl-utils.h" | |
42 | #include "pinctrl-mtk-common.h" | |
43 | ||
44 | #define MAX_GPIO_MODE_PER_REG 5 | |
45 | #define GPIO_MODE_BITS 3 | |
46 | ||
47 | static const char * const mtk_gpio_functions[] = { | |
48 | "func0", "func1", "func2", "func3", | |
49 | "func4", "func5", "func6", "func7", | |
50 | }; | |
51 | ||
52 | /* | |
53 | * There are two base address for pull related configuration | |
54 | * in mt8135, and different GPIO pins use different base address. | |
55 | * When pin number greater than type1_start and less than type1_end, | |
56 | * should use the second base address. | |
57 | */ | |
58 | static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, | |
59 | unsigned long pin) | |
60 | { | |
61 | if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) | |
62 | return pctl->regmap2; | |
63 | return pctl->regmap1; | |
64 | } | |
65 | ||
66 | static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) | |
67 | { | |
68 | /* Different SoC has different mask and port shift. */ | |
69 | return ((pin >> 4) & pctl->devdata->port_mask) | |
70 | << pctl->devdata->port_shf; | |
71 | } | |
72 | ||
73 | static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
74 | struct pinctrl_gpio_range *range, unsigned offset, | |
75 | bool input) | |
76 | { | |
77 | unsigned int reg_addr; | |
78 | unsigned int bit; | |
79 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
80 | ||
81 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; | |
82 | bit = BIT(offset & 0xf); | |
83 | ||
84 | if (input) | |
85 | /* Different SoC has different alignment offset. */ | |
86 | reg_addr = CLR_ADDR(reg_addr, pctl); | |
87 | else | |
88 | reg_addr = SET_ADDR(reg_addr, pctl); | |
89 | ||
90 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); | |
91 | return 0; | |
92 | } | |
93 | ||
94 | static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
95 | { | |
96 | unsigned int reg_addr; | |
97 | unsigned int bit; | |
98 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
99 | ||
100 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; | |
101 | bit = BIT(offset & 0xf); | |
102 | ||
103 | if (value) | |
104 | reg_addr = SET_ADDR(reg_addr, pctl); | |
105 | else | |
106 | reg_addr = CLR_ADDR(reg_addr, pctl); | |
107 | ||
108 | regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); | |
109 | } | |
110 | ||
25d76b21 HY |
111 | static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, |
112 | int value, enum pin_config_param arg) | |
a6df410d HY |
113 | { |
114 | unsigned int reg_addr, offset; | |
115 | unsigned int bit; | |
25d76b21 HY |
116 | |
117 | /** | |
118 | * Due to some soc are not support ies/smt config, add this special | |
119 | * control to handle it. | |
120 | */ | |
121 | if (!pctl->devdata->spec_ies_smt_set && | |
122 | pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && | |
123 | arg == PIN_CONFIG_INPUT_ENABLE) | |
124 | return -EINVAL; | |
125 | ||
126 | if (!pctl->devdata->spec_ies_smt_set && | |
127 | pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && | |
128 | arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) | |
129 | return -EINVAL; | |
30f010f5 HY |
130 | |
131 | /* | |
132 | * Due to some pins are irregular, their input enable and smt | |
25d76b21 | 133 | * control register are discontinuous, so we need this special handle. |
30f010f5 HY |
134 | */ |
135 | if (pctl->devdata->spec_ies_smt_set) { | |
25d76b21 HY |
136 | return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), |
137 | pin, pctl->devdata->port_align, value, arg); | |
30f010f5 | 138 | } |
a6df410d HY |
139 | |
140 | bit = BIT(pin & 0xf); | |
141 | ||
25d76b21 | 142 | if (arg == PIN_CONFIG_INPUT_ENABLE) |
a6df410d HY |
143 | offset = pctl->devdata->ies_offset; |
144 | else | |
145 | offset = pctl->devdata->smt_offset; | |
146 | ||
147 | if (value) | |
148 | reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); | |
149 | else | |
150 | reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); | |
151 | ||
152 | regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); | |
25d76b21 HY |
153 | return 0; |
154 | } | |
155 | ||
156 | int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, | |
157 | const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, | |
158 | unsigned int pin, unsigned char align, int value) | |
159 | { | |
160 | unsigned int i, reg_addr, bit; | |
161 | ||
162 | for (i = 0; i < info_num; i++) { | |
163 | if (pin >= ies_smt_infos[i].start && | |
164 | pin <= ies_smt_infos[i].end) { | |
165 | break; | |
166 | } | |
167 | } | |
168 | ||
169 | if (i == info_num) | |
170 | return -EINVAL; | |
171 | ||
172 | if (value) | |
173 | reg_addr = ies_smt_infos[i].offset + align; | |
174 | else | |
175 | reg_addr = ies_smt_infos[i].offset + (align << 1); | |
176 | ||
177 | bit = BIT(ies_smt_infos[i].bit); | |
178 | regmap_write(regmap, reg_addr, bit); | |
179 | return 0; | |
a6df410d HY |
180 | } |
181 | ||
182 | static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( | |
183 | struct mtk_pinctrl *pctl, unsigned long pin) { | |
184 | int i; | |
185 | ||
186 | for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) { | |
187 | const struct mtk_pin_drv_grp *pin_drv = | |
188 | pctl->devdata->pin_drv_grp + i; | |
189 | if (pin == pin_drv->pin) | |
190 | return pin_drv; | |
191 | } | |
192 | ||
193 | return NULL; | |
194 | } | |
195 | ||
196 | static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, | |
197 | unsigned int pin, unsigned char driving) | |
198 | { | |
199 | const struct mtk_pin_drv_grp *pin_drv; | |
200 | unsigned int val; | |
201 | unsigned int bits, mask, shift; | |
202 | const struct mtk_drv_group_desc *drv_grp; | |
203 | ||
204 | if (pin >= pctl->devdata->npins) | |
205 | return -EINVAL; | |
206 | ||
207 | pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin); | |
208 | if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls) | |
209 | return -EINVAL; | |
210 | ||
211 | drv_grp = pctl->devdata->grp_desc + pin_drv->grp; | |
212 | if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv | |
213 | && !(driving % drv_grp->step)) { | |
214 | val = driving / drv_grp->step - 1; | |
215 | bits = drv_grp->high_bit - drv_grp->low_bit + 1; | |
216 | mask = BIT(bits) - 1; | |
217 | shift = pin_drv->bit + drv_grp->low_bit; | |
218 | mask <<= shift; | |
219 | val <<= shift; | |
220 | return regmap_update_bits(mtk_get_regmap(pctl, pin), | |
221 | pin_drv->offset, mask, val); | |
222 | } | |
223 | ||
224 | return -EINVAL; | |
225 | } | |
226 | ||
e73fe271 YC |
227 | int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, |
228 | const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, | |
229 | unsigned int info_num, unsigned int pin, | |
230 | unsigned char align, bool isup, unsigned int r1r0) | |
231 | { | |
232 | unsigned int i; | |
233 | unsigned int reg_pupd, reg_set, reg_rst; | |
234 | unsigned int bit_pupd, bit_r0, bit_r1; | |
235 | const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; | |
236 | bool find = false; | |
237 | ||
238 | for (i = 0; i < info_num; i++) { | |
239 | if (pin == pupd_infos[i].pin) { | |
240 | find = true; | |
241 | break; | |
242 | } | |
243 | } | |
244 | ||
245 | if (!find) | |
246 | return -EINVAL; | |
247 | ||
248 | spec_pupd_pin = pupd_infos + i; | |
249 | reg_set = spec_pupd_pin->offset + align; | |
250 | reg_rst = spec_pupd_pin->offset + (align << 1); | |
251 | ||
252 | if (isup) | |
253 | reg_pupd = reg_rst; | |
254 | else | |
255 | reg_pupd = reg_set; | |
256 | ||
257 | bit_pupd = BIT(spec_pupd_pin->pupd_bit); | |
258 | regmap_write(regmap, reg_pupd, bit_pupd); | |
259 | ||
260 | bit_r0 = BIT(spec_pupd_pin->r0_bit); | |
261 | bit_r1 = BIT(spec_pupd_pin->r1_bit); | |
262 | ||
263 | switch (r1r0) { | |
264 | case MTK_PUPD_SET_R1R0_00: | |
265 | regmap_write(regmap, reg_rst, bit_r0); | |
266 | regmap_write(regmap, reg_rst, bit_r1); | |
267 | break; | |
268 | case MTK_PUPD_SET_R1R0_01: | |
269 | regmap_write(regmap, reg_set, bit_r0); | |
270 | regmap_write(regmap, reg_rst, bit_r1); | |
271 | break; | |
272 | case MTK_PUPD_SET_R1R0_10: | |
273 | regmap_write(regmap, reg_rst, bit_r0); | |
274 | regmap_write(regmap, reg_set, bit_r1); | |
275 | break; | |
276 | case MTK_PUPD_SET_R1R0_11: | |
277 | regmap_write(regmap, reg_set, bit_r0); | |
278 | regmap_write(regmap, reg_set, bit_r1); | |
279 | break; | |
280 | default: | |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
a6df410d HY |
287 | static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, |
288 | unsigned int pin, bool enable, bool isup, unsigned int arg) | |
289 | { | |
290 | unsigned int bit; | |
291 | unsigned int reg_pullen, reg_pullsel; | |
292 | int ret; | |
293 | ||
294 | /* Some pins' pull setting are very different, | |
295 | * they have separate pull up/down bit, R0 and R1 | |
296 | * resistor bit, so we need this special handle. | |
297 | */ | |
298 | if (pctl->devdata->spec_pull_set) { | |
299 | ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), | |
300 | pin, pctl->devdata->port_align, isup, arg); | |
301 | if (!ret) | |
302 | return 0; | |
303 | } | |
304 | ||
305 | /* For generic pull config, default arg value should be 0 or 1. */ | |
306 | if (arg != 0 && arg != 1) { | |
307 | dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n", | |
308 | arg, pin); | |
309 | return -EINVAL; | |
310 | } | |
311 | ||
312 | bit = BIT(pin & 0xf); | |
313 | if (enable) | |
314 | reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + | |
315 | pctl->devdata->pullen_offset, pctl); | |
316 | else | |
317 | reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) + | |
318 | pctl->devdata->pullen_offset, pctl); | |
319 | ||
320 | if (isup) | |
321 | reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) + | |
322 | pctl->devdata->pullsel_offset, pctl); | |
323 | else | |
324 | reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + | |
325 | pctl->devdata->pullsel_offset, pctl); | |
326 | ||
327 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); | |
328 | regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); | |
329 | return 0; | |
330 | } | |
331 | ||
332 | static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, | |
333 | unsigned int pin, enum pin_config_param param, | |
334 | enum pin_config_param arg) | |
335 | { | |
25d76b21 | 336 | int ret = 0; |
a6df410d HY |
337 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
338 | ||
339 | switch (param) { | |
340 | case PIN_CONFIG_BIAS_DISABLE: | |
25d76b21 | 341 | ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); |
a6df410d HY |
342 | break; |
343 | case PIN_CONFIG_BIAS_PULL_UP: | |
25d76b21 | 344 | ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); |
a6df410d HY |
345 | break; |
346 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
25d76b21 | 347 | ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); |
a6df410d HY |
348 | break; |
349 | case PIN_CONFIG_INPUT_ENABLE: | |
25d76b21 | 350 | ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
a6df410d HY |
351 | break; |
352 | case PIN_CONFIG_OUTPUT: | |
353 | mtk_gpio_set(pctl->chip, pin, arg); | |
25d76b21 | 354 | ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); |
a6df410d HY |
355 | break; |
356 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
25d76b21 | 357 | ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); |
a6df410d HY |
358 | break; |
359 | case PIN_CONFIG_DRIVE_STRENGTH: | |
25d76b21 | 360 | ret = mtk_pconf_set_driving(pctl, pin, arg); |
a6df410d HY |
361 | break; |
362 | default: | |
25d76b21 | 363 | ret = -EINVAL; |
a6df410d HY |
364 | } |
365 | ||
25d76b21 | 366 | return ret; |
a6df410d HY |
367 | } |
368 | ||
369 | static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, | |
370 | unsigned group, | |
371 | unsigned long *config) | |
372 | { | |
373 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
374 | ||
375 | *config = pctl->groups[group].config; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, | |
381 | unsigned long *configs, unsigned num_configs) | |
382 | { | |
383 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
384 | struct mtk_pinctrl_group *g = &pctl->groups[group]; | |
25d76b21 | 385 | int i, ret; |
a6df410d HY |
386 | |
387 | for (i = 0; i < num_configs; i++) { | |
25d76b21 | 388 | ret = mtk_pconf_parse_conf(pctldev, g->pin, |
a6df410d HY |
389 | pinconf_to_config_param(configs[i]), |
390 | pinconf_to_config_argument(configs[i])); | |
25d76b21 HY |
391 | if (ret < 0) |
392 | return ret; | |
a6df410d HY |
393 | |
394 | g->config = configs[i]; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | static const struct pinconf_ops mtk_pconf_ops = { | |
401 | .pin_config_group_get = mtk_pconf_group_get, | |
402 | .pin_config_group_set = mtk_pconf_group_set, | |
403 | }; | |
404 | ||
405 | static struct mtk_pinctrl_group * | |
406 | mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin) | |
407 | { | |
408 | int i; | |
409 | ||
410 | for (i = 0; i < pctl->ngroups; i++) { | |
411 | struct mtk_pinctrl_group *grp = pctl->groups + i; | |
412 | ||
413 | if (grp->pin == pin) | |
414 | return grp; | |
415 | } | |
416 | ||
417 | return NULL; | |
418 | } | |
419 | ||
420 | static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin( | |
421 | struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum) | |
422 | { | |
423 | const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num; | |
424 | const struct mtk_desc_function *func = pin->functions; | |
425 | ||
426 | while (func && func->name) { | |
427 | if (func->muxval == fnum) | |
428 | return func; | |
429 | func++; | |
430 | } | |
431 | ||
432 | return NULL; | |
433 | } | |
434 | ||
435 | static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl, | |
436 | u32 pin_num, u32 fnum) | |
437 | { | |
438 | int i; | |
439 | ||
440 | for (i = 0; i < pctl->devdata->npins; i++) { | |
441 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; | |
442 | ||
443 | if (pin->pin.number == pin_num) { | |
444 | const struct mtk_desc_function *func = | |
445 | pin->functions; | |
446 | ||
447 | while (func && func->name) { | |
448 | if (func->muxval == fnum) | |
449 | return true; | |
450 | func++; | |
451 | } | |
452 | ||
453 | break; | |
454 | } | |
455 | } | |
456 | ||
457 | return false; | |
458 | } | |
459 | ||
460 | static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl, | |
461 | u32 pin, u32 fnum, struct mtk_pinctrl_group *grp, | |
462 | struct pinctrl_map **map, unsigned *reserved_maps, | |
463 | unsigned *num_maps) | |
464 | { | |
465 | bool ret; | |
466 | ||
467 | if (*num_maps == *reserved_maps) | |
468 | return -ENOSPC; | |
469 | ||
470 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
471 | (*map)[*num_maps].data.mux.group = grp->name; | |
472 | ||
473 | ret = mtk_pctrl_is_function_valid(pctl, pin, fnum); | |
474 | if (!ret) { | |
475 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", | |
476 | fnum, pin); | |
477 | return -EINVAL; | |
478 | } | |
479 | ||
480 | (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum]; | |
481 | (*num_maps)++; | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
487 | struct device_node *node, | |
488 | struct pinctrl_map **map, | |
489 | unsigned *reserved_maps, | |
490 | unsigned *num_maps) | |
491 | { | |
492 | struct property *pins; | |
493 | u32 pinfunc, pin, func; | |
494 | int num_pins, num_funcs, maps_per_pin; | |
495 | unsigned long *configs; | |
496 | unsigned int num_configs; | |
497 | bool has_config = 0; | |
498 | int i, err; | |
499 | unsigned reserve = 0; | |
500 | struct mtk_pinctrl_group *grp; | |
501 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
502 | ||
503 | pins = of_find_property(node, "pinmux", NULL); | |
504 | if (!pins) { | |
505 | dev_err(pctl->dev, "missing pins property in node %s .\n", | |
506 | node->name); | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
c445cac3 HY |
510 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, |
511 | &num_configs); | |
a6df410d HY |
512 | if (num_configs) |
513 | has_config = 1; | |
514 | ||
515 | num_pins = pins->length / sizeof(u32); | |
516 | num_funcs = num_pins; | |
517 | maps_per_pin = 0; | |
518 | if (num_funcs) | |
519 | maps_per_pin++; | |
520 | if (has_config && num_pins >= 1) | |
521 | maps_per_pin++; | |
522 | ||
523 | if (!num_pins || !maps_per_pin) | |
524 | return -EINVAL; | |
525 | ||
526 | reserve = num_pins * maps_per_pin; | |
527 | ||
528 | err = pinctrl_utils_reserve_map(pctldev, map, | |
529 | reserved_maps, num_maps, reserve); | |
530 | if (err < 0) | |
531 | goto fail; | |
532 | ||
533 | for (i = 0; i < num_pins; i++) { | |
534 | err = of_property_read_u32_index(node, "pinmux", | |
535 | i, &pinfunc); | |
536 | if (err) | |
537 | goto fail; | |
538 | ||
539 | pin = MTK_GET_PIN_NO(pinfunc); | |
540 | func = MTK_GET_PIN_FUNC(pinfunc); | |
541 | ||
542 | if (pin >= pctl->devdata->npins || | |
543 | func >= ARRAY_SIZE(mtk_gpio_functions)) { | |
544 | dev_err(pctl->dev, "invalid pins value.\n"); | |
545 | err = -EINVAL; | |
546 | goto fail; | |
547 | } | |
548 | ||
549 | grp = mtk_pctrl_find_group_by_pin(pctl, pin); | |
550 | if (!grp) { | |
551 | dev_err(pctl->dev, "unable to match pin %d to group\n", | |
552 | pin); | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
556 | err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, | |
557 | reserved_maps, num_maps); | |
558 | if (err < 0) | |
559 | goto fail; | |
560 | ||
561 | if (has_config) { | |
562 | err = pinctrl_utils_add_map_configs(pctldev, map, | |
563 | reserved_maps, num_maps, grp->name, | |
564 | configs, num_configs, | |
565 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
566 | if (err < 0) | |
567 | goto fail; | |
568 | } | |
569 | } | |
570 | ||
571 | return 0; | |
572 | ||
573 | fail: | |
574 | return err; | |
575 | } | |
576 | ||
577 | static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
578 | struct device_node *np_config, | |
579 | struct pinctrl_map **map, unsigned *num_maps) | |
580 | { | |
581 | struct device_node *np; | |
582 | unsigned reserved_maps; | |
583 | int ret; | |
584 | ||
585 | *map = NULL; | |
586 | *num_maps = 0; | |
587 | reserved_maps = 0; | |
588 | ||
589 | for_each_child_of_node(np_config, np) { | |
590 | ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map, | |
591 | &reserved_maps, num_maps); | |
592 | if (ret < 0) { | |
593 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); | |
594 | return ret; | |
595 | } | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
602 | { | |
603 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
604 | ||
605 | return pctl->ngroups; | |
606 | } | |
607 | ||
608 | static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
609 | unsigned group) | |
610 | { | |
611 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
612 | ||
613 | return pctl->groups[group].name; | |
614 | } | |
615 | ||
616 | static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
617 | unsigned group, | |
618 | const unsigned **pins, | |
619 | unsigned *num_pins) | |
620 | { | |
621 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
622 | ||
623 | *pins = (unsigned *)&pctl->groups[group].pin; | |
624 | *num_pins = 1; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static const struct pinctrl_ops mtk_pctrl_ops = { | |
630 | .dt_node_to_map = mtk_pctrl_dt_node_to_map, | |
631 | .dt_free_map = pinctrl_utils_dt_free_map, | |
632 | .get_groups_count = mtk_pctrl_get_groups_count, | |
633 | .get_group_name = mtk_pctrl_get_group_name, | |
634 | .get_group_pins = mtk_pctrl_get_group_pins, | |
635 | }; | |
636 | ||
637 | static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
638 | { | |
639 | return ARRAY_SIZE(mtk_gpio_functions); | |
640 | } | |
641 | ||
642 | static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
643 | unsigned selector) | |
644 | { | |
645 | return mtk_gpio_functions[selector]; | |
646 | } | |
647 | ||
648 | static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
649 | unsigned function, | |
650 | const char * const **groups, | |
651 | unsigned * const num_groups) | |
652 | { | |
653 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
654 | ||
655 | *groups = pctl->grp_names; | |
656 | *num_groups = pctl->ngroups; | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, | |
662 | unsigned long pin, unsigned long mode) | |
663 | { | |
664 | unsigned int reg_addr; | |
665 | unsigned char bit; | |
666 | unsigned int val; | |
667 | unsigned int mask = (1L << GPIO_MODE_BITS) - 1; | |
668 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
669 | ||
670 | reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) | |
671 | + pctl->devdata->pinmux_offset; | |
672 | ||
673 | bit = pin % MAX_GPIO_MODE_PER_REG; | |
674 | mask <<= (GPIO_MODE_BITS * bit); | |
675 | val = (mode << (GPIO_MODE_BITS * bit)); | |
676 | return regmap_update_bits(mtk_get_regmap(pctl, pin), | |
677 | reg_addr, mask, val); | |
678 | } | |
679 | ||
d9819eb9 MM |
680 | static const struct mtk_desc_pin * |
681 | mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num) | |
682 | { | |
683 | int i; | |
684 | const struct mtk_desc_pin *pin; | |
685 | ||
686 | for (i = 0; i < pctl->devdata->npins; i++) { | |
687 | pin = pctl->devdata->pins + i; | |
688 | if (pin->eint.eintnum == eint_num) | |
689 | return pin; | |
690 | } | |
691 | ||
692 | return NULL; | |
693 | } | |
694 | ||
a6df410d HY |
695 | static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev, |
696 | unsigned function, | |
697 | unsigned group) | |
698 | { | |
699 | bool ret; | |
700 | const struct mtk_desc_function *desc; | |
701 | struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
702 | struct mtk_pinctrl_group *g = pctl->groups + group; | |
703 | ||
704 | ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); | |
705 | if (!ret) { | |
c70336cc | 706 | dev_err(pctl->dev, "invalid function %d on group %d .\n", |
a6df410d HY |
707 | function, group); |
708 | return -EINVAL; | |
709 | } | |
710 | ||
711 | desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function); | |
712 | if (!desc) | |
713 | return -EINVAL; | |
714 | mtk_pmx_set_mode(pctldev, g->pin, desc->muxval); | |
715 | return 0; | |
716 | } | |
717 | ||
718 | static const struct pinmux_ops mtk_pmx_ops = { | |
719 | .get_functions_count = mtk_pmx_get_funcs_cnt, | |
720 | .get_function_name = mtk_pmx_get_func_name, | |
721 | .get_function_groups = mtk_pmx_get_func_groups, | |
722 | .set_mux = mtk_pmx_set_mux, | |
723 | .gpio_set_direction = mtk_pmx_gpio_set_direction, | |
724 | }; | |
725 | ||
a6df410d HY |
726 | static int mtk_gpio_direction_input(struct gpio_chip *chip, |
727 | unsigned offset) | |
728 | { | |
729 | return pinctrl_gpio_direction_input(chip->base + offset); | |
730 | } | |
731 | ||
732 | static int mtk_gpio_direction_output(struct gpio_chip *chip, | |
733 | unsigned offset, int value) | |
734 | { | |
735 | mtk_gpio_set(chip, offset, value); | |
736 | return pinctrl_gpio_direction_output(chip->base + offset); | |
737 | } | |
738 | ||
739 | static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
740 | { | |
741 | unsigned int reg_addr; | |
742 | unsigned int bit; | |
743 | unsigned int read_val = 0; | |
744 | ||
745 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
746 | ||
747 | reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; | |
748 | bit = BIT(offset & 0xf); | |
749 | regmap_read(pctl->regmap1, reg_addr, &read_val); | |
750 | return !!(read_val & bit); | |
751 | } | |
752 | ||
753 | static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) | |
754 | { | |
755 | unsigned int reg_addr; | |
756 | unsigned int bit; | |
757 | unsigned int read_val = 0; | |
758 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
759 | ||
760 | if (mtk_gpio_get_direction(chip, offset)) | |
761 | reg_addr = mtk_get_port(pctl, offset) + | |
762 | pctl->devdata->dout_offset; | |
763 | else | |
764 | reg_addr = mtk_get_port(pctl, offset) + | |
765 | pctl->devdata->din_offset; | |
766 | ||
767 | bit = BIT(offset & 0xf); | |
768 | regmap_read(pctl->regmap1, reg_addr, &read_val); | |
769 | return !!(read_val & bit); | |
770 | } | |
771 | ||
d9819eb9 MM |
772 | static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
773 | { | |
774 | const struct mtk_desc_pin *pin; | |
775 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
776 | int irq; | |
777 | ||
778 | pin = pctl->devdata->pins + offset; | |
779 | if (pin->eint.eintnum == NO_EINT_SUPPORT) | |
780 | return -EINVAL; | |
781 | ||
782 | irq = irq_find_mapping(pctl->domain, pin->eint.eintnum); | |
783 | if (!irq) | |
784 | return -EINVAL; | |
785 | ||
786 | return irq; | |
787 | } | |
788 | ||
789 | static int mtk_pinctrl_irq_request_resources(struct irq_data *d) | |
790 | { | |
791 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
792 | const struct mtk_desc_pin *pin; | |
793 | int ret; | |
794 | ||
795 | pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); | |
796 | ||
797 | if (!pin) { | |
798 | dev_err(pctl->dev, "Can not find pin\n"); | |
799 | return -EINVAL; | |
800 | } | |
801 | ||
802 | ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number); | |
803 | if (ret) { | |
804 | dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
805 | irqd_to_hwirq(d)); | |
806 | return ret; | |
807 | } | |
808 | ||
809 | /* set mux to INT mode */ | |
810 | mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux); | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
815 | static void mtk_pinctrl_irq_release_resources(struct irq_data *d) | |
816 | { | |
817 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
818 | const struct mtk_desc_pin *pin; | |
819 | ||
820 | pin = mtk_find_pin_by_eint_num(pctl, d->hwirq); | |
821 | ||
822 | if (!pin) { | |
823 | dev_err(pctl->dev, "Can not find pin\n"); | |
824 | return; | |
825 | } | |
826 | ||
827 | gpiochip_unlock_as_irq(pctl->chip, pin->pin.number); | |
828 | } | |
829 | ||
830 | static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl, | |
831 | unsigned int eint_num, unsigned int offset) | |
832 | { | |
833 | unsigned int eint_base = 0; | |
834 | void __iomem *reg; | |
835 | ||
836 | if (eint_num >= pctl->devdata->ap_num) | |
837 | eint_base = pctl->devdata->ap_num; | |
838 | ||
839 | reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4; | |
840 | ||
841 | return reg; | |
842 | } | |
843 | ||
844 | /* | |
845 | * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not | |
846 | * @eint_num: the EINT number to setmtk_pinctrl | |
847 | */ | |
848 | static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl, | |
849 | unsigned int eint_num) | |
850 | { | |
851 | unsigned int sens; | |
852 | unsigned int bit = BIT(eint_num % 32); | |
853 | const struct mtk_eint_offsets *eint_offsets = | |
854 | &pctl->devdata->eint_offsets; | |
855 | ||
856 | void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, | |
857 | eint_offsets->sens); | |
858 | ||
859 | if (readl(reg) & bit) | |
860 | sens = MT_LEVEL_SENSITIVE; | |
861 | else | |
862 | sens = MT_EDGE_SENSITIVE; | |
863 | ||
864 | if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE)) | |
865 | return 1; | |
866 | else | |
867 | return 0; | |
868 | } | |
869 | ||
870 | /* | |
871 | * mtk_eint_get_mask: To get the eint mask | |
872 | * @eint_num: the EINT number to get | |
873 | */ | |
874 | static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl, | |
875 | unsigned int eint_num) | |
876 | { | |
877 | unsigned int bit = BIT(eint_num % 32); | |
878 | const struct mtk_eint_offsets *eint_offsets = | |
879 | &pctl->devdata->eint_offsets; | |
880 | ||
881 | void __iomem *reg = mtk_eint_get_offset(pctl, eint_num, | |
882 | eint_offsets->mask); | |
883 | ||
884 | return !!(readl(reg) & bit); | |
885 | } | |
886 | ||
3221f40b YC |
887 | static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq) |
888 | { | |
889 | int start_level, curr_level; | |
890 | unsigned int reg_offset; | |
891 | const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); | |
b4b05b9a | 892 | u32 mask = BIT(hwirq & 0x1f); |
3221f40b YC |
893 | u32 port = (hwirq >> 5) & eint_offsets->port_mask; |
894 | void __iomem *reg = pctl->eint_reg_base + (port << 2); | |
895 | const struct mtk_desc_pin *pin; | |
896 | ||
897 | pin = mtk_find_pin_by_eint_num(pctl, hwirq); | |
898 | curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); | |
899 | do { | |
900 | start_level = curr_level; | |
901 | if (start_level) | |
902 | reg_offset = eint_offsets->pol_clr; | |
903 | else | |
904 | reg_offset = eint_offsets->pol_set; | |
905 | writel(mask, reg + reg_offset); | |
906 | ||
907 | curr_level = mtk_gpio_get(pctl->chip, pin->pin.number); | |
908 | } while (start_level != curr_level); | |
909 | ||
910 | return start_level; | |
911 | } | |
912 | ||
d9819eb9 MM |
913 | static void mtk_eint_mask(struct irq_data *d) |
914 | { | |
915 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
916 | const struct mtk_eint_offsets *eint_offsets = | |
917 | &pctl->devdata->eint_offsets; | |
918 | u32 mask = BIT(d->hwirq & 0x1f); | |
919 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, | |
920 | eint_offsets->mask_set); | |
921 | ||
922 | writel(mask, reg); | |
923 | } | |
924 | ||
925 | static void mtk_eint_unmask(struct irq_data *d) | |
926 | { | |
927 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
928 | const struct mtk_eint_offsets *eint_offsets = | |
929 | &pctl->devdata->eint_offsets; | |
930 | u32 mask = BIT(d->hwirq & 0x1f); | |
931 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, | |
932 | eint_offsets->mask_clr); | |
933 | ||
934 | writel(mask, reg); | |
3221f40b YC |
935 | |
936 | if (pctl->eint_dual_edges[d->hwirq]) | |
937 | mtk_eint_flip_edge(pctl, d->hwirq); | |
d9819eb9 MM |
938 | } |
939 | ||
940 | static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset, | |
941 | unsigned debounce) | |
942 | { | |
943 | struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev); | |
944 | int eint_num, virq, eint_offset; | |
945 | unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc; | |
946 | static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256}; | |
947 | const struct mtk_desc_pin *pin; | |
948 | struct irq_data *d; | |
949 | ||
950 | pin = pctl->devdata->pins + offset; | |
951 | if (pin->eint.eintnum == NO_EINT_SUPPORT) | |
952 | return -EINVAL; | |
953 | ||
954 | eint_num = pin->eint.eintnum; | |
955 | virq = irq_find_mapping(pctl->domain, eint_num); | |
956 | eint_offset = (eint_num % 4) * 8; | |
957 | d = irq_get_irq_data(virq); | |
958 | ||
959 | set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set; | |
960 | clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr; | |
961 | if (!mtk_eint_can_en_debounce(pctl, eint_num)) | |
962 | return -ENOSYS; | |
963 | ||
964 | dbnc = ARRAY_SIZE(dbnc_arr); | |
965 | for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) { | |
966 | if (debounce <= dbnc_arr[i]) { | |
967 | dbnc = i; | |
968 | break; | |
969 | } | |
970 | } | |
971 | ||
972 | if (!mtk_eint_get_mask(pctl, eint_num)) { | |
973 | mtk_eint_mask(d); | |
974 | unmask = 1; | |
74d77e50 CIK |
975 | } else { |
976 | unmask = 0; | |
d9819eb9 MM |
977 | } |
978 | ||
979 | clr_bit = 0xff << eint_offset; | |
980 | writel(clr_bit, pctl->eint_reg_base + clr_offset); | |
981 | ||
982 | bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) << | |
983 | eint_offset; | |
984 | rst = EINT_DBNC_RST_BIT << eint_offset; | |
985 | writel(rst | bit, pctl->eint_reg_base + set_offset); | |
986 | ||
987 | /* Delay a while (more than 2T) to wait for hw debounce counter reset | |
988 | work correctly */ | |
989 | udelay(1); | |
990 | if (unmask == 1) | |
991 | mtk_eint_unmask(d); | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
a6df410d HY |
996 | static struct gpio_chip mtk_gpio_chip = { |
997 | .owner = THIS_MODULE, | |
98c85d58 JG |
998 | .request = gpiochip_generic_request, |
999 | .free = gpiochip_generic_free, | |
a6df410d HY |
1000 | .direction_input = mtk_gpio_direction_input, |
1001 | .direction_output = mtk_gpio_direction_output, | |
1002 | .get = mtk_gpio_get, | |
1003 | .set = mtk_gpio_set, | |
d9819eb9 MM |
1004 | .to_irq = mtk_gpio_to_irq, |
1005 | .set_debounce = mtk_gpio_set_debounce, | |
a6df410d HY |
1006 | .of_gpio_n_cells = 2, |
1007 | }; | |
1008 | ||
d9819eb9 MM |
1009 | static int mtk_eint_set_type(struct irq_data *d, |
1010 | unsigned int type) | |
1011 | { | |
1012 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
1013 | const struct mtk_eint_offsets *eint_offsets = | |
1014 | &pctl->devdata->eint_offsets; | |
1015 | u32 mask = BIT(d->hwirq & 0x1f); | |
1016 | void __iomem *reg; | |
1017 | ||
1018 | if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) || | |
d9819eb9 MM |
1019 | ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) { |
1020 | dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n", | |
1021 | d->irq, d->hwirq, type); | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
3221f40b YC |
1025 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
1026 | pctl->eint_dual_edges[d->hwirq] = 1; | |
1027 | else | |
1028 | pctl->eint_dual_edges[d->hwirq] = 0; | |
1029 | ||
d9819eb9 MM |
1030 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) { |
1031 | reg = mtk_eint_get_offset(pctl, d->hwirq, | |
1032 | eint_offsets->pol_clr); | |
1033 | writel(mask, reg); | |
1034 | } else { | |
1035 | reg = mtk_eint_get_offset(pctl, d->hwirq, | |
1036 | eint_offsets->pol_set); | |
1037 | writel(mask, reg); | |
1038 | } | |
1039 | ||
1040 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | |
1041 | reg = mtk_eint_get_offset(pctl, d->hwirq, | |
1042 | eint_offsets->sens_clr); | |
1043 | writel(mask, reg); | |
1044 | } else { | |
1045 | reg = mtk_eint_get_offset(pctl, d->hwirq, | |
1046 | eint_offsets->sens_set); | |
1047 | writel(mask, reg); | |
1048 | } | |
1049 | ||
3221f40b YC |
1050 | if (pctl->eint_dual_edges[d->hwirq]) |
1051 | mtk_eint_flip_edge(pctl, d->hwirq); | |
1052 | ||
d9819eb9 MM |
1053 | return 0; |
1054 | } | |
1055 | ||
58a5e1b6 MM |
1056 | static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on) |
1057 | { | |
1058 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
1059 | int shift = d->hwirq & 0x1f; | |
1060 | int reg = d->hwirq >> 5; | |
1061 | ||
1062 | if (on) | |
1063 | pctl->wake_mask[reg] |= BIT(shift); | |
1064 | else | |
1065 | pctl->wake_mask[reg] &= ~BIT(shift); | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip, | |
1071 | void __iomem *eint_reg_base, u32 *buf) | |
1072 | { | |
1073 | int port; | |
1074 | void __iomem *reg; | |
1075 | ||
1076 | for (port = 0; port < chip->ports; port++) { | |
1077 | reg = eint_reg_base + (port << 2); | |
1078 | writel_relaxed(~buf[port], reg + chip->mask_set); | |
1079 | writel_relaxed(buf[port], reg + chip->mask_clr); | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip, | |
1084 | void __iomem *eint_reg_base, u32 *buf) | |
1085 | { | |
1086 | int port; | |
1087 | void __iomem *reg; | |
1088 | ||
1089 | for (port = 0; port < chip->ports; port++) { | |
1090 | reg = eint_reg_base + chip->mask + (port << 2); | |
1091 | buf[port] = ~readl_relaxed(reg); | |
1092 | /* Mask is 0 when irq is enabled, and 1 when disabled. */ | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | static int mtk_eint_suspend(struct device *device) | |
1097 | { | |
1098 | void __iomem *reg; | |
1099 | struct mtk_pinctrl *pctl = dev_get_drvdata(device); | |
1100 | const struct mtk_eint_offsets *eint_offsets = | |
1101 | &pctl->devdata->eint_offsets; | |
1102 | ||
1103 | reg = pctl->eint_reg_base; | |
1104 | mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask); | |
1105 | mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask); | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | static int mtk_eint_resume(struct device *device) | |
1111 | { | |
1112 | struct mtk_pinctrl *pctl = dev_get_drvdata(device); | |
1113 | const struct mtk_eint_offsets *eint_offsets = | |
1114 | &pctl->devdata->eint_offsets; | |
1115 | ||
1116 | mtk_eint_chip_write_mask(eint_offsets, | |
1117 | pctl->eint_reg_base, pctl->cur_mask); | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | const struct dev_pm_ops mtk_eint_pm_ops = { | |
1123 | .suspend = mtk_eint_suspend, | |
1124 | .resume = mtk_eint_resume, | |
1125 | }; | |
1126 | ||
d9819eb9 MM |
1127 | static void mtk_eint_ack(struct irq_data *d) |
1128 | { | |
1129 | struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); | |
1130 | const struct mtk_eint_offsets *eint_offsets = | |
1131 | &pctl->devdata->eint_offsets; | |
1132 | u32 mask = BIT(d->hwirq & 0x1f); | |
1133 | void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq, | |
1134 | eint_offsets->ack); | |
1135 | ||
1136 | writel(mask, reg); | |
1137 | } | |
1138 | ||
1139 | static struct irq_chip mtk_pinctrl_irq_chip = { | |
1140 | .name = "mt-eint", | |
58a5e1b6 | 1141 | .irq_disable = mtk_eint_mask, |
d9819eb9 MM |
1142 | .irq_mask = mtk_eint_mask, |
1143 | .irq_unmask = mtk_eint_unmask, | |
1144 | .irq_ack = mtk_eint_ack, | |
1145 | .irq_set_type = mtk_eint_set_type, | |
58a5e1b6 | 1146 | .irq_set_wake = mtk_eint_irq_set_wake, |
d9819eb9 MM |
1147 | .irq_request_resources = mtk_pinctrl_irq_request_resources, |
1148 | .irq_release_resources = mtk_pinctrl_irq_release_resources, | |
1149 | }; | |
1150 | ||
1151 | static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl) | |
1152 | { | |
1153 | const struct mtk_eint_offsets *eint_offsets = | |
1154 | &pctl->devdata->eint_offsets; | |
1155 | void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en; | |
1156 | unsigned int i; | |
1157 | ||
1158 | for (i = 0; i < pctl->devdata->ap_num; i += 32) { | |
1159 | writel(0xffffffff, reg); | |
1160 | reg += 4; | |
1161 | } | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | static inline void | |
1166 | mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index) | |
1167 | { | |
1168 | unsigned int rst, ctrl_offset; | |
1169 | unsigned int bit, dbnc; | |
1170 | const struct mtk_eint_offsets *eint_offsets = | |
1171 | &pctl->devdata->eint_offsets; | |
1172 | ||
1173 | ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl; | |
1174 | dbnc = readl(pctl->eint_reg_base + ctrl_offset); | |
1175 | bit = EINT_DBNC_SET_EN << ((index % 4) * 8); | |
1176 | if ((bit & dbnc) > 0) { | |
1177 | ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set; | |
1178 | rst = EINT_DBNC_RST_BIT << ((index % 4) * 8); | |
1179 | writel(rst, pctl->eint_reg_base + ctrl_offset); | |
1180 | } | |
1181 | } | |
1182 | ||
bd0b9ac4 | 1183 | static void mtk_eint_irq_handler(struct irq_desc *desc) |
d9819eb9 | 1184 | { |
5663bb27 JL |
1185 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1186 | struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc); | |
d9819eb9 MM |
1187 | unsigned int status, eint_num; |
1188 | int offset, index, virq; | |
1189 | const struct mtk_eint_offsets *eint_offsets = | |
1190 | &pctl->devdata->eint_offsets; | |
1191 | void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat); | |
3221f40b YC |
1192 | int dual_edges, start_level, curr_level; |
1193 | const struct mtk_desc_pin *pin; | |
d9819eb9 MM |
1194 | |
1195 | chained_irq_enter(chip, desc); | |
1196 | for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) { | |
1197 | status = readl(reg); | |
1198 | reg += 4; | |
1199 | while (status) { | |
1200 | offset = __ffs(status); | |
1201 | index = eint_num + offset; | |
1202 | virq = irq_find_mapping(pctl->domain, index); | |
1203 | status &= ~BIT(offset); | |
1204 | ||
3221f40b YC |
1205 | dual_edges = pctl->eint_dual_edges[index]; |
1206 | if (dual_edges) { | |
1207 | /* Clear soft-irq in case we raised it | |
1208 | last time */ | |
1209 | writel(BIT(offset), reg - eint_offsets->stat + | |
1210 | eint_offsets->soft_clr); | |
1211 | ||
1212 | pin = mtk_find_pin_by_eint_num(pctl, index); | |
1213 | start_level = mtk_gpio_get(pctl->chip, | |
1214 | pin->pin.number); | |
1215 | } | |
1216 | ||
d9819eb9 MM |
1217 | generic_handle_irq(virq); |
1218 | ||
3221f40b YC |
1219 | if (dual_edges) { |
1220 | curr_level = mtk_eint_flip_edge(pctl, index); | |
1221 | ||
1222 | /* If level changed, we might lost one edge | |
1223 | interrupt, raised it through soft-irq */ | |
1224 | if (start_level != curr_level) | |
1225 | writel(BIT(offset), reg - | |
1226 | eint_offsets->stat + | |
1227 | eint_offsets->soft_set); | |
1228 | } | |
1229 | ||
d9819eb9 MM |
1230 | if (index < pctl->devdata->db_cnt) |
1231 | mtk_eint_debounce_process(pctl , index); | |
1232 | } | |
1233 | } | |
1234 | chained_irq_exit(chip, desc); | |
1235 | } | |
1236 | ||
a6df410d HY |
1237 | static int mtk_pctrl_build_state(struct platform_device *pdev) |
1238 | { | |
1239 | struct mtk_pinctrl *pctl = platform_get_drvdata(pdev); | |
1240 | int i; | |
1241 | ||
1242 | pctl->ngroups = pctl->devdata->npins; | |
1243 | ||
1244 | /* Allocate groups */ | |
0206caa8 AL |
1245 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, |
1246 | sizeof(*pctl->groups), GFP_KERNEL); | |
a6df410d HY |
1247 | if (!pctl->groups) |
1248 | return -ENOMEM; | |
1249 | ||
1250 | /* We assume that one pin is one group, use pin name as group name. */ | |
0206caa8 AL |
1251 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, |
1252 | sizeof(*pctl->grp_names), GFP_KERNEL); | |
a6df410d HY |
1253 | if (!pctl->grp_names) |
1254 | return -ENOMEM; | |
1255 | ||
1256 | for (i = 0; i < pctl->devdata->npins; i++) { | |
1257 | const struct mtk_desc_pin *pin = pctl->devdata->pins + i; | |
1258 | struct mtk_pinctrl_group *group = pctl->groups + i; | |
1259 | ||
1260 | group->name = pin->pin.name; | |
1261 | group->pin = pin->pin.number; | |
1262 | ||
1263 | pctl->grp_names[i] = pin->pin.name; | |
1264 | } | |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | ||
a6df410d | 1269 | int mtk_pctrl_init(struct platform_device *pdev, |
fc59e66c HY |
1270 | const struct mtk_pinctrl_devdata *data, |
1271 | struct regmap *regmap) | |
a6df410d HY |
1272 | { |
1273 | struct pinctrl_pin_desc *pins; | |
1274 | struct mtk_pinctrl *pctl; | |
1275 | struct device_node *np = pdev->dev.of_node, *node; | |
1276 | struct property *prop; | |
d9819eb9 | 1277 | struct resource *res; |
58a5e1b6 | 1278 | int i, ret, irq, ports_buf; |
a6df410d HY |
1279 | |
1280 | pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); | |
1281 | if (!pctl) | |
1282 | return -ENOMEM; | |
1283 | ||
1284 | platform_set_drvdata(pdev, pctl); | |
1285 | ||
1286 | prop = of_find_property(np, "pins-are-numbered", NULL); | |
1287 | if (!prop) { | |
c445cac3 | 1288 | dev_err(&pdev->dev, "only support pins-are-numbered format\n"); |
a6df410d HY |
1289 | return -EINVAL; |
1290 | } | |
1291 | ||
1292 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); | |
1293 | if (node) { | |
1294 | pctl->regmap1 = syscon_node_to_regmap(node); | |
1295 | if (IS_ERR(pctl->regmap1)) | |
1296 | return PTR_ERR(pctl->regmap1); | |
fc59e66c HY |
1297 | } else if (regmap) { |
1298 | pctl->regmap1 = regmap; | |
1299 | } else { | |
1300 | dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); | |
1301 | return -EINVAL; | |
a6df410d HY |
1302 | } |
1303 | ||
1304 | /* Only 8135 has two base addr, other SoCs have only one. */ | |
1305 | node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); | |
1306 | if (node) { | |
1307 | pctl->regmap2 = syscon_node_to_regmap(node); | |
1308 | if (IS_ERR(pctl->regmap2)) | |
1309 | return PTR_ERR(pctl->regmap2); | |
1310 | } | |
1311 | ||
1312 | pctl->devdata = data; | |
1313 | ret = mtk_pctrl_build_state(pdev); | |
1314 | if (ret) { | |
1315 | dev_err(&pdev->dev, "build state failed: %d\n", ret); | |
1316 | return -EINVAL; | |
1317 | } | |
1318 | ||
0206caa8 | 1319 | pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), |
a6df410d HY |
1320 | GFP_KERNEL); |
1321 | if (!pins) | |
1322 | return -ENOMEM; | |
1323 | ||
1324 | for (i = 0; i < pctl->devdata->npins; i++) | |
1325 | pins[i] = pctl->devdata->pins[i].pin; | |
d48c2c02 HY |
1326 | |
1327 | pctl->pctl_desc.name = dev_name(&pdev->dev); | |
1328 | pctl->pctl_desc.owner = THIS_MODULE; | |
1329 | pctl->pctl_desc.pins = pins; | |
1330 | pctl->pctl_desc.npins = pctl->devdata->npins; | |
1331 | pctl->pctl_desc.confops = &mtk_pconf_ops; | |
1332 | pctl->pctl_desc.pctlops = &mtk_pctrl_ops; | |
1333 | pctl->pctl_desc.pmxops = &mtk_pmx_ops; | |
a6df410d | 1334 | pctl->dev = &pdev->dev; |
d48c2c02 HY |
1335 | |
1336 | pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl); | |
323de9ef | 1337 | if (IS_ERR(pctl->pctl_dev)) { |
a6df410d | 1338 | dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); |
323de9ef | 1339 | return PTR_ERR(pctl->pctl_dev); |
a6df410d HY |
1340 | } |
1341 | ||
1342 | pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); | |
1343 | if (!pctl->chip) { | |
1344 | ret = -ENOMEM; | |
1345 | goto pctrl_error; | |
1346 | } | |
1347 | ||
fc63d854 | 1348 | *pctl->chip = mtk_gpio_chip; |
a6df410d HY |
1349 | pctl->chip->ngpio = pctl->devdata->npins; |
1350 | pctl->chip->label = dev_name(&pdev->dev); | |
1351 | pctl->chip->dev = &pdev->dev; | |
fc59e66c | 1352 | pctl->chip->base = -1; |
a6df410d HY |
1353 | |
1354 | ret = gpiochip_add(pctl->chip); | |
1355 | if (ret) { | |
1356 | ret = -EINVAL; | |
1357 | goto pctrl_error; | |
1358 | } | |
1359 | ||
1360 | /* Register the GPIO to pin mappings. */ | |
1361 | ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), | |
1362 | 0, 0, pctl->devdata->npins); | |
1363 | if (ret) { | |
1364 | ret = -EINVAL; | |
1365 | goto chip_error; | |
1366 | } | |
1367 | ||
fc63d854 | 1368 | if (!of_property_read_bool(np, "interrupt-controller")) |
fc59e66c HY |
1369 | return 0; |
1370 | ||
d9819eb9 MM |
1371 | /* Get EINT register base from dts. */ |
1372 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1373 | if (!res) { | |
1374 | dev_err(&pdev->dev, "Unable to get Pinctrl resource\n"); | |
1375 | ret = -EINVAL; | |
1376 | goto chip_error; | |
1377 | } | |
1378 | ||
1379 | pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res); | |
1380 | if (IS_ERR(pctl->eint_reg_base)) { | |
1381 | ret = -EINVAL; | |
1382 | goto chip_error; | |
1383 | } | |
1384 | ||
58a5e1b6 MM |
1385 | ports_buf = pctl->devdata->eint_offsets.ports; |
1386 | pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf, | |
1387 | sizeof(*pctl->wake_mask), GFP_KERNEL); | |
1388 | if (!pctl->wake_mask) { | |
1389 | ret = -ENOMEM; | |
1390 | goto chip_error; | |
1391 | } | |
1392 | ||
1393 | pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf, | |
1394 | sizeof(*pctl->cur_mask), GFP_KERNEL); | |
1395 | if (!pctl->cur_mask) { | |
1396 | ret = -ENOMEM; | |
1397 | goto chip_error; | |
1398 | } | |
1399 | ||
0206caa8 AL |
1400 | pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, |
1401 | sizeof(int), GFP_KERNEL); | |
3221f40b YC |
1402 | if (!pctl->eint_dual_edges) { |
1403 | ret = -ENOMEM; | |
1404 | goto chip_error; | |
1405 | } | |
1406 | ||
d9819eb9 MM |
1407 | irq = irq_of_parse_and_map(np, 0); |
1408 | if (!irq) { | |
1409 | dev_err(&pdev->dev, "couldn't parse and map irq\n"); | |
1410 | ret = -EINVAL; | |
61a35576 | 1411 | goto chip_error; |
d9819eb9 MM |
1412 | } |
1413 | ||
1414 | pctl->domain = irq_domain_add_linear(np, | |
1415 | pctl->devdata->ap_num, &irq_domain_simple_ops, NULL); | |
1416 | if (!pctl->domain) { | |
1417 | dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); | |
1418 | ret = -ENOMEM; | |
61a35576 | 1419 | goto chip_error; |
d9819eb9 MM |
1420 | } |
1421 | ||
1422 | mtk_eint_init(pctl); | |
1423 | for (i = 0; i < pctl->devdata->ap_num; i++) { | |
1424 | int virq = irq_create_mapping(pctl->domain, i); | |
1425 | ||
1426 | irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, | |
1427 | handle_level_irq); | |
1428 | irq_set_chip_data(virq, pctl); | |
e4411899 | 1429 | } |
d9819eb9 | 1430 | |
1e105921 | 1431 | irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); |
a6df410d HY |
1432 | return 0; |
1433 | ||
1434 | chip_error: | |
1435 | gpiochip_remove(pctl->chip); | |
1436 | pctrl_error: | |
1437 | pinctrl_unregister(pctl->pctl_dev); | |
1438 | return ret; | |
1439 | } | |
1440 | ||
1441 | MODULE_LICENSE("GPL"); | |
1442 | MODULE_DESCRIPTION("MediaTek Pinctrl Driver"); | |
1443 | MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); |