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6ac73095 BG |
1 | /* |
2 | * Pin controller and GPIO driver for Amlogic Meson SoCs | |
3 | * | |
4 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * You should have received a copy of the GNU General Public License | |
11 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
12 | */ | |
13 | ||
14 | /* | |
15 | * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, | |
faa246de CC |
16 | * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and |
17 | * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a | |
18 | * variable number of pins. | |
6ac73095 BG |
19 | * |
20 | * The AO bank is special because it belongs to the Always-On power | |
21 | * domain which can't be powered off; the bank also uses a set of | |
22 | * registers different from the other banks. | |
23 | * | |
24 | * For each of the two power domains (regular and always-on) there are | |
25 | * 4 different register ranges that control the following properties | |
26 | * of the pins: | |
27 | * 1) pin muxing | |
28 | * 2) pull enable/disable | |
29 | * 3) pull up/down | |
30 | * 4) GPIO direction, output value, input value | |
31 | * | |
32 | * In some cases the register ranges for pull enable and pull | |
33 | * direction are the same and thus there are only 3 register ranges. | |
34 | * | |
35 | * Every pinmux group can be enabled by a specific bit in the first | |
36 | * register range of the domain; when all groups for a given pin are | |
37 | * disabled the pin acts as a GPIO. | |
38 | * | |
39 | * For the pull and GPIO configuration every bank uses a contiguous | |
40 | * set of bits in the register sets described above; the same register | |
41 | * can be shared by more banks with different offsets. | |
42 | * | |
43 | * In addition to this there are some registers shared between all | |
44 | * banks that control the IRQ functionality. This feature is not | |
45 | * supported at the moment by the driver. | |
46 | */ | |
47 | ||
48 | #include <linux/device.h> | |
49 | #include <linux/gpio.h> | |
50 | #include <linux/init.h> | |
51 | #include <linux/io.h> | |
52 | #include <linux/module.h> | |
53 | #include <linux/of.h> | |
54 | #include <linux/of_address.h> | |
55 | #include <linux/pinctrl/pinconf-generic.h> | |
56 | #include <linux/pinctrl/pinconf.h> | |
57 | #include <linux/pinctrl/pinctrl.h> | |
58 | #include <linux/pinctrl/pinmux.h> | |
59 | #include <linux/platform_device.h> | |
60 | #include <linux/regmap.h> | |
61 | #include <linux/seq_file.h> | |
62 | ||
63 | #include "../core.h" | |
64 | #include "../pinctrl-utils.h" | |
65 | #include "pinctrl-meson.h" | |
66 | ||
67 | /** | |
68 | * meson_get_bank() - find the bank containing a given pin | |
69 | * | |
70 | * @domain: the domain containing the pin | |
71 | * @pin: the pin number | |
72 | * @bank: the found bank | |
73 | * | |
74 | * Return: 0 on success, a negative value on error | |
75 | */ | |
76 | static int meson_get_bank(struct meson_domain *domain, unsigned int pin, | |
77 | struct meson_bank **bank) | |
78 | { | |
79 | int i; | |
80 | ||
81 | for (i = 0; i < domain->data->num_banks; i++) { | |
82 | if (pin >= domain->data->banks[i].first && | |
83 | pin <= domain->data->banks[i].last) { | |
84 | *bank = &domain->data->banks[i]; | |
85 | return 0; | |
86 | } | |
87 | } | |
88 | ||
89 | return -EINVAL; | |
90 | } | |
91 | ||
92 | /** | |
93 | * meson_get_domain_and_bank() - find domain and bank containing a given pin | |
94 | * | |
95 | * @pc: Meson pin controller device | |
96 | * @pin: the pin number | |
97 | * @domain: the found domain | |
98 | * @bank: the found bank | |
99 | * | |
100 | * Return: 0 on success, a negative value on error | |
101 | */ | |
102 | static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin, | |
103 | struct meson_domain **domain, | |
104 | struct meson_bank **bank) | |
105 | { | |
106 | struct meson_domain *d; | |
107 | int i; | |
108 | ||
109 | for (i = 0; i < pc->data->num_domains; i++) { | |
110 | d = &pc->domains[i]; | |
111 | if (pin >= d->data->pin_base && | |
112 | pin < d->data->pin_base + d->data->num_pins) { | |
113 | *domain = d; | |
114 | return meson_get_bank(d, pin, bank); | |
115 | } | |
116 | } | |
117 | ||
118 | return -EINVAL; | |
119 | } | |
120 | ||
121 | /** | |
122 | * meson_calc_reg_and_bit() - calculate register and bit for a pin | |
123 | * | |
124 | * @bank: the bank containing the pin | |
125 | * @pin: the pin number | |
126 | * @reg_type: the type of register needed (pull-enable, pull, etc...) | |
127 | * @reg: the computed register offset | |
128 | * @bit: the computed bit | |
129 | */ | |
130 | static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin, | |
131 | enum meson_reg_type reg_type, | |
132 | unsigned int *reg, unsigned int *bit) | |
133 | { | |
134 | struct meson_reg_desc *desc = &bank->regs[reg_type]; | |
135 | ||
136 | *reg = desc->reg * 4; | |
137 | *bit = desc->bit + pin - bank->first; | |
138 | } | |
139 | ||
140 | static int meson_get_groups_count(struct pinctrl_dev *pcdev) | |
141 | { | |
142 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
143 | ||
144 | return pc->data->num_groups; | |
145 | } | |
146 | ||
147 | static const char *meson_get_group_name(struct pinctrl_dev *pcdev, | |
148 | unsigned selector) | |
149 | { | |
150 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
151 | ||
152 | return pc->data->groups[selector].name; | |
153 | } | |
154 | ||
155 | static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector, | |
156 | const unsigned **pins, unsigned *num_pins) | |
157 | { | |
158 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
159 | ||
160 | *pins = pc->data->groups[selector].pins; | |
161 | *num_pins = pc->data->groups[selector].num_pins; | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s, | |
167 | unsigned offset) | |
168 | { | |
169 | seq_printf(s, " %s", dev_name(pcdev->dev)); | |
170 | } | |
171 | ||
172 | static const struct pinctrl_ops meson_pctrl_ops = { | |
173 | .get_groups_count = meson_get_groups_count, | |
174 | .get_group_name = meson_get_group_name, | |
175 | .get_group_pins = meson_get_group_pins, | |
176 | .dt_node_to_map = pinconf_generic_dt_node_to_map_all, | |
177 | .dt_free_map = pinctrl_utils_dt_free_map, | |
178 | .pin_dbg_show = meson_pin_dbg_show, | |
179 | }; | |
180 | ||
181 | /** | |
182 | * meson_pmx_disable_other_groups() - disable other groups using a given pin | |
183 | * | |
184 | * @pc: meson pin controller device | |
185 | * @pin: number of the pin | |
186 | * @sel_group: index of the selected group, or -1 if none | |
187 | * | |
188 | * The function disables all pinmux groups using a pin except the | |
189 | * selected one. If @sel_group is -1 all groups are disabled, leaving | |
190 | * the pin in GPIO mode. | |
191 | */ | |
192 | static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, | |
193 | unsigned int pin, int sel_group) | |
194 | { | |
195 | struct meson_pmx_group *group; | |
196 | struct meson_domain *domain; | |
197 | int i, j; | |
198 | ||
199 | for (i = 0; i < pc->data->num_groups; i++) { | |
200 | group = &pc->data->groups[i]; | |
201 | if (group->is_gpio || i == sel_group) | |
202 | continue; | |
203 | ||
204 | for (j = 0; j < group->num_pins; j++) { | |
205 | if (group->pins[j] == pin) { | |
206 | /* We have found a group using the pin */ | |
207 | domain = &pc->domains[group->domain]; | |
208 | regmap_update_bits(domain->reg_mux, | |
209 | group->reg * 4, | |
210 | BIT(group->bit), 0); | |
211 | } | |
212 | } | |
213 | } | |
214 | } | |
215 | ||
216 | static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, | |
217 | unsigned group_num) | |
218 | { | |
219 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
220 | struct meson_pmx_func *func = &pc->data->funcs[func_num]; | |
221 | struct meson_pmx_group *group = &pc->data->groups[group_num]; | |
222 | struct meson_domain *domain = &pc->domains[group->domain]; | |
223 | int i, ret = 0; | |
224 | ||
225 | dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, | |
226 | group->name); | |
227 | ||
228 | /* | |
229 | * Disable groups using the same pin. | |
230 | * The selected group is not disabled to avoid glitches. | |
231 | */ | |
232 | for (i = 0; i < group->num_pins; i++) | |
233 | meson_pmx_disable_other_groups(pc, group->pins[i], group_num); | |
234 | ||
235 | /* Function 0 (GPIO) doesn't need any additional setting */ | |
236 | if (func_num) | |
237 | ret = regmap_update_bits(domain->reg_mux, group->reg * 4, | |
238 | BIT(group->bit), BIT(group->bit)); | |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, | |
244 | struct pinctrl_gpio_range *range, | |
245 | unsigned offset) | |
246 | { | |
247 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
248 | ||
249 | meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) | |
255 | { | |
256 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
257 | ||
258 | return pc->data->num_funcs; | |
259 | } | |
260 | ||
261 | static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, | |
262 | unsigned selector) | |
263 | { | |
264 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
265 | ||
266 | return pc->data->funcs[selector].name; | |
267 | } | |
268 | ||
269 | static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, | |
270 | const char * const **groups, | |
271 | unsigned * const num_groups) | |
272 | { | |
273 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
274 | ||
275 | *groups = pc->data->funcs[selector].groups; | |
276 | *num_groups = pc->data->funcs[selector].num_groups; | |
277 | ||
278 | return 0; | |
279 | } | |
280 | ||
281 | static const struct pinmux_ops meson_pmx_ops = { | |
282 | .set_mux = meson_pmx_set_mux, | |
283 | .get_functions_count = meson_pmx_get_funcs_count, | |
284 | .get_function_name = meson_pmx_get_func_name, | |
285 | .get_function_groups = meson_pmx_get_groups, | |
286 | .gpio_request_enable = meson_pmx_request_gpio, | |
287 | }; | |
288 | ||
289 | static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, | |
290 | unsigned long *configs, unsigned num_configs) | |
291 | { | |
292 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
293 | struct meson_domain *domain; | |
294 | struct meson_bank *bank; | |
295 | enum pin_config_param param; | |
296 | unsigned int reg, bit; | |
297 | int i, ret; | |
298 | u16 arg; | |
299 | ||
300 | ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); | |
301 | if (ret) | |
302 | return ret; | |
303 | ||
304 | for (i = 0; i < num_configs; i++) { | |
305 | param = pinconf_to_config_param(configs[i]); | |
306 | arg = pinconf_to_config_argument(configs[i]); | |
307 | ||
308 | switch (param) { | |
309 | case PIN_CONFIG_BIAS_DISABLE: | |
310 | dev_dbg(pc->dev, "pin %u: disable bias\n", pin); | |
311 | ||
312 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
313 | ret = regmap_update_bits(domain->reg_pull, reg, | |
314 | BIT(bit), 0); | |
315 | if (ret) | |
316 | return ret; | |
317 | break; | |
318 | case PIN_CONFIG_BIAS_PULL_UP: | |
319 | dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin); | |
320 | ||
321 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, | |
322 | ®, &bit); | |
323 | ret = regmap_update_bits(domain->reg_pullen, reg, | |
324 | BIT(bit), BIT(bit)); | |
325 | if (ret) | |
326 | return ret; | |
327 | ||
328 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
329 | ret = regmap_update_bits(domain->reg_pull, reg, | |
330 | BIT(bit), BIT(bit)); | |
331 | if (ret) | |
332 | return ret; | |
333 | break; | |
334 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
335 | dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin); | |
336 | ||
337 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, | |
338 | ®, &bit); | |
339 | ret = regmap_update_bits(domain->reg_pullen, reg, | |
340 | BIT(bit), BIT(bit)); | |
341 | if (ret) | |
342 | return ret; | |
343 | ||
344 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
345 | ret = regmap_update_bits(domain->reg_pull, reg, | |
346 | BIT(bit), 0); | |
347 | if (ret) | |
348 | return ret; | |
349 | break; | |
350 | default: | |
351 | return -ENOTSUPP; | |
352 | } | |
353 | } | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin) | |
359 | { | |
360 | struct meson_domain *domain; | |
361 | struct meson_bank *bank; | |
362 | unsigned int reg, bit, val; | |
363 | int ret, conf; | |
364 | ||
365 | ret = meson_get_domain_and_bank(pc, pin, &domain, &bank); | |
366 | if (ret) | |
367 | return ret; | |
368 | ||
369 | meson_calc_reg_and_bit(bank, pin, REG_PULLEN, ®, &bit); | |
370 | ||
371 | ret = regmap_read(domain->reg_pullen, reg, &val); | |
372 | if (ret) | |
373 | return ret; | |
374 | ||
375 | if (!(val & BIT(bit))) { | |
376 | conf = PIN_CONFIG_BIAS_DISABLE; | |
377 | } else { | |
378 | meson_calc_reg_and_bit(bank, pin, REG_PULL, ®, &bit); | |
379 | ||
380 | ret = regmap_read(domain->reg_pull, reg, &val); | |
381 | if (ret) | |
382 | return ret; | |
383 | ||
384 | if (val & BIT(bit)) | |
385 | conf = PIN_CONFIG_BIAS_PULL_UP; | |
386 | else | |
387 | conf = PIN_CONFIG_BIAS_PULL_DOWN; | |
388 | } | |
389 | ||
390 | return conf; | |
391 | } | |
392 | ||
393 | static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin, | |
394 | unsigned long *config) | |
395 | { | |
396 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
397 | enum pin_config_param param = pinconf_to_config_param(*config); | |
398 | u16 arg; | |
399 | ||
400 | switch (param) { | |
401 | case PIN_CONFIG_BIAS_DISABLE: | |
402 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
403 | case PIN_CONFIG_BIAS_PULL_UP: | |
404 | if (meson_pinconf_get_pull(pc, pin) == param) | |
405 | arg = 1; | |
406 | else | |
407 | return -EINVAL; | |
408 | break; | |
409 | default: | |
410 | return -ENOTSUPP; | |
411 | } | |
412 | ||
413 | *config = pinconf_to_config_packed(param, arg); | |
414 | dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, | |
420 | unsigned int num_group, | |
421 | unsigned long *configs, unsigned num_configs) | |
422 | { | |
423 | struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); | |
424 | struct meson_pmx_group *group = &pc->data->groups[num_group]; | |
425 | int i; | |
426 | ||
427 | dev_dbg(pc->dev, "set pinconf for group %s\n", group->name); | |
428 | ||
429 | for (i = 0; i < group->num_pins; i++) { | |
430 | meson_pinconf_set(pcdev, group->pins[i], configs, | |
431 | num_configs); | |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, | |
438 | unsigned int group, unsigned long *config) | |
439 | { | |
440 | return -ENOSYS; | |
441 | } | |
442 | ||
443 | static const struct pinconf_ops meson_pinconf_ops = { | |
444 | .pin_config_get = meson_pinconf_get, | |
445 | .pin_config_set = meson_pinconf_set, | |
446 | .pin_config_group_get = meson_pinconf_group_get, | |
447 | .pin_config_group_set = meson_pinconf_group_set, | |
448 | .is_generic = true, | |
449 | }; | |
450 | ||
6ac73095 BG |
451 | static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) |
452 | { | |
453 | return pinctrl_request_gpio(chip->base + gpio); | |
454 | } | |
455 | ||
456 | static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) | |
457 | { | |
827c93da | 458 | struct meson_domain *domain = gpiochip_get_data(chip); |
6ac73095 BG |
459 | |
460 | pinctrl_free_gpio(domain->data->pin_base + gpio); | |
461 | } | |
462 | ||
463 | static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
464 | { | |
827c93da | 465 | struct meson_domain *domain = gpiochip_get_data(chip); |
6ac73095 BG |
466 | unsigned int reg, bit, pin; |
467 | struct meson_bank *bank; | |
468 | int ret; | |
469 | ||
470 | pin = domain->data->pin_base + gpio; | |
471 | ret = meson_get_bank(domain, pin, &bank); | |
472 | if (ret) | |
473 | return ret; | |
474 | ||
475 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); | |
476 | ||
477 | return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit)); | |
478 | } | |
479 | ||
480 | static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, | |
481 | int value) | |
482 | { | |
827c93da | 483 | struct meson_domain *domain = gpiochip_get_data(chip); |
6ac73095 BG |
484 | unsigned int reg, bit, pin; |
485 | struct meson_bank *bank; | |
486 | int ret; | |
487 | ||
488 | pin = domain->data->pin_base + gpio; | |
489 | ret = meson_get_bank(domain, pin, &bank); | |
490 | if (ret) | |
491 | return ret; | |
492 | ||
493 | meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); | |
494 | ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0); | |
495 | if (ret) | |
496 | return ret; | |
497 | ||
498 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); | |
499 | return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), | |
500 | value ? BIT(bit) : 0); | |
501 | } | |
502 | ||
503 | static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) | |
504 | { | |
827c93da | 505 | struct meson_domain *domain = gpiochip_get_data(chip); |
6ac73095 BG |
506 | unsigned int reg, bit, pin; |
507 | struct meson_bank *bank; | |
508 | int ret; | |
509 | ||
510 | pin = domain->data->pin_base + gpio; | |
511 | ret = meson_get_bank(domain, pin, &bank); | |
512 | if (ret) | |
513 | return; | |
514 | ||
515 | meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); | |
516 | regmap_update_bits(domain->reg_gpio, reg, BIT(bit), | |
517 | value ? BIT(bit) : 0); | |
518 | } | |
519 | ||
520 | static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
521 | { | |
827c93da | 522 | struct meson_domain *domain = gpiochip_get_data(chip); |
6ac73095 BG |
523 | unsigned int reg, bit, val, pin; |
524 | struct meson_bank *bank; | |
525 | int ret; | |
526 | ||
527 | pin = domain->data->pin_base + gpio; | |
528 | ret = meson_get_bank(domain, pin, &bank); | |
529 | if (ret) | |
530 | return ret; | |
531 | ||
532 | meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); | |
533 | regmap_read(domain->reg_gpio, reg, &val); | |
534 | ||
535 | return !!(val & BIT(bit)); | |
536 | } | |
537 | ||
538 | static const struct of_device_id meson_pinctrl_dt_match[] = { | |
539 | { | |
540 | .compatible = "amlogic,meson8-pinctrl", | |
541 | .data = &meson8_pinctrl_data, | |
542 | }, | |
0fefcb68 CC |
543 | { |
544 | .compatible = "amlogic,meson8b-pinctrl", | |
545 | .data = &meson8b_pinctrl_data, | |
546 | }, | |
6ac73095 BG |
547 | { }, |
548 | }; | |
549 | MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match); | |
550 | ||
551 | static int meson_gpiolib_register(struct meson_pinctrl *pc) | |
552 | { | |
553 | struct meson_domain *domain; | |
554 | int i, ret; | |
555 | ||
556 | for (i = 0; i < pc->data->num_domains; i++) { | |
557 | domain = &pc->domains[i]; | |
558 | ||
559 | domain->chip.label = domain->data->name; | |
58383c78 | 560 | domain->chip.parent = pc->dev; |
6ac73095 BG |
561 | domain->chip.request = meson_gpio_request; |
562 | domain->chip.free = meson_gpio_free; | |
563 | domain->chip.direction_input = meson_gpio_direction_input; | |
564 | domain->chip.direction_output = meson_gpio_direction_output; | |
565 | domain->chip.get = meson_gpio_get; | |
566 | domain->chip.set = meson_gpio_set; | |
984cffde | 567 | domain->chip.base = domain->data->pin_base; |
6ac73095 BG |
568 | domain->chip.ngpio = domain->data->num_pins; |
569 | domain->chip.can_sleep = false; | |
570 | domain->chip.of_node = domain->of_node; | |
571 | domain->chip.of_gpio_n_cells = 2; | |
572 | ||
827c93da | 573 | ret = gpiochip_add_data(&domain->chip, domain); |
6ac73095 BG |
574 | if (ret) { |
575 | dev_err(pc->dev, "can't add gpio chip %s\n", | |
576 | domain->data->name); | |
577 | goto fail; | |
578 | } | |
579 | ||
580 | ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev), | |
581 | 0, domain->data->pin_base, | |
582 | domain->chip.ngpio); | |
583 | if (ret) { | |
584 | dev_err(pc->dev, "can't add pin range\n"); | |
585 | goto fail; | |
586 | } | |
587 | } | |
588 | ||
589 | return 0; | |
590 | fail: | |
591 | for (i--; i >= 0; i--) | |
592 | gpiochip_remove(&pc->domains[i].chip); | |
593 | ||
594 | return ret; | |
595 | } | |
596 | ||
597 | static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc, | |
598 | struct device_node *np) | |
599 | { | |
600 | int i; | |
601 | ||
602 | for (i = 0; i < pc->data->num_domains; i++) { | |
603 | if (!strcmp(np->name, pc->data->domain_data[i].name)) | |
604 | return &pc->data->domain_data[i]; | |
605 | } | |
606 | ||
607 | return NULL; | |
608 | } | |
609 | ||
610 | static struct regmap_config meson_regmap_config = { | |
611 | .reg_bits = 32, | |
612 | .val_bits = 32, | |
613 | .reg_stride = 4, | |
614 | }; | |
615 | ||
616 | static struct regmap *meson_map_resource(struct meson_pinctrl *pc, | |
617 | struct device_node *node, char *name) | |
618 | { | |
619 | struct resource res; | |
620 | void __iomem *base; | |
621 | int i; | |
622 | ||
623 | i = of_property_match_string(node, "reg-names", name); | |
624 | if (of_address_to_resource(node, i, &res)) | |
625 | return ERR_PTR(-ENOENT); | |
626 | ||
627 | base = devm_ioremap_resource(pc->dev, &res); | |
628 | if (IS_ERR(base)) | |
629 | return ERR_CAST(base); | |
630 | ||
631 | meson_regmap_config.max_register = resource_size(&res) - 4; | |
632 | meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL, | |
633 | "%s-%s", node->name, | |
634 | name); | |
635 | if (!meson_regmap_config.name) | |
636 | return ERR_PTR(-ENOMEM); | |
637 | ||
638 | return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); | |
639 | } | |
640 | ||
641 | static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, | |
642 | struct device_node *node) | |
643 | { | |
644 | struct device_node *np; | |
645 | struct meson_domain *domain; | |
646 | int i = 0, num_domains = 0; | |
647 | ||
648 | for_each_child_of_node(node, np) { | |
649 | if (!of_find_property(np, "gpio-controller", NULL)) | |
650 | continue; | |
651 | num_domains++; | |
652 | } | |
653 | ||
654 | if (num_domains != pc->data->num_domains) { | |
655 | dev_err(pc->dev, "wrong number of subnodes\n"); | |
656 | return -EINVAL; | |
657 | } | |
658 | ||
659 | pc->domains = devm_kzalloc(pc->dev, num_domains * | |
660 | sizeof(struct meson_domain), GFP_KERNEL); | |
661 | if (!pc->domains) | |
662 | return -ENOMEM; | |
663 | ||
664 | for_each_child_of_node(node, np) { | |
665 | if (!of_find_property(np, "gpio-controller", NULL)) | |
666 | continue; | |
667 | ||
668 | domain = &pc->domains[i]; | |
669 | ||
670 | domain->data = meson_get_domain_data(pc, np); | |
671 | if (!domain->data) { | |
672 | dev_err(pc->dev, "domain data not found for node %s\n", | |
673 | np->name); | |
674 | return -ENODEV; | |
675 | } | |
676 | ||
677 | domain->of_node = np; | |
678 | ||
679 | domain->reg_mux = meson_map_resource(pc, np, "mux"); | |
680 | if (IS_ERR(domain->reg_mux)) { | |
681 | dev_err(pc->dev, "mux registers not found\n"); | |
682 | return PTR_ERR(domain->reg_mux); | |
683 | } | |
684 | ||
685 | domain->reg_pull = meson_map_resource(pc, np, "pull"); | |
686 | if (IS_ERR(domain->reg_pull)) { | |
687 | dev_err(pc->dev, "pull registers not found\n"); | |
688 | return PTR_ERR(domain->reg_pull); | |
689 | } | |
690 | ||
691 | domain->reg_pullen = meson_map_resource(pc, np, "pull-enable"); | |
692 | /* Use pull region if pull-enable one is not present */ | |
693 | if (IS_ERR(domain->reg_pullen)) | |
694 | domain->reg_pullen = domain->reg_pull; | |
695 | ||
696 | domain->reg_gpio = meson_map_resource(pc, np, "gpio"); | |
697 | if (IS_ERR(domain->reg_gpio)) { | |
698 | dev_err(pc->dev, "gpio registers not found\n"); | |
699 | return PTR_ERR(domain->reg_gpio); | |
700 | } | |
701 | ||
702 | i++; | |
703 | } | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | static int meson_pinctrl_probe(struct platform_device *pdev) | |
709 | { | |
710 | const struct of_device_id *match; | |
711 | struct device *dev = &pdev->dev; | |
712 | struct meson_pinctrl *pc; | |
713 | int ret; | |
714 | ||
715 | pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL); | |
716 | if (!pc) | |
717 | return -ENOMEM; | |
718 | ||
719 | pc->dev = dev; | |
720 | match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); | |
721 | pc->data = (struct meson_pinctrl_data *)match->data; | |
722 | ||
723 | ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
727 | pc->desc.name = "pinctrl-meson"; | |
728 | pc->desc.owner = THIS_MODULE; | |
729 | pc->desc.pctlops = &meson_pctrl_ops; | |
730 | pc->desc.pmxops = &meson_pmx_ops; | |
731 | pc->desc.confops = &meson_pinconf_ops; | |
732 | pc->desc.pins = pc->data->pins; | |
733 | pc->desc.npins = pc->data->num_pins; | |
734 | ||
735 | pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc); | |
323de9ef | 736 | if (IS_ERR(pc->pcdev)) { |
6ac73095 | 737 | dev_err(pc->dev, "can't register pinctrl device"); |
323de9ef | 738 | return PTR_ERR(pc->pcdev); |
6ac73095 BG |
739 | } |
740 | ||
741 | ret = meson_gpiolib_register(pc); | |
742 | if (ret) { | |
743 | pinctrl_unregister(pc->pcdev); | |
744 | return ret; | |
745 | } | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
750 | static struct platform_driver meson_pinctrl_driver = { | |
751 | .probe = meson_pinctrl_probe, | |
752 | .driver = { | |
753 | .name = "meson-pinctrl", | |
754 | .of_match_table = meson_pinctrl_dt_match, | |
755 | }, | |
756 | }; | |
757 | module_platform_driver(meson_pinctrl_driver); | |
758 | ||
759 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); | |
760 | MODULE_DESCRIPTION("Amlogic Meson pinctrl driver"); | |
761 | MODULE_LICENSE("GPL v2"); |