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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / drivers / pinctrl / meson / pinctrl-meson.c
CommitLineData
6ac73095
BG		 1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14/*
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
17 * each bank has a variable number of pins.
18 *
19 * The AO bank is special because it belongs to the Always-On power
20 * domain which can't be powered off; the bank also uses a set of
21 * registers different from the other banks.
22 *
23 * For each of the two power domains (regular and always-on) there are
24 * 4 different register ranges that control the following properties
25 * of the pins:
26 * 1) pin muxing
27 * 2) pull enable/disable
28 * 3) pull up/down
29 * 4) GPIO direction, output value, input value
30 *
31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges.
33 *
34 * Every pinmux group can be enabled by a specific bit in the first
35 * register range of the domain; when all groups for a given pin are
36 * disabled the pin acts as a GPIO.
37 *
38 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets.
41 *
42 * In addition to this there are some registers shared between all
43 * banks that control the IRQ functionality. This feature is not
44 * supported at the moment by the driver.
45 */
46
47#include <linux/device.h>
48#include <linux/gpio.h>
49#include <linux/init.h>
50#include <linux/io.h>
51#include <linux/module.h>
52#include <linux/of.h>
53#include <linux/of_address.h>
54#include <linux/pinctrl/pinconf-generic.h>
55#include <linux/pinctrl/pinconf.h>
56#include <linux/pinctrl/pinctrl.h>
57#include <linux/pinctrl/pinmux.h>
58#include <linux/platform_device.h>
59#include <linux/regmap.h>
60#include <linux/seq_file.h>
61
62#include "../core.h"
63#include "../pinctrl-utils.h"
64#include "pinctrl-meson.h"
65
66/**
67 * meson_get_bank() - find the bank containing a given pin
68 *
69 * @domain: the domain containing the pin
70 * @pin: the pin number
71 * @bank: the found bank
72 *
73 * Return: 0 on success, a negative value on error
74 */
75static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
76 struct meson_bank **bank)
77{
78 int i;
79
80 for (i = 0; i < domain->data->num_banks; i++) {
81 if (pin >= domain->data->banks[i].first &&
82 pin <= domain->data->banks[i].last) {
83 *bank = &domain->data->banks[i];
84 return 0;
85 }
86 }
87
88 return -EINVAL;
89}
90
91/**
92 * meson_get_domain_and_bank() - find domain and bank containing a given pin
93 *
94 * @pc: Meson pin controller device
95 * @pin: the pin number
96 * @domain: the found domain
97 * @bank: the found bank
98 *
99 * Return: 0 on success, a negative value on error
100 */
101static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
102 struct meson_domain **domain,
103 struct meson_bank **bank)
104{
105 struct meson_domain *d;
106 int i;
107
108 for (i = 0; i < pc->data->num_domains; i++) {
109 d = &pc->domains[i];
110 if (pin >= d->data->pin_base &&
111 pin < d->data->pin_base + d->data->num_pins) {
112 *domain = d;
113 return meson_get_bank(d, pin, bank);
114 }
115 }
116
117 return -EINVAL;
118}
119
120/**
121 * meson_calc_reg_and_bit() - calculate register and bit for a pin
122 *
123 * @bank: the bank containing the pin
124 * @pin: the pin number
125 * @reg_type: the type of register needed (pull-enable, pull, etc...)
126 * @reg: the computed register offset
127 * @bit: the computed bit
128 */
129static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
130 enum meson_reg_type reg_type,
131 unsigned int *reg, unsigned int *bit)
132{
133 struct meson_reg_desc *desc = &bank->regs[reg_type];
134
135 *reg = desc->reg * 4;
136 *bit = desc->bit + pin - bank->first;
137}
138
139static int meson_get_groups_count(struct pinctrl_dev *pcdev)
140{
141 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
142
143 return pc->data->num_groups;
144}
145
146static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
147 unsigned selector)
148{
149 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
150
151 return pc->data->groups[selector].name;
152}
153
154static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
155 const unsigned **pins, unsigned *num_pins)
156{
157 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
158
159 *pins = pc->data->groups[selector].pins;
160 *num_pins = pc->data->groups[selector].num_pins;
161
162 return 0;
163}
164
165static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
166 unsigned offset)
167{
168 seq_printf(s, " %s", dev_name(pcdev->dev));
169}
170
171static const struct pinctrl_ops meson_pctrl_ops = {
172 .get_groups_count = meson_get_groups_count,
173 .get_group_name = meson_get_group_name,
174 .get_group_pins = meson_get_group_pins,
175 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
176 .dt_free_map = pinctrl_utils_dt_free_map,
177 .pin_dbg_show = meson_pin_dbg_show,
178};
179
180/**
181 * meson_pmx_disable_other_groups() - disable other groups using a given pin
182 *
183 * @pc: meson pin controller device
184 * @pin: number of the pin
185 * @sel_group: index of the selected group, or -1 if none
186 *
187 * The function disables all pinmux groups using a pin except the
188 * selected one. If @sel_group is -1 all groups are disabled, leaving
189 * the pin in GPIO mode.
190 */
191static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
192 unsigned int pin, int sel_group)
193{
194 struct meson_pmx_group *group;
195 struct meson_domain *domain;
196 int i, j;
197
198 for (i = 0; i < pc->data->num_groups; i++) {
199 group = &pc->data->groups[i];
200 if (group->is_gpio || i == sel_group)
201 continue;
202
203 for (j = 0; j < group->num_pins; j++) {
204 if (group->pins[j] == pin) {
205 /* We have found a group using the pin */
206 domain = &pc->domains[group->domain];
207 regmap_update_bits(domain->reg_mux,
208 group->reg * 4,
209 BIT(group->bit), 0);
210 }
211 }
212 }
213}
214
215static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
216 unsigned group_num)
217{
218 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
219 struct meson_pmx_func *func = &pc->data->funcs[func_num];
220 struct meson_pmx_group *group = &pc->data->groups[group_num];
221 struct meson_domain *domain = &pc->domains[group->domain];
222 int i, ret = 0;
223
224 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
225 group->name);
226
227 /*
228 * Disable groups using the same pin.
229 * The selected group is not disabled to avoid glitches.
230 */
231 for (i = 0; i < group->num_pins; i++)
232 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
233
234 /* Function 0 (GPIO) doesn't need any additional setting */
235 if (func_num)
236 ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
237 BIT(group->bit), BIT(group->bit));
238
239 return ret;
240}
241
242static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
243 struct pinctrl_gpio_range *range,
244 unsigned offset)
245{
246 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
247
248 meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
249
250 return 0;
251}
252
253static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
254{
255 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
256
257 return pc->data->num_funcs;
258}
259
260static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
261 unsigned selector)
262{
263 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
264
265 return pc->data->funcs[selector].name;
266}
267
268static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
269 const char * const **groups,
270 unsigned * const num_groups)
271{
272 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
273
274 *groups = pc->data->funcs[selector].groups;
275 *num_groups = pc->data->funcs[selector].num_groups;
276
277 return 0;
278}
279
280static const struct pinmux_ops meson_pmx_ops = {
281 .set_mux = meson_pmx_set_mux,
282 .get_functions_count = meson_pmx_get_funcs_count,
283 .get_function_name = meson_pmx_get_func_name,
284 .get_function_groups = meson_pmx_get_groups,
285 .gpio_request_enable = meson_pmx_request_gpio,
286};
287
288static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
289 unsigned long *configs, unsigned num_configs)
290{
291 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
292 struct meson_domain *domain;
293 struct meson_bank *bank;
294 enum pin_config_param param;
295 unsigned int reg, bit;
296 int i, ret;
297 u16 arg;
298
299 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
300 if (ret)
301 return ret;
302
303 for (i = 0; i < num_configs; i++) {
304 param = pinconf_to_config_param(configs[i]);
305 arg = pinconf_to_config_argument(configs[i]);
306
307 switch (param) {
308 case PIN_CONFIG_BIAS_DISABLE:
309 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
310
311 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
312 ret = regmap_update_bits(domain->reg_pull, reg,
313 BIT(bit), 0);
314 if (ret)
315 return ret;
316 break;
317 case PIN_CONFIG_BIAS_PULL_UP:
318 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
319
320 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
321 &reg, &bit);
322 ret = regmap_update_bits(domain->reg_pullen, reg,
323 BIT(bit), BIT(bit));
324 if (ret)
325 return ret;
326
327 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
328 ret = regmap_update_bits(domain->reg_pull, reg,
329 BIT(bit), BIT(bit));
330 if (ret)
331 return ret;
332 break;
333 case PIN_CONFIG_BIAS_PULL_DOWN:
334 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
335
336 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
337 &reg, &bit);
338 ret = regmap_update_bits(domain->reg_pullen, reg,
339 BIT(bit), BIT(bit));
340 if (ret)
341 return ret;
342
343 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
344 ret = regmap_update_bits(domain->reg_pull, reg,
345 BIT(bit), 0);
346 if (ret)
347 return ret;
348 break;
349 default:
350 return -ENOTSUPP;
351 }
352 }
353
354 return 0;
355}
356
357static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
358{
359 struct meson_domain *domain;
360 struct meson_bank *bank;
361 unsigned int reg, bit, val;
362 int ret, conf;
363
364 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
365 if (ret)
366 return ret;
367
368 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
369
370 ret = regmap_read(domain->reg_pullen, reg, &val);
371 if (ret)
372 return ret;
373
374 if (!(val & BIT(bit))) {
375 conf = PIN_CONFIG_BIAS_DISABLE;
376 } else {
377 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
378
379 ret = regmap_read(domain->reg_pull, reg, &val);
380 if (ret)
381 return ret;
382
383 if (val & BIT(bit))
384 conf = PIN_CONFIG_BIAS_PULL_UP;
385 else
386 conf = PIN_CONFIG_BIAS_PULL_DOWN;
387 }
388
389 return conf;
390}
391
392static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
393 unsigned long *config)
394{
395 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
396 enum pin_config_param param = pinconf_to_config_param(*config);
397 u16 arg;
398
399 switch (param) {
400 case PIN_CONFIG_BIAS_DISABLE:
401 case PIN_CONFIG_BIAS_PULL_DOWN:
402 case PIN_CONFIG_BIAS_PULL_UP:
403 if (meson_pinconf_get_pull(pc, pin) == param)
404 arg = 1;
405 else
406 return -EINVAL;
407 break;
408 default:
409 return -ENOTSUPP;
410 }
411
412 *config = pinconf_to_config_packed(param, arg);
413 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
414
415 return 0;
416}
417
418static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
419 unsigned int num_group,
420 unsigned long *configs, unsigned num_configs)
421{
422 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
423 struct meson_pmx_group *group = &pc->data->groups[num_group];
424 int i;
425
426 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
427
428 for (i = 0; i < group->num_pins; i++) {
429 meson_pinconf_set(pcdev, group->pins[i], configs,
430 num_configs);
431 }
432
433 return 0;
434}
435
436static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
437 unsigned int group, unsigned long *config)
438{
439 return -ENOSYS;
440}
441
442static const struct pinconf_ops meson_pinconf_ops = {
443 .pin_config_get = meson_pinconf_get,
444 .pin_config_set = meson_pinconf_set,
445 .pin_config_group_get = meson_pinconf_group_get,
446 .pin_config_group_set = meson_pinconf_group_set,
447 .is_generic = true,
448};
449
450static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
451{
452 return container_of(chip, struct meson_domain, chip);
453}
454
455static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
456{
457 return pinctrl_request_gpio(chip->base + gpio);
458}
459
460static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
461{
462 struct meson_domain *domain = to_meson_domain(chip);
463
464 pinctrl_free_gpio(domain->data->pin_base + gpio);
465}
466
467static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
468{
469 struct meson_domain *domain = to_meson_domain(chip);
470 unsigned int reg, bit, pin;
471 struct meson_bank *bank;
472 int ret;
473
474 pin = domain->data->pin_base + gpio;
475 ret = meson_get_bank(domain, pin, &bank);
476 if (ret)
477 return ret;
478
479 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
480
481 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
482}
483
484static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
485 int value)
486{
487 struct meson_domain *domain = to_meson_domain(chip);
488 unsigned int reg, bit, pin;
489 struct meson_bank *bank;
490 int ret;
491
492 pin = domain->data->pin_base + gpio;
493 ret = meson_get_bank(domain, pin, &bank);
494 if (ret)
495 return ret;
496
497 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
498 ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
499 if (ret)
500 return ret;
501
502 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
503 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
504 value ? BIT(bit) : 0);
505}
506
507static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
508{
509 struct meson_domain *domain = to_meson_domain(chip);
510 unsigned int reg, bit, pin;
511 struct meson_bank *bank;
512 int ret;
513
514 pin = domain->data->pin_base + gpio;
515 ret = meson_get_bank(domain, pin, &bank);
516 if (ret)
517 return;
518
519 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
520 regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
521 value ? BIT(bit) : 0);
522}
523
524static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
525{
526 struct meson_domain *domain = to_meson_domain(chip);
527 unsigned int reg, bit, val, pin;
528 struct meson_bank *bank;
529 int ret;
530
531 pin = domain->data->pin_base + gpio;
532 ret = meson_get_bank(domain, pin, &bank);
533 if (ret)
534 return ret;
535
536 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit);
537 regmap_read(domain->reg_gpio, reg, &val);
538
539 return !!(val & BIT(bit));
540}
541
542static const struct of_device_id meson_pinctrl_dt_match[] = {
543 {
544 .compatible = "amlogic,meson8-pinctrl",
545 .data = &meson8_pinctrl_data,
546 },
547 { },
548};
549MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
550
551static int meson_gpiolib_register(struct meson_pinctrl *pc)
552{
553 struct meson_domain *domain;
554 int i, ret;
555
556 for (i = 0; i < pc->data->num_domains; i++) {
557 domain = &pc->domains[i];
558
559 domain->chip.label = domain->data->name;
560 domain->chip.dev = pc->dev;
561 domain->chip.request = meson_gpio_request;
562 domain->chip.free = meson_gpio_free;
563 domain->chip.direction_input = meson_gpio_direction_input;
564 domain->chip.direction_output = meson_gpio_direction_output;
565 domain->chip.get = meson_gpio_get;
566 domain->chip.set = meson_gpio_set;
567 domain->chip.base = -1;
568 domain->chip.ngpio = domain->data->num_pins;
569 domain->chip.can_sleep = false;
570 domain->chip.of_node = domain->of_node;
571 domain->chip.of_gpio_n_cells = 2;
572
573 ret = gpiochip_add(&domain->chip);
574 if (ret) {
575 dev_err(pc->dev, "can't add gpio chip %s\n",
576 domain->data->name);
577 goto fail;
578 }
579
580 ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
581 0, domain->data->pin_base,
582 domain->chip.ngpio);
583 if (ret) {
584 dev_err(pc->dev, "can't add pin range\n");
585 goto fail;
586 }
587 }
588
589 return 0;
590fail:
591 for (i--; i >= 0; i--)
592 gpiochip_remove(&pc->domains[i].chip);
593
594 return ret;
595}
596
597static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
598 struct device_node *np)
599{
600 int i;
601
602 for (i = 0; i < pc->data->num_domains; i++) {
603 if (!strcmp(np->name, pc->data->domain_data[i].name))
604 return &pc->data->domain_data[i];
605 }
606
607 return NULL;
608}
609
610static struct regmap_config meson_regmap_config = {
611 .reg_bits = 32,
612 .val_bits = 32,
613 .reg_stride = 4,
614};
615
616static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
617 struct device_node *node, char *name)
618{
619 struct resource res;
620 void __iomem *base;
621 int i;
622
623 i = of_property_match_string(node, "reg-names", name);
624 if (of_address_to_resource(node, i, &res))
625 return ERR_PTR(-ENOENT);
626
627 base = devm_ioremap_resource(pc->dev, &res);
628 if (IS_ERR(base))
629 return ERR_CAST(base);
630
631 meson_regmap_config.max_register = resource_size(&res) - 4;
632 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
633 "%s-%s", node->name,
634 name);
635 if (!meson_regmap_config.name)
636 return ERR_PTR(-ENOMEM);
637
638 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
639}
640
641static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
642 struct device_node *node)
643{
644 struct device_node *np;
645 struct meson_domain *domain;
646 int i = 0, num_domains = 0;
647
648 for_each_child_of_node(node, np) {
649 if (!of_find_property(np, "gpio-controller", NULL))
650 continue;
651 num_domains++;
652 }
653
654 if (num_domains != pc->data->num_domains) {
655 dev_err(pc->dev, "wrong number of subnodes\n");
656 return -EINVAL;
657 }
658
659 pc->domains = devm_kzalloc(pc->dev, num_domains *
660 sizeof(struct meson_domain), GFP_KERNEL);
661 if (!pc->domains)
662 return -ENOMEM;
663
664 for_each_child_of_node(node, np) {
665 if (!of_find_property(np, "gpio-controller", NULL))
666 continue;
667
668 domain = &pc->domains[i];
669
670 domain->data = meson_get_domain_data(pc, np);
671 if (!domain->data) {
672 dev_err(pc->dev, "domain data not found for node %s\n",
673 np->name);
674 return -ENODEV;
675 }
676
677 domain->of_node = np;
678
679 domain->reg_mux = meson_map_resource(pc, np, "mux");
680 if (IS_ERR(domain->reg_mux)) {
681 dev_err(pc->dev, "mux registers not found\n");
682 return PTR_ERR(domain->reg_mux);
683 }
684
685 domain->reg_pull = meson_map_resource(pc, np, "pull");
686 if (IS_ERR(domain->reg_pull)) {
687 dev_err(pc->dev, "pull registers not found\n");
688 return PTR_ERR(domain->reg_pull);
689 }
690
691 domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
692 /* Use pull region if pull-enable one is not present */
693 if (IS_ERR(domain->reg_pullen))
694 domain->reg_pullen = domain->reg_pull;
695
696 domain->reg_gpio = meson_map_resource(pc, np, "gpio");
697 if (IS_ERR(domain->reg_gpio)) {
698 dev_err(pc->dev, "gpio registers not found\n");
699 return PTR_ERR(domain->reg_gpio);
700 }
701
702 i++;
703 }
704
705 return 0;
706}
707
708static int meson_pinctrl_probe(struct platform_device *pdev)
709{
710 const struct of_device_id *match;
711 struct device *dev = &pdev->dev;
712 struct meson_pinctrl *pc;
713 int ret;
714
715 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
716 if (!pc)
717 return -ENOMEM;
718
719 pc->dev = dev;
720 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
721 pc->data = (struct meson_pinctrl_data *)match->data;
722
723 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
724 if (ret)
725 return ret;
726
727 pc->desc.name = "pinctrl-meson";
728 pc->desc.owner = THIS_MODULE;
729 pc->desc.pctlops = &meson_pctrl_ops;
730 pc->desc.pmxops = &meson_pmx_ops;
731 pc->desc.confops = &meson_pinconf_ops;
732 pc->desc.pins = pc->data->pins;
733 pc->desc.npins = pc->data->num_pins;
734
735 pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
736 if (!pc->pcdev) {
737 dev_err(pc->dev, "can't register pinctrl device");
738 return -EINVAL;
739 }
740
741 ret = meson_gpiolib_register(pc);
742 if (ret) {
743 pinctrl_unregister(pc->pcdev);
744 return ret;
745 }
746
747 return 0;
748}
749
750static struct platform_driver meson_pinctrl_driver = {
751 .probe = meson_pinctrl_probe,
752 .driver = {
753 .name = "meson-pinctrl",
754 .of_match_table = meson_pinctrl_dt_match,
755 },
756};
757module_platform_driver(meson_pinctrl_driver);
758
759MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
760MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
761MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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