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Merge remote-tracking branch 'pinctrl/for-next'
[deliverable/linux.git] / drivers / pinctrl / nomadik / pinctrl-abx500.c
CommitLineData
0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
8b51fad0
PG		 7 * Driver allows to use AxB5xx unused pins to be used as GPIO
8 *
0493e649
PC		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/slab.h>
16#include <linux/init.h>
0493e649 17#include <linux/err.h>
f30a3839
LJ		 18#include <linux/of.h>
19#include <linux/of_device.h>
0493e649
PC		 20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/irq.h>
ac652d79 23#include <linux/irqdomain.h>
0493e649
PC		 24#include <linux/interrupt.h>
25#include <linux/bitops.h>
26#include <linux/mfd/abx500.h>
27#include <linux/mfd/abx500/ab8500.h>
0493e649
PC		 28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinconf-generic.h>
64a45c98 33#include <linux/pinctrl/machine.h>
0493e649
PC		 34
35#include "pinctrl-abx500.h"
3a198059
LW		 36#include "../core.h"
37#include "../pinconf.h"
b07f92a2 38#include "../pinctrl-utils.h"
0493e649
PC		 39
40/*
41 * The AB9540 and AB8540 GPIO support are extended versions
42 * of the AB8500 GPIO support.
43 * The AB9540 supports an additional (7th) register so that
44 * more GPIO may be configured and used.
45 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
46 * internal pull-up and pull-down capabilities.
47 */
48
49/*
50 * GPIO registers offset
51 * Bank: 0x10
52 */
53#define AB8500_GPIO_SEL1_REG 0x00
54#define AB8500_GPIO_SEL2_REG 0x01
55#define AB8500_GPIO_SEL3_REG 0x02
56#define AB8500_GPIO_SEL4_REG 0x03
57#define AB8500_GPIO_SEL5_REG 0x04
58#define AB8500_GPIO_SEL6_REG 0x05
59#define AB9540_GPIO_SEL7_REG 0x06
60
61#define AB8500_GPIO_DIR1_REG 0x10
62#define AB8500_GPIO_DIR2_REG 0x11
63#define AB8500_GPIO_DIR3_REG 0x12
64#define AB8500_GPIO_DIR4_REG 0x13
65#define AB8500_GPIO_DIR5_REG 0x14
66#define AB8500_GPIO_DIR6_REG 0x15
67#define AB9540_GPIO_DIR7_REG 0x16
68
69#define AB8500_GPIO_OUT1_REG 0x20
70#define AB8500_GPIO_OUT2_REG 0x21
71#define AB8500_GPIO_OUT3_REG 0x22
72#define AB8500_GPIO_OUT4_REG 0x23
73#define AB8500_GPIO_OUT5_REG 0x24
74#define AB8500_GPIO_OUT6_REG 0x25
75#define AB9540_GPIO_OUT7_REG 0x26
76
77#define AB8500_GPIO_PUD1_REG 0x30
78#define AB8500_GPIO_PUD2_REG 0x31
79#define AB8500_GPIO_PUD3_REG 0x32
80#define AB8500_GPIO_PUD4_REG 0x33
81#define AB8500_GPIO_PUD5_REG 0x34
82#define AB8500_GPIO_PUD6_REG 0x35
83#define AB9540_GPIO_PUD7_REG 0x36
84
85#define AB8500_GPIO_IN1_REG 0x40
86#define AB8500_GPIO_IN2_REG 0x41
87#define AB8500_GPIO_IN3_REG 0x42
88#define AB8500_GPIO_IN4_REG 0x43
89#define AB8500_GPIO_IN5_REG 0x44
90#define AB8500_GPIO_IN6_REG 0x45
91#define AB9540_GPIO_IN7_REG 0x46
92#define AB8540_GPIO_VINSEL_REG 0x47
93#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
94#define AB8500_GPIO_ALTFUN_REG 0x50
0493e649
PC		 95#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
96#define AB8540_GPIO_VINSEL_MASK 0x03
97#define AB8540_GPIOX_VBAT_START 51
98#define AB8540_GPIOX_VBAT_END 54
99
acd260b0
PC		 100#define ABX500_GPIO_INPUT 0
101#define ABX500_GPIO_OUTPUT 1
102
0493e649
PC		 103struct abx500_pinctrl {
104 struct device *dev;
105 struct pinctrl_dev *pctldev;
106 struct abx500_pinctrl_soc_data *soc;
107 struct gpio_chip chip;
108 struct ab8500 *parent;
0493e649
PC		 109 struct abx500_gpio_irq_cluster *irq_cluster;
110 int irq_cluster_size;
0493e649
PC		 111};
112
0493e649 113static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 114 unsigned offset, bool *bit)
0493e649 115{
2b016d27 116 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 117 u8 pos = offset % 8;
118 u8 val;
119 int ret;
120
121 reg += offset / 8;
122 ret = abx500_get_register_interruptible(pct->dev,
123 AB8500_MISC, reg, &val);
124
125 *bit = !!(val & BIT(pos));
126
127 if (ret < 0)
128 dev_err(pct->dev,
9be580af
PC		 129 "%s read reg =%x, offset=%x failed (%d)\n",
130 __func__, reg, offset, ret);
0493e649
PC		 131
132 return ret;
133}
134
135static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 136 unsigned offset, int val)
0493e649 137{
2b016d27 138 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 139 u8 pos = offset % 8;
140 int ret;
141
142 reg += offset / 8;
143 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 144 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649 145 if (ret < 0)
9be580af
PC		 146 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
147 __func__, reg, offset, ret);
83b423c8 148
0493e649
PC		 149 return ret;
150}
83b423c8 151
0493e649
PC		 152/**
153 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 154 * @chip: Gpio device
155 * @offset: GPIO number to read
0493e649
PC		 156 */
157static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
158{
2b016d27 159 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649 160 bool bit;
d8d4f7f8
PC		 161 bool is_out;
162 u8 gpio_offset = offset - 1;
0493e649
PC		 163 int ret;
164
d8d4f7f8
PC		 165 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
166 gpio_offset, &is_out);
9be580af
PC		 167 if (ret < 0)
168 goto out;
d8d4f7f8
PC		 169
170 if (is_out)
171 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
172 gpio_offset, &bit);
173 else
174 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
175 gpio_offset, &bit);
9be580af 176out:
0493e649 177 if (ret < 0) {
9be580af 178 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 179 return ret;
180 }
83b423c8 181
0493e649
PC		 182 return bit;
183}
184
185static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
186{
2b016d27 187 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 188 int ret;
189
190 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
191 if (ret < 0)
9be580af 192 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
0493e649
PC		 193}
194
39178bb2 195#ifdef CONFIG_DEBUG_FS
d2752ae5
PC		 196static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
197 enum abx500_gpio_pull_updown *pull_updown)
0493e649
PC		 198{
199 u8 pos;
d2752ae5 200 u8 val;
0493e649
PC		 201 int ret;
202 struct pullud *pullud;
203
204 if (!pct->soc->pullud) {
205 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
206 __func__);
207 ret = -EPERM;
208 goto out;
209 }
210
211 pullud = pct->soc->pullud;
212
213 if ((offset < pullud->first_pin)
214 || (offset > pullud->last_pin)) {
215 ret = -EINVAL;
216 goto out;
217 }
218
d2752ae5
PC		 219 ret = abx500_get_register_interruptible(pct->dev,
220 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
221
222 pos = (offset - pullud->first_pin) << 1;
223 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
224
225out:
226 if (ret < 0)
227 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
228
229 return ret;
230}
39178bb2 231#endif
d2752ae5
PC		 232
233static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
234 int offset, enum abx500_gpio_pull_updown val)
235{
236 u8 pos;
237 int ret;
238 struct pullud *pullud;
239
240 if (!pct->soc->pullud) {
241 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
242 __func__);
243 ret = -EPERM;
244 goto out;
245 }
246
247 pullud = pct->soc->pullud;
248
249 if ((offset < pullud->first_pin)
250 || (offset > pullud->last_pin)) {
251 ret = -EINVAL;
252 goto out;
253 }
10a8be54 254 pos = (offset - pullud->first_pin) << 1;
0493e649
PC		 255
256 ret = abx500_mask_and_set_register_interruptible(pct->dev,
257 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
258 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
259
260out:
261 if (ret < 0)
262 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 263
0493e649
PC		 264 return ret;
265}
266
8b5abd18
PC		 267static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
268{
2b016d27 269 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
8b5abd18
PC		 270 struct pullud *pullud = pct->soc->pullud;
271
272 return (pullud &&
273 gpio >= pullud->first_pin &&
274 gpio <= pullud->last_pin);
275}
276
0493e649
PC		 277static int abx500_gpio_direction_output(struct gpio_chip *chip,
278 unsigned offset,
279 int val)
280{
2b016d27 281 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 282 unsigned gpio;
283 int ret;
83b423c8 284
0493e649 285 /* set direction as output */
acd260b0
PC		 286 ret = abx500_gpio_set_bits(chip,
287 AB8500_GPIO_DIR1_REG,
288 offset,
289 ABX500_GPIO_OUTPUT);
0493e649 290 if (ret < 0)
9be580af 291 goto out;
0493e649
PC		 292
293 /* disable pull down */
acd260b0
PC		 294 ret = abx500_gpio_set_bits(chip,
295 AB8500_GPIO_PUD1_REG,
296 offset,
297 ABX500_GPIO_PULL_NONE);
0493e649 298 if (ret < 0)
9be580af 299 goto out;
0493e649
PC		 300
301 /* if supported, disable both pull down and pull up */
302 gpio = offset + 1;
8b5abd18 303 if (abx500_pullud_supported(chip, gpio)) {
d2752ae5 304 ret = abx500_set_pull_updown(pct,
0493e649
PC		 305 gpio,
306 ABX500_GPIO_PULL_NONE);
9be580af
PC		 307 }
308out:
309 if (ret < 0) {
310 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
311 return ret;
0493e649 312 }
83b423c8 313
0493e649
PC		 314 /* set the output as 1 or 0 */
315 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
316}
317
318static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
319{
320 /* set the register as input */
acd260b0
PC		 321 return abx500_gpio_set_bits(chip,
322 AB8500_GPIO_DIR1_REG,
323 offset,
324 ABX500_GPIO_INPUT);
0493e649
PC		 325}
326
327static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
328{
2b016d27 329 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
b9fab6e4
LJ		 330 /* The AB8500 GPIO numbers are off by one */
331 int gpio = offset + 1;
a6a16d27 332 int hwirq;
0493e649
PC		 333 int i;
334
335 for (i = 0; i < pct->irq_cluster_size; i++) {
336 struct abx500_gpio_irq_cluster *cluster =
337 &pct->irq_cluster[i];
338
a6a16d27
LJ		 339 if (gpio >= cluster->start && gpio <= cluster->end) {
340 /*
341 * The ABx500 GPIO's associated IRQs are clustered together
342 * throughout the interrupt numbers at irregular intervals.
343 * To solve this quandry, we have placed the read-in values
344 * into the cluster information table.
345 */
43a255db 346 hwirq = gpio - cluster->start + cluster->to_irq;
a6a16d27
LJ		 347 return irq_create_mapping(pct->parent->domain, hwirq);
348 }
0493e649
PC		 349 }
350
351 return -EINVAL;
352}
353
354static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 355 unsigned gpio, int alt_setting)
0493e649
PC		 356{
357 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
358 struct alternate_functions af = pct->soc->alternate_functions[gpio];
359 int ret;
360 int val;
361 unsigned offset;
83b423c8 362
0493e649
PC		 363 const char *modes[] = {
364 [ABX500_DEFAULT] = "default",
365 [ABX500_ALT_A] = "altA",
366 [ABX500_ALT_B] = "altB",
367 [ABX500_ALT_C] = "altC",
368 };
369
370 /* sanity check */
371 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
372 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
373 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
374 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
375 modes[alt_setting]);
376 return -EINVAL;
377 }
378
379 /* on ABx5xx, there is no GPIO0, so adjust the offset */
380 offset = gpio - 1;
83b423c8 381
0493e649
PC		 382 switch (alt_setting) {
383 case ABX500_DEFAULT:
384 /*
385 * for ABx5xx family, default mode is always selected by
386 * writing 0 to GPIOSELx register, except for pins which
387 * support at least ALT_B mode, default mode is selected
388 * by writing 1 to GPIOSELx register
389 */
390 val = 0;
391 if (af.alt_bit1 != UNUSED)
392 val++;
393
394 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
395 offset, val);
396 break;
83b423c8 397
0493e649
PC		 398 case ABX500_ALT_A:
399 /*
400 * for ABx5xx family, alt_a mode is always selected by
401 * writing 1 to GPIOSELx register, except for pins which
402 * support at least ALT_B mode, alt_a mode is selected
403 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
404 * register
405 */
406 if (af.alt_bit1 != UNUSED) {
407 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
408 offset, 0);
9be580af
PC		 409 if (ret < 0)
410 goto out;
411
0493e649
PC		 412 ret = abx500_gpio_set_bits(chip,
413 AB8500_GPIO_ALTFUN_REG,
414 af.alt_bit1,
c590854d 415 !!(af.alta_val & BIT(0)));
9be580af
PC		 416 if (ret < 0)
417 goto out;
418
0493e649
PC		 419 if (af.alt_bit2 != UNUSED)
420 ret = abx500_gpio_set_bits(chip,
421 AB8500_GPIO_ALTFUN_REG,
422 af.alt_bit2,
6da33dbd 423 !!(af.alta_val & BIT(1)));
0493e649
PC		 424 } else
425 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
426 offset, 1);
427 break;
83b423c8 428
0493e649
PC		 429 case ABX500_ALT_B:
430 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
431 offset, 0);
9be580af
PC		 432 if (ret < 0)
433 goto out;
434
0493e649 435 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 436 af.alt_bit1, !!(af.altb_val & BIT(0)));
9be580af
PC		 437 if (ret < 0)
438 goto out;
439
0493e649
PC		 440 if (af.alt_bit2 != UNUSED)
441 ret = abx500_gpio_set_bits(chip,
442 AB8500_GPIO_ALTFUN_REG,
443 af.alt_bit2,
6da33dbd 444 !!(af.altb_val & BIT(1)));
0493e649 445 break;
83b423c8 446
0493e649
PC		 447 case ABX500_ALT_C:
448 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
449 offset, 0);
9be580af
PC		 450 if (ret < 0)
451 goto out;
452
0493e649 453 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
6da33dbd 454 af.alt_bit2, !!(af.altc_val & BIT(0)));
9be580af
PC		 455 if (ret < 0)
456 goto out;
457
0493e649 458 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 459 af.alt_bit2, !!(af.altc_val & BIT(1)));
0493e649
PC		 460 break;
461
462 default:
f42cf8d6 463 dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting);
83b423c8 464
0493e649
PC		 465 return -EINVAL;
466 }
9be580af
PC		 467out:
468 if (ret < 0)
469 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 470
0493e649
PC		 471 return ret;
472}
473
39178bb2 474#ifdef CONFIG_DEBUG_FS
9be580af 475static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 476 unsigned gpio)
0493e649
PC		 477{
478 u8 mode;
479 bool bit_mode;
480 bool alt_bit1;
481 bool alt_bit2;
482 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
483 struct alternate_functions af = pct->soc->alternate_functions[gpio];
a950cb74
LW		 484 /* on ABx5xx, there is no GPIO0, so adjust the offset */
485 unsigned offset = gpio - 1;
9be580af 486 int ret;
0493e649
PC		 487
488 /*
489 * if gpiosel_bit is set to unused,
490 * it means no GPIO or special case
491 */
492 if (af.gpiosel_bit == UNUSED)
493 return ABX500_DEFAULT;
494
495 /* read GpioSelx register */
9be580af 496 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
0493e649 497 af.gpiosel_bit, &bit_mode);
9be580af
PC		 498 if (ret < 0)
499 goto out;
500
0493e649
PC		 501 mode = bit_mode;
502
503 /* sanity check */
504 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
505 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
506 dev_err(pct->dev,
507 "alt_bitX value not in correct range (-1 to 7)\n");
508 return -EINVAL;
509 }
83b423c8 510
0493e649
PC		 511 /* if alt_bit2 is used, alt_bit1 must be used too */
512 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
513 dev_err(pct->dev,
514 "if alt_bit2 is used, alt_bit1 can't be unused\n");
515 return -EINVAL;
516 }
517
518 /* check if pin use AlternateFunction register */
6a40cdd5 519 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
0493e649
PC		 520 return mode;
521 /*
522 * if pin GPIOSEL bit is set and pin supports alternate function,
523 * it means DEFAULT mode
524 */
525 if (mode)
526 return ABX500_DEFAULT;
83b423c8 527
0493e649
PC		 528 /*
529 * pin use the AlternatFunction register
530 * read alt_bit1 value
531 */
9be580af 532 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
0493e649 533 af.alt_bit1, &alt_bit1);
9be580af
PC		 534 if (ret < 0)
535 goto out;
0493e649 536
9be580af 537 if (af.alt_bit2 != UNUSED) {
0493e649 538 /* read alt_bit2 value */
9be580af
PC		 539 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
540 af.alt_bit2,
0493e649 541 &alt_bit2);
9be580af
PC		 542 if (ret < 0)
543 goto out;
544 } else
0493e649
PC		 545 alt_bit2 = 0;
546
547 mode = (alt_bit2 << 1) + alt_bit1;
548 if (mode == af.alta_val)
549 return ABX500_ALT_A;
550 else if (mode == af.altb_val)
551 return ABX500_ALT_B;
552 else
553 return ABX500_ALT_C;
9be580af
PC		 554
555out:
556 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
557 return ret;
0493e649
PC		 558}
559
0493e649
PC		 560#include <linux/seq_file.h>
561
562static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 563 struct pinctrl_dev *pctldev,
564 struct gpio_chip *chip,
565 unsigned offset, unsigned gpio)
0493e649 566{
d2752ae5 567 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 568 const char *label = gpiochip_is_requested(chip, offset - 1);
569 u8 gpio_offset = offset - 1;
570 int mode = -1;
571 bool is_out;
d2752ae5 572 bool pd;
ce06f407 573 enum abx500_gpio_pull_updown pud = 0;
9be580af 574 int ret;
83b423c8 575
0493e649
PC		 576 const char *modes[] = {
577 [ABX500_DEFAULT] = "default",
578 [ABX500_ALT_A] = "altA",
579 [ABX500_ALT_B] = "altB",
580 [ABX500_ALT_C] = "altC",
581 };
582
d2752ae5
PC		 583 const char *pull_up_down[] = {
584 [ABX500_GPIO_PULL_DOWN] = "pull down",
585 [ABX500_GPIO_PULL_NONE] = "pull none",
586 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
587 [ABX500_GPIO_PULL_UP] = "pull up",
588 };
589
9be580af
PC		 590 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
591 gpio_offset, &is_out);
592 if (ret < 0)
593 goto out;
d2752ae5
PC		 594
595 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
596 gpio, label ?: "(none)",
597 is_out ? "out" : "in ");
598
599 if (!is_out) {
8b5abd18 600 if (abx500_pullud_supported(chip, offset)) {
9be580af
PC		 601 ret = abx500_get_pull_updown(pct, offset, &pud);
602 if (ret < 0)
603 goto out;
604
d2752ae5
PC		 605 seq_printf(s, " %-9s", pull_up_down[pud]);
606 } else {
9be580af
PC		 607 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
608 gpio_offset, &pd);
609 if (ret < 0)
610 goto out;
611
d2752ae5
PC		 612 seq_printf(s, " %-9s", pull_up_down[pd]);
613 }
614 } else
615 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
0493e649 616
1d54f0fd 617 mode = abx500_get_mode(pctldev, chip, offset);
0493e649 618
d2752ae5 619 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
9be580af
PC		 620
621out:
622 if (ret < 0)
623 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 624}
625
626static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
627{
628 unsigned i;
629 unsigned gpio = chip->base;
2b016d27 630 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 631 struct pinctrl_dev *pctldev = pct->pctldev;
632
633 for (i = 0; i < chip->ngpio; i++, gpio++) {
634 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
635 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
636 seq_printf(s, "\n");
637 }
638}
639
640#else
641static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 642 struct pinctrl_dev *pctldev,
643 struct gpio_chip *chip,
644 unsigned offset, unsigned gpio)
0493e649
PC		 645{
646}
647#define abx500_gpio_dbg_show NULL
648#endif
649
0493e649
PC		 650static struct gpio_chip abx500gpio_chip = {
651 .label = "abx500-gpio",
652 .owner = THIS_MODULE,
98c85d58
JG		 653 .request = gpiochip_generic_request,
654 .free = gpiochip_generic_free,
0493e649
PC		 655 .direction_input = abx500_gpio_direction_input,
656 .get = abx500_gpio_get,
657 .direction_output = abx500_gpio_direction_output,
658 .set = abx500_gpio_set,
659 .to_irq = abx500_gpio_to_irq,
660 .dbg_show = abx500_gpio_dbg_show,
661};
662
0493e649
PC		 663static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
664{
665 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
666
667 return pct->soc->nfunctions;
668}
669
670static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
671 unsigned function)
672{
673 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
674
675 return pct->soc->functions[function].name;
676}
677
678static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 679 unsigned function,
680 const char * const **groups,
681 unsigned * const num_groups)
0493e649
PC		 682{
683 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
684
685 *groups = pct->soc->functions[function].groups;
686 *num_groups = pct->soc->functions[function].ngroups;
687
688 return 0;
689}
690
03e9f0ca
LW		 691static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
692 unsigned group)
0493e649
PC		 693{
694 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
695 struct gpio_chip *chip = &pct->chip;
696 const struct abx500_pingroup *g;
697 int i;
698 int ret = 0;
699
700 g = &pct->soc->groups[group];
701 if (g->altsetting < 0)
702 return -EINVAL;
703
704 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
705
706 for (i = 0; i < g->npins; i++) {
707 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
708 g->pins[i], g->altsetting);
709
0493e649
PC		 710 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
711 }
83b423c8 712
9be580af
PC		 713 if (ret < 0)
714 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
715
0493e649
PC		 716 return ret;
717}
718
9c4154ef 719static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 720 struct pinctrl_gpio_range *range,
721 unsigned offset)
0493e649
PC		 722{
723 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
724 const struct abx500_pinrange *p;
725 int ret;
726 int i;
727
728 /*
729 * Different ranges have different ways to enable GPIO function on a
730 * pin, so refer back to our local range type, where we handily define
731 * what altfunc enables GPIO for a certain pin.
732 */
733 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
734 p = &pct->soc->gpio_ranges[i];
735 if ((offset >= p->offset) &&
736 (offset < (p->offset + p->npins)))
737 break;
738 }
739
740 if (i == pct->soc->gpio_num_ranges) {
741 dev_err(pct->dev, "%s failed to locate range\n", __func__);
742 return -ENODEV;
743 }
744
745 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
746 p->altfunc, offset);
747
748 ret = abx500_set_mode(pct->pctldev, &pct->chip,
749 offset, p->altfunc);
9be580af 750 if (ret < 0)
0493e649 751 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
0493e649
PC		 752
753 return ret;
754}
755
756static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 757 struct pinctrl_gpio_range *range,
758 unsigned offset)
0493e649
PC		 759{
760}
761
022ab148 762static const struct pinmux_ops abx500_pinmux_ops = {
0493e649
PC		 763 .get_functions_count = abx500_pmx_get_funcs_cnt,
764 .get_function_name = abx500_pmx_get_func_name,
765 .get_function_groups = abx500_pmx_get_func_groups,
03e9f0ca 766 .set_mux = abx500_pmx_set,
0493e649
PC		 767 .gpio_request_enable = abx500_gpio_request_enable,
768 .gpio_disable_free = abx500_gpio_disable_free,
769};
770
771static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
772{
773 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
774
775 return pct->soc->ngroups;
776}
777
778static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 779 unsigned selector)
0493e649
PC		 780{
781 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
782
783 return pct->soc->groups[selector].name;
784}
785
786static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 787 unsigned selector,
788 const unsigned **pins,
789 unsigned *num_pins)
0493e649
PC		 790{
791 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
792
793 *pins = pct->soc->groups[selector].pins;
794 *num_pins = pct->soc->groups[selector].npins;
83b423c8 795
0493e649
PC		 796 return 0;
797}
798
799static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 800 struct seq_file *s, unsigned offset)
0493e649
PC		 801{
802 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
803 struct gpio_chip *chip = &pct->chip;
804
805 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
806 chip->base + offset - 1);
807}
808
64a45c98
PC		 809static int abx500_dt_add_map_mux(struct pinctrl_map **map,
810 unsigned *reserved_maps,
811 unsigned *num_maps, const char *group,
812 const char *function)
813{
814 if (*num_maps == *reserved_maps)
815 return -ENOSPC;
816
817 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
818 (*map)[*num_maps].data.mux.group = group;
819 (*map)[*num_maps].data.mux.function = function;
820 (*num_maps)++;
821
822 return 0;
823}
824
825static int abx500_dt_add_map_configs(struct pinctrl_map **map,
826 unsigned *reserved_maps,
827 unsigned *num_maps, const char *group,
828 unsigned long *configs, unsigned num_configs)
829{
830 unsigned long *dup_configs;
831
832 if (*num_maps == *reserved_maps)
833 return -ENOSPC;
834
835 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
836 GFP_KERNEL);
837 if (!dup_configs)
838 return -ENOMEM;
839
840 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
841
842 (*map)[*num_maps].data.configs.group_or_pin = group;
843 (*map)[*num_maps].data.configs.configs = dup_configs;
844 (*map)[*num_maps].data.configs.num_configs = num_configs;
845 (*num_maps)++;
846
847 return 0;
848}
849
850static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
851 const char *pin_name)
852{
853 int i, pin_number;
854 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
855
856 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
857 for (i = 0; i < npct->soc->npins; i++)
858 if (npct->soc->pins[i].number == pin_number)
859 return npct->soc->pins[i].name;
860 return NULL;
861}
862
863static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
864 struct device_node *np,
865 struct pinctrl_map **map,
866 unsigned *reserved_maps,
867 unsigned *num_maps)
868{
869 int ret;
870 const char *function = NULL;
871 unsigned long *configs;
872 unsigned int nconfigs = 0;
64a45c98 873 struct property *prop;
64a45c98 874
51d39936 875 ret = of_property_read_string(np, "function", &function);
259145fe 876 if (ret >= 0) {
51d39936
LW		 877 const char *group;
878
879 ret = of_property_count_strings(np, "groups");
259145fe
LW		 880 if (ret < 0)
881 goto exit;
882
883 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
884 num_maps, ret);
885 if (ret < 0)
886 goto exit;
887
51d39936 888 of_property_for_each_string(np, "groups", prop, group) {
259145fe
LW		 889 ret = abx500_dt_add_map_mux(map, reserved_maps,
890 num_maps, group, function);
891 if (ret < 0)
892 goto exit;
893 }
894 }
64a45c98 895
dd4d01f7 896 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
eea11b0b 897 if (nconfigs) {
51d39936
LW		 898 const char *gpio_name;
899 const char *pin;
900
0564f7d9 901 ret = of_property_count_strings(np, "pins");
259145fe
LW		 902 if (ret < 0)
903 goto exit;
64a45c98 904
259145fe
LW		 905 ret = pinctrl_utils_reserve_map(pctldev, map,
906 reserved_maps,
907 num_maps, ret);
908 if (ret < 0)
909 goto exit;
64a45c98 910
0564f7d9 911 of_property_for_each_string(np, "pins", prop, pin) {
51d39936 912 gpio_name = abx500_find_pin_name(pctldev, pin);
64a45c98
PC		 913
914 ret = abx500_dt_add_map_configs(map, reserved_maps,
915 num_maps, gpio_name, configs, 1);
916 if (ret < 0)
917 goto exit;
918 }
64a45c98 919 }
259145fe 920
64a45c98
PC		 921exit:
922 return ret;
923}
924
925static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
926 struct device_node *np_config,
927 struct pinctrl_map **map, unsigned *num_maps)
928{
929 unsigned reserved_maps;
930 struct device_node *np;
931 int ret;
932
933 reserved_maps = 0;
934 *map = NULL;
935 *num_maps = 0;
936
937 for_each_child_of_node(np_config, np) {
938 ret = abx500_dt_subnode_to_map(pctldev, np, map,
939 &reserved_maps, num_maps);
940 if (ret < 0) {
d32f7fd3 941 pinctrl_utils_free_map(pctldev, *map, *num_maps);
64a45c98
PC		 942 return ret;
943 }
944 }
945
946 return 0;
947}
948
022ab148 949static const struct pinctrl_ops abx500_pinctrl_ops = {
0493e649
PC		 950 .get_groups_count = abx500_get_groups_cnt,
951 .get_group_name = abx500_get_group_name,
952 .get_group_pins = abx500_get_group_pins,
953 .pin_dbg_show = abx500_pin_dbg_show,
64a45c98 954 .dt_node_to_map = abx500_dt_node_to_map,
d32f7fd3 955 .dt_free_map = pinctrl_utils_free_map,
0493e649
PC		 956};
957
9c4154ef 958static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 959 unsigned pin,
960 unsigned long *config)
0493e649 961{
1abeebea 962 return -ENOSYS;
0493e649
PC		 963}
964
9c4154ef 965static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8 966 unsigned pin,
03b054e9
SY		 967 unsigned long *configs,
968 unsigned num_configs)
0493e649
PC		 969{
970 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 971 struct gpio_chip *chip = &pct->chip;
972 unsigned offset;
61ce1356 973 int ret = -EINVAL;
03b054e9
SY		 974 int i;
975 enum pin_config_param param;
976 enum pin_config_param argument;
977
978 for (i = 0; i < num_configs; i++) {
979 param = pinconf_to_config_param(configs[i]);
980 argument = pinconf_to_config_argument(configs[i]);
981
58383c78 982 dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
03b054e9
SY		 983 pin, configs[i],
984 (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
985 (param == PIN_CONFIG_OUTPUT) ?
986 (argument ? "high" : "low") :
987 (argument ? "pull up" : "pull down"));
988
989 /* on ABx500, there is no GPIO0, so adjust the offset */
990 offset = pin - 1;
991
992 switch (param) {
993 case PIN_CONFIG_BIAS_DISABLE:
994 ret = abx500_gpio_direction_input(chip, offset);
995 if (ret < 0)
996 goto out;
997 /*
998 * Some chips only support pull down, while some
999 * actually support both pull up and pull down. Such
1000 * chips have a "pullud" range specified for the pins
1001 * that support both features. If the pin is not
1002 * within that range, we fall back to the old bit set
1003 * that only support pull down.
1004 */
1005 if (abx500_pullud_supported(chip, pin))
1006 ret = abx500_set_pull_updown(pct,
1007 pin,
1008 ABX500_GPIO_PULL_NONE);
1009 else
1010 /* Chip only supports pull down */
1011 ret = abx500_gpio_set_bits(chip,
1012 AB8500_GPIO_PUD1_REG, offset,
1013 ABX500_GPIO_PULL_NONE);
1014 break;
9ed3cd33 1015
03b054e9
SY		 1016 case PIN_CONFIG_BIAS_PULL_DOWN:
1017 ret = abx500_gpio_direction_input(chip, offset);
1018 if (ret < 0)
1019 goto out;
1020 /*
1021 * if argument = 1 set the pull down
1022 * else clear the pull down
1023 * Some chips only support pull down, while some
1024 * actually support both pull up and pull down. Such
1025 * chips have a "pullud" range specified for the pins
1026 * that support both features. If the pin is not
1027 * within that range, we fall back to the old bit set
1028 * that only support pull down.
1029 */
1030 if (abx500_pullud_supported(chip, pin))
1031 ret = abx500_set_pull_updown(pct,
1032 pin,
1033 argument ? ABX500_GPIO_PULL_DOWN :
1034 ABX500_GPIO_PULL_NONE);
1035 else
1036 /* Chip only supports pull down */
1037 ret = abx500_gpio_set_bits(chip,
1038 AB8500_GPIO_PUD1_REG,
1039 offset,
1040 argument ? ABX500_GPIO_PULL_DOWN :
1041 ABX500_GPIO_PULL_NONE);
1042 break;
83b423c8 1043
03b054e9
SY		 1044 case PIN_CONFIG_BIAS_PULL_UP:
1045 ret = abx500_gpio_direction_input(chip, offset);
1046 if (ret < 0)
1047 goto out;
1048 /*
1049 * if argument = 1 set the pull up
1050 * else clear the pull up
1051 */
1052 ret = abx500_gpio_direction_input(chip, offset);
1053 /*
1054 * Some chips only support pull down, while some
1055 * actually support both pull up and pull down. Such
1056 * chips have a "pullud" range specified for the pins
1057 * that support both features. If the pin is not
1058 * within that range, do nothing
1059 */
1060 if (abx500_pullud_supported(chip, pin))
1061 ret = abx500_set_pull_updown(pct,
1062 pin,
1063 argument ? ABX500_GPIO_PULL_UP :
1064 ABX500_GPIO_PULL_NONE);
1065 break;
1066
1067 case PIN_CONFIG_OUTPUT:
1068 ret = abx500_gpio_direction_output(chip, offset,
1069 argument);
1070 break;
1071
1072 default:
58383c78
LW		 1073 dev_err(chip->parent,
1074 "illegal configuration requested\n");
03b054e9
SY		 1075 }
1076 } /* for each config */
9be580af
PC		 1077out:
1078 if (ret < 0)
1079 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 1080
0493e649
PC		 1081 return ret;
1082}
1083
022ab148 1084static const struct pinconf_ops abx500_pinconf_ops = {
0493e649
PC		 1085 .pin_config_get = abx500_pin_config_get,
1086 .pin_config_set = abx500_pin_config_set,
71ca917a 1087 .is_generic = true,
0493e649
PC		 1088};
1089
1090static struct pinctrl_desc abx500_pinctrl_desc = {
1091 .name = "pinctrl-abx500",
1092 .pctlops = &abx500_pinctrl_ops,
1093 .pmxops = &abx500_pinmux_ops,
1094 .confops = &abx500_pinconf_ops,
1095 .owner = THIS_MODULE,
1096};
1097
1098static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1099{
1100 unsigned int lowest = 0;
1101 unsigned int highest = 0;
1102 unsigned int npins = 0;
1103 int i;
1104
1105 /*
1106 * Compute number of GPIOs from the last SoC gpio range descriptors
1107 * These ranges may include "holes" but the GPIO number space shall
1108 * still be homogeneous, so we need to detect and account for any
1109 * such holes so that these are included in the number of GPIO pins.
1110 */
1111 for (i = 0; i < soc->gpio_num_ranges; i++) {
1112 unsigned gstart;
1113 unsigned gend;
1114 const struct abx500_pinrange *p;
1115
1116 p = &soc->gpio_ranges[i];
1117 gstart = p->offset;
1118 gend = p->offset + p->npins - 1;
1119
1120 if (i == 0) {
1121 /* First iteration, set start values */
1122 lowest = gstart;
1123 highest = gend;
1124 } else {
1125 if (gstart < lowest)
1126 lowest = gstart;
1127 if (gend > highest)
1128 highest = gend;
1129 }
1130 }
1131 /* this gives the absolute number of pins */
1132 npins = highest - lowest + 1;
1133 return npins;
1134}
1135
f30a3839
LJ		 1136static const struct of_device_id abx500_gpio_match[] = {
1137 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
1138 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
1139 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
1140 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
e3929714 1141 { }
f30a3839
LJ		 1142};
1143
0493e649
PC		 1144static int abx500_gpio_probe(struct platform_device *pdev)
1145{
f30a3839 1146 struct device_node *np = pdev->dev.of_node;
ac99a037 1147 const struct of_device_id *match;
0493e649 1148 struct abx500_pinctrl *pct;
f30a3839 1149 unsigned int id = -1;
3a4b094d 1150 int ret;
0493e649
PC		 1151 int i;
1152
ac99a037
LW		 1153 if (!np) {
1154 dev_err(&pdev->dev, "gpio dt node missing\n");
86c976e4 1155 return -ENODEV;
0493e649
PC		 1156 }
1157
1158 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1159 GFP_KERNEL);
1160 if (pct == NULL) {
1161 dev_err(&pdev->dev,
1162 "failed to allocate memory for pct\n");
1163 return -ENOMEM;
1164 }
1165
1166 pct->dev = &pdev->dev;
1167 pct->parent = dev_get_drvdata(pdev->dev.parent);
1168 pct->chip = abx500gpio_chip;
58383c78 1169 pct->chip.parent = &pdev->dev;
ac99a037 1170 pct->chip.base = -1; /* Dynamic allocation */
86c976e4 1171
ac99a037
LW		 1172 match = of_match_device(abx500_gpio_match, &pdev->dev);
1173 if (!match) {
1174 dev_err(&pdev->dev, "gpio dt not matching\n");
1175 return -ENODEV;
86c976e4 1176 }
ac99a037 1177 id = (unsigned long)match->data;
86c976e4 1178
0493e649 1179 /* Poke in other ASIC variants here */
f30a3839 1180 switch (id) {
3c937993
PC		 1181 case PINCTRL_AB8500:
1182 abx500_pinctrl_ab8500_init(&pct->soc);
1183 break;
a8f96e41
PC		 1184 case PINCTRL_AB8540:
1185 abx500_pinctrl_ab8540_init(&pct->soc);
1186 break;
09dbec3f
PC		 1187 case PINCTRL_AB9540:
1188 abx500_pinctrl_ab9540_init(&pct->soc);
1189 break;
1aa2d8d4
PC		 1190 case PINCTRL_AB8505:
1191 abx500_pinctrl_ab8505_init(&pct->soc);
1192 break;
0493e649 1193 default:
2fcad12e 1194 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
0493e649
PC		 1195 return -EINVAL;
1196 }
1197
1198 if (!pct->soc) {
1199 dev_err(&pdev->dev, "Invalid SOC data\n");
1200 return -EINVAL;
1201 }
1202
1203 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1204 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1205 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
0493e649 1206
2b016d27 1207 ret = gpiochip_add_data(&pct->chip, pct);
0493e649 1208 if (ret) {
83b423c8 1209 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
ac652d79 1210 return ret;
0493e649
PC		 1211 }
1212 dev_info(&pdev->dev, "added gpiochip\n");
1213
1214 abx500_pinctrl_desc.pins = pct->soc->pins;
1215 abx500_pinctrl_desc.npins = pct->soc->npins;
0ee60110
LD		 1216 pct->pctldev = devm_pinctrl_register(&pdev->dev, &abx500_pinctrl_desc,
1217 pct);
323de9ef 1218 if (IS_ERR(pct->pctldev)) {
0493e649
PC		 1219 dev_err(&pdev->dev,
1220 "could not register abx500 pinctrl driver\n");
323de9ef 1221 ret = PTR_ERR(pct->pctldev);
0493e649
PC		 1222 goto out_rem_chip;
1223 }
1224 dev_info(&pdev->dev, "registered pin controller\n");
1225
1226 /* We will handle a range of GPIO pins */
1227 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1228 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1229
1230 ret = gpiochip_add_pin_range(&pct->chip,
1231 dev_name(&pdev->dev),
1232 p->offset - 1, p->offset, p->npins);
1233 if (ret < 0)
fa1ec996 1234 goto out_rem_chip;
0493e649
PC		 1235 }
1236
1237 platform_set_drvdata(pdev, pct);
1238 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1239
1240 return 0;
1241
1242out_rem_chip:
2fcea6ce 1243 gpiochip_remove(&pct->chip);
0493e649
PC		 1244 return ret;
1245}
1246
83b423c8 1247/**
0493e649 1248 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1249 * @pdev: Platform device registered
0493e649
PC		 1250 */
1251static int abx500_gpio_remove(struct platform_device *pdev)
1252{
1253 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
0493e649 1254
2fcea6ce 1255 gpiochip_remove(&pct->chip);
0493e649
PC		 1256 return 0;
1257}
1258
0493e649
PC		 1259static struct platform_driver abx500_gpio_driver = {
1260 .driver = {
1261 .name = "abx500-gpio",
f30a3839 1262 .of_match_table = abx500_gpio_match,
0493e649
PC		 1263 },
1264 .probe = abx500_gpio_probe,
1265 .remove = abx500_gpio_remove,
0493e649
PC		 1266};
1267
1268static int __init abx500_gpio_init(void)
1269{
1270 return platform_driver_register(&abx500_gpio_driver);
1271}
1272core_initcall(abx500_gpio_init);
Linux kernel - Deliverables
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