Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
f4b3f523 | 7 | * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
855f80cd | 25 | #include <linux/of_device.h> |
32e67eee | 26 | #include <linux/of_address.h> |
5e81e0a0 | 27 | #include <linux/bitops.h> |
e32af889 | 28 | #include <linux/pinctrl/machine.h> |
e98ea774 | 29 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 30 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 31 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
32 | /* Since we request GPIOs from ourself */ |
33 | #include <linux/pinctrl/consumer.h> | |
e98ea774 | 34 | #include "pinctrl-nomadik.h" |
3a198059 | 35 | #include "../core.h" |
ba388294 | 36 | #include "../pinctrl-utils.h" |
e98ea774 | 37 | |
2ec1d359 AR |
38 | /* |
39 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
40 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 41 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
42 | * |
43 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
44 | */ | |
45 | ||
8d993397 LW |
46 | /* |
47 | * pin configurations are represented by 32-bit integers: | |
48 | * | |
49 | * bit 0.. 8 - Pin Number (512 Pins Maximum) | |
50 | * bit 9..10 - Alternate Function Selection | |
51 | * bit 11..12 - Pull up/down state | |
52 | * bit 13 - Sleep mode behaviour | |
53 | * bit 14 - Direction | |
54 | * bit 15 - Value (if output) | |
55 | * bit 16..18 - SLPM pull up/down state | |
56 | * bit 19..20 - SLPM direction | |
57 | * bit 21..22 - SLPM Value (if output) | |
58 | * bit 23..25 - PDIS value (if input) | |
59 | * bit 26 - Gpio mode | |
60 | * bit 27 - Sleep mode | |
61 | * | |
62 | * to facilitate the definition, the following macros are provided | |
63 | * | |
64 | * PIN_CFG_DEFAULT - default config (0): | |
65 | * pull up/down = disabled | |
66 | * sleep mode = input/wakeup | |
67 | * direction = input | |
68 | * value = low | |
69 | * SLPM direction = same as normal | |
70 | * SLPM pull = same as normal | |
71 | * SLPM value = same as normal | |
72 | * | |
73 | * PIN_CFG - default config with alternate function | |
74 | */ | |
75 | ||
76 | typedef unsigned long pin_cfg_t; | |
77 | ||
78 | #define PIN_NUM_MASK 0x1ff | |
79 | #define PIN_NUM(x) ((x) & PIN_NUM_MASK) | |
80 | ||
81 | #define PIN_ALT_SHIFT 9 | |
82 | #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) | |
83 | #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) | |
84 | #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) | |
85 | #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) | |
86 | #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) | |
87 | #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) | |
88 | ||
89 | #define PIN_PULL_SHIFT 11 | |
90 | #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) | |
91 | #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) | |
92 | #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) | |
93 | #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) | |
94 | #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) | |
95 | ||
96 | #define PIN_SLPM_SHIFT 13 | |
97 | #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) | |
98 | #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) | |
99 | #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) | |
100 | #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) | |
101 | /* These two replace the above in DB8500v2+ */ | |
102 | #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) | |
103 | #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) | |
104 | #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE | |
105 | ||
106 | #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ | |
107 | #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ | |
108 | ||
109 | #define PIN_DIR_SHIFT 14 | |
110 | #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) | |
111 | #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) | |
112 | #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) | |
113 | #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) | |
114 | ||
115 | #define PIN_VAL_SHIFT 15 | |
116 | #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) | |
117 | #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) | |
118 | #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) | |
119 | #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) | |
120 | ||
121 | #define PIN_SLPM_PULL_SHIFT 16 | |
122 | #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) | |
123 | #define PIN_SLPM_PULL(x) \ | |
124 | (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) | |
125 | #define PIN_SLPM_PULL_NONE \ | |
126 | ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) | |
127 | #define PIN_SLPM_PULL_UP \ | |
128 | ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) | |
129 | #define PIN_SLPM_PULL_DOWN \ | |
130 | ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) | |
131 | ||
132 | #define PIN_SLPM_DIR_SHIFT 19 | |
133 | #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) | |
134 | #define PIN_SLPM_DIR(x) \ | |
135 | (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) | |
136 | #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) | |
137 | #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) | |
138 | ||
139 | #define PIN_SLPM_VAL_SHIFT 21 | |
140 | #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) | |
141 | #define PIN_SLPM_VAL(x) \ | |
142 | (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) | |
143 | #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) | |
144 | #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) | |
145 | ||
146 | #define PIN_SLPM_PDIS_SHIFT 23 | |
147 | #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) | |
148 | #define PIN_SLPM_PDIS(x) \ | |
149 | (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) | |
150 | #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) | |
151 | #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) | |
152 | #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) | |
153 | ||
154 | #define PIN_LOWEMI_SHIFT 25 | |
155 | #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) | |
156 | #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) | |
157 | #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) | |
158 | #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) | |
159 | ||
160 | #define PIN_GPIOMODE_SHIFT 26 | |
161 | #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) | |
162 | #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) | |
163 | #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) | |
164 | #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) | |
165 | ||
166 | #define PIN_SLEEPMODE_SHIFT 27 | |
167 | #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) | |
168 | #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) | |
169 | #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) | |
170 | #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) | |
171 | ||
172 | ||
173 | /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ | |
174 | #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) | |
175 | #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) | |
176 | #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) | |
177 | #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) | |
178 | #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) | |
179 | ||
180 | #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) | |
181 | #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) | |
182 | #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) | |
183 | #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) | |
184 | #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) | |
185 | ||
186 | #define PIN_CFG_DEFAULT (0) | |
187 | ||
188 | #define PIN_CFG(num, alt) \ | |
189 | (PIN_CFG_DEFAULT |\ | |
190 | (PIN_NUM(num) | PIN_##alt)) | |
191 | ||
192 | #define PIN_CFG_INPUT(num, alt, pull) \ | |
193 | (PIN_CFG_DEFAULT |\ | |
194 | (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) | |
195 | ||
196 | #define PIN_CFG_OUTPUT(num, alt, val) \ | |
197 | (PIN_CFG_DEFAULT |\ | |
198 | (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) | |
199 | ||
200 | /* | |
201 | * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving | |
202 | * the "gpio" namespace for generic and cross-machine functions | |
203 | */ | |
204 | ||
205 | #define GPIO_BLOCK_SHIFT 5 | |
206 | #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) | |
bc222ef4 | 207 | #define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP) |
8d993397 LW |
208 | |
209 | /* Register in the logic block */ | |
210 | #define NMK_GPIO_DAT 0x00 | |
211 | #define NMK_GPIO_DATS 0x04 | |
212 | #define NMK_GPIO_DATC 0x08 | |
213 | #define NMK_GPIO_PDIS 0x0c | |
214 | #define NMK_GPIO_DIR 0x10 | |
215 | #define NMK_GPIO_DIRS 0x14 | |
216 | #define NMK_GPIO_DIRC 0x18 | |
217 | #define NMK_GPIO_SLPC 0x1c | |
218 | #define NMK_GPIO_AFSLA 0x20 | |
219 | #define NMK_GPIO_AFSLB 0x24 | |
220 | #define NMK_GPIO_LOWEMI 0x28 | |
221 | ||
222 | #define NMK_GPIO_RIMSC 0x40 | |
223 | #define NMK_GPIO_FIMSC 0x44 | |
224 | #define NMK_GPIO_IS 0x48 | |
225 | #define NMK_GPIO_IC 0x4c | |
226 | #define NMK_GPIO_RWIMSC 0x50 | |
227 | #define NMK_GPIO_FWIMSC 0x54 | |
228 | #define NMK_GPIO_WKS 0x58 | |
229 | /* These appear in DB8540 and later ASICs */ | |
230 | #define NMK_GPIO_EDGELEVEL 0x5C | |
231 | #define NMK_GPIO_LEVEL 0x60 | |
232 | ||
233 | ||
234 | /* Pull up/down values */ | |
235 | enum nmk_gpio_pull { | |
236 | NMK_GPIO_PULL_NONE, | |
237 | NMK_GPIO_PULL_UP, | |
238 | NMK_GPIO_PULL_DOWN, | |
239 | }; | |
240 | ||
241 | /* Sleep mode */ | |
242 | enum nmk_gpio_slpm { | |
243 | NMK_GPIO_SLPM_INPUT, | |
244 | NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, | |
245 | NMK_GPIO_SLPM_NOCHANGE, | |
246 | NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, | |
247 | }; | |
248 | ||
2ec1d359 AR |
249 | struct nmk_gpio_chip { |
250 | struct gpio_chip chip; | |
3007d941 | 251 | struct irq_chip irqchip; |
2ec1d359 | 252 | void __iomem *addr; |
af7dc228 | 253 | struct clk *clk; |
33b744b3 | 254 | unsigned int bank; |
2ec1d359 | 255 | unsigned int parent_irq; |
194e15ba LW |
256 | int latent_parent_irq; |
257 | u32 (*get_latent_status)(unsigned int bank); | |
01727e61 | 258 | void (*set_ioforce)(bool enable); |
c0fcb8db | 259 | spinlock_t lock; |
33d78647 | 260 | bool sleepmode; |
2ec1d359 AR |
261 | /* Keep track of configured edges */ |
262 | u32 edge_rising; | |
263 | u32 edge_falling; | |
b9df468d RV |
264 | u32 real_wake; |
265 | u32 rwimsc; | |
266 | u32 fwimsc; | |
6c12fe88 RV |
267 | u32 rimsc; |
268 | u32 fimsc; | |
bc6f5cf6 | 269 | u32 pull_up; |
ebc6178d | 270 | u32 lowemi; |
2ec1d359 AR |
271 | }; |
272 | ||
f1671bf5 JA |
273 | /** |
274 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
275 | * @dev: containing device pointer | |
276 | * @pctl: corresponding pin controller device | |
277 | * @soc: SoC data for this specific chip | |
278 | * @prcm_base: PRCM register range virtual base | |
279 | */ | |
e98ea774 LW |
280 | struct nmk_pinctrl { |
281 | struct device *dev; | |
282 | struct pinctrl_dev *pctl; | |
283 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 284 | void __iomem *prcm_base; |
e98ea774 LW |
285 | }; |
286 | ||
bc222ef4 | 287 | static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS]; |
01727e61 RV |
288 | |
289 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
290 | ||
291 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
292 | ||
6f9a974c RV |
293 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
294 | unsigned offset, int gpio_mode) | |
295 | { | |
6f9a974c RV |
296 | u32 afunc, bfunc; |
297 | ||
5e81e0a0 LW |
298 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset); |
299 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset); | |
6f9a974c | 300 | if (gpio_mode & NMK_GPIO_ALT_A) |
5e81e0a0 | 301 | afunc |= BIT(offset); |
6f9a974c | 302 | if (gpio_mode & NMK_GPIO_ALT_B) |
5e81e0a0 | 303 | bfunc |= BIT(offset); |
6f9a974c RV |
304 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); |
305 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
306 | } | |
307 | ||
81a3c298 RV |
308 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
309 | unsigned offset, enum nmk_gpio_slpm mode) | |
310 | { | |
81a3c298 RV |
311 | u32 slpm; |
312 | ||
313 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
314 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
5e81e0a0 | 315 | slpm |= BIT(offset); |
81a3c298 | 316 | else |
5e81e0a0 | 317 | slpm &= ~BIT(offset); |
81a3c298 RV |
318 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); |
319 | } | |
320 | ||
5b327edf RV |
321 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
322 | unsigned offset, enum nmk_gpio_pull pull) | |
323 | { | |
5b327edf RV |
324 | u32 pdis; |
325 | ||
326 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 327 | if (pull == NMK_GPIO_PULL_NONE) { |
5e81e0a0 LW |
328 | pdis |= BIT(offset); |
329 | nmk_chip->pull_up &= ~BIT(offset); | |
bc6f5cf6 | 330 | } else { |
5e81e0a0 | 331 | pdis &= ~BIT(offset); |
bc6f5cf6 RA |
332 | } |
333 | ||
5b327edf RV |
334 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
335 | ||
bc6f5cf6 | 336 | if (pull == NMK_GPIO_PULL_UP) { |
5e81e0a0 LW |
337 | nmk_chip->pull_up |= BIT(offset); |
338 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); | |
bc6f5cf6 | 339 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
5e81e0a0 LW |
340 | nmk_chip->pull_up &= ~BIT(offset); |
341 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); | |
bc6f5cf6 | 342 | } |
5b327edf RV |
343 | } |
344 | ||
ebc6178d RV |
345 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
346 | unsigned offset, bool lowemi) | |
347 | { | |
5e81e0a0 | 348 | bool enabled = nmk_chip->lowemi & BIT(offset); |
ebc6178d RV |
349 | |
350 | if (lowemi == enabled) | |
351 | return; | |
352 | ||
353 | if (lowemi) | |
5e81e0a0 | 354 | nmk_chip->lowemi |= BIT(offset); |
ebc6178d | 355 | else |
5e81e0a0 | 356 | nmk_chip->lowemi &= ~BIT(offset); |
ebc6178d RV |
357 | |
358 | writel_relaxed(nmk_chip->lowemi, | |
359 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
360 | } | |
361 | ||
378be066 RV |
362 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
363 | unsigned offset) | |
364 | { | |
5e81e0a0 | 365 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); |
378be066 RV |
366 | } |
367 | ||
6720db7c RV |
368 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
369 | unsigned offset, int val) | |
370 | { | |
371 | if (val) | |
5e81e0a0 | 372 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); |
6720db7c | 373 | else |
5e81e0a0 | 374 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); |
6720db7c RV |
375 | } |
376 | ||
377 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
378 | unsigned offset, int val) | |
379 | { | |
5e81e0a0 | 380 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); |
6720db7c RV |
381 | __nmk_gpio_set_output(nmk_chip, offset, val); |
382 | } | |
383 | ||
01727e61 RV |
384 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
385 | unsigned offset, int gpio_mode, | |
386 | bool glitch) | |
387 | { | |
6c12fe88 RV |
388 | u32 rwimsc = nmk_chip->rwimsc; |
389 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
390 | |
391 | if (glitch && nmk_chip->set_ioforce) { | |
392 | u32 bit = BIT(offset); | |
393 | ||
01727e61 RV |
394 | /* Prevent spurious wakeups */ |
395 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
396 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
397 | ||
398 | nmk_chip->set_ioforce(true); | |
399 | } | |
400 | ||
401 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
402 | ||
403 | if (glitch && nmk_chip->set_ioforce) { | |
404 | nmk_chip->set_ioforce(false); | |
405 | ||
406 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
407 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
408 | } | |
409 | } | |
410 | ||
6c42ad1c RV |
411 | static void |
412 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
413 | { | |
414 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
415 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
416 | int gpio = nmk_chip->chip.base + offset; | |
e0bc34a3 | 417 | int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); |
6c42ad1c RV |
418 | struct irq_data *d = irq_get_irq_data(irq); |
419 | ||
420 | if (!rising && !falling) | |
421 | return; | |
422 | ||
423 | if (!d || !irqd_irq_disabled(d)) | |
424 | return; | |
425 | ||
426 | if (rising) { | |
427 | nmk_chip->rimsc &= ~BIT(offset); | |
428 | writel_relaxed(nmk_chip->rimsc, | |
429 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
430 | } | |
431 | ||
432 | if (falling) { | |
433 | nmk_chip->fimsc &= ~BIT(offset); | |
434 | writel_relaxed(nmk_chip->fimsc, | |
435 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
436 | } | |
437 | ||
58383c78 | 438 | dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio); |
6c42ad1c RV |
439 | } |
440 | ||
f1671bf5 JA |
441 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
442 | { | |
443 | u32 val; | |
444 | ||
445 | val = readl(reg); | |
446 | val = ((val & ~mask) | (value & mask)); | |
447 | writel(val, reg); | |
448 | } | |
449 | ||
c22df08c JNG |
450 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
451 | unsigned offset, unsigned alt_num) | |
452 | { | |
453 | int i; | |
454 | u16 reg; | |
455 | u8 bit; | |
456 | u8 alt_index; | |
457 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
458 | const u16 *gpiocr_regs; | |
459 | ||
4ca075de FB |
460 | if (!npct->prcm_base) |
461 | return; | |
462 | ||
c22df08c JNG |
463 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
464 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
465 | alt_num); | |
466 | return; | |
467 | } | |
468 | ||
469 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
470 | if (npct->soc->altcx_pins[i].pin == offset) | |
471 | break; | |
472 | } | |
473 | if (i == npct->soc->npins_altcx) { | |
474 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
475 | offset); | |
476 | return; | |
477 | } | |
478 | ||
479 | pin_desc = npct->soc->altcx_pins + i; | |
480 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
481 | ||
482 | /* | |
483 | * If alt_num is NULL, just clear current ALTCx selection | |
484 | * to make sure we come back to a pure ALTC selection | |
485 | */ | |
486 | if (!alt_num) { | |
487 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
488 | if (pin_desc->altcx[i].used == true) { | |
489 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
490 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
491 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
492 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
493 | dev_dbg(npct->dev, |
494 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
495 | offset, i+1); | |
496 | } | |
497 | } | |
498 | } | |
499 | return; | |
500 | } | |
501 | ||
502 | alt_index = alt_num - 1; | |
503 | if (pin_desc->altcx[alt_index].used == false) { | |
504 | dev_warn(npct->dev, | |
505 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
506 | offset, alt_num); | |
507 | return; | |
508 | } | |
509 | ||
510 | /* | |
511 | * Check if any other ALTCx functions are activated on this pin | |
512 | * and disable it first. | |
513 | */ | |
514 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
515 | if (i == alt_index) | |
516 | continue; | |
517 | if (pin_desc->altcx[i].used == true) { | |
518 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
519 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
520 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
521 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
522 | dev_dbg(npct->dev, |
523 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
524 | offset, i+1); | |
525 | } | |
526 | } | |
527 | } | |
528 | ||
529 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
530 | bit = pin_desc->altcx[alt_index].control_bit; | |
531 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
532 | offset, alt_index+1); | |
f1671bf5 | 533 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
534 | } |
535 | ||
01727e61 RV |
536 | /* |
537 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
538 | * - Save SLPM registers | |
539 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
540 | * - Configure the GPIO registers for the IOs that are being switched | |
541 | * - Set IOFORCE=1 | |
542 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
543 | * - Set IOFORCE=0 | |
544 | * - Restore SLPM registers | |
545 | * - Any spurious wake up event during switch sequence to be ignored and | |
546 | * cleared | |
547 | */ | |
548 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
549 | { | |
550 | int i; | |
551 | ||
552 | for (i = 0; i < NUM_BANKS; i++) { | |
553 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
554 | unsigned int temp = slpm[i]; | |
555 | ||
556 | if (!chip) | |
557 | break; | |
558 | ||
3c0227d2 RV |
559 | clk_enable(chip->clk); |
560 | ||
01727e61 RV |
561 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
562 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
563 | } | |
564 | } | |
565 | ||
566 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
567 | { | |
568 | int i; | |
569 | ||
570 | for (i = 0; i < NUM_BANKS; i++) { | |
571 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
572 | ||
573 | if (!chip) | |
574 | break; | |
575 | ||
576 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
577 | |
578 | clk_disable(chip->clk); | |
01727e61 RV |
579 | } |
580 | } | |
581 | ||
0fafd50e | 582 | static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
2249b19f JNG |
583 | { |
584 | int i; | |
585 | u16 reg; | |
586 | u8 bit; | |
587 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
588 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
589 | const u16 *gpiocr_regs; | |
590 | ||
4ca075de FB |
591 | if (!npct->prcm_base) |
592 | return NMK_GPIO_ALT_C; | |
593 | ||
2249b19f JNG |
594 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
595 | if (npct->soc->altcx_pins[i].pin == gpio) | |
596 | break; | |
597 | } | |
598 | if (i == npct->soc->npins_altcx) | |
599 | return NMK_GPIO_ALT_C; | |
600 | ||
601 | pin_desc = npct->soc->altcx_pins + i; | |
602 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
603 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
604 | if (pin_desc->altcx[i].used == true) { | |
605 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
606 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 607 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
608 | return NMK_GPIO_ALT_C+i+1; |
609 | } | |
610 | } | |
611 | return NMK_GPIO_ALT_C; | |
612 | } | |
613 | ||
2ec1d359 | 614 | /* IRQ functions */ |
2ec1d359 | 615 | |
f272c00e | 616 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 617 | { |
e0bc34a3 | 618 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
68ab0126 | 619 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
3c0227d2 RV |
620 | |
621 | clk_enable(nmk_chip->clk); | |
5e81e0a0 | 622 | writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 623 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
624 | } |
625 | ||
4d4e20f7 RV |
626 | enum nmk_gpio_irq_type { |
627 | NORMAL, | |
628 | WAKE, | |
629 | }; | |
630 | ||
040e5ecd | 631 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
5e81e0a0 | 632 | int offset, enum nmk_gpio_irq_type which, |
4d4e20f7 | 633 | bool enable) |
2ec1d359 | 634 | { |
6c12fe88 RV |
635 | u32 *rimscval; |
636 | u32 *fimscval; | |
637 | u32 rimscreg; | |
638 | u32 fimscreg; | |
639 | ||
640 | if (which == NORMAL) { | |
641 | rimscreg = NMK_GPIO_RIMSC; | |
642 | fimscreg = NMK_GPIO_FIMSC; | |
643 | rimscval = &nmk_chip->rimsc; | |
644 | fimscval = &nmk_chip->fimsc; | |
645 | } else { | |
646 | rimscreg = NMK_GPIO_RWIMSC; | |
647 | fimscreg = NMK_GPIO_FWIMSC; | |
648 | rimscval = &nmk_chip->rwimsc; | |
649 | fimscval = &nmk_chip->fwimsc; | |
650 | } | |
2ec1d359 | 651 | |
040e5ecd | 652 | /* we must individually set/clear the two edges */ |
5e81e0a0 | 653 | if (nmk_chip->edge_rising & BIT(offset)) { |
040e5ecd | 654 | if (enable) |
5e81e0a0 | 655 | *rimscval |= BIT(offset); |
040e5ecd | 656 | else |
5e81e0a0 | 657 | *rimscval &= ~BIT(offset); |
6c12fe88 | 658 | writel(*rimscval, nmk_chip->addr + rimscreg); |
2ec1d359 | 659 | } |
5e81e0a0 | 660 | if (nmk_chip->edge_falling & BIT(offset)) { |
040e5ecd | 661 | if (enable) |
5e81e0a0 | 662 | *fimscval |= BIT(offset); |
040e5ecd | 663 | else |
5e81e0a0 | 664 | *fimscval &= ~BIT(offset); |
6c12fe88 | 665 | writel(*fimscval, nmk_chip->addr + fimscreg); |
2ec1d359 | 666 | } |
040e5ecd | 667 | } |
2ec1d359 | 668 | |
b9df468d | 669 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
5e81e0a0 | 670 | int offset, bool on) |
b9df468d | 671 | { |
b982ff0e RV |
672 | /* |
673 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
674 | * disabled, since setting SLPM to 1 increases power consumption, and | |
675 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
676 | */ | |
677 | if (nmk_chip->sleepmode && on) { | |
5e81e0a0 | 678 | __nmk_gpio_set_slpm(nmk_chip, offset, |
b982ff0e | 679 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
680 | } |
681 | ||
5e81e0a0 | 682 | __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); |
b9df468d RV |
683 | } |
684 | ||
685 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 686 | { |
2ec1d359 AR |
687 | struct nmk_gpio_chip *nmk_chip; |
688 | unsigned long flags; | |
2ec1d359 | 689 | |
f272c00e | 690 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 | 691 | if (!nmk_chip) |
4d4e20f7 | 692 | return -EINVAL; |
2ec1d359 | 693 | |
3c0227d2 | 694 | clk_enable(nmk_chip->clk); |
b9df468d RV |
695 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
696 | spin_lock(&nmk_chip->lock); | |
697 | ||
a60b57ed | 698 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d | 699 | |
5e81e0a0 | 700 | if (!(nmk_chip->real_wake & BIT(d->hwirq))) |
a60b57ed | 701 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
702 | |
703 | spin_unlock(&nmk_chip->lock); | |
704 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 705 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
706 | |
707 | return 0; | |
2ec1d359 AR |
708 | } |
709 | ||
f272c00e | 710 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 711 | { |
b9df468d | 712 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 713 | } |
040e5ecd | 714 | |
f272c00e | 715 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 716 | { |
b9df468d | 717 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
718 | } |
719 | ||
f272c00e | 720 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 721 | { |
7e3f7e59 RV |
722 | struct nmk_gpio_chip *nmk_chip; |
723 | unsigned long flags; | |
7e3f7e59 | 724 | |
f272c00e | 725 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
726 | if (!nmk_chip) |
727 | return -EINVAL; | |
728 | ||
3c0227d2 | 729 | clk_enable(nmk_chip->clk); |
01727e61 RV |
730 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
731 | spin_lock(&nmk_chip->lock); | |
732 | ||
479a0c7e | 733 | if (irqd_irq_disabled(d)) |
a60b57ed | 734 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
735 | |
736 | if (on) | |
5e81e0a0 | 737 | nmk_chip->real_wake |= BIT(d->hwirq); |
b9df468d | 738 | else |
5e81e0a0 | 739 | nmk_chip->real_wake &= ~BIT(d->hwirq); |
01727e61 RV |
740 | |
741 | spin_unlock(&nmk_chip->lock); | |
742 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 743 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
744 | |
745 | return 0; | |
040e5ecd RV |
746 | } |
747 | ||
f272c00e | 748 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 749 | { |
479a0c7e | 750 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 751 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
752 | struct nmk_gpio_chip *nmk_chip; |
753 | unsigned long flags; | |
2ec1d359 | 754 | |
f272c00e | 755 | nmk_chip = irq_data_get_irq_chip_data(d); |
2ec1d359 AR |
756 | if (!nmk_chip) |
757 | return -EINVAL; | |
2ec1d359 AR |
758 | if (type & IRQ_TYPE_LEVEL_HIGH) |
759 | return -EINVAL; | |
760 | if (type & IRQ_TYPE_LEVEL_LOW) | |
761 | return -EINVAL; | |
762 | ||
3c0227d2 | 763 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
764 | spin_lock_irqsave(&nmk_chip->lock, flags); |
765 | ||
7a852d80 | 766 | if (enabled) |
a60b57ed | 767 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 768 | |
b9df468d | 769 | if (enabled || wake) |
a60b57ed | 770 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 771 | |
5e81e0a0 | 772 | nmk_chip->edge_rising &= ~BIT(d->hwirq); |
2ec1d359 | 773 | if (type & IRQ_TYPE_EDGE_RISING) |
5e81e0a0 | 774 | nmk_chip->edge_rising |= BIT(d->hwirq); |
2ec1d359 | 775 | |
5e81e0a0 | 776 | nmk_chip->edge_falling &= ~BIT(d->hwirq); |
2ec1d359 | 777 | if (type & IRQ_TYPE_EDGE_FALLING) |
5e81e0a0 | 778 | nmk_chip->edge_falling |= BIT(d->hwirq); |
2ec1d359 | 779 | |
7a852d80 | 780 | if (enabled) |
a60b57ed | 781 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 782 | |
b9df468d | 783 | if (enabled || wake) |
a60b57ed | 784 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 785 | |
7a852d80 | 786 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 787 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
788 | |
789 | return 0; | |
790 | } | |
791 | ||
3c0227d2 RV |
792 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
793 | { | |
794 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 795 | |
3c0227d2 RV |
796 | clk_enable(nmk_chip->clk); |
797 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
798 | return 0; |
799 | } | |
800 | ||
3c0227d2 RV |
801 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
802 | { | |
803 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
804 | ||
805 | nmk_gpio_irq_mask(d); | |
806 | clk_disable(nmk_chip->clk); | |
807 | } | |
808 | ||
5663bb27 | 809 | static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) |
2ec1d359 | 810 | { |
5663bb27 | 811 | struct irq_chip *host_chip = irq_desc_get_chip(desc); |
e0bc34a3 | 812 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
2ec1d359 | 813 | |
adfed159 | 814 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 815 | |
33b744b3 RV |
816 | while (status) { |
817 | int bit = __ffs(status); | |
818 | ||
e0bc34a3 | 819 | generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); |
33b744b3 | 820 | status &= ~BIT(bit); |
2ec1d359 | 821 | } |
aaedaa2b | 822 | |
adfed159 | 823 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
824 | } |
825 | ||
bd0b9ac4 | 826 | static void nmk_gpio_irq_handler(struct irq_desc *desc) |
33b744b3 | 827 | { |
e0bc34a3 | 828 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
68ab0126 | 829 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
3c0227d2 RV |
830 | u32 status; |
831 | ||
832 | clk_enable(nmk_chip->clk); | |
833 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
834 | clk_disable(nmk_chip->clk); | |
33b744b3 | 835 | |
5663bb27 | 836 | __nmk_gpio_irq_handler(desc, status); |
33b744b3 RV |
837 | } |
838 | ||
bd0b9ac4 | 839 | static void nmk_gpio_latent_irq_handler(struct irq_desc *desc) |
33b744b3 | 840 | { |
e0bc34a3 | 841 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
68ab0126 | 842 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
194e15ba | 843 | u32 status = nmk_chip->get_latent_status(nmk_chip->bank); |
33b744b3 | 844 | |
5663bb27 | 845 | __nmk_gpio_irq_handler(desc, status); |
33b744b3 RV |
846 | } |
847 | ||
2ec1d359 | 848 | /* I/O Functions */ |
dbfe8ca2 | 849 | |
67668a57 LW |
850 | static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset) |
851 | { | |
852 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); | |
853 | int dir; | |
854 | ||
855 | clk_enable(nmk_chip->clk); | |
856 | ||
6b1a7c9e | 857 | dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); |
67668a57 LW |
858 | |
859 | clk_disable(nmk_chip->clk); | |
860 | ||
861 | return dir; | |
862 | } | |
863 | ||
2ec1d359 AR |
864 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
865 | { | |
68ab0126 | 866 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
2ec1d359 | 867 | |
3c0227d2 RV |
868 | clk_enable(nmk_chip->clk); |
869 | ||
5e81e0a0 | 870 | writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
871 | |
872 | clk_disable(nmk_chip->clk); | |
873 | ||
2ec1d359 AR |
874 | return 0; |
875 | } | |
876 | ||
2ec1d359 AR |
877 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
878 | { | |
68ab0126 | 879 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
3c0227d2 RV |
880 | int value; |
881 | ||
882 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 883 | |
5e81e0a0 | 884 | value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); |
2ec1d359 | 885 | |
3c0227d2 RV |
886 | clk_disable(nmk_chip->clk); |
887 | ||
888 | return value; | |
2ec1d359 AR |
889 | } |
890 | ||
891 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
892 | int val) | |
893 | { | |
68ab0126 | 894 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
2ec1d359 | 895 | |
3c0227d2 RV |
896 | clk_enable(nmk_chip->clk); |
897 | ||
6720db7c | 898 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
899 | |
900 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
901 | } |
902 | ||
6647c6c0 RV |
903 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
904 | int val) | |
905 | { | |
68ab0126 | 906 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
6647c6c0 | 907 | |
3c0227d2 RV |
908 | clk_enable(nmk_chip->clk); |
909 | ||
6720db7c | 910 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 911 | |
3c0227d2 RV |
912 | clk_disable(nmk_chip->clk); |
913 | ||
6647c6c0 RV |
914 | return 0; |
915 | } | |
916 | ||
d0b543c7 | 917 | #ifdef CONFIG_DEBUG_FS |
caee57ec AB |
918 | static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) |
919 | { | |
920 | u32 afunc, bfunc; | |
921 | ||
922 | clk_enable(nmk_chip->clk); | |
923 | ||
924 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); | |
925 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); | |
926 | ||
927 | clk_disable(nmk_chip->clk); | |
928 | ||
929 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
930 | } | |
d0b543c7 RV |
931 | |
932 | #include <linux/seq_file.h> | |
933 | ||
2249b19f JNG |
934 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
935 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
936 | unsigned offset, unsigned gpio) | |
d0b543c7 | 937 | { |
6f4350a6 | 938 | const char *label = gpiochip_is_requested(chip, offset); |
68ab0126 | 939 | struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); |
6f4350a6 LW |
940 | int mode; |
941 | bool is_out; | |
8f1774a2 | 942 | bool data_out; |
6f4350a6 | 943 | bool pull; |
d0b543c7 RV |
944 | const char *modes[] = { |
945 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
946 | [NMK_GPIO_ALT_A] = "altA", | |
947 | [NMK_GPIO_ALT_B] = "altB", | |
948 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
949 | [NMK_GPIO_ALT_C+1] = "altC1", |
950 | [NMK_GPIO_ALT_C+2] = "altC2", | |
951 | [NMK_GPIO_ALT_C+3] = "altC3", | |
952 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 | 953 | }; |
8f1774a2 LW |
954 | const char *pulls[] = { |
955 | "none ", | |
956 | "pull down", | |
957 | "pull up ", | |
958 | }; | |
d0b543c7 | 959 | |
3c0227d2 | 960 | clk_enable(nmk_chip->clk); |
5e81e0a0 LW |
961 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); |
962 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); | |
963 | data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); | |
964 | mode = nmk_gpio_get_mode(nmk_chip, offset); | |
2249b19f JNG |
965 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
966 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 | 967 | |
8f1774a2 LW |
968 | if (is_out) { |
969 | seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", | |
970 | gpio, | |
971 | label ?: "(none)", | |
972 | data_out ? "hi" : "lo", | |
973 | (mode < 0) ? "unknown" : modes[mode]); | |
974 | } else { | |
4705845b | 975 | int irq = gpio_to_irq(gpio); |
6f4350a6 | 976 | struct irq_desc *desc = irq_to_desc(irq); |
8f1774a2 | 977 | int pullidx = 0; |
d7f005e8 | 978 | int val; |
8f1774a2 LW |
979 | |
980 | if (pull) | |
6ee33455 | 981 | pullidx = data_out ? 2 : 1; |
8f1774a2 LW |
982 | |
983 | seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", | |
984 | gpio, | |
985 | label ?: "(none)", | |
986 | pulls[pullidx], | |
987 | (mode < 0) ? "unknown" : modes[mode]); | |
d7f005e8 LW |
988 | |
989 | val = nmk_gpio_get_input(chip, offset); | |
990 | seq_printf(s, " VAL %d", val); | |
991 | ||
8f1774a2 LW |
992 | /* |
993 | * This races with request_irq(), set_irq_type(), | |
6f4350a6 LW |
994 | * and set_irq_wake() ... but those are "rare". |
995 | */ | |
4705845b | 996 | if (irq > 0 && desc && desc->action) { |
6f4350a6 | 997 | char *trigger; |
6f4350a6 | 998 | |
5e81e0a0 | 999 | if (nmk_chip->edge_rising & BIT(offset)) |
6f4350a6 | 1000 | trigger = "edge-rising"; |
5e81e0a0 | 1001 | else if (nmk_chip->edge_falling & BIT(offset)) |
6f4350a6 LW |
1002 | trigger = "edge-falling"; |
1003 | else | |
1004 | trigger = "edge-undefined"; | |
1005 | ||
1006 | seq_printf(s, " irq-%d %s%s", | |
1007 | irq, trigger, | |
1008 | irqd_is_wakeup_set(&desc->irq_data) | |
1009 | ? " wakeup" : ""); | |
8ea72a30 | 1010 | } |
6f4350a6 LW |
1011 | } |
1012 | clk_disable(nmk_chip->clk); | |
1013 | } | |
1014 | ||
1015 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1016 | { | |
1017 | unsigned i; | |
1018 | unsigned gpio = chip->base; | |
8ea72a30 | 1019 | |
6f4350a6 | 1020 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 1021 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
1022 | seq_printf(s, "\n"); |
1023 | } | |
1024 | } | |
1025 | ||
1026 | #else | |
6f4350a6 | 1027 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1028 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1029 | struct gpio_chip *chip, |
1030 | unsigned offset, unsigned gpio) | |
1031 | { | |
1032 | } | |
d0b543c7 RV |
1033 | #define nmk_gpio_dbg_show NULL |
1034 | #endif | |
1035 | ||
3c0227d2 RV |
1036 | void nmk_gpio_clocks_enable(void) |
1037 | { | |
1038 | int i; | |
1039 | ||
1040 | for (i = 0; i < NUM_BANKS; i++) { | |
1041 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1042 | ||
1043 | if (!chip) | |
1044 | continue; | |
1045 | ||
1046 | clk_enable(chip->clk); | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | void nmk_gpio_clocks_disable(void) | |
1051 | { | |
1052 | int i; | |
1053 | ||
1054 | for (i = 0; i < NUM_BANKS; i++) { | |
1055 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1056 | ||
1057 | if (!chip) | |
1058 | continue; | |
1059 | ||
1060 | clk_disable(chip->clk); | |
1061 | } | |
1062 | } | |
1063 | ||
b9df468d RV |
1064 | /* |
1065 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1066 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1067 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1068 | * cpuidle. | |
1069 | * | |
1070 | * PM ops are not used since this needs to be done at the end, after all the | |
1071 | * other drivers are done with their suspend callbacks. | |
1072 | */ | |
1073 | void nmk_gpio_wakeups_suspend(void) | |
1074 | { | |
1075 | int i; | |
1076 | ||
1077 | for (i = 0; i < NUM_BANKS; i++) { | |
1078 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1079 | ||
1080 | if (!chip) | |
1081 | break; | |
1082 | ||
3c0227d2 RV |
1083 | clk_enable(chip->clk); |
1084 | ||
b9df468d RV |
1085 | writel(chip->rwimsc & chip->real_wake, |
1086 | chip->addr + NMK_GPIO_RWIMSC); | |
1087 | writel(chip->fwimsc & chip->real_wake, | |
1088 | chip->addr + NMK_GPIO_FWIMSC); | |
1089 | ||
3c0227d2 | 1090 | clk_disable(chip->clk); |
b9df468d RV |
1091 | } |
1092 | } | |
1093 | ||
1094 | void nmk_gpio_wakeups_resume(void) | |
1095 | { | |
1096 | int i; | |
1097 | ||
1098 | for (i = 0; i < NUM_BANKS; i++) { | |
1099 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1100 | ||
1101 | if (!chip) | |
1102 | break; | |
1103 | ||
3c0227d2 RV |
1104 | clk_enable(chip->clk); |
1105 | ||
b9df468d RV |
1106 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1107 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1108 | ||
3c0227d2 | 1109 | clk_disable(chip->clk); |
b9df468d RV |
1110 | } |
1111 | } | |
1112 | ||
bc6f5cf6 RA |
1113 | /* |
1114 | * Read the pull up/pull down status. | |
1115 | * A bit set in 'pull_up' means that pull up | |
1116 | * is selected if pull is enabled in PDIS register. | |
1117 | * Note: only pull up/down set via this driver can | |
1118 | * be detected due to HW limitations. | |
1119 | */ | |
1120 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1121 | { | |
1122 | if (gpio_bank < NUM_BANKS) { | |
1123 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1124 | ||
1125 | if (!chip) | |
1126 | return; | |
1127 | ||
1128 | *pull_up = chip->pull_up; | |
1129 | } | |
1130 | } | |
1131 | ||
bc222ef4 LW |
1132 | /* |
1133 | * We will allocate memory for the state container using devm* allocators | |
1134 | * binding to the first device reaching this point, it doesn't matter if | |
1135 | * it is the pin controller or GPIO driver. However we need to use the right | |
1136 | * platform device when looking up resources so pay attention to pdev. | |
1137 | */ | |
1138 | static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np, | |
1139 | struct platform_device *pdev) | |
1140 | { | |
1141 | struct nmk_gpio_chip *nmk_chip; | |
1142 | struct platform_device *gpio_pdev; | |
1143 | struct gpio_chip *chip; | |
1144 | struct resource *res; | |
1145 | struct clk *clk; | |
1146 | void __iomem *base; | |
1147 | u32 id; | |
1148 | ||
1149 | gpio_pdev = of_find_device_by_node(np); | |
1150 | if (!gpio_pdev) { | |
1151 | pr_err("populate \"%s\": device not found\n", np->name); | |
1152 | return ERR_PTR(-ENODEV); | |
1153 | } | |
1154 | if (of_property_read_u32(np, "gpio-bank", &id)) { | |
1155 | dev_err(&pdev->dev, "populate: gpio-bank property not found\n"); | |
1156 | return ERR_PTR(-EINVAL); | |
1157 | } | |
1158 | ||
1159 | /* Already populated? */ | |
1160 | nmk_chip = nmk_gpio_chips[id]; | |
1161 | if (nmk_chip) | |
1162 | return nmk_chip; | |
1163 | ||
1164 | nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL); | |
1165 | if (!nmk_chip) | |
1166 | return ERR_PTR(-ENOMEM); | |
1167 | ||
1168 | nmk_chip->bank = id; | |
1169 | chip = &nmk_chip->chip; | |
1170 | chip->base = id * NMK_GPIO_PER_CHIP; | |
1171 | chip->ngpio = NMK_GPIO_PER_CHIP; | |
1172 | chip->label = dev_name(&gpio_pdev->dev); | |
58383c78 | 1173 | chip->parent = &gpio_pdev->dev; |
bc222ef4 LW |
1174 | |
1175 | res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); | |
1176 | base = devm_ioremap_resource(&pdev->dev, res); | |
1177 | if (IS_ERR(base)) | |
1178 | return base; | |
1179 | nmk_chip->addr = base; | |
1180 | ||
1181 | clk = clk_get(&gpio_pdev->dev, NULL); | |
1182 | if (IS_ERR(clk)) | |
1183 | return (void *) clk; | |
1184 | clk_prepare(clk); | |
1185 | nmk_chip->clk = clk; | |
1186 | ||
1187 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); | |
1188 | nmk_gpio_chips[id] = nmk_chip; | |
1189 | return nmk_chip; | |
1190 | } | |
1191 | ||
150632b0 | 1192 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1193 | { |
513c27f8 | 1194 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1195 | struct nmk_gpio_chip *nmk_chip; |
1196 | struct gpio_chip *chip; | |
3007d941 | 1197 | struct irq_chip *irqchip; |
194e15ba | 1198 | int latent_irq; |
8f18bcfc | 1199 | bool supports_sleepmode; |
3e3c62ca | 1200 | int irq; |
2ec1d359 AR |
1201 | int ret; |
1202 | ||
bc222ef4 LW |
1203 | nmk_chip = nmk_gpio_populate_chip(np, dev); |
1204 | if (IS_ERR(nmk_chip)) { | |
1205 | dev_err(&dev->dev, "could not populate nmk chip struct\n"); | |
1206 | return PTR_ERR(nmk_chip); | |
1207 | } | |
1208 | ||
f4b3f523 | 1209 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
8f18bcfc LW |
1210 | supports_sleepmode = true; |
1211 | else | |
1212 | supports_sleepmode = false; | |
513c27f8 | 1213 | |
bc222ef4 LW |
1214 | /* Correct platform device ID */ |
1215 | dev->id = nmk_chip->bank; | |
3e3c62ca | 1216 | |
3e3c62ca | 1217 | irq = platform_get_irq(dev, 0); |
50f690d8 LW |
1218 | if (irq < 0) |
1219 | return irq; | |
3e3c62ca | 1220 | |
8f18bcfc | 1221 | /* It's OK for this IRQ not to be present */ |
194e15ba | 1222 | latent_irq = platform_get_irq(dev, 1); |
33b744b3 | 1223 | |
2ec1d359 AR |
1224 | /* |
1225 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1226 | * so we can simply convert the resource address, without remapping | |
1227 | */ | |
3e3c62ca | 1228 | nmk_chip->parent_irq = irq; |
194e15ba | 1229 | nmk_chip->latent_parent_irq = latent_irq; |
8f18bcfc | 1230 | nmk_chip->sleepmode = supports_sleepmode; |
c0fcb8db | 1231 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1232 | |
1233 | chip = &nmk_chip->chip; | |
98c85d58 JG |
1234 | chip->request = gpiochip_generic_request; |
1235 | chip->free = gpiochip_generic_free; | |
67668a57 | 1236 | chip->get_direction = nmk_gpio_get_dir; |
3007d941 LW |
1237 | chip->direction_input = nmk_gpio_make_input; |
1238 | chip->get = nmk_gpio_get_input; | |
1239 | chip->direction_output = nmk_gpio_make_output; | |
1240 | chip->set = nmk_gpio_set_output; | |
1241 | chip->dbg_show = nmk_gpio_dbg_show; | |
1242 | chip->can_sleep = false; | |
2ec1d359 AR |
1243 | chip->owner = THIS_MODULE; |
1244 | ||
3007d941 LW |
1245 | irqchip = &nmk_chip->irqchip; |
1246 | irqchip->irq_ack = nmk_gpio_irq_ack; | |
1247 | irqchip->irq_mask = nmk_gpio_irq_mask; | |
1248 | irqchip->irq_unmask = nmk_gpio_irq_unmask; | |
1249 | irqchip->irq_set_type = nmk_gpio_irq_set_type; | |
1250 | irqchip->irq_set_wake = nmk_gpio_irq_set_wake; | |
1251 | irqchip->irq_startup = nmk_gpio_irq_startup; | |
1252 | irqchip->irq_shutdown = nmk_gpio_irq_shutdown; | |
1253 | irqchip->flags = IRQCHIP_MASK_ON_SUSPEND; | |
1254 | irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u", | |
1255 | dev->id, | |
1256 | chip->base, | |
1257 | chip->base + chip->ngpio - 1); | |
1258 | ||
ebc6178d RV |
1259 | clk_enable(nmk_chip->clk); |
1260 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1261 | clk_disable(nmk_chip->clk); | |
513c27f8 LJ |
1262 | chip->of_node = np; |
1263 | ||
68ab0126 | 1264 | ret = gpiochip_add_data(chip, nmk_chip); |
2ec1d359 | 1265 | if (ret) |
50f690d8 | 1266 | return ret; |
2ec1d359 | 1267 | |
3e3c62ca | 1268 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1269 | |
e0bc34a3 LW |
1270 | /* |
1271 | * Let the generic code handle this edge IRQ, the the chained | |
1272 | * handler will perform the actual work of handling the parent | |
1273 | * interrupt. | |
1274 | */ | |
3007d941 LW |
1275 | ret = gpiochip_irqchip_add(chip, |
1276 | irqchip, | |
e0bc34a3 LW |
1277 | 0, |
1278 | handle_edge_irq, | |
1279 | IRQ_TYPE_EDGE_FALLING); | |
1280 | if (ret) { | |
1281 | dev_err(&dev->dev, "could not add irqchip\n"); | |
2fcea6ce | 1282 | gpiochip_remove(&nmk_chip->chip); |
e0bc34a3 | 1283 | return -ENODEV; |
a60b57ed | 1284 | } |
e0bc34a3 | 1285 | /* Then register the chain on the parent IRQ */ |
3007d941 LW |
1286 | gpiochip_set_chained_irqchip(chip, |
1287 | irqchip, | |
e0bc34a3 LW |
1288 | nmk_chip->parent_irq, |
1289 | nmk_gpio_irq_handler); | |
1290 | if (nmk_chip->latent_parent_irq > 0) | |
3007d941 LW |
1291 | gpiochip_set_chained_irqchip(chip, |
1292 | irqchip, | |
e0bc34a3 LW |
1293 | nmk_chip->latent_parent_irq, |
1294 | nmk_gpio_latent_irq_handler); | |
2ec1d359 | 1295 | |
513c27f8 LJ |
1296 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1297 | ||
2ec1d359 | 1298 | return 0; |
2ec1d359 AR |
1299 | } |
1300 | ||
e98ea774 LW |
1301 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1302 | { | |
1303 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1304 | ||
1305 | return npct->soc->ngroups; | |
1306 | } | |
1307 | ||
1308 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1309 | unsigned selector) | |
1310 | { | |
1311 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1312 | ||
1313 | return npct->soc->groups[selector].name; | |
1314 | } | |
1315 | ||
1316 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1317 | const unsigned **pins, | |
1318 | unsigned *num_pins) | |
1319 | { | |
1320 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1321 | ||
1322 | *pins = npct->soc->groups[selector].pins; | |
1323 | *num_pins = npct->soc->groups[selector].npins; | |
1324 | return 0; | |
1325 | } | |
1326 | ||
6ca7d2e3 | 1327 | static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin) |
24cbdd75 | 1328 | { |
24cbdd75 | 1329 | int i; |
6ca7d2e3 | 1330 | struct nmk_gpio_chip *nmk_gpio; |
24cbdd75 | 1331 | |
6ca7d2e3 LW |
1332 | for(i = 0; i < NMK_MAX_BANKS; i++) { |
1333 | nmk_gpio = nmk_gpio_chips[i]; | |
1334 | if (!nmk_gpio) | |
1335 | continue; | |
1336 | if (pin >= nmk_gpio->chip.base && | |
1337 | pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio) | |
1338 | return nmk_gpio; | |
24cbdd75 LW |
1339 | } |
1340 | return NULL; | |
1341 | } | |
1342 | ||
6ca7d2e3 LW |
1343 | static struct gpio_chip *find_gc_from_pin(unsigned pin) |
1344 | { | |
1345 | struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin); | |
1346 | ||
1347 | if (nmk_gpio) | |
1348 | return &nmk_gpio->chip; | |
1349 | return NULL; | |
1350 | } | |
1351 | ||
e98ea774 LW |
1352 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1353 | unsigned offset) | |
1354 | { | |
6ca7d2e3 | 1355 | struct gpio_chip *chip = find_gc_from_pin(offset); |
24cbdd75 | 1356 | |
6ca7d2e3 | 1357 | if (!chip) { |
24cbdd75 LW |
1358 | seq_printf(s, "invalid pin offset"); |
1359 | return; | |
1360 | } | |
2249b19f | 1361 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1362 | } |
1363 | ||
e32af889 GF |
1364 | static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, |
1365 | unsigned *num_maps, const char *group, | |
1366 | const char *function) | |
1367 | { | |
1368 | if (*num_maps == *reserved_maps) | |
1369 | return -ENOSPC; | |
1370 | ||
1371 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
1372 | (*map)[*num_maps].data.mux.group = group; | |
1373 | (*map)[*num_maps].data.mux.function = function; | |
1374 | (*num_maps)++; | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | static int nmk_dt_add_map_configs(struct pinctrl_map **map, | |
1380 | unsigned *reserved_maps, | |
1381 | unsigned *num_maps, const char *group, | |
1382 | unsigned long *configs, unsigned num_configs) | |
1383 | { | |
1384 | unsigned long *dup_configs; | |
1385 | ||
1386 | if (*num_maps == *reserved_maps) | |
1387 | return -ENOSPC; | |
1388 | ||
1389 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
1390 | GFP_KERNEL); | |
1391 | if (!dup_configs) | |
1392 | return -ENOMEM; | |
1393 | ||
1394 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
1395 | ||
1396 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
1397 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
1398 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
1399 | (*num_maps)++; | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
87ff934a SK |
1404 | #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } |
1405 | #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ | |
e32af889 GF |
1406 | .size = ARRAY_SIZE(y), } |
1407 | ||
1408 | static const unsigned long nmk_pin_input_modes[] = { | |
1409 | PIN_INPUT_NOPULL, | |
1410 | PIN_INPUT_PULLUP, | |
1411 | PIN_INPUT_PULLDOWN, | |
1412 | }; | |
1413 | ||
1414 | static const unsigned long nmk_pin_output_modes[] = { | |
1415 | PIN_OUTPUT_LOW, | |
1416 | PIN_OUTPUT_HIGH, | |
1417 | PIN_DIR_OUTPUT, | |
1418 | }; | |
1419 | ||
1420 | static const unsigned long nmk_pin_sleep_modes[] = { | |
1421 | PIN_SLEEPMODE_DISABLED, | |
1422 | PIN_SLEEPMODE_ENABLED, | |
1423 | }; | |
1424 | ||
1425 | static const unsigned long nmk_pin_sleep_input_modes[] = { | |
1426 | PIN_SLPM_INPUT_NOPULL, | |
1427 | PIN_SLPM_INPUT_PULLUP, | |
1428 | PIN_SLPM_INPUT_PULLDOWN, | |
1429 | PIN_SLPM_DIR_INPUT, | |
1430 | }; | |
1431 | ||
1432 | static const unsigned long nmk_pin_sleep_output_modes[] = { | |
1433 | PIN_SLPM_OUTPUT_LOW, | |
1434 | PIN_SLPM_OUTPUT_HIGH, | |
1435 | PIN_SLPM_DIR_OUTPUT, | |
1436 | }; | |
1437 | ||
1438 | static const unsigned long nmk_pin_sleep_wakeup_modes[] = { | |
1439 | PIN_SLPM_WAKEUP_DISABLE, | |
1440 | PIN_SLPM_WAKEUP_ENABLE, | |
1441 | }; | |
1442 | ||
1443 | static const unsigned long nmk_pin_gpio_modes[] = { | |
1444 | PIN_GPIOMODE_DISABLED, | |
1445 | PIN_GPIOMODE_ENABLED, | |
1446 | }; | |
1447 | ||
1448 | static const unsigned long nmk_pin_sleep_pdis_modes[] = { | |
1449 | PIN_SLPM_PDIS_DISABLED, | |
1450 | PIN_SLPM_PDIS_ENABLED, | |
1451 | }; | |
1452 | ||
1453 | struct nmk_cfg_param { | |
1454 | const char *property; | |
1455 | unsigned long config; | |
1456 | const unsigned long *choice; | |
1457 | int size; | |
1458 | }; | |
1459 | ||
1460 | static const struct nmk_cfg_param nmk_cfg_params[] = { | |
1461 | NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), | |
1462 | NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), | |
1463 | NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), | |
1464 | NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), | |
1465 | NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), | |
1466 | NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), | |
1467 | NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), | |
1468 | NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), | |
1469 | }; | |
1470 | ||
1471 | static int nmk_dt_pin_config(int index, int val, unsigned long *config) | |
1472 | { | |
1473 | int ret = 0; | |
1474 | ||
1475 | if (nmk_cfg_params[index].choice == NULL) | |
1476 | *config = nmk_cfg_params[index].config; | |
1477 | else { | |
1478 | /* test if out of range */ | |
1479 | if (val < nmk_cfg_params[index].size) { | |
1480 | *config = nmk_cfg_params[index].config | | |
1481 | nmk_cfg_params[index].choice[val]; | |
1482 | } | |
1483 | } | |
1484 | return ret; | |
1485 | } | |
1486 | ||
1487 | static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) | |
1488 | { | |
1489 | int i, pin_number; | |
1490 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1491 | ||
1492 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
1493 | for (i = 0; i < npct->soc->npins; i++) | |
1494 | if (npct->soc->pins[i].number == pin_number) | |
1495 | return npct->soc->pins[i].name; | |
1496 | return NULL; | |
1497 | } | |
1498 | ||
1499 | static bool nmk_pinctrl_dt_get_config(struct device_node *np, | |
1500 | unsigned long *configs) | |
1501 | { | |
1502 | bool has_config = 0; | |
1503 | unsigned long cfg = 0; | |
1504 | int i, val, ret; | |
1505 | ||
1506 | for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { | |
1507 | ret = of_property_read_u32(np, | |
1508 | nmk_cfg_params[i].property, &val); | |
1509 | if (ret != -EINVAL) { | |
1510 | if (nmk_dt_pin_config(i, val, &cfg) == 0) { | |
1511 | *configs |= cfg; | |
1512 | has_config = 1; | |
1513 | } | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | return has_config; | |
1518 | } | |
1519 | ||
2230a36e | 1520 | static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1521 | struct device_node *np, |
1522 | struct pinctrl_map **map, | |
1523 | unsigned *reserved_maps, | |
1524 | unsigned *num_maps) | |
1525 | { | |
1526 | int ret; | |
1527 | const char *function = NULL; | |
1528 | unsigned long configs = 0; | |
1529 | bool has_config = 0; | |
e32af889 | 1530 | struct property *prop; |
e32af889 GF |
1531 | struct device_node *np_config; |
1532 | ||
68d41f23 | 1533 | ret = of_property_read_string(np, "function", &function); |
c2f6d059 | 1534 | if (ret >= 0) { |
68d41f23 LW |
1535 | const char *group; |
1536 | ||
1537 | ret = of_property_count_strings(np, "groups"); | |
c2f6d059 LW |
1538 | if (ret < 0) |
1539 | goto exit; | |
1540 | ||
1541 | ret = pinctrl_utils_reserve_map(pctldev, map, | |
1542 | reserved_maps, | |
1543 | num_maps, ret); | |
1544 | if (ret < 0) | |
1545 | goto exit; | |
1546 | ||
68d41f23 | 1547 | of_property_for_each_string(np, "groups", prop, group) { |
e32af889 GF |
1548 | ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, |
1549 | group, function); | |
1550 | if (ret < 0) | |
1551 | goto exit; | |
1552 | } | |
c2f6d059 LW |
1553 | } |
1554 | ||
1555 | has_config = nmk_pinctrl_dt_get_config(np, &configs); | |
1556 | np_config = of_parse_phandle(np, "ste,config", 0); | |
1557 | if (np_config) | |
1558 | has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); | |
1559 | if (has_config) { | |
68d41f23 LW |
1560 | const char *gpio_name; |
1561 | const char *pin; | |
1562 | ||
1637d480 | 1563 | ret = of_property_count_strings(np, "pins"); |
c2f6d059 LW |
1564 | if (ret < 0) |
1565 | goto exit; | |
1566 | ret = pinctrl_utils_reserve_map(pctldev, map, | |
1567 | reserved_maps, | |
1568 | num_maps, ret); | |
1569 | if (ret < 0) | |
1570 | goto exit; | |
1571 | ||
1637d480 | 1572 | of_property_for_each_string(np, "pins", prop, pin) { |
68d41f23 | 1573 | gpio_name = nmk_find_pin_name(pctldev, pin); |
e32af889 | 1574 | |
c2f6d059 LW |
1575 | ret = nmk_dt_add_map_configs(map, reserved_maps, |
1576 | num_maps, | |
1577 | gpio_name, &configs, 1); | |
e32af889 GF |
1578 | if (ret < 0) |
1579 | goto exit; | |
1580 | } | |
e32af889 | 1581 | } |
c2f6d059 | 1582 | |
e32af889 GF |
1583 | exit: |
1584 | return ret; | |
1585 | } | |
1586 | ||
2230a36e | 1587 | static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1588 | struct device_node *np_config, |
1589 | struct pinctrl_map **map, unsigned *num_maps) | |
1590 | { | |
1591 | unsigned reserved_maps; | |
1592 | struct device_node *np; | |
1593 | int ret; | |
1594 | ||
1595 | reserved_maps = 0; | |
1596 | *map = NULL; | |
1597 | *num_maps = 0; | |
1598 | ||
1599 | for_each_child_of_node(np_config, np) { | |
1600 | ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, | |
1601 | &reserved_maps, num_maps); | |
1602 | if (ret < 0) { | |
d32f7fd3 | 1603 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
e32af889 GF |
1604 | return ret; |
1605 | } | |
1606 | } | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
022ab148 | 1611 | static const struct pinctrl_ops nmk_pinctrl_ops = { |
e98ea774 LW |
1612 | .get_groups_count = nmk_get_groups_cnt, |
1613 | .get_group_name = nmk_get_group_name, | |
1614 | .get_group_pins = nmk_get_group_pins, | |
1615 | .pin_dbg_show = nmk_pin_dbg_show, | |
e32af889 | 1616 | .dt_node_to_map = nmk_pinctrl_dt_node_to_map, |
d32f7fd3 | 1617 | .dt_free_map = pinctrl_utils_free_map, |
e98ea774 LW |
1618 | }; |
1619 | ||
dbfe8ca2 LW |
1620 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1621 | { | |
1622 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1623 | ||
1624 | return npct->soc->nfunctions; | |
1625 | } | |
1626 | ||
1627 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1628 | unsigned function) | |
1629 | { | |
1630 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1631 | ||
1632 | return npct->soc->functions[function].name; | |
1633 | } | |
1634 | ||
1635 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1636 | unsigned function, | |
1637 | const char * const **groups, | |
1638 | unsigned * const num_groups) | |
1639 | { | |
1640 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1641 | ||
1642 | *groups = npct->soc->functions[function].groups; | |
1643 | *num_groups = npct->soc->functions[function].ngroups; | |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
03e9f0ca LW |
1648 | static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function, |
1649 | unsigned group) | |
dbfe8ca2 LW |
1650 | { |
1651 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1652 | const struct nmk_pingroup *g; | |
1653 | static unsigned int slpm[NUM_BANKS]; | |
f84b4171 | 1654 | unsigned long flags = 0; |
dbfe8ca2 LW |
1655 | bool glitch; |
1656 | int ret = -EINVAL; | |
1657 | int i; | |
1658 | ||
1659 | g = &npct->soc->groups[group]; | |
1660 | ||
1661 | if (g->altsetting < 0) | |
1662 | return -EINVAL; | |
1663 | ||
1664 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1665 | ||
daf73174 LW |
1666 | /* |
1667 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1668 | * we may pass through an undesired state. In this case we take | |
1669 | * some extra care. | |
1670 | * | |
1671 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1672 | * - Save SLPM registers (since we have a shadow register in the | |
1673 | * nmk_chip we're using that as backup) | |
1674 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1675 | * - Configure the GPIO registers for the IOs that are being switched | |
1676 | * - Set IOFORCE=1 | |
1677 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1678 | * - Set IOFORCE=0 | |
1679 | * - Restore SLPM registers | |
1680 | * - Any spurious wake up event during switch sequence to be ignored | |
1681 | * and cleared | |
1682 | * | |
1683 | * We REALLY need to save ALL slpm registers, because the external | |
1684 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1685 | * to avoid glitches. (Not just one port!) | |
1686 | */ | |
c22df08c | 1687 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1688 | |
1689 | if (glitch) { | |
1690 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1691 | ||
1692 | /* Initially don't put any pins to sleep when switching */ | |
1693 | memset(slpm, 0xff, sizeof(slpm)); | |
1694 | ||
1695 | /* | |
1696 | * Then mask the pins that need to be sleeping now when we're | |
1697 | * switching to the ALT C function. | |
1698 | */ | |
1699 | for (i = 0; i < g->npins; i++) | |
1700 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1701 | nmk_gpio_glitch_slpm_init(slpm); | |
1702 | } | |
1703 | ||
1704 | for (i = 0; i < g->npins; i++) { | |
dbfe8ca2 | 1705 | struct nmk_gpio_chip *nmk_chip; |
dbfe8ca2 LW |
1706 | unsigned bit; |
1707 | ||
6ca7d2e3 LW |
1708 | nmk_chip = find_nmk_gpio_from_pin(g->pins[i]); |
1709 | if (!nmk_chip) { | |
dbfe8ca2 LW |
1710 | dev_err(npct->dev, |
1711 | "invalid pin offset %d in group %s at index %d\n", | |
1712 | g->pins[i], g->name, i); | |
1713 | goto out_glitch; | |
1714 | } | |
dbfe8ca2 LW |
1715 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); |
1716 | ||
1717 | clk_enable(nmk_chip->clk); | |
1718 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1719 | /* | |
1720 | * If the pin is switching to altfunc, and there was an | |
1721 | * interrupt installed on it which has been lazy disabled, | |
1722 | * actually mask the interrupt to prevent spurious interrupts | |
1723 | * that would occur while the pin is under control of the | |
1724 | * peripheral. Only SKE does this. | |
1725 | */ | |
1726 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1727 | ||
c22df08c JNG |
1728 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1729 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1730 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1731 | |
1732 | /* | |
1733 | * Call PRCM GPIOCR config function in case ALTC | |
1734 | * has been selected: | |
1735 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1736 | * must be set. | |
1737 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1738 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1739 | */ | |
1740 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1741 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1742 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1743 | } |
1744 | ||
1745 | /* When all pins are successfully reconfigured we get here */ | |
1746 | ret = 0; | |
1747 | ||
1748 | out_glitch: | |
1749 | if (glitch) { | |
1750 | nmk_gpio_glitch_slpm_restore(slpm); | |
1751 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1752 | } | |
1753 | ||
1754 | return ret; | |
1755 | } | |
1756 | ||
5212d096 AL |
1757 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1758 | struct pinctrl_gpio_range *range, | |
1759 | unsigned offset) | |
dbfe8ca2 LW |
1760 | { |
1761 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1762 | struct nmk_gpio_chip *nmk_chip; | |
1763 | struct gpio_chip *chip; | |
1764 | unsigned bit; | |
1765 | ||
1766 | if (!range) { | |
1767 | dev_err(npct->dev, "invalid range\n"); | |
1768 | return -EINVAL; | |
1769 | } | |
1770 | if (!range->gc) { | |
1771 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1772 | return -EINVAL; | |
1773 | } | |
1774 | chip = range->gc; | |
68ab0126 | 1775 | nmk_chip = gpiochip_get_data(chip); |
dbfe8ca2 LW |
1776 | |
1777 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1778 | ||
1779 | clk_enable(nmk_chip->clk); | |
1780 | bit = offset % NMK_GPIO_PER_CHIP; | |
1781 | /* There is no glitch when converting any pin to GPIO */ | |
1782 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1783 | clk_disable(nmk_chip->clk); | |
1784 | ||
1785 | return 0; | |
1786 | } | |
1787 | ||
5212d096 AL |
1788 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1789 | struct pinctrl_gpio_range *range, | |
1790 | unsigned offset) | |
dbfe8ca2 LW |
1791 | { |
1792 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1793 | ||
1794 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1795 | /* Set the pin to some default state, GPIO is usually default */ | |
1796 | } | |
1797 | ||
022ab148 | 1798 | static const struct pinmux_ops nmk_pinmux_ops = { |
dbfe8ca2 LW |
1799 | .get_functions_count = nmk_pmx_get_funcs_cnt, |
1800 | .get_function_name = nmk_pmx_get_func_name, | |
1801 | .get_function_groups = nmk_pmx_get_func_groups, | |
03e9f0ca | 1802 | .set_mux = nmk_pmx_set, |
dbfe8ca2 LW |
1803 | .gpio_request_enable = nmk_gpio_request_enable, |
1804 | .gpio_disable_free = nmk_gpio_disable_free, | |
a21763a0 | 1805 | .strict = true, |
dbfe8ca2 LW |
1806 | }; |
1807 | ||
5212d096 AL |
1808 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1809 | unsigned long *config) | |
d41af627 LW |
1810 | { |
1811 | /* Not implemented */ | |
1812 | return -EINVAL; | |
1813 | } | |
1814 | ||
5212d096 | 1815 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
03b054e9 | 1816 | unsigned long *configs, unsigned num_configs) |
d41af627 LW |
1817 | { |
1818 | static const char *pullnames[] = { | |
1819 | [NMK_GPIO_PULL_NONE] = "none", | |
1820 | [NMK_GPIO_PULL_UP] = "up", | |
1821 | [NMK_GPIO_PULL_DOWN] = "down", | |
1822 | [3] /* illegal */ = "??" | |
1823 | }; | |
1824 | static const char *slpmnames[] = { | |
1825 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1826 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1827 | }; | |
1828 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1829 | struct nmk_gpio_chip *nmk_chip; | |
d41af627 | 1830 | unsigned bit; |
03b054e9 SY |
1831 | pin_cfg_t cfg; |
1832 | int pull, slpm, output, val, i; | |
1833 | bool lowemi, gpiomode, sleep; | |
d41af627 | 1834 | |
6ca7d2e3 LW |
1835 | nmk_chip = find_nmk_gpio_from_pin(pin); |
1836 | if (!nmk_chip) { | |
1837 | dev_err(npct->dev, | |
1838 | "invalid pin offset %d\n", pin); | |
d41af627 LW |
1839 | return -EINVAL; |
1840 | } | |
d41af627 | 1841 | |
03b054e9 | 1842 | for (i = 0; i < num_configs; i++) { |
d41af627 | 1843 | /* |
03b054e9 SY |
1844 | * The pin config contains pin number and altfunction fields, |
1845 | * here we just ignore that part. It's being handled by the | |
1846 | * framework and pinmux callback respectively. | |
d41af627 | 1847 | */ |
03b054e9 SY |
1848 | cfg = (pin_cfg_t) configs[i]; |
1849 | pull = PIN_PULL(cfg); | |
1850 | slpm = PIN_SLPM(cfg); | |
1851 | output = PIN_DIR(cfg); | |
1852 | val = PIN_VAL(cfg); | |
1853 | lowemi = PIN_LOWEMI(cfg); | |
1854 | gpiomode = PIN_GPIOMODE(cfg); | |
1855 | sleep = PIN_SLEEPMODE(cfg); | |
1856 | ||
1857 | if (sleep) { | |
1858 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1859 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1860 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1861 | ||
1862 | /* All pins go into GPIO mode at sleep */ | |
1863 | gpiomode = true; | |
1864 | ||
1865 | /* | |
1866 | * The SLPM_* values are normal values + 1 to allow zero | |
1867 | * to mean "same as normal". | |
1868 | */ | |
1869 | if (slpm_pull) | |
1870 | pull = slpm_pull - 1; | |
1871 | if (slpm_output) | |
1872 | output = slpm_output - 1; | |
1873 | if (slpm_val) | |
1874 | val = slpm_val - 1; | |
1875 | ||
58383c78 | 1876 | dev_dbg(nmk_chip->chip.parent, |
03b054e9 SY |
1877 | "pin %d: sleep pull %s, dir %s, val %s\n", |
1878 | pin, | |
1879 | slpm_pull ? pullnames[pull] : "same", | |
1880 | slpm_output ? (output ? "output" : "input") | |
1881 | : "same", | |
1882 | slpm_val ? (val ? "high" : "low") : "same"); | |
1883 | } | |
d41af627 | 1884 | |
58383c78 | 1885 | dev_dbg(nmk_chip->chip.parent, |
03b054e9 SY |
1886 | "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", |
1887 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1888 | output ? "output " : "input", | |
1889 | output ? (val ? "high" : "low") : "", | |
1890 | lowemi ? "on" : "off"); | |
d41af627 | 1891 | |
03b054e9 SY |
1892 | clk_enable(nmk_chip->clk); |
1893 | bit = pin % NMK_GPIO_PER_CHIP; | |
1894 | if (gpiomode) | |
1895 | /* No glitch when going to GPIO mode */ | |
1896 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1897 | if (output) | |
1898 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1899 | else { | |
1900 | __nmk_gpio_make_input(nmk_chip, bit); | |
1901 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1902 | } | |
1903 | /* TODO: isn't this only applicable on output pins? */ | |
1904 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1905 | ||
1906 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1907 | clk_disable(nmk_chip->clk); | |
1908 | } /* for each config */ | |
d41af627 | 1909 | |
d41af627 LW |
1910 | return 0; |
1911 | } | |
1912 | ||
022ab148 | 1913 | static const struct pinconf_ops nmk_pinconf_ops = { |
d41af627 LW |
1914 | .pin_config_get = nmk_pin_config_get, |
1915 | .pin_config_set = nmk_pin_config_set, | |
1916 | }; | |
1917 | ||
e98ea774 LW |
1918 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1919 | .name = "pinctrl-nomadik", | |
1920 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1921 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1922 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1923 | .owner = THIS_MODULE, |
1924 | }; | |
1925 | ||
855f80cd | 1926 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 | 1927 | { |
3fd765a9 | 1928 | .compatible = "stericsson,stn8815-pinctrl", |
6010d403 LW |
1929 | .data = (void *)PINCTRL_NMK_STN8815, |
1930 | }, | |
855f80cd | 1931 | { |
6b09a834 | 1932 | .compatible = "stericsson,db8500-pinctrl", |
855f80cd LJ |
1933 | .data = (void *)PINCTRL_NMK_DB8500, |
1934 | }, | |
356d3e45 | 1935 | { |
6b09a834 | 1936 | .compatible = "stericsson,db8540-pinctrl", |
356d3e45 GF |
1937 | .data = (void *)PINCTRL_NMK_DB8540, |
1938 | }, | |
855f80cd LJ |
1939 | {}, |
1940 | }; | |
1941 | ||
131d85bc | 1942 | #ifdef CONFIG_PM_SLEEP |
c003eed7 | 1943 | static int nmk_pinctrl_suspend(struct device *dev) |
8d99b32d JD |
1944 | { |
1945 | struct nmk_pinctrl *npct; | |
1946 | ||
c003eed7 | 1947 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1948 | if (!npct) |
1949 | return -EINVAL; | |
1950 | ||
1951 | return pinctrl_force_sleep(npct->pctl); | |
1952 | } | |
1953 | ||
c003eed7 | 1954 | static int nmk_pinctrl_resume(struct device *dev) |
8d99b32d JD |
1955 | { |
1956 | struct nmk_pinctrl *npct; | |
1957 | ||
c003eed7 | 1958 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1959 | if (!npct) |
1960 | return -EINVAL; | |
1961 | ||
1962 | return pinctrl_force_default(npct->pctl); | |
1963 | } | |
131d85bc | 1964 | #endif |
8d99b32d | 1965 | |
150632b0 | 1966 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 | 1967 | { |
f4b3f523 | 1968 | const struct of_device_id *match; |
855f80cd | 1969 | struct device_node *np = pdev->dev.of_node; |
32e67eee | 1970 | struct device_node *prcm_np; |
e98ea774 | 1971 | struct nmk_pinctrl *npct; |
855f80cd | 1972 | unsigned int version = 0; |
e98ea774 LW |
1973 | int i; |
1974 | ||
1975 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
1976 | if (!npct) | |
1977 | return -ENOMEM; | |
1978 | ||
f4b3f523 LW |
1979 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); |
1980 | if (!match) | |
1981 | return -ENODEV; | |
1982 | version = (unsigned int) match->data; | |
855f80cd | 1983 | |
e98ea774 | 1984 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
1985 | if (version == PINCTRL_NMK_STN8815) |
1986 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 1987 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 1988 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
1989 | if (version == PINCTRL_NMK_DB8540) |
1990 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 1991 | |
ab4a9362 LW |
1992 | /* |
1993 | * Since we depend on the GPIO chips to provide clock and register base | |
1994 | * for the pin control operations, make sure that we have these | |
1995 | * populated before we continue. Follow the phandles to instantiate | |
1996 | * them. The GPIO portion of the actual hardware may be probed before | |
1997 | * or after this point: it shouldn't matter as the APIs are orthogonal. | |
1998 | */ | |
1999 | for (i = 0; i < NMK_MAX_BANKS; i++) { | |
2000 | struct device_node *gpio_np; | |
2001 | struct nmk_gpio_chip *nmk_chip; | |
2002 | ||
2003 | gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i); | |
2004 | if (gpio_np) { | |
2005 | dev_info(&pdev->dev, | |
2006 | "populate NMK GPIO %d \"%s\"\n", | |
2007 | i, gpio_np->name); | |
2008 | nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev); | |
2009 | if (IS_ERR(nmk_chip)) | |
2010 | dev_err(&pdev->dev, | |
2011 | "could not populate nmk chip struct " | |
2012 | "- continue anyway\n"); | |
2013 | of_node_put(gpio_np); | |
2014 | } | |
2015 | } | |
2016 | ||
f4b3f523 LW |
2017 | prcm_np = of_parse_phandle(np, "prcm", 0); |
2018 | if (prcm_np) | |
2019 | npct->prcm_base = of_iomap(prcm_np, 0); | |
32e67eee LJ |
2020 | if (!npct->prcm_base) { |
2021 | if (version == PINCTRL_NMK_STN8815) { | |
2022 | dev_info(&pdev->dev, | |
2023 | "No PRCM base, " | |
2024 | "assuming no ALT-Cx control is available\n"); | |
2025 | } else { | |
2026 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
2027 | return -EINVAL; | |
f1671bf5 | 2028 | } |
f1671bf5 JA |
2029 | } |
2030 | ||
e98ea774 LW |
2031 | nmk_pinctrl_desc.pins = npct->soc->pins; |
2032 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
2033 | npct->dev = &pdev->dev; | |
f1671bf5 | 2034 | |
0ee60110 | 2035 | npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct); |
323de9ef | 2036 | if (IS_ERR(npct->pctl)) { |
e98ea774 | 2037 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); |
323de9ef | 2038 | return PTR_ERR(npct->pctl); |
e98ea774 LW |
2039 | } |
2040 | ||
e98ea774 LW |
2041 | platform_set_drvdata(pdev, npct); |
2042 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
513c27f8 LJ |
2047 | static const struct of_device_id nmk_gpio_match[] = { |
2048 | { .compatible = "st,nomadik-gpio", }, | |
2049 | {} | |
2050 | }; | |
2051 | ||
3e3c62ca RV |
2052 | static struct platform_driver nmk_gpio_driver = { |
2053 | .driver = { | |
2ec1d359 | 2054 | .name = "gpio", |
513c27f8 | 2055 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 2056 | }, |
2ec1d359 | 2057 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
2058 | }; |
2059 | ||
c003eed7 UH |
2060 | static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, |
2061 | nmk_pinctrl_suspend, | |
2062 | nmk_pinctrl_resume); | |
2063 | ||
e98ea774 LW |
2064 | static struct platform_driver nmk_pinctrl_driver = { |
2065 | .driver = { | |
e98ea774 | 2066 | .name = "pinctrl-nomadik", |
855f80cd | 2067 | .of_match_table = nmk_pinctrl_match, |
c003eed7 | 2068 | .pm = &nmk_pinctrl_pm_ops, |
e98ea774 LW |
2069 | }, |
2070 | .probe = nmk_pinctrl_probe, | |
e98ea774 LW |
2071 | }; |
2072 | ||
2ec1d359 AR |
2073 | static int __init nmk_gpio_init(void) |
2074 | { | |
802bb9b6 LW |
2075 | return platform_driver_register(&nmk_gpio_driver); |
2076 | } | |
2077 | subsys_initcall(nmk_gpio_init); | |
e98ea774 | 2078 | |
802bb9b6 LW |
2079 | static int __init nmk_pinctrl_init(void) |
2080 | { | |
e98ea774 | 2081 | return platform_driver_register(&nmk_pinctrl_driver); |
2ec1d359 | 2082 | } |
802bb9b6 | 2083 | core_initcall(nmk_pinctrl_init); |
2ec1d359 AR |
2084 | |
2085 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
2086 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
2087 | MODULE_LICENSE("GPL"); |