Commit | Line | Data |
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0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
f30a3839 LJ |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
0493e649 PC |
19 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/irq.h> | |
ac652d79 | 22 | #include <linux/irqdomain.h> |
0493e649 PC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/mfd/abx500.h> | |
26 | #include <linux/mfd/abx500/ab8500.h> | |
27 | #include <linux/mfd/abx500/ab8500-gpio.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/consumer.h> | |
30 | #include <linux/pinctrl/pinmux.h> | |
31 | #include <linux/pinctrl/pinconf.h> | |
32 | #include <linux/pinctrl/pinconf-generic.h> | |
64a45c98 | 33 | #include <linux/pinctrl/machine.h> |
0493e649 PC |
34 | |
35 | #include "pinctrl-abx500.h" | |
61ce1356 | 36 | #include "core.h" |
64a45c98 | 37 | #include "pinconf.h" |
0493e649 PC |
38 | |
39 | /* | |
40 | * The AB9540 and AB8540 GPIO support are extended versions | |
41 | * of the AB8500 GPIO support. | |
42 | * The AB9540 supports an additional (7th) register so that | |
43 | * more GPIO may be configured and used. | |
44 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
45 | * internal pull-up and pull-down capabilities. | |
46 | */ | |
47 | ||
48 | /* | |
49 | * GPIO registers offset | |
50 | * Bank: 0x10 | |
51 | */ | |
52 | #define AB8500_GPIO_SEL1_REG 0x00 | |
53 | #define AB8500_GPIO_SEL2_REG 0x01 | |
54 | #define AB8500_GPIO_SEL3_REG 0x02 | |
55 | #define AB8500_GPIO_SEL4_REG 0x03 | |
56 | #define AB8500_GPIO_SEL5_REG 0x04 | |
57 | #define AB8500_GPIO_SEL6_REG 0x05 | |
58 | #define AB9540_GPIO_SEL7_REG 0x06 | |
59 | ||
60 | #define AB8500_GPIO_DIR1_REG 0x10 | |
61 | #define AB8500_GPIO_DIR2_REG 0x11 | |
62 | #define AB8500_GPIO_DIR3_REG 0x12 | |
63 | #define AB8500_GPIO_DIR4_REG 0x13 | |
64 | #define AB8500_GPIO_DIR5_REG 0x14 | |
65 | #define AB8500_GPIO_DIR6_REG 0x15 | |
66 | #define AB9540_GPIO_DIR7_REG 0x16 | |
67 | ||
68 | #define AB8500_GPIO_OUT1_REG 0x20 | |
69 | #define AB8500_GPIO_OUT2_REG 0x21 | |
70 | #define AB8500_GPIO_OUT3_REG 0x22 | |
71 | #define AB8500_GPIO_OUT4_REG 0x23 | |
72 | #define AB8500_GPIO_OUT5_REG 0x24 | |
73 | #define AB8500_GPIO_OUT6_REG 0x25 | |
74 | #define AB9540_GPIO_OUT7_REG 0x26 | |
75 | ||
76 | #define AB8500_GPIO_PUD1_REG 0x30 | |
77 | #define AB8500_GPIO_PUD2_REG 0x31 | |
78 | #define AB8500_GPIO_PUD3_REG 0x32 | |
79 | #define AB8500_GPIO_PUD4_REG 0x33 | |
80 | #define AB8500_GPIO_PUD5_REG 0x34 | |
81 | #define AB8500_GPIO_PUD6_REG 0x35 | |
82 | #define AB9540_GPIO_PUD7_REG 0x36 | |
83 | ||
84 | #define AB8500_GPIO_IN1_REG 0x40 | |
85 | #define AB8500_GPIO_IN2_REG 0x41 | |
86 | #define AB8500_GPIO_IN3_REG 0x42 | |
87 | #define AB8500_GPIO_IN4_REG 0x43 | |
88 | #define AB8500_GPIO_IN5_REG 0x44 | |
89 | #define AB8500_GPIO_IN6_REG 0x45 | |
90 | #define AB9540_GPIO_IN7_REG 0x46 | |
91 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
92 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
93 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
0493e649 PC |
94 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
95 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
96 | #define AB8540_GPIOX_VBAT_START 51 | |
97 | #define AB8540_GPIOX_VBAT_END 54 | |
98 | ||
acd260b0 PC |
99 | #define ABX500_GPIO_INPUT 0 |
100 | #define ABX500_GPIO_OUTPUT 1 | |
101 | ||
0493e649 PC |
102 | struct abx500_pinctrl { |
103 | struct device *dev; | |
104 | struct pinctrl_dev *pctldev; | |
105 | struct abx500_pinctrl_soc_data *soc; | |
106 | struct gpio_chip chip; | |
107 | struct ab8500 *parent; | |
0493e649 PC |
108 | struct abx500_gpio_irq_cluster *irq_cluster; |
109 | int irq_cluster_size; | |
0493e649 PC |
110 | }; |
111 | ||
112 | /** | |
113 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
114 | * @chip: Member of the structure abx500_pinctrl | |
115 | */ | |
116 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
117 | { | |
118 | return container_of(chip, struct abx500_pinctrl, chip); | |
119 | } | |
120 | ||
121 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 122 | unsigned offset, bool *bit) |
0493e649 PC |
123 | { |
124 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
125 | u8 pos = offset % 8; | |
126 | u8 val; | |
127 | int ret; | |
128 | ||
129 | reg += offset / 8; | |
130 | ret = abx500_get_register_interruptible(pct->dev, | |
131 | AB8500_MISC, reg, &val); | |
132 | ||
133 | *bit = !!(val & BIT(pos)); | |
134 | ||
135 | if (ret < 0) | |
136 | dev_err(pct->dev, | |
9be580af PC |
137 | "%s read reg =%x, offset=%x failed (%d)\n", |
138 | __func__, reg, offset, ret); | |
0493e649 PC |
139 | |
140 | return ret; | |
141 | } | |
142 | ||
143 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 144 | unsigned offset, int val) |
0493e649 PC |
145 | { |
146 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
147 | u8 pos = offset % 8; | |
148 | int ret; | |
149 | ||
150 | reg += offset / 8; | |
151 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 152 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 | 153 | if (ret < 0) |
9be580af PC |
154 | dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", |
155 | __func__, reg, offset, ret); | |
83b423c8 | 156 | |
0493e649 PC |
157 | return ret; |
158 | } | |
83b423c8 | 159 | |
0493e649 PC |
160 | /** |
161 | * abx500_gpio_get() - Get the particular GPIO value | |
83b423c8 LJ |
162 | * @chip: Gpio device |
163 | * @offset: GPIO number to read | |
0493e649 PC |
164 | */ |
165 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
166 | { | |
167 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
168 | bool bit; | |
d8d4f7f8 PC |
169 | bool is_out; |
170 | u8 gpio_offset = offset - 1; | |
0493e649 PC |
171 | int ret; |
172 | ||
d8d4f7f8 PC |
173 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, |
174 | gpio_offset, &is_out); | |
9be580af PC |
175 | if (ret < 0) |
176 | goto out; | |
d8d4f7f8 PC |
177 | |
178 | if (is_out) | |
179 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, | |
180 | gpio_offset, &bit); | |
181 | else | |
182 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
183 | gpio_offset, &bit); | |
9be580af | 184 | out: |
0493e649 | 185 | if (ret < 0) { |
9be580af | 186 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); |
0493e649 PC |
187 | return ret; |
188 | } | |
83b423c8 | 189 | |
0493e649 PC |
190 | return bit; |
191 | } | |
192 | ||
193 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
194 | { | |
195 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
196 | int ret; | |
197 | ||
198 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
199 | if (ret < 0) | |
9be580af | 200 | dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); |
0493e649 PC |
201 | } |
202 | ||
d2752ae5 PC |
203 | static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, |
204 | enum abx500_gpio_pull_updown *pull_updown) | |
0493e649 PC |
205 | { |
206 | u8 pos; | |
d2752ae5 | 207 | u8 val; |
0493e649 PC |
208 | int ret; |
209 | struct pullud *pullud; | |
210 | ||
211 | if (!pct->soc->pullud) { | |
212 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
213 | __func__); | |
214 | ret = -EPERM; | |
215 | goto out; | |
216 | } | |
217 | ||
218 | pullud = pct->soc->pullud; | |
219 | ||
220 | if ((offset < pullud->first_pin) | |
221 | || (offset > pullud->last_pin)) { | |
222 | ret = -EINVAL; | |
223 | goto out; | |
224 | } | |
225 | ||
d2752ae5 PC |
226 | ret = abx500_get_register_interruptible(pct->dev, |
227 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); | |
228 | ||
229 | pos = (offset - pullud->first_pin) << 1; | |
230 | *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; | |
231 | ||
232 | out: | |
233 | if (ret < 0) | |
234 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
239 | static int abx500_set_pull_updown(struct abx500_pinctrl *pct, | |
240 | int offset, enum abx500_gpio_pull_updown val) | |
241 | { | |
242 | u8 pos; | |
243 | int ret; | |
244 | struct pullud *pullud; | |
245 | ||
246 | if (!pct->soc->pullud) { | |
247 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
248 | __func__); | |
249 | ret = -EPERM; | |
250 | goto out; | |
251 | } | |
252 | ||
253 | pullud = pct->soc->pullud; | |
254 | ||
255 | if ((offset < pullud->first_pin) | |
256 | || (offset > pullud->last_pin)) { | |
257 | ret = -EINVAL; | |
258 | goto out; | |
259 | } | |
10a8be54 | 260 | pos = (offset - pullud->first_pin) << 1; |
0493e649 PC |
261 | |
262 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
263 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
264 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
265 | ||
266 | out: | |
267 | if (ret < 0) | |
268 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 269 | |
0493e649 PC |
270 | return ret; |
271 | } | |
272 | ||
8b5abd18 PC |
273 | static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) |
274 | { | |
275 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
276 | struct pullud *pullud = pct->soc->pullud; | |
277 | ||
278 | return (pullud && | |
279 | gpio >= pullud->first_pin && | |
280 | gpio <= pullud->last_pin); | |
281 | } | |
282 | ||
0493e649 PC |
283 | static int abx500_gpio_direction_output(struct gpio_chip *chip, |
284 | unsigned offset, | |
285 | int val) | |
286 | { | |
287 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
0493e649 PC |
288 | unsigned gpio; |
289 | int ret; | |
83b423c8 | 290 | |
0493e649 | 291 | /* set direction as output */ |
acd260b0 PC |
292 | ret = abx500_gpio_set_bits(chip, |
293 | AB8500_GPIO_DIR1_REG, | |
294 | offset, | |
295 | ABX500_GPIO_OUTPUT); | |
0493e649 | 296 | if (ret < 0) |
9be580af | 297 | goto out; |
0493e649 PC |
298 | |
299 | /* disable pull down */ | |
acd260b0 PC |
300 | ret = abx500_gpio_set_bits(chip, |
301 | AB8500_GPIO_PUD1_REG, | |
302 | offset, | |
303 | ABX500_GPIO_PULL_NONE); | |
0493e649 | 304 | if (ret < 0) |
9be580af | 305 | goto out; |
0493e649 PC |
306 | |
307 | /* if supported, disable both pull down and pull up */ | |
308 | gpio = offset + 1; | |
8b5abd18 | 309 | if (abx500_pullud_supported(chip, gpio)) { |
d2752ae5 | 310 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
311 | gpio, |
312 | ABX500_GPIO_PULL_NONE); | |
9be580af PC |
313 | } |
314 | out: | |
315 | if (ret < 0) { | |
316 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
317 | return ret; | |
0493e649 | 318 | } |
83b423c8 | 319 | |
0493e649 PC |
320 | /* set the output as 1 or 0 */ |
321 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
322 | } | |
323 | ||
324 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
325 | { | |
326 | /* set the register as input */ | |
acd260b0 PC |
327 | return abx500_gpio_set_bits(chip, |
328 | AB8500_GPIO_DIR1_REG, | |
329 | offset, | |
330 | ABX500_GPIO_INPUT); | |
0493e649 PC |
331 | } |
332 | ||
333 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
334 | { | |
335 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
b9fab6e4 LJ |
336 | /* The AB8500 GPIO numbers are off by one */ |
337 | int gpio = offset + 1; | |
a6a16d27 | 338 | int hwirq; |
0493e649 PC |
339 | int i; |
340 | ||
341 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
342 | struct abx500_gpio_irq_cluster *cluster = | |
343 | &pct->irq_cluster[i]; | |
344 | ||
a6a16d27 LJ |
345 | if (gpio >= cluster->start && gpio <= cluster->end) { |
346 | /* | |
347 | * The ABx500 GPIO's associated IRQs are clustered together | |
348 | * throughout the interrupt numbers at irregular intervals. | |
349 | * To solve this quandry, we have placed the read-in values | |
350 | * into the cluster information table. | |
351 | */ | |
43a255db | 352 | hwirq = gpio - cluster->start + cluster->to_irq; |
a6a16d27 LJ |
353 | return irq_create_mapping(pct->parent->domain, hwirq); |
354 | } | |
0493e649 PC |
355 | } |
356 | ||
357 | return -EINVAL; | |
358 | } | |
359 | ||
360 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 361 | unsigned gpio, int alt_setting) |
0493e649 PC |
362 | { |
363 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
364 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
365 | int ret; | |
366 | int val; | |
367 | unsigned offset; | |
83b423c8 | 368 | |
0493e649 PC |
369 | const char *modes[] = { |
370 | [ABX500_DEFAULT] = "default", | |
371 | [ABX500_ALT_A] = "altA", | |
372 | [ABX500_ALT_B] = "altB", | |
373 | [ABX500_ALT_C] = "altC", | |
374 | }; | |
375 | ||
376 | /* sanity check */ | |
377 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
378 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
379 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
380 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
381 | modes[alt_setting]); | |
382 | return -EINVAL; | |
383 | } | |
384 | ||
385 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
386 | offset = gpio - 1; | |
83b423c8 | 387 | |
0493e649 PC |
388 | switch (alt_setting) { |
389 | case ABX500_DEFAULT: | |
390 | /* | |
391 | * for ABx5xx family, default mode is always selected by | |
392 | * writing 0 to GPIOSELx register, except for pins which | |
393 | * support at least ALT_B mode, default mode is selected | |
394 | * by writing 1 to GPIOSELx register | |
395 | */ | |
396 | val = 0; | |
397 | if (af.alt_bit1 != UNUSED) | |
398 | val++; | |
399 | ||
400 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
401 | offset, val); | |
402 | break; | |
83b423c8 | 403 | |
0493e649 PC |
404 | case ABX500_ALT_A: |
405 | /* | |
406 | * for ABx5xx family, alt_a mode is always selected by | |
407 | * writing 1 to GPIOSELx register, except for pins which | |
408 | * support at least ALT_B mode, alt_a mode is selected | |
409 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
410 | * register | |
411 | */ | |
412 | if (af.alt_bit1 != UNUSED) { | |
413 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
414 | offset, 0); | |
9be580af PC |
415 | if (ret < 0) |
416 | goto out; | |
417 | ||
0493e649 PC |
418 | ret = abx500_gpio_set_bits(chip, |
419 | AB8500_GPIO_ALTFUN_REG, | |
420 | af.alt_bit1, | |
c590854d | 421 | !!(af.alta_val & BIT(0))); |
9be580af PC |
422 | if (ret < 0) |
423 | goto out; | |
424 | ||
0493e649 PC |
425 | if (af.alt_bit2 != UNUSED) |
426 | ret = abx500_gpio_set_bits(chip, | |
427 | AB8500_GPIO_ALTFUN_REG, | |
428 | af.alt_bit2, | |
6da33dbd | 429 | !!(af.alta_val & BIT(1))); |
0493e649 PC |
430 | } else |
431 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
432 | offset, 1); | |
433 | break; | |
83b423c8 | 434 | |
0493e649 PC |
435 | case ABX500_ALT_B: |
436 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
437 | offset, 0); | |
9be580af PC |
438 | if (ret < 0) |
439 | goto out; | |
440 | ||
0493e649 | 441 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
c590854d | 442 | af.alt_bit1, !!(af.altb_val & BIT(0))); |
9be580af PC |
443 | if (ret < 0) |
444 | goto out; | |
445 | ||
0493e649 PC |
446 | if (af.alt_bit2 != UNUSED) |
447 | ret = abx500_gpio_set_bits(chip, | |
448 | AB8500_GPIO_ALTFUN_REG, | |
449 | af.alt_bit2, | |
6da33dbd | 450 | !!(af.altb_val & BIT(1))); |
0493e649 | 451 | break; |
83b423c8 | 452 | |
0493e649 PC |
453 | case ABX500_ALT_C: |
454 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
455 | offset, 0); | |
9be580af PC |
456 | if (ret < 0) |
457 | goto out; | |
458 | ||
0493e649 | 459 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
6da33dbd | 460 | af.alt_bit2, !!(af.altc_val & BIT(0))); |
9be580af PC |
461 | if (ret < 0) |
462 | goto out; | |
463 | ||
0493e649 | 464 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
c590854d | 465 | af.alt_bit2, !!(af.altc_val & BIT(1))); |
0493e649 PC |
466 | break; |
467 | ||
468 | default: | |
469 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
83b423c8 | 470 | |
0493e649 PC |
471 | return -EINVAL; |
472 | } | |
9be580af PC |
473 | out: |
474 | if (ret < 0) | |
475 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 476 | |
0493e649 PC |
477 | return ret; |
478 | } | |
479 | ||
9be580af | 480 | static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, |
83b423c8 | 481 | unsigned gpio) |
0493e649 PC |
482 | { |
483 | u8 mode; | |
484 | bool bit_mode; | |
485 | bool alt_bit1; | |
486 | bool alt_bit2; | |
487 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
488 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
a950cb74 LW |
489 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
490 | unsigned offset = gpio - 1; | |
9be580af | 491 | int ret; |
0493e649 PC |
492 | |
493 | /* | |
494 | * if gpiosel_bit is set to unused, | |
495 | * it means no GPIO or special case | |
496 | */ | |
497 | if (af.gpiosel_bit == UNUSED) | |
498 | return ABX500_DEFAULT; | |
499 | ||
500 | /* read GpioSelx register */ | |
9be580af | 501 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
0493e649 | 502 | af.gpiosel_bit, &bit_mode); |
9be580af PC |
503 | if (ret < 0) |
504 | goto out; | |
505 | ||
0493e649 PC |
506 | mode = bit_mode; |
507 | ||
508 | /* sanity check */ | |
509 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
510 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
511 | dev_err(pct->dev, | |
512 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
513 | return -EINVAL; | |
514 | } | |
83b423c8 | 515 | |
0493e649 PC |
516 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
517 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
518 | dev_err(pct->dev, | |
519 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
520 | return -EINVAL; | |
521 | } | |
522 | ||
523 | /* check if pin use AlternateFunction register */ | |
6a40cdd5 | 524 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) |
0493e649 PC |
525 | return mode; |
526 | /* | |
527 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
528 | * it means DEFAULT mode | |
529 | */ | |
530 | if (mode) | |
531 | return ABX500_DEFAULT; | |
83b423c8 | 532 | |
0493e649 PC |
533 | /* |
534 | * pin use the AlternatFunction register | |
535 | * read alt_bit1 value | |
536 | */ | |
9be580af | 537 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, |
0493e649 | 538 | af.alt_bit1, &alt_bit1); |
9be580af PC |
539 | if (ret < 0) |
540 | goto out; | |
0493e649 | 541 | |
9be580af | 542 | if (af.alt_bit2 != UNUSED) { |
0493e649 | 543 | /* read alt_bit2 value */ |
9be580af PC |
544 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, |
545 | af.alt_bit2, | |
0493e649 | 546 | &alt_bit2); |
9be580af PC |
547 | if (ret < 0) |
548 | goto out; | |
549 | } else | |
0493e649 PC |
550 | alt_bit2 = 0; |
551 | ||
552 | mode = (alt_bit2 << 1) + alt_bit1; | |
553 | if (mode == af.alta_val) | |
554 | return ABX500_ALT_A; | |
555 | else if (mode == af.altb_val) | |
556 | return ABX500_ALT_B; | |
557 | else | |
558 | return ABX500_ALT_C; | |
9be580af PC |
559 | |
560 | out: | |
561 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
562 | return ret; | |
0493e649 PC |
563 | } |
564 | ||
565 | #ifdef CONFIG_DEBUG_FS | |
566 | ||
567 | #include <linux/seq_file.h> | |
568 | ||
569 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
570 | struct pinctrl_dev *pctldev, |
571 | struct gpio_chip *chip, | |
572 | unsigned offset, unsigned gpio) | |
0493e649 | 573 | { |
d2752ae5 | 574 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
0493e649 PC |
575 | const char *label = gpiochip_is_requested(chip, offset - 1); |
576 | u8 gpio_offset = offset - 1; | |
577 | int mode = -1; | |
578 | bool is_out; | |
d2752ae5 | 579 | bool pd; |
ce06f407 | 580 | enum abx500_gpio_pull_updown pud = 0; |
9be580af | 581 | int ret; |
83b423c8 | 582 | |
0493e649 PC |
583 | const char *modes[] = { |
584 | [ABX500_DEFAULT] = "default", | |
585 | [ABX500_ALT_A] = "altA", | |
586 | [ABX500_ALT_B] = "altB", | |
587 | [ABX500_ALT_C] = "altC", | |
588 | }; | |
589 | ||
d2752ae5 PC |
590 | const char *pull_up_down[] = { |
591 | [ABX500_GPIO_PULL_DOWN] = "pull down", | |
592 | [ABX500_GPIO_PULL_NONE] = "pull none", | |
593 | [ABX500_GPIO_PULL_NONE + 1] = "pull none", | |
594 | [ABX500_GPIO_PULL_UP] = "pull up", | |
595 | }; | |
596 | ||
9be580af PC |
597 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, |
598 | gpio_offset, &is_out); | |
599 | if (ret < 0) | |
600 | goto out; | |
d2752ae5 PC |
601 | |
602 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", | |
603 | gpio, label ?: "(none)", | |
604 | is_out ? "out" : "in "); | |
605 | ||
606 | if (!is_out) { | |
8b5abd18 | 607 | if (abx500_pullud_supported(chip, offset)) { |
9be580af PC |
608 | ret = abx500_get_pull_updown(pct, offset, &pud); |
609 | if (ret < 0) | |
610 | goto out; | |
611 | ||
d2752ae5 PC |
612 | seq_printf(s, " %-9s", pull_up_down[pud]); |
613 | } else { | |
9be580af PC |
614 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, |
615 | gpio_offset, &pd); | |
616 | if (ret < 0) | |
617 | goto out; | |
618 | ||
d2752ae5 PC |
619 | seq_printf(s, " %-9s", pull_up_down[pd]); |
620 | } | |
621 | } else | |
622 | seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); | |
0493e649 PC |
623 | |
624 | if (pctldev) | |
625 | mode = abx500_get_mode(pctldev, chip, offset); | |
626 | ||
d2752ae5 | 627 | seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); |
9be580af PC |
628 | |
629 | out: | |
630 | if (ret < 0) | |
631 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
0493e649 PC |
632 | } |
633 | ||
634 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
635 | { | |
636 | unsigned i; | |
637 | unsigned gpio = chip->base; | |
638 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
639 | struct pinctrl_dev *pctldev = pct->pctldev; | |
640 | ||
641 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
642 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
643 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
644 | seq_printf(s, "\n"); | |
645 | } | |
646 | } | |
647 | ||
648 | #else | |
649 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
650 | struct pinctrl_dev *pctldev, |
651 | struct gpio_chip *chip, | |
652 | unsigned offset, unsigned gpio) | |
0493e649 PC |
653 | { |
654 | } | |
655 | #define abx500_gpio_dbg_show NULL | |
656 | #endif | |
657 | ||
9c4154ef | 658 | static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
659 | { |
660 | int gpio = chip->base + offset; | |
661 | ||
662 | return pinctrl_request_gpio(gpio); | |
663 | } | |
664 | ||
9c4154ef | 665 | static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
666 | { |
667 | int gpio = chip->base + offset; | |
668 | ||
669 | pinctrl_free_gpio(gpio); | |
670 | } | |
671 | ||
672 | static struct gpio_chip abx500gpio_chip = { | |
673 | .label = "abx500-gpio", | |
674 | .owner = THIS_MODULE, | |
675 | .request = abx500_gpio_request, | |
676 | .free = abx500_gpio_free, | |
677 | .direction_input = abx500_gpio_direction_input, | |
678 | .get = abx500_gpio_get, | |
679 | .direction_output = abx500_gpio_direction_output, | |
680 | .set = abx500_gpio_set, | |
681 | .to_irq = abx500_gpio_to_irq, | |
682 | .dbg_show = abx500_gpio_dbg_show, | |
683 | }; | |
684 | ||
0493e649 PC |
685 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
686 | { | |
687 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
688 | ||
689 | return pct->soc->nfunctions; | |
690 | } | |
691 | ||
692 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
693 | unsigned function) | |
694 | { | |
695 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
696 | ||
697 | return pct->soc->functions[function].name; | |
698 | } | |
699 | ||
700 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
701 | unsigned function, |
702 | const char * const **groups, | |
703 | unsigned * const num_groups) | |
0493e649 PC |
704 | { |
705 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
706 | ||
707 | *groups = pct->soc->functions[function].groups; | |
708 | *num_groups = pct->soc->functions[function].ngroups; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
0493e649 | 713 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, |
83b423c8 | 714 | unsigned group) |
0493e649 PC |
715 | { |
716 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
717 | struct gpio_chip *chip = &pct->chip; | |
718 | const struct abx500_pingroup *g; | |
719 | int i; | |
720 | int ret = 0; | |
721 | ||
722 | g = &pct->soc->groups[group]; | |
723 | if (g->altsetting < 0) | |
724 | return -EINVAL; | |
725 | ||
726 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
727 | ||
728 | for (i = 0; i < g->npins; i++) { | |
729 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
730 | g->pins[i], g->altsetting); | |
731 | ||
0493e649 PC |
732 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
733 | } | |
83b423c8 | 734 | |
9be580af PC |
735 | if (ret < 0) |
736 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
737 | ||
0493e649 PC |
738 | return ret; |
739 | } | |
740 | ||
741 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, | |
83b423c8 | 742 | unsigned function, unsigned group) |
0493e649 PC |
743 | { |
744 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
745 | const struct abx500_pingroup *g; | |
746 | ||
747 | g = &pct->soc->groups[group]; | |
748 | if (g->altsetting < 0) | |
749 | return; | |
750 | ||
751 | /* FIXME: poke out the mux, set the pin to some default state? */ | |
752 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
753 | } | |
754 | ||
9c4154ef | 755 | static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
756 | struct pinctrl_gpio_range *range, |
757 | unsigned offset) | |
0493e649 PC |
758 | { |
759 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
760 | const struct abx500_pinrange *p; | |
761 | int ret; | |
762 | int i; | |
763 | ||
764 | /* | |
765 | * Different ranges have different ways to enable GPIO function on a | |
766 | * pin, so refer back to our local range type, where we handily define | |
767 | * what altfunc enables GPIO for a certain pin. | |
768 | */ | |
769 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
770 | p = &pct->soc->gpio_ranges[i]; | |
771 | if ((offset >= p->offset) && | |
772 | (offset < (p->offset + p->npins))) | |
773 | break; | |
774 | } | |
775 | ||
776 | if (i == pct->soc->gpio_num_ranges) { | |
777 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
778 | return -ENODEV; | |
779 | } | |
780 | ||
781 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
782 | p->altfunc, offset); | |
783 | ||
784 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
785 | offset, p->altfunc); | |
9be580af | 786 | if (ret < 0) |
0493e649 | 787 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); |
0493e649 PC |
788 | |
789 | return ret; | |
790 | } | |
791 | ||
792 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
793 | struct pinctrl_gpio_range *range, |
794 | unsigned offset) | |
0493e649 PC |
795 | { |
796 | } | |
797 | ||
022ab148 | 798 | static const struct pinmux_ops abx500_pinmux_ops = { |
0493e649 PC |
799 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
800 | .get_function_name = abx500_pmx_get_func_name, | |
801 | .get_function_groups = abx500_pmx_get_func_groups, | |
802 | .enable = abx500_pmx_enable, | |
803 | .disable = abx500_pmx_disable, | |
804 | .gpio_request_enable = abx500_gpio_request_enable, | |
805 | .gpio_disable_free = abx500_gpio_disable_free, | |
806 | }; | |
807 | ||
808 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
809 | { | |
810 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
811 | ||
812 | return pct->soc->ngroups; | |
813 | } | |
814 | ||
815 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
83b423c8 | 816 | unsigned selector) |
0493e649 PC |
817 | { |
818 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
819 | ||
820 | return pct->soc->groups[selector].name; | |
821 | } | |
822 | ||
823 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
824 | unsigned selector, |
825 | const unsigned **pins, | |
826 | unsigned *num_pins) | |
0493e649 PC |
827 | { |
828 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
829 | ||
830 | *pins = pct->soc->groups[selector].pins; | |
831 | *num_pins = pct->soc->groups[selector].npins; | |
83b423c8 | 832 | |
0493e649 PC |
833 | return 0; |
834 | } | |
835 | ||
836 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
83b423c8 | 837 | struct seq_file *s, unsigned offset) |
0493e649 PC |
838 | { |
839 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
840 | struct gpio_chip *chip = &pct->chip; | |
841 | ||
842 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
843 | chip->base + offset - 1); | |
844 | } | |
845 | ||
64a45c98 PC |
846 | static void abx500_dt_free_map(struct pinctrl_dev *pctldev, |
847 | struct pinctrl_map *map, unsigned num_maps) | |
848 | { | |
849 | int i; | |
850 | ||
851 | for (i = 0; i < num_maps; i++) | |
852 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
853 | kfree(map[i].data.configs.configs); | |
854 | kfree(map); | |
855 | } | |
856 | ||
857 | static int abx500_dt_reserve_map(struct pinctrl_map **map, | |
858 | unsigned *reserved_maps, | |
859 | unsigned *num_maps, | |
860 | unsigned reserve) | |
861 | { | |
862 | unsigned old_num = *reserved_maps; | |
863 | unsigned new_num = *num_maps + reserve; | |
864 | struct pinctrl_map *new_map; | |
865 | ||
866 | if (old_num >= new_num) | |
867 | return 0; | |
868 | ||
869 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
870 | if (!new_map) | |
871 | return -ENOMEM; | |
872 | ||
873 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
874 | ||
875 | *map = new_map; | |
876 | *reserved_maps = new_num; | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static int abx500_dt_add_map_mux(struct pinctrl_map **map, | |
882 | unsigned *reserved_maps, | |
883 | unsigned *num_maps, const char *group, | |
884 | const char *function) | |
885 | { | |
886 | if (*num_maps == *reserved_maps) | |
887 | return -ENOSPC; | |
888 | ||
889 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
890 | (*map)[*num_maps].data.mux.group = group; | |
891 | (*map)[*num_maps].data.mux.function = function; | |
892 | (*num_maps)++; | |
893 | ||
894 | return 0; | |
895 | } | |
896 | ||
897 | static int abx500_dt_add_map_configs(struct pinctrl_map **map, | |
898 | unsigned *reserved_maps, | |
899 | unsigned *num_maps, const char *group, | |
900 | unsigned long *configs, unsigned num_configs) | |
901 | { | |
902 | unsigned long *dup_configs; | |
903 | ||
904 | if (*num_maps == *reserved_maps) | |
905 | return -ENOSPC; | |
906 | ||
907 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
908 | GFP_KERNEL); | |
909 | if (!dup_configs) | |
910 | return -ENOMEM; | |
911 | ||
912 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
913 | ||
914 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
915 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
916 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
917 | (*num_maps)++; | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, | |
923 | const char *pin_name) | |
924 | { | |
925 | int i, pin_number; | |
926 | struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
927 | ||
928 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
929 | for (i = 0; i < npct->soc->npins; i++) | |
930 | if (npct->soc->pins[i].number == pin_number) | |
931 | return npct->soc->pins[i].name; | |
932 | return NULL; | |
933 | } | |
934 | ||
935 | static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
936 | struct device_node *np, | |
937 | struct pinctrl_map **map, | |
938 | unsigned *reserved_maps, | |
939 | unsigned *num_maps) | |
940 | { | |
941 | int ret; | |
942 | const char *function = NULL; | |
943 | unsigned long *configs; | |
944 | unsigned int nconfigs = 0; | |
945 | bool has_config = 0; | |
946 | unsigned reserve = 0; | |
947 | struct property *prop; | |
948 | const char *group, *gpio_name; | |
949 | struct device_node *np_config; | |
950 | ||
951 | ret = of_property_read_string(np, "ste,function", &function); | |
952 | if (ret >= 0) | |
953 | reserve = 1; | |
954 | ||
955 | ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); | |
956 | if (nconfigs) | |
957 | has_config = 1; | |
958 | ||
959 | np_config = of_parse_phandle(np, "ste,config", 0); | |
960 | if (np_config) { | |
961 | ret = pinconf_generic_parse_dt_config(np_config, &configs, | |
962 | &nconfigs); | |
963 | if (ret) | |
964 | goto exit; | |
965 | has_config |= nconfigs; | |
966 | } | |
967 | ||
968 | ret = of_property_count_strings(np, "ste,pins"); | |
969 | if (ret < 0) | |
970 | goto exit; | |
971 | ||
972 | if (has_config) | |
973 | reserve++; | |
974 | ||
975 | reserve *= ret; | |
976 | ||
977 | ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve); | |
978 | if (ret < 0) | |
979 | goto exit; | |
980 | ||
981 | of_property_for_each_string(np, "ste,pins", prop, group) { | |
982 | if (function) { | |
983 | ret = abx500_dt_add_map_mux(map, reserved_maps, | |
984 | num_maps, group, function); | |
985 | if (ret < 0) | |
986 | goto exit; | |
987 | } | |
988 | if (has_config) { | |
989 | gpio_name = abx500_find_pin_name(pctldev, group); | |
990 | ||
991 | ret = abx500_dt_add_map_configs(map, reserved_maps, | |
992 | num_maps, gpio_name, configs, 1); | |
993 | if (ret < 0) | |
994 | goto exit; | |
995 | } | |
996 | ||
997 | } | |
998 | exit: | |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1003 | struct device_node *np_config, | |
1004 | struct pinctrl_map **map, unsigned *num_maps) | |
1005 | { | |
1006 | unsigned reserved_maps; | |
1007 | struct device_node *np; | |
1008 | int ret; | |
1009 | ||
1010 | reserved_maps = 0; | |
1011 | *map = NULL; | |
1012 | *num_maps = 0; | |
1013 | ||
1014 | for_each_child_of_node(np_config, np) { | |
1015 | ret = abx500_dt_subnode_to_map(pctldev, np, map, | |
1016 | &reserved_maps, num_maps); | |
1017 | if (ret < 0) { | |
1018 | abx500_dt_free_map(pctldev, *map, *num_maps); | |
1019 | return ret; | |
1020 | } | |
1021 | } | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
022ab148 | 1026 | static const struct pinctrl_ops abx500_pinctrl_ops = { |
0493e649 PC |
1027 | .get_groups_count = abx500_get_groups_cnt, |
1028 | .get_group_name = abx500_get_group_name, | |
1029 | .get_group_pins = abx500_get_group_pins, | |
1030 | .pin_dbg_show = abx500_pin_dbg_show, | |
64a45c98 PC |
1031 | .dt_node_to_map = abx500_dt_node_to_map, |
1032 | .dt_free_map = abx500_dt_free_map, | |
0493e649 PC |
1033 | }; |
1034 | ||
9c4154ef | 1035 | static int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
1036 | unsigned pin, |
1037 | unsigned long *config) | |
0493e649 | 1038 | { |
1abeebea | 1039 | return -ENOSYS; |
0493e649 PC |
1040 | } |
1041 | ||
9c4154ef | 1042 | static int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
83b423c8 | 1043 | unsigned pin, |
03b054e9 SY |
1044 | unsigned long *configs, |
1045 | unsigned num_configs) | |
0493e649 PC |
1046 | { |
1047 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
0493e649 PC |
1048 | struct gpio_chip *chip = &pct->chip; |
1049 | unsigned offset; | |
61ce1356 | 1050 | int ret = -EINVAL; |
03b054e9 SY |
1051 | int i; |
1052 | enum pin_config_param param; | |
1053 | enum pin_config_param argument; | |
1054 | ||
1055 | for (i = 0; i < num_configs; i++) { | |
1056 | param = pinconf_to_config_param(configs[i]); | |
1057 | argument = pinconf_to_config_argument(configs[i]); | |
1058 | ||
1059 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
1060 | pin, configs[i], | |
1061 | (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
1062 | (param == PIN_CONFIG_OUTPUT) ? | |
1063 | (argument ? "high" : "low") : | |
1064 | (argument ? "pull up" : "pull down")); | |
1065 | ||
1066 | /* on ABx500, there is no GPIO0, so adjust the offset */ | |
1067 | offset = pin - 1; | |
1068 | ||
1069 | switch (param) { | |
1070 | case PIN_CONFIG_BIAS_DISABLE: | |
1071 | ret = abx500_gpio_direction_input(chip, offset); | |
1072 | if (ret < 0) | |
1073 | goto out; | |
1074 | /* | |
1075 | * Some chips only support pull down, while some | |
1076 | * actually support both pull up and pull down. Such | |
1077 | * chips have a "pullud" range specified for the pins | |
1078 | * that support both features. If the pin is not | |
1079 | * within that range, we fall back to the old bit set | |
1080 | * that only support pull down. | |
1081 | */ | |
1082 | if (abx500_pullud_supported(chip, pin)) | |
1083 | ret = abx500_set_pull_updown(pct, | |
1084 | pin, | |
1085 | ABX500_GPIO_PULL_NONE); | |
1086 | else | |
1087 | /* Chip only supports pull down */ | |
1088 | ret = abx500_gpio_set_bits(chip, | |
1089 | AB8500_GPIO_PUD1_REG, offset, | |
1090 | ABX500_GPIO_PULL_NONE); | |
1091 | break; | |
9ed3cd33 | 1092 | |
03b054e9 SY |
1093 | case PIN_CONFIG_BIAS_PULL_DOWN: |
1094 | ret = abx500_gpio_direction_input(chip, offset); | |
1095 | if (ret < 0) | |
1096 | goto out; | |
1097 | /* | |
1098 | * if argument = 1 set the pull down | |
1099 | * else clear the pull down | |
1100 | * Some chips only support pull down, while some | |
1101 | * actually support both pull up and pull down. Such | |
1102 | * chips have a "pullud" range specified for the pins | |
1103 | * that support both features. If the pin is not | |
1104 | * within that range, we fall back to the old bit set | |
1105 | * that only support pull down. | |
1106 | */ | |
1107 | if (abx500_pullud_supported(chip, pin)) | |
1108 | ret = abx500_set_pull_updown(pct, | |
1109 | pin, | |
1110 | argument ? ABX500_GPIO_PULL_DOWN : | |
1111 | ABX500_GPIO_PULL_NONE); | |
1112 | else | |
1113 | /* Chip only supports pull down */ | |
1114 | ret = abx500_gpio_set_bits(chip, | |
1115 | AB8500_GPIO_PUD1_REG, | |
1116 | offset, | |
1117 | argument ? ABX500_GPIO_PULL_DOWN : | |
1118 | ABX500_GPIO_PULL_NONE); | |
1119 | break; | |
83b423c8 | 1120 | |
03b054e9 SY |
1121 | case PIN_CONFIG_BIAS_PULL_UP: |
1122 | ret = abx500_gpio_direction_input(chip, offset); | |
1123 | if (ret < 0) | |
1124 | goto out; | |
1125 | /* | |
1126 | * if argument = 1 set the pull up | |
1127 | * else clear the pull up | |
1128 | */ | |
1129 | ret = abx500_gpio_direction_input(chip, offset); | |
1130 | /* | |
1131 | * Some chips only support pull down, while some | |
1132 | * actually support both pull up and pull down. Such | |
1133 | * chips have a "pullud" range specified for the pins | |
1134 | * that support both features. If the pin is not | |
1135 | * within that range, do nothing | |
1136 | */ | |
1137 | if (abx500_pullud_supported(chip, pin)) | |
1138 | ret = abx500_set_pull_updown(pct, | |
1139 | pin, | |
1140 | argument ? ABX500_GPIO_PULL_UP : | |
1141 | ABX500_GPIO_PULL_NONE); | |
1142 | break; | |
1143 | ||
1144 | case PIN_CONFIG_OUTPUT: | |
1145 | ret = abx500_gpio_direction_output(chip, offset, | |
1146 | argument); | |
1147 | break; | |
1148 | ||
1149 | default: | |
1150 | dev_err(chip->dev, "illegal configuration requested\n"); | |
1151 | } | |
1152 | } /* for each config */ | |
9be580af PC |
1153 | out: |
1154 | if (ret < 0) | |
1155 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 1156 | |
0493e649 PC |
1157 | return ret; |
1158 | } | |
1159 | ||
022ab148 | 1160 | static const struct pinconf_ops abx500_pinconf_ops = { |
0493e649 PC |
1161 | .pin_config_get = abx500_pin_config_get, |
1162 | .pin_config_set = abx500_pin_config_set, | |
1163 | }; | |
1164 | ||
1165 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
1166 | .name = "pinctrl-abx500", | |
1167 | .pctlops = &abx500_pinctrl_ops, | |
1168 | .pmxops = &abx500_pinmux_ops, | |
1169 | .confops = &abx500_pinconf_ops, | |
1170 | .owner = THIS_MODULE, | |
1171 | }; | |
1172 | ||
1173 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
1174 | { | |
1175 | unsigned int lowest = 0; | |
1176 | unsigned int highest = 0; | |
1177 | unsigned int npins = 0; | |
1178 | int i; | |
1179 | ||
1180 | /* | |
1181 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
1182 | * These ranges may include "holes" but the GPIO number space shall | |
1183 | * still be homogeneous, so we need to detect and account for any | |
1184 | * such holes so that these are included in the number of GPIO pins. | |
1185 | */ | |
1186 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
1187 | unsigned gstart; | |
1188 | unsigned gend; | |
1189 | const struct abx500_pinrange *p; | |
1190 | ||
1191 | p = &soc->gpio_ranges[i]; | |
1192 | gstart = p->offset; | |
1193 | gend = p->offset + p->npins - 1; | |
1194 | ||
1195 | if (i == 0) { | |
1196 | /* First iteration, set start values */ | |
1197 | lowest = gstart; | |
1198 | highest = gend; | |
1199 | } else { | |
1200 | if (gstart < lowest) | |
1201 | lowest = gstart; | |
1202 | if (gend > highest) | |
1203 | highest = gend; | |
1204 | } | |
1205 | } | |
1206 | /* this gives the absolute number of pins */ | |
1207 | npins = highest - lowest + 1; | |
1208 | return npins; | |
1209 | } | |
1210 | ||
f30a3839 LJ |
1211 | static const struct of_device_id abx500_gpio_match[] = { |
1212 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, | |
1213 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, | |
1214 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, | |
1215 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, | |
e3929714 | 1216 | { } |
f30a3839 LJ |
1217 | }; |
1218 | ||
0493e649 PC |
1219 | static int abx500_gpio_probe(struct platform_device *pdev) |
1220 | { | |
1221 | struct ab8500_platform_data *abx500_pdata = | |
1222 | dev_get_platdata(pdev->dev.parent); | |
f30a3839 LJ |
1223 | struct abx500_gpio_platform_data *pdata = NULL; |
1224 | struct device_node *np = pdev->dev.of_node; | |
0493e649 PC |
1225 | struct abx500_pinctrl *pct; |
1226 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
f30a3839 | 1227 | unsigned int id = -1; |
fa1ec996 | 1228 | int ret, err; |
0493e649 PC |
1229 | int i; |
1230 | ||
f30a3839 LJ |
1231 | if (abx500_pdata) |
1232 | pdata = abx500_pdata->gpio; | |
f30a3839 | 1233 | |
86c976e4 LJ |
1234 | if (!(pdata || np)) { |
1235 | dev_err(&pdev->dev, "gpio dt and platform data missing\n"); | |
1236 | return -ENODEV; | |
0493e649 PC |
1237 | } |
1238 | ||
1239 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
1240 | GFP_KERNEL); | |
1241 | if (pct == NULL) { | |
1242 | dev_err(&pdev->dev, | |
1243 | "failed to allocate memory for pct\n"); | |
1244 | return -ENOMEM; | |
1245 | } | |
1246 | ||
1247 | pct->dev = &pdev->dev; | |
1248 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
1249 | pct->chip = abx500gpio_chip; | |
1250 | pct->chip.dev = &pdev->dev; | |
f30a3839 | 1251 | pct->chip.base = (np) ? -1 : pdata->gpio_base; |
0493e649 | 1252 | |
86c976e4 LJ |
1253 | if (platid) |
1254 | id = platid->driver_data; | |
1255 | else if (np) { | |
1256 | const struct of_device_id *match; | |
1257 | ||
1258 | match = of_match_device(abx500_gpio_match, &pdev->dev); | |
1259 | if (match) | |
1260 | id = (unsigned long)match->data; | |
1261 | } | |
1262 | ||
0493e649 | 1263 | /* Poke in other ASIC variants here */ |
f30a3839 | 1264 | switch (id) { |
3c937993 PC |
1265 | case PINCTRL_AB8500: |
1266 | abx500_pinctrl_ab8500_init(&pct->soc); | |
1267 | break; | |
a8f96e41 PC |
1268 | case PINCTRL_AB8540: |
1269 | abx500_pinctrl_ab8540_init(&pct->soc); | |
1270 | break; | |
09dbec3f PC |
1271 | case PINCTRL_AB9540: |
1272 | abx500_pinctrl_ab9540_init(&pct->soc); | |
1273 | break; | |
1aa2d8d4 PC |
1274 | case PINCTRL_AB8505: |
1275 | abx500_pinctrl_ab8505_init(&pct->soc); | |
1276 | break; | |
0493e649 | 1277 | default: |
2fcad12e | 1278 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); |
0493e649 PC |
1279 | return -EINVAL; |
1280 | } | |
1281 | ||
1282 | if (!pct->soc) { | |
1283 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
1284 | return -EINVAL; | |
1285 | } | |
1286 | ||
1287 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
1288 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
1289 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
0493e649 | 1290 | |
0493e649 PC |
1291 | ret = gpiochip_add(&pct->chip); |
1292 | if (ret) { | |
83b423c8 | 1293 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
ac652d79 | 1294 | return ret; |
0493e649 PC |
1295 | } |
1296 | dev_info(&pdev->dev, "added gpiochip\n"); | |
1297 | ||
1298 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
1299 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
1300 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
1301 | if (!pct->pctldev) { | |
1302 | dev_err(&pdev->dev, | |
1303 | "could not register abx500 pinctrl driver\n"); | |
fa1ec996 | 1304 | ret = -EINVAL; |
0493e649 PC |
1305 | goto out_rem_chip; |
1306 | } | |
1307 | dev_info(&pdev->dev, "registered pin controller\n"); | |
1308 | ||
1309 | /* We will handle a range of GPIO pins */ | |
1310 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
1311 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
1312 | ||
1313 | ret = gpiochip_add_pin_range(&pct->chip, | |
1314 | dev_name(&pdev->dev), | |
1315 | p->offset - 1, p->offset, p->npins); | |
1316 | if (ret < 0) | |
fa1ec996 | 1317 | goto out_rem_chip; |
0493e649 PC |
1318 | } |
1319 | ||
1320 | platform_set_drvdata(pdev, pct); | |
1321 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
1322 | ||
1323 | return 0; | |
1324 | ||
1325 | out_rem_chip: | |
fa1ec996 LJ |
1326 | err = gpiochip_remove(&pct->chip); |
1327 | if (err) | |
0493e649 | 1328 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); |
ac652d79 | 1329 | |
0493e649 PC |
1330 | return ret; |
1331 | } | |
1332 | ||
83b423c8 | 1333 | /** |
0493e649 | 1334 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
83b423c8 | 1335 | * @pdev: Platform device registered |
0493e649 PC |
1336 | */ |
1337 | static int abx500_gpio_remove(struct platform_device *pdev) | |
1338 | { | |
1339 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
1340 | int ret; | |
1341 | ||
1342 | ret = gpiochip_remove(&pct->chip); | |
1343 | if (ret < 0) { | |
1344 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", | |
1345 | ret); | |
1346 | return ret; | |
1347 | } | |
1348 | ||
0493e649 PC |
1349 | return 0; |
1350 | } | |
1351 | ||
1352 | static const struct platform_device_id abx500_pinctrl_id[] = { | |
1353 | { "pinctrl-ab8500", PINCTRL_AB8500 }, | |
1354 | { "pinctrl-ab8540", PINCTRL_AB8540 }, | |
1355 | { "pinctrl-ab9540", PINCTRL_AB9540 }, | |
1356 | { "pinctrl-ab8505", PINCTRL_AB8505 }, | |
1357 | { }, | |
1358 | }; | |
1359 | ||
1360 | static struct platform_driver abx500_gpio_driver = { | |
1361 | .driver = { | |
1362 | .name = "abx500-gpio", | |
1363 | .owner = THIS_MODULE, | |
f30a3839 | 1364 | .of_match_table = abx500_gpio_match, |
0493e649 PC |
1365 | }, |
1366 | .probe = abx500_gpio_probe, | |
1367 | .remove = abx500_gpio_remove, | |
1368 | .id_table = abx500_pinctrl_id, | |
1369 | }; | |
1370 | ||
1371 | static int __init abx500_gpio_init(void) | |
1372 | { | |
1373 | return platform_driver_register(&abx500_gpio_driver); | |
1374 | } | |
1375 | core_initcall(abx500_gpio_init); | |
1376 | ||
1377 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1378 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1379 | MODULE_ALIAS("platform:abx500-gpio"); | |
1380 | MODULE_LICENSE("GPL v2"); |