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0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
f30a3839 LJ |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
0493e649 PC |
19 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/irq.h> | |
ac652d79 | 22 | #include <linux/irqdomain.h> |
0493e649 PC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/mfd/abx500.h> | |
26 | #include <linux/mfd/abx500/ab8500.h> | |
27 | #include <linux/mfd/abx500/ab8500-gpio.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/consumer.h> | |
30 | #include <linux/pinctrl/pinmux.h> | |
31 | #include <linux/pinctrl/pinconf.h> | |
32 | #include <linux/pinctrl/pinconf-generic.h> | |
33 | ||
34 | #include "pinctrl-abx500.h" | |
35 | ||
36 | /* | |
37 | * The AB9540 and AB8540 GPIO support are extended versions | |
38 | * of the AB8500 GPIO support. | |
39 | * The AB9540 supports an additional (7th) register so that | |
40 | * more GPIO may be configured and used. | |
41 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
42 | * internal pull-up and pull-down capabilities. | |
43 | */ | |
44 | ||
45 | /* | |
46 | * GPIO registers offset | |
47 | * Bank: 0x10 | |
48 | */ | |
49 | #define AB8500_GPIO_SEL1_REG 0x00 | |
50 | #define AB8500_GPIO_SEL2_REG 0x01 | |
51 | #define AB8500_GPIO_SEL3_REG 0x02 | |
52 | #define AB8500_GPIO_SEL4_REG 0x03 | |
53 | #define AB8500_GPIO_SEL5_REG 0x04 | |
54 | #define AB8500_GPIO_SEL6_REG 0x05 | |
55 | #define AB9540_GPIO_SEL7_REG 0x06 | |
56 | ||
57 | #define AB8500_GPIO_DIR1_REG 0x10 | |
58 | #define AB8500_GPIO_DIR2_REG 0x11 | |
59 | #define AB8500_GPIO_DIR3_REG 0x12 | |
60 | #define AB8500_GPIO_DIR4_REG 0x13 | |
61 | #define AB8500_GPIO_DIR5_REG 0x14 | |
62 | #define AB8500_GPIO_DIR6_REG 0x15 | |
63 | #define AB9540_GPIO_DIR7_REG 0x16 | |
64 | ||
65 | #define AB8500_GPIO_OUT1_REG 0x20 | |
66 | #define AB8500_GPIO_OUT2_REG 0x21 | |
67 | #define AB8500_GPIO_OUT3_REG 0x22 | |
68 | #define AB8500_GPIO_OUT4_REG 0x23 | |
69 | #define AB8500_GPIO_OUT5_REG 0x24 | |
70 | #define AB8500_GPIO_OUT6_REG 0x25 | |
71 | #define AB9540_GPIO_OUT7_REG 0x26 | |
72 | ||
73 | #define AB8500_GPIO_PUD1_REG 0x30 | |
74 | #define AB8500_GPIO_PUD2_REG 0x31 | |
75 | #define AB8500_GPIO_PUD3_REG 0x32 | |
76 | #define AB8500_GPIO_PUD4_REG 0x33 | |
77 | #define AB8500_GPIO_PUD5_REG 0x34 | |
78 | #define AB8500_GPIO_PUD6_REG 0x35 | |
79 | #define AB9540_GPIO_PUD7_REG 0x36 | |
80 | ||
81 | #define AB8500_GPIO_IN1_REG 0x40 | |
82 | #define AB8500_GPIO_IN2_REG 0x41 | |
83 | #define AB8500_GPIO_IN3_REG 0x42 | |
84 | #define AB8500_GPIO_IN4_REG 0x43 | |
85 | #define AB8500_GPIO_IN5_REG 0x44 | |
86 | #define AB8500_GPIO_IN6_REG 0x45 | |
87 | #define AB9540_GPIO_IN7_REG 0x46 | |
88 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
89 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
90 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
0493e649 PC |
91 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
92 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
93 | #define AB8540_GPIOX_VBAT_START 51 | |
94 | #define AB8540_GPIOX_VBAT_END 54 | |
95 | ||
0493e649 PC |
96 | struct abx500_pinctrl { |
97 | struct device *dev; | |
98 | struct pinctrl_dev *pctldev; | |
99 | struct abx500_pinctrl_soc_data *soc; | |
100 | struct gpio_chip chip; | |
101 | struct ab8500 *parent; | |
0493e649 PC |
102 | struct abx500_gpio_irq_cluster *irq_cluster; |
103 | int irq_cluster_size; | |
0493e649 PC |
104 | }; |
105 | ||
106 | /** | |
107 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
108 | * @chip: Member of the structure abx500_pinctrl | |
109 | */ | |
110 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
111 | { | |
112 | return container_of(chip, struct abx500_pinctrl, chip); | |
113 | } | |
114 | ||
115 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 116 | unsigned offset, bool *bit) |
0493e649 PC |
117 | { |
118 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
119 | u8 pos = offset % 8; | |
120 | u8 val; | |
121 | int ret; | |
122 | ||
123 | reg += offset / 8; | |
124 | ret = abx500_get_register_interruptible(pct->dev, | |
125 | AB8500_MISC, reg, &val); | |
126 | ||
127 | *bit = !!(val & BIT(pos)); | |
128 | ||
129 | if (ret < 0) | |
130 | dev_err(pct->dev, | |
131 | "%s read reg =%x, offset=%x failed\n", | |
132 | __func__, reg, offset); | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
137 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 138 | unsigned offset, int val) |
0493e649 PC |
139 | { |
140 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
141 | u8 pos = offset % 8; | |
142 | int ret; | |
143 | ||
144 | reg += offset / 8; | |
145 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 146 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 PC |
147 | if (ret < 0) |
148 | dev_err(pct->dev, "%s write failed\n", __func__); | |
83b423c8 | 149 | |
0493e649 PC |
150 | return ret; |
151 | } | |
83b423c8 | 152 | |
0493e649 PC |
153 | /** |
154 | * abx500_gpio_get() - Get the particular GPIO value | |
83b423c8 LJ |
155 | * @chip: Gpio device |
156 | * @offset: GPIO number to read | |
0493e649 PC |
157 | */ |
158 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
159 | { | |
160 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
161 | bool bit; | |
162 | int ret; | |
163 | ||
164 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
165 | offset, &bit); | |
166 | if (ret < 0) { | |
167 | dev_err(pct->dev, "%s failed\n", __func__); | |
168 | return ret; | |
169 | } | |
83b423c8 | 170 | |
0493e649 PC |
171 | return bit; |
172 | } | |
173 | ||
174 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
175 | { | |
176 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
177 | int ret; | |
178 | ||
179 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
180 | if (ret < 0) | |
181 | dev_err(pct->dev, "%s write failed\n", __func__); | |
182 | } | |
183 | ||
d2752ae5 PC |
184 | static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, |
185 | enum abx500_gpio_pull_updown *pull_updown) | |
0493e649 PC |
186 | { |
187 | u8 pos; | |
d2752ae5 | 188 | u8 val; |
0493e649 PC |
189 | int ret; |
190 | struct pullud *pullud; | |
191 | ||
192 | if (!pct->soc->pullud) { | |
193 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
194 | __func__); | |
195 | ret = -EPERM; | |
196 | goto out; | |
197 | } | |
198 | ||
199 | pullud = pct->soc->pullud; | |
200 | ||
201 | if ((offset < pullud->first_pin) | |
202 | || (offset > pullud->last_pin)) { | |
203 | ret = -EINVAL; | |
204 | goto out; | |
205 | } | |
206 | ||
d2752ae5 PC |
207 | ret = abx500_get_register_interruptible(pct->dev, |
208 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); | |
209 | ||
210 | pos = (offset - pullud->first_pin) << 1; | |
211 | *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; | |
212 | ||
213 | out: | |
214 | if (ret < 0) | |
215 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
220 | static int abx500_set_pull_updown(struct abx500_pinctrl *pct, | |
221 | int offset, enum abx500_gpio_pull_updown val) | |
222 | { | |
223 | u8 pos; | |
224 | int ret; | |
225 | struct pullud *pullud; | |
226 | ||
227 | if (!pct->soc->pullud) { | |
228 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
229 | __func__); | |
230 | ret = -EPERM; | |
231 | goto out; | |
232 | } | |
233 | ||
234 | pullud = pct->soc->pullud; | |
235 | ||
236 | if ((offset < pullud->first_pin) | |
237 | || (offset > pullud->last_pin)) { | |
238 | ret = -EINVAL; | |
239 | goto out; | |
240 | } | |
10a8be54 | 241 | pos = (offset - pullud->first_pin) << 1; |
0493e649 PC |
242 | |
243 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
244 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
245 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
246 | ||
247 | out: | |
248 | if (ret < 0) | |
249 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 250 | |
0493e649 PC |
251 | return ret; |
252 | } | |
253 | ||
254 | static int abx500_gpio_direction_output(struct gpio_chip *chip, | |
255 | unsigned offset, | |
256 | int val) | |
257 | { | |
258 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
259 | struct pullud *pullud = pct->soc->pullud; | |
260 | unsigned gpio; | |
261 | int ret; | |
83b423c8 | 262 | |
0493e649 PC |
263 | /* set direction as output */ |
264 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); | |
265 | if (ret < 0) | |
266 | return ret; | |
267 | ||
268 | /* disable pull down */ | |
269 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); | |
270 | if (ret < 0) | |
271 | return ret; | |
272 | ||
273 | /* if supported, disable both pull down and pull up */ | |
274 | gpio = offset + 1; | |
275 | if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { | |
d2752ae5 | 276 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
277 | gpio, |
278 | ABX500_GPIO_PULL_NONE); | |
279 | if (ret < 0) | |
280 | return ret; | |
281 | } | |
83b423c8 | 282 | |
0493e649 PC |
283 | /* set the output as 1 or 0 */ |
284 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
285 | } | |
286 | ||
287 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
288 | { | |
289 | /* set the register as input */ | |
290 | return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); | |
291 | } | |
292 | ||
293 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
294 | { | |
295 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
b9fab6e4 LJ |
296 | /* The AB8500 GPIO numbers are off by one */ |
297 | int gpio = offset + 1; | |
a6a16d27 | 298 | int hwirq; |
0493e649 PC |
299 | int i; |
300 | ||
301 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
302 | struct abx500_gpio_irq_cluster *cluster = | |
303 | &pct->irq_cluster[i]; | |
304 | ||
a6a16d27 LJ |
305 | if (gpio >= cluster->start && gpio <= cluster->end) { |
306 | /* | |
307 | * The ABx500 GPIO's associated IRQs are clustered together | |
308 | * throughout the interrupt numbers at irregular intervals. | |
309 | * To solve this quandry, we have placed the read-in values | |
310 | * into the cluster information table. | |
311 | */ | |
43a255db | 312 | hwirq = gpio - cluster->start + cluster->to_irq; |
a6a16d27 LJ |
313 | return irq_create_mapping(pct->parent->domain, hwirq); |
314 | } | |
0493e649 PC |
315 | } |
316 | ||
317 | return -EINVAL; | |
318 | } | |
319 | ||
320 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 321 | unsigned gpio, int alt_setting) |
0493e649 PC |
322 | { |
323 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
324 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
325 | int ret; | |
326 | int val; | |
327 | unsigned offset; | |
83b423c8 | 328 | |
0493e649 PC |
329 | const char *modes[] = { |
330 | [ABX500_DEFAULT] = "default", | |
331 | [ABX500_ALT_A] = "altA", | |
332 | [ABX500_ALT_B] = "altB", | |
333 | [ABX500_ALT_C] = "altC", | |
334 | }; | |
335 | ||
336 | /* sanity check */ | |
337 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
338 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
339 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
340 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
341 | modes[alt_setting]); | |
342 | return -EINVAL; | |
343 | } | |
344 | ||
345 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
346 | offset = gpio - 1; | |
83b423c8 | 347 | |
0493e649 PC |
348 | switch (alt_setting) { |
349 | case ABX500_DEFAULT: | |
350 | /* | |
351 | * for ABx5xx family, default mode is always selected by | |
352 | * writing 0 to GPIOSELx register, except for pins which | |
353 | * support at least ALT_B mode, default mode is selected | |
354 | * by writing 1 to GPIOSELx register | |
355 | */ | |
356 | val = 0; | |
357 | if (af.alt_bit1 != UNUSED) | |
358 | val++; | |
359 | ||
360 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
361 | offset, val); | |
362 | break; | |
83b423c8 | 363 | |
0493e649 PC |
364 | case ABX500_ALT_A: |
365 | /* | |
366 | * for ABx5xx family, alt_a mode is always selected by | |
367 | * writing 1 to GPIOSELx register, except for pins which | |
368 | * support at least ALT_B mode, alt_a mode is selected | |
369 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
370 | * register | |
371 | */ | |
372 | if (af.alt_bit1 != UNUSED) { | |
373 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
374 | offset, 0); | |
375 | ret = abx500_gpio_set_bits(chip, | |
376 | AB8500_GPIO_ALTFUN_REG, | |
377 | af.alt_bit1, | |
378 | !!(af.alta_val && BIT(0))); | |
379 | if (af.alt_bit2 != UNUSED) | |
380 | ret = abx500_gpio_set_bits(chip, | |
381 | AB8500_GPIO_ALTFUN_REG, | |
382 | af.alt_bit2, | |
383 | !!(af.alta_val && BIT(1))); | |
384 | } else | |
385 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
386 | offset, 1); | |
387 | break; | |
83b423c8 | 388 | |
0493e649 PC |
389 | case ABX500_ALT_B: |
390 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
391 | offset, 0); | |
392 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
393 | af.alt_bit1, !!(af.altb_val && BIT(0))); | |
394 | if (af.alt_bit2 != UNUSED) | |
395 | ret = abx500_gpio_set_bits(chip, | |
396 | AB8500_GPIO_ALTFUN_REG, | |
397 | af.alt_bit2, | |
398 | !!(af.altb_val && BIT(1))); | |
399 | break; | |
83b423c8 | 400 | |
0493e649 PC |
401 | case ABX500_ALT_C: |
402 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
403 | offset, 0); | |
404 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
405 | af.alt_bit2, !!(af.altc_val && BIT(0))); | |
406 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
407 | af.alt_bit2, !!(af.altc_val && BIT(1))); | |
408 | break; | |
409 | ||
410 | default: | |
411 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
83b423c8 | 412 | |
0493e649 PC |
413 | return -EINVAL; |
414 | } | |
83b423c8 | 415 | |
0493e649 PC |
416 | return ret; |
417 | } | |
418 | ||
419 | static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 420 | unsigned gpio) |
0493e649 PC |
421 | { |
422 | u8 mode; | |
423 | bool bit_mode; | |
424 | bool alt_bit1; | |
425 | bool alt_bit2; | |
426 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
427 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
a950cb74 LW |
428 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
429 | unsigned offset = gpio - 1; | |
0493e649 PC |
430 | |
431 | /* | |
432 | * if gpiosel_bit is set to unused, | |
433 | * it means no GPIO or special case | |
434 | */ | |
435 | if (af.gpiosel_bit == UNUSED) | |
436 | return ABX500_DEFAULT; | |
437 | ||
438 | /* read GpioSelx register */ | |
a950cb74 | 439 | abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
0493e649 PC |
440 | af.gpiosel_bit, &bit_mode); |
441 | mode = bit_mode; | |
442 | ||
443 | /* sanity check */ | |
444 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
445 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
446 | dev_err(pct->dev, | |
447 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
448 | return -EINVAL; | |
449 | } | |
83b423c8 | 450 | |
0493e649 PC |
451 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
452 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
453 | dev_err(pct->dev, | |
454 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
458 | /* check if pin use AlternateFunction register */ | |
6a40cdd5 | 459 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) |
0493e649 PC |
460 | return mode; |
461 | /* | |
462 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
463 | * it means DEFAULT mode | |
464 | */ | |
465 | if (mode) | |
466 | return ABX500_DEFAULT; | |
83b423c8 | 467 | |
0493e649 PC |
468 | /* |
469 | * pin use the AlternatFunction register | |
470 | * read alt_bit1 value | |
471 | */ | |
472 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, | |
473 | af.alt_bit1, &alt_bit1); | |
474 | ||
475 | if (af.alt_bit2 != UNUSED) | |
476 | /* read alt_bit2 value */ | |
477 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, | |
478 | &alt_bit2); | |
479 | else | |
480 | alt_bit2 = 0; | |
481 | ||
482 | mode = (alt_bit2 << 1) + alt_bit1; | |
483 | if (mode == af.alta_val) | |
484 | return ABX500_ALT_A; | |
485 | else if (mode == af.altb_val) | |
486 | return ABX500_ALT_B; | |
487 | else | |
488 | return ABX500_ALT_C; | |
489 | } | |
490 | ||
491 | #ifdef CONFIG_DEBUG_FS | |
492 | ||
493 | #include <linux/seq_file.h> | |
494 | ||
495 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
496 | struct pinctrl_dev *pctldev, |
497 | struct gpio_chip *chip, | |
498 | unsigned offset, unsigned gpio) | |
0493e649 | 499 | { |
d2752ae5 PC |
500 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
501 | struct pullud *pullud = pct->soc->pullud; | |
0493e649 PC |
502 | const char *label = gpiochip_is_requested(chip, offset - 1); |
503 | u8 gpio_offset = offset - 1; | |
504 | int mode = -1; | |
505 | bool is_out; | |
d2752ae5 | 506 | bool pd; |
ce06f407 | 507 | enum abx500_gpio_pull_updown pud = 0; |
83b423c8 | 508 | |
0493e649 PC |
509 | const char *modes[] = { |
510 | [ABX500_DEFAULT] = "default", | |
511 | [ABX500_ALT_A] = "altA", | |
512 | [ABX500_ALT_B] = "altB", | |
513 | [ABX500_ALT_C] = "altC", | |
514 | }; | |
515 | ||
d2752ae5 PC |
516 | const char *pull_up_down[] = { |
517 | [ABX500_GPIO_PULL_DOWN] = "pull down", | |
518 | [ABX500_GPIO_PULL_NONE] = "pull none", | |
519 | [ABX500_GPIO_PULL_NONE + 1] = "pull none", | |
520 | [ABX500_GPIO_PULL_UP] = "pull up", | |
521 | }; | |
522 | ||
0493e649 | 523 | abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); |
d2752ae5 PC |
524 | |
525 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", | |
526 | gpio, label ?: "(none)", | |
527 | is_out ? "out" : "in "); | |
528 | ||
529 | if (!is_out) { | |
530 | if (pullud && | |
531 | (offset >= pullud->first_pin) && | |
532 | (offset <= pullud->last_pin)) { | |
533 | abx500_get_pull_updown(pct, offset, &pud); | |
534 | seq_printf(s, " %-9s", pull_up_down[pud]); | |
535 | } else { | |
536 | abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, | |
537 | gpio_offset, &pd); | |
538 | seq_printf(s, " %-9s", pull_up_down[pd]); | |
539 | } | |
540 | } else | |
541 | seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); | |
0493e649 PC |
542 | |
543 | if (pctldev) | |
544 | mode = abx500_get_mode(pctldev, chip, offset); | |
545 | ||
d2752ae5 | 546 | seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); |
0493e649 PC |
547 | } |
548 | ||
549 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
550 | { | |
551 | unsigned i; | |
552 | unsigned gpio = chip->base; | |
553 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
554 | struct pinctrl_dev *pctldev = pct->pctldev; | |
555 | ||
556 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
557 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
558 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
559 | seq_printf(s, "\n"); | |
560 | } | |
561 | } | |
562 | ||
563 | #else | |
564 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
565 | struct pinctrl_dev *pctldev, |
566 | struct gpio_chip *chip, | |
567 | unsigned offset, unsigned gpio) | |
0493e649 PC |
568 | { |
569 | } | |
570 | #define abx500_gpio_dbg_show NULL | |
571 | #endif | |
572 | ||
9c4154ef | 573 | static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
574 | { |
575 | int gpio = chip->base + offset; | |
576 | ||
577 | return pinctrl_request_gpio(gpio); | |
578 | } | |
579 | ||
9c4154ef | 580 | static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
581 | { |
582 | int gpio = chip->base + offset; | |
583 | ||
584 | pinctrl_free_gpio(gpio); | |
585 | } | |
586 | ||
587 | static struct gpio_chip abx500gpio_chip = { | |
588 | .label = "abx500-gpio", | |
589 | .owner = THIS_MODULE, | |
590 | .request = abx500_gpio_request, | |
591 | .free = abx500_gpio_free, | |
592 | .direction_input = abx500_gpio_direction_input, | |
593 | .get = abx500_gpio_get, | |
594 | .direction_output = abx500_gpio_direction_output, | |
595 | .set = abx500_gpio_set, | |
596 | .to_irq = abx500_gpio_to_irq, | |
597 | .dbg_show = abx500_gpio_dbg_show, | |
598 | }; | |
599 | ||
0493e649 PC |
600 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
601 | { | |
602 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
603 | ||
604 | return pct->soc->nfunctions; | |
605 | } | |
606 | ||
607 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
608 | unsigned function) | |
609 | { | |
610 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
611 | ||
612 | return pct->soc->functions[function].name; | |
613 | } | |
614 | ||
615 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
616 | unsigned function, |
617 | const char * const **groups, | |
618 | unsigned * const num_groups) | |
0493e649 PC |
619 | { |
620 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
621 | ||
622 | *groups = pct->soc->functions[function].groups; | |
623 | *num_groups = pct->soc->functions[function].ngroups; | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
0493e649 | 628 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, |
83b423c8 | 629 | unsigned group) |
0493e649 PC |
630 | { |
631 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
632 | struct gpio_chip *chip = &pct->chip; | |
633 | const struct abx500_pingroup *g; | |
634 | int i; | |
635 | int ret = 0; | |
636 | ||
637 | g = &pct->soc->groups[group]; | |
638 | if (g->altsetting < 0) | |
639 | return -EINVAL; | |
640 | ||
641 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
642 | ||
643 | for (i = 0; i < g->npins; i++) { | |
644 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
645 | g->pins[i], g->altsetting); | |
646 | ||
0493e649 PC |
647 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
648 | } | |
83b423c8 | 649 | |
0493e649 PC |
650 | return ret; |
651 | } | |
652 | ||
653 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, | |
83b423c8 | 654 | unsigned function, unsigned group) |
0493e649 PC |
655 | { |
656 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
657 | const struct abx500_pingroup *g; | |
658 | ||
659 | g = &pct->soc->groups[group]; | |
660 | if (g->altsetting < 0) | |
661 | return; | |
662 | ||
663 | /* FIXME: poke out the mux, set the pin to some default state? */ | |
664 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
665 | } | |
666 | ||
9c4154ef | 667 | static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
668 | struct pinctrl_gpio_range *range, |
669 | unsigned offset) | |
0493e649 PC |
670 | { |
671 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
672 | const struct abx500_pinrange *p; | |
673 | int ret; | |
674 | int i; | |
675 | ||
676 | /* | |
677 | * Different ranges have different ways to enable GPIO function on a | |
678 | * pin, so refer back to our local range type, where we handily define | |
679 | * what altfunc enables GPIO for a certain pin. | |
680 | */ | |
681 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
682 | p = &pct->soc->gpio_ranges[i]; | |
683 | if ((offset >= p->offset) && | |
684 | (offset < (p->offset + p->npins))) | |
685 | break; | |
686 | } | |
687 | ||
688 | if (i == pct->soc->gpio_num_ranges) { | |
689 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
690 | return -ENODEV; | |
691 | } | |
692 | ||
693 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
694 | p->altfunc, offset); | |
695 | ||
696 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
697 | offset, p->altfunc); | |
698 | if (ret < 0) { | |
699 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); | |
700 | return ret; | |
701 | } | |
702 | ||
703 | return ret; | |
704 | } | |
705 | ||
706 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
707 | struct pinctrl_gpio_range *range, |
708 | unsigned offset) | |
0493e649 PC |
709 | { |
710 | } | |
711 | ||
022ab148 | 712 | static const struct pinmux_ops abx500_pinmux_ops = { |
0493e649 PC |
713 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
714 | .get_function_name = abx500_pmx_get_func_name, | |
715 | .get_function_groups = abx500_pmx_get_func_groups, | |
716 | .enable = abx500_pmx_enable, | |
717 | .disable = abx500_pmx_disable, | |
718 | .gpio_request_enable = abx500_gpio_request_enable, | |
719 | .gpio_disable_free = abx500_gpio_disable_free, | |
720 | }; | |
721 | ||
722 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
723 | { | |
724 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
725 | ||
726 | return pct->soc->ngroups; | |
727 | } | |
728 | ||
729 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
83b423c8 | 730 | unsigned selector) |
0493e649 PC |
731 | { |
732 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
733 | ||
734 | return pct->soc->groups[selector].name; | |
735 | } | |
736 | ||
737 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
738 | unsigned selector, |
739 | const unsigned **pins, | |
740 | unsigned *num_pins) | |
0493e649 PC |
741 | { |
742 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
743 | ||
744 | *pins = pct->soc->groups[selector].pins; | |
745 | *num_pins = pct->soc->groups[selector].npins; | |
83b423c8 | 746 | |
0493e649 PC |
747 | return 0; |
748 | } | |
749 | ||
750 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
83b423c8 | 751 | struct seq_file *s, unsigned offset) |
0493e649 PC |
752 | { |
753 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
754 | struct gpio_chip *chip = &pct->chip; | |
755 | ||
756 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
757 | chip->base + offset - 1); | |
758 | } | |
759 | ||
022ab148 | 760 | static const struct pinctrl_ops abx500_pinctrl_ops = { |
0493e649 PC |
761 | .get_groups_count = abx500_get_groups_cnt, |
762 | .get_group_name = abx500_get_group_name, | |
763 | .get_group_pins = abx500_get_group_pins, | |
764 | .pin_dbg_show = abx500_pin_dbg_show, | |
765 | }; | |
766 | ||
9c4154ef | 767 | static int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
768 | unsigned pin, |
769 | unsigned long *config) | |
0493e649 | 770 | { |
1abeebea | 771 | return -ENOSYS; |
0493e649 PC |
772 | } |
773 | ||
9c4154ef | 774 | static int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
775 | unsigned pin, |
776 | unsigned long config) | |
0493e649 PC |
777 | { |
778 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
779 | struct pullud *pullud = pct->soc->pullud; | |
780 | struct gpio_chip *chip = &pct->chip; | |
781 | unsigned offset; | |
9ed3cd33 | 782 | int ret = 0; |
0493e649 PC |
783 | enum pin_config_param param = pinconf_to_config_param(config); |
784 | enum pin_config_param argument = pinconf_to_config_argument(config); | |
785 | ||
786 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
787 | pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
788 | (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : | |
789 | (argument ? "pull up" : "pull down")); | |
83b423c8 | 790 | |
0493e649 PC |
791 | /* on ABx500, there is no GPIO0, so adjust the offset */ |
792 | offset = pin - 1; | |
793 | ||
794 | switch (param) { | |
795 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
796 | /* | |
797 | * if argument = 1 set the pull down | |
798 | * else clear the pull down | |
799 | */ | |
800 | ret = abx500_gpio_direction_input(chip, offset); | |
801 | /* | |
802 | * Some chips only support pull down, while some actually | |
803 | * support both pull up and pull down. Such chips have | |
804 | * a "pullud" range specified for the pins that support | |
805 | * both features. If the pin is not within that range, we | |
806 | * fall back to the old bit set that only support pull down. | |
807 | */ | |
808 | if (pullud && | |
809 | pin >= pullud->first_pin && | |
810 | pin <= pullud->last_pin) | |
d2752ae5 | 811 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
812 | pin, |
813 | argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); | |
814 | else | |
815 | /* Chip only supports pull down */ | |
816 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, | |
817 | offset, argument ? 0 : 1); | |
818 | break; | |
83b423c8 | 819 | |
9ed3cd33 PC |
820 | case PIN_CONFIG_BIAS_PULL_UP: |
821 | /* | |
822 | * if argument = 1 set the pull up | |
823 | * else clear the pull up | |
824 | */ | |
825 | ret = abx500_gpio_direction_input(chip, offset); | |
826 | /* | |
827 | * Some chips only support pull down, while some actually | |
828 | * support both pull up and pull down. Such chips have | |
829 | * a "pullud" range specified for the pins that support | |
830 | * both features. If the pin is not within that range, do | |
831 | * nothing | |
832 | */ | |
833 | if (pullud && | |
834 | pin >= pullud->first_pin && | |
835 | pin <= pullud->last_pin) { | |
d2752ae5 | 836 | ret = abx500_set_pull_updown(pct, |
9ed3cd33 PC |
837 | pin, |
838 | argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE); | |
839 | } | |
840 | break; | |
841 | ||
0493e649 PC |
842 | case PIN_CONFIG_OUTPUT: |
843 | ret = abx500_gpio_direction_output(chip, offset, argument); | |
83b423c8 | 844 | |
0493e649 | 845 | break; |
83b423c8 | 846 | |
0493e649 PC |
847 | default: |
848 | dev_err(chip->dev, "illegal configuration requested\n"); | |
83b423c8 | 849 | |
0493e649 PC |
850 | return -EINVAL; |
851 | } | |
83b423c8 | 852 | |
0493e649 PC |
853 | return ret; |
854 | } | |
855 | ||
022ab148 | 856 | static const struct pinconf_ops abx500_pinconf_ops = { |
0493e649 PC |
857 | .pin_config_get = abx500_pin_config_get, |
858 | .pin_config_set = abx500_pin_config_set, | |
859 | }; | |
860 | ||
861 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
862 | .name = "pinctrl-abx500", | |
863 | .pctlops = &abx500_pinctrl_ops, | |
864 | .pmxops = &abx500_pinmux_ops, | |
865 | .confops = &abx500_pinconf_ops, | |
866 | .owner = THIS_MODULE, | |
867 | }; | |
868 | ||
869 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
870 | { | |
871 | unsigned int lowest = 0; | |
872 | unsigned int highest = 0; | |
873 | unsigned int npins = 0; | |
874 | int i; | |
875 | ||
876 | /* | |
877 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
878 | * These ranges may include "holes" but the GPIO number space shall | |
879 | * still be homogeneous, so we need to detect and account for any | |
880 | * such holes so that these are included in the number of GPIO pins. | |
881 | */ | |
882 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
883 | unsigned gstart; | |
884 | unsigned gend; | |
885 | const struct abx500_pinrange *p; | |
886 | ||
887 | p = &soc->gpio_ranges[i]; | |
888 | gstart = p->offset; | |
889 | gend = p->offset + p->npins - 1; | |
890 | ||
891 | if (i == 0) { | |
892 | /* First iteration, set start values */ | |
893 | lowest = gstart; | |
894 | highest = gend; | |
895 | } else { | |
896 | if (gstart < lowest) | |
897 | lowest = gstart; | |
898 | if (gend > highest) | |
899 | highest = gend; | |
900 | } | |
901 | } | |
902 | /* this gives the absolute number of pins */ | |
903 | npins = highest - lowest + 1; | |
904 | return npins; | |
905 | } | |
906 | ||
f30a3839 LJ |
907 | static const struct of_device_id abx500_gpio_match[] = { |
908 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, | |
909 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, | |
910 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, | |
911 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, | |
e3929714 | 912 | { } |
f30a3839 LJ |
913 | }; |
914 | ||
0493e649 PC |
915 | static int abx500_gpio_probe(struct platform_device *pdev) |
916 | { | |
917 | struct ab8500_platform_data *abx500_pdata = | |
918 | dev_get_platdata(pdev->dev.parent); | |
f30a3839 LJ |
919 | struct abx500_gpio_platform_data *pdata = NULL; |
920 | struct device_node *np = pdev->dev.of_node; | |
0493e649 PC |
921 | struct abx500_pinctrl *pct; |
922 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
f30a3839 | 923 | unsigned int id = -1; |
fa1ec996 | 924 | int ret, err; |
0493e649 PC |
925 | int i; |
926 | ||
f30a3839 LJ |
927 | if (abx500_pdata) |
928 | pdata = abx500_pdata->gpio; | |
f30a3839 | 929 | |
86c976e4 LJ |
930 | if (!(pdata || np)) { |
931 | dev_err(&pdev->dev, "gpio dt and platform data missing\n"); | |
932 | return -ENODEV; | |
0493e649 PC |
933 | } |
934 | ||
935 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
936 | GFP_KERNEL); | |
937 | if (pct == NULL) { | |
938 | dev_err(&pdev->dev, | |
939 | "failed to allocate memory for pct\n"); | |
940 | return -ENOMEM; | |
941 | } | |
942 | ||
943 | pct->dev = &pdev->dev; | |
944 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
945 | pct->chip = abx500gpio_chip; | |
946 | pct->chip.dev = &pdev->dev; | |
f30a3839 | 947 | pct->chip.base = (np) ? -1 : pdata->gpio_base; |
0493e649 | 948 | |
86c976e4 LJ |
949 | if (platid) |
950 | id = platid->driver_data; | |
951 | else if (np) { | |
952 | const struct of_device_id *match; | |
953 | ||
954 | match = of_match_device(abx500_gpio_match, &pdev->dev); | |
955 | if (match) | |
956 | id = (unsigned long)match->data; | |
957 | } | |
958 | ||
0493e649 | 959 | /* Poke in other ASIC variants here */ |
f30a3839 | 960 | switch (id) { |
3c937993 PC |
961 | case PINCTRL_AB8500: |
962 | abx500_pinctrl_ab8500_init(&pct->soc); | |
963 | break; | |
a8f96e41 PC |
964 | case PINCTRL_AB8540: |
965 | abx500_pinctrl_ab8540_init(&pct->soc); | |
966 | break; | |
09dbec3f PC |
967 | case PINCTRL_AB9540: |
968 | abx500_pinctrl_ab9540_init(&pct->soc); | |
969 | break; | |
1aa2d8d4 PC |
970 | case PINCTRL_AB8505: |
971 | abx500_pinctrl_ab8505_init(&pct->soc); | |
972 | break; | |
0493e649 | 973 | default: |
2fcad12e | 974 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); |
0493e649 PC |
975 | return -EINVAL; |
976 | } | |
977 | ||
978 | if (!pct->soc) { | |
979 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
980 | return -EINVAL; | |
981 | } | |
982 | ||
983 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
984 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
985 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
0493e649 | 986 | |
0493e649 PC |
987 | ret = gpiochip_add(&pct->chip); |
988 | if (ret) { | |
83b423c8 | 989 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
ac652d79 | 990 | return ret; |
0493e649 PC |
991 | } |
992 | dev_info(&pdev->dev, "added gpiochip\n"); | |
993 | ||
994 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
995 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
996 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
997 | if (!pct->pctldev) { | |
998 | dev_err(&pdev->dev, | |
999 | "could not register abx500 pinctrl driver\n"); | |
fa1ec996 | 1000 | ret = -EINVAL; |
0493e649 PC |
1001 | goto out_rem_chip; |
1002 | } | |
1003 | dev_info(&pdev->dev, "registered pin controller\n"); | |
1004 | ||
1005 | /* We will handle a range of GPIO pins */ | |
1006 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
1007 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
1008 | ||
1009 | ret = gpiochip_add_pin_range(&pct->chip, | |
1010 | dev_name(&pdev->dev), | |
1011 | p->offset - 1, p->offset, p->npins); | |
1012 | if (ret < 0) | |
fa1ec996 | 1013 | goto out_rem_chip; |
0493e649 PC |
1014 | } |
1015 | ||
1016 | platform_set_drvdata(pdev, pct); | |
1017 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
1018 | ||
1019 | return 0; | |
1020 | ||
1021 | out_rem_chip: | |
fa1ec996 LJ |
1022 | err = gpiochip_remove(&pct->chip); |
1023 | if (err) | |
0493e649 | 1024 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); |
ac652d79 | 1025 | |
0493e649 PC |
1026 | return ret; |
1027 | } | |
1028 | ||
83b423c8 | 1029 | /** |
0493e649 | 1030 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
83b423c8 | 1031 | * @pdev: Platform device registered |
0493e649 PC |
1032 | */ |
1033 | static int abx500_gpio_remove(struct platform_device *pdev) | |
1034 | { | |
1035 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
1036 | int ret; | |
1037 | ||
1038 | ret = gpiochip_remove(&pct->chip); | |
1039 | if (ret < 0) { | |
1040 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", | |
1041 | ret); | |
1042 | return ret; | |
1043 | } | |
1044 | ||
0493e649 PC |
1045 | return 0; |
1046 | } | |
1047 | ||
1048 | static const struct platform_device_id abx500_pinctrl_id[] = { | |
1049 | { "pinctrl-ab8500", PINCTRL_AB8500 }, | |
1050 | { "pinctrl-ab8540", PINCTRL_AB8540 }, | |
1051 | { "pinctrl-ab9540", PINCTRL_AB9540 }, | |
1052 | { "pinctrl-ab8505", PINCTRL_AB8505 }, | |
1053 | { }, | |
1054 | }; | |
1055 | ||
1056 | static struct platform_driver abx500_gpio_driver = { | |
1057 | .driver = { | |
1058 | .name = "abx500-gpio", | |
1059 | .owner = THIS_MODULE, | |
f30a3839 | 1060 | .of_match_table = abx500_gpio_match, |
0493e649 PC |
1061 | }, |
1062 | .probe = abx500_gpio_probe, | |
1063 | .remove = abx500_gpio_remove, | |
1064 | .id_table = abx500_pinctrl_id, | |
1065 | }; | |
1066 | ||
1067 | static int __init abx500_gpio_init(void) | |
1068 | { | |
1069 | return platform_driver_register(&abx500_gpio_driver); | |
1070 | } | |
1071 | core_initcall(abx500_gpio_init); | |
1072 | ||
1073 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1074 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1075 | MODULE_ALIAS("platform:abx500-gpio"); | |
1076 | MODULE_LICENSE("GPL v2"); |