projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings
[deliverable/linux.git] / drivers / pinctrl / pinctrl-at91-pio4.c
CommitLineData
77618084
LD		 1/*
2 * Driver for the Atmel PIO4 controller
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/gpio.h>
de4e882f 19#include <linux/interrupt.h>
77618084
LD		 20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/slab.h>
29#include "core.h"
30#include "pinconf.h"
31#include "pinctrl-utils.h"
32
33/*
34 * Warning:
35 * In order to not introduce confusion between Atmel PIO groups and pinctrl
36 * framework groups, Atmel PIO groups will be called banks, line is kept to
37 * designed the pin id into this bank.
38 */
39
40#define ATMEL_PIO_MSKR 0x0000
41#define ATMEL_PIO_CFGR 0x0004
42#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
43#define ATMEL_PIO_DIR_MASK BIT(8)
44#define ATMEL_PIO_PUEN_MASK BIT(9)
45#define ATMEL_PIO_PDEN_MASK BIT(10)
46#define ATMEL_PIO_IFEN_MASK BIT(12)
47#define ATMEL_PIO_IFSCEN_MASK BIT(13)
48#define ATMEL_PIO_OPD_MASK BIT(14)
49#define ATMEL_PIO_SCHMITT_MASK BIT(15)
50#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
51#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
52#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
53#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
54#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
55#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
56#define ATMEL_PIO_PDSR 0x0008
57#define ATMEL_PIO_LOCKSR 0x000C
58#define ATMEL_PIO_SODR 0x0010
59#define ATMEL_PIO_CODR 0x0014
60#define ATMEL_PIO_ODSR 0x0018
61#define ATMEL_PIO_IER 0x0020
62#define ATMEL_PIO_IDR 0x0024
63#define ATMEL_PIO_IMR 0x0028
64#define ATMEL_PIO_ISR 0x002C
65#define ATMEL_PIO_IOFR 0x003C
66
67#define ATMEL_PIO_NPINS_PER_BANK 32
68#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
69#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
70#define ATMEL_PIO_BANK_OFFSET 0x40
71
72#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
73#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
74#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
75
76struct atmel_pioctrl_data {
77 unsigned nbanks;
78};
79
80struct atmel_group {
81 const char *name;
82 u32 pin;
83};
84
85struct atmel_pin {
86 unsigned pin_id;
87 unsigned mux;
88 unsigned ioset;
89 unsigned bank;
90 unsigned line;
91 const char *device;
92};
93
94/**
95 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
96 * @reg_base: base address of the controller.
97 * @clk: clock of the controller.
98 * @nbanks: number of PIO groups, it can vary depending on the SoC.
99 * @pinctrl_dev: pinctrl device registered.
100 * @groups: groups table to provide group name and pin in the group to pinctrl.
101 * @group_names: group names table to provide all the group/pin names to
102 * pinctrl or gpio.
103 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
104 * fields are set at probe time. Other ones are set when parsing dt
105 * pinctrl.
106 * @npins: number of pins.
107 * @gpio_chip: gpio chip registered.
108 * @irq_domain: irq domain for the gpio controller.
109 * @irqs: table containing the hw irq number of the bank. The index of the
110 * table is the bank id.
111 * @dev: device entry for the Atmel PIO controller.
112 * @node: node of the Atmel PIO controller.
113 */
114struct atmel_pioctrl {
115 void __iomem *reg_base;
116 struct clk *clk;
117 unsigned nbanks;
118 struct pinctrl_dev *pinctrl_dev;
119 struct atmel_group *groups;
120 const char * const *group_names;
121 struct atmel_pin **pins;
122 unsigned npins;
123 struct gpio_chip *gpio_chip;
124 struct irq_domain *irq_domain;
125 int *irqs;
de4e882f
LD		 126 unsigned *pm_wakeup_sources;
127 unsigned *pm_suspend_backup;
77618084
LD		 128 struct device *dev;
129 struct device_node *node;
130};
131
132static const char * const atmel_functions[] = {
133 "GPIO", "A", "B", "C", "D", "E", "F", "G"
134};
135
136/* --- GPIO --- */
137static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
138 unsigned int bank, unsigned int reg)
139{
140 return readl_relaxed(atmel_pioctrl->reg_base
141 + ATMEL_PIO_BANK_OFFSET * bank + reg);
142}
143
144static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
145 unsigned int bank, unsigned int reg,
146 unsigned int val)
147{
148 writel_relaxed(val, atmel_pioctrl->reg_base
149 + ATMEL_PIO_BANK_OFFSET * bank + reg);
150}
151
152static void atmel_gpio_irq_ack(struct irq_data *d)
153{
154 /*
155 * Nothing to do, interrupt is cleared when reading the status
156 * register.
157 */
158}
159
160static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
161{
162 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
163 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
164 unsigned reg;
165
166 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
167 BIT(pin->line));
168 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
169 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
170
171 switch (type) {
172 case IRQ_TYPE_EDGE_RISING:
173 __irq_set_handler_locked(d->irq, handle_edge_irq);
174 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
175 break;
176 case IRQ_TYPE_EDGE_FALLING:
177 __irq_set_handler_locked(d->irq, handle_edge_irq);
178 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
179 break;
180 case IRQ_TYPE_EDGE_BOTH:
181 __irq_set_handler_locked(d->irq, handle_edge_irq);
182 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
183 break;
184 case IRQ_TYPE_LEVEL_LOW:
185 __irq_set_handler_locked(d->irq, handle_level_irq);
186 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
187 break;
188 case IRQ_TYPE_LEVEL_HIGH:
189 __irq_set_handler_locked(d->irq, handle_level_irq);
190 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
191 break;
192 case IRQ_TYPE_NONE:
193 default:
194 return -EINVAL;
195 }
196
197 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
198
199 return 0;
200}
201
202static void atmel_gpio_irq_mask(struct irq_data *d)
203{
204 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
205 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
206
207 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
208 BIT(pin->line));
209}
210
211static void atmel_gpio_irq_unmask(struct irq_data *d)
212{
213 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
214 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
215
216 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
217 BIT(pin->line));
218}
219
de4e882f
LD		 220#ifdef CONFIG_PM_SLEEP
221
222static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
223{
224 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
225 int bank = ATMEL_PIO_BANK(d->hwirq);
226 int line = ATMEL_PIO_LINE(d->hwirq);
227
228 /* The gpio controller has one interrupt line per bank. */
229 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
230
231 if (on)
232 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
233 else
234 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
235
236 return 0;
237}
238#else
239#define atmel_gpio_irq_set_wake NULL
240#endif /* CONFIG_PM_SLEEP */
241
77618084
LD		 242static struct irq_chip atmel_gpio_irq_chip = {
243 .name = "GPIO",
244 .irq_ack = atmel_gpio_irq_ack,
245 .irq_mask = atmel_gpio_irq_mask,
246 .irq_unmask = atmel_gpio_irq_unmask,
247 .irq_set_type = atmel_gpio_irq_set_type,
de4e882f 248 .irq_set_wake = atmel_gpio_irq_set_wake,
77618084
LD		 249};
250
251static void atmel_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
252{
253 struct atmel_pioctrl *atmel_pioctrl = irq_get_handler_data(irq);
254 struct irq_chip *chip = irq_desc_get_chip(desc);
255 unsigned long isr;
256 int n, bank = -1;
257
258 /* Find from which bank is the irq received. */
259 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
260 if (atmel_pioctrl->irqs[n] == irq) {
261 bank = n;
262 break;
263 }
264 }
265
266 if (bank < 0) {
267 dev_err(atmel_pioctrl->dev,
268 "no bank associated to irq %u\n", irq);
269 return;
270 }
271
272 chained_irq_enter(chip, desc);
273
274 for (;;) {
275 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
276 ATMEL_PIO_ISR);
277 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
278 ATMEL_PIO_IMR);
279 if (!isr)
280 break;
281
282 for_each_set_bit(n, &isr, BITS_PER_LONG)
283 generic_handle_irq(gpio_to_irq(bank *
284 ATMEL_PIO_NPINS_PER_BANK + n));
285 }
286
287 chained_irq_exit(chip, desc);
288}
289
290static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
291{
292 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
293 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
294 unsigned reg;
295
296 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
297 BIT(pin->line));
298 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
299 reg &= ~ATMEL_PIO_DIR_MASK;
300 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
301
302 return 0;
303}
304
305static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
306{
307 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
308 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
309 unsigned reg;
310
311 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
312
313 return !!(reg & BIT(pin->line));
314}
315
316static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
317 int value)
318{
319 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
320 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
321 unsigned reg;
322
323 atmel_gpio_write(atmel_pioctrl, pin->bank,
324 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
325 BIT(pin->line));
326
327 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
328 BIT(pin->line));
329 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
330 reg |= ATMEL_PIO_DIR_MASK;
331 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
332
333 return 0;
334}
335
336static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
337{
338 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
339 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
340
341 atmel_gpio_write(atmel_pioctrl, pin->bank,
342 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
343 BIT(pin->line));
344}
345
346static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
347{
348 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
349
350 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
351}
352
353static struct gpio_chip atmel_gpio_chip = {
354 .direction_input = atmel_gpio_direction_input,
355 .get = atmel_gpio_get,
356 .direction_output = atmel_gpio_direction_output,
357 .set = atmel_gpio_set,
358 .to_irq = atmel_gpio_to_irq,
359 .base = 0,
360};
361
362/* --- PINCTRL --- */
363static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
364 unsigned pin_id)
365{
366 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
367 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
368 unsigned line = atmel_pioctrl->pins[pin_id]->line;
369 void __iomem *addr = atmel_pioctrl->reg_base
370 + bank * ATMEL_PIO_BANK_OFFSET;
371
372 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
373 /* Have to set MSKR first, to access the right pin CFGR. */
374 wmb();
375
376 return readl_relaxed(addr + ATMEL_PIO_CFGR);
377}
378
379static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
380 unsigned pin_id, u32 conf)
381{
382 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
383 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
384 unsigned line = atmel_pioctrl->pins[pin_id]->line;
385 void __iomem *addr = atmel_pioctrl->reg_base
386 + bank * ATMEL_PIO_BANK_OFFSET;
387
388 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
389 /* Have to set MSKR first, to access the right pin CFGR. */
390 wmb();
391 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
392}
393
394static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
395{
396 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
397
398 return atmel_pioctrl->npins;
399}
400
401static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
402 unsigned selector)
403{
404 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
405
406 return atmel_pioctrl->groups[selector].name;
407}
408
409static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
410 unsigned selector, const unsigned **pins,
411 unsigned *num_pins)
412{
413 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
414
415 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
416 *num_pins = 1;
417
418 return 0;
419}
420
421struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev,
422 unsigned pin)
423{
424 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
425 int i;
426
427 for (i = 0; i < atmel_pioctrl->npins; i++) {
428 struct atmel_group *grp = atmel_pioctrl->groups + i;
429
430 if (grp->pin == pin)
431 return grp;
432 }
433
434 return NULL;
435}
436
437static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
438 struct device_node *np,
439 u32 pinfunc, const char **grp_name,
440 const char **func_name)
441{
442 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
443 unsigned pin_id, func_id;
444 struct atmel_group *grp;
445
446 pin_id = ATMEL_GET_PIN_NO(pinfunc);
447 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
448
449 if (func_id >= ARRAY_SIZE(atmel_functions))
450 return -EINVAL;
451
452 *func_name = atmel_functions[func_id];
453
454 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
455 if (!grp)
456 return -EINVAL;
457 *grp_name = grp->name;
458
459 atmel_pioctrl->pins[pin_id]->mux = func_id;
460 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
461 /* Want the device name not the group one. */
462 if (np->parent == atmel_pioctrl->node)
463 atmel_pioctrl->pins[pin_id]->device = np->name;
464 else
465 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
466
467 return 0;
468}
469
470static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
471 struct device_node *np,
472 struct pinctrl_map **map,
473 unsigned *reserved_maps,
474 unsigned *num_maps)
475{
476 unsigned num_pins, num_configs, reserve;
477 unsigned long *configs;
478 struct property *pins;
479 bool has_config;
480 u32 pinfunc;
481 int ret, i;
482
483 pins = of_find_property(np, "pinmux", NULL);
484 if (!pins)
485 return -EINVAL;
486
487 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
488 &num_configs);
489 if (ret < 0) {
490 dev_err(pctldev->dev, "%s: could not parse node property\n",
491 of_node_full_name(np));
492 return ret;
493 }
494
495 if (num_configs)
496 has_config = true;
497
498 num_pins = pins->length / sizeof(u32);
499 if (!num_pins) {
500 dev_err(pctldev->dev, "no pins found in node %s\n",
501 of_node_full_name(np));
502 return -EINVAL;
503 }
504
505 /*
506 * Reserve maps, at least there is a mux map and an optional conf
507 * map for each pin.
508 */
509 reserve = 1;
510 if (has_config && num_pins >= 1)
511 reserve++;
512 reserve *= num_pins;
513 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
514 reserve);
515 if (ret < 0)
516 return ret;
517
518 for (i = 0; i < num_pins; i++) {
519 const char *group, *func;
520
521 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
522 if (ret)
523 return ret;
524
525 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
526 &func);
527 if (ret)
528 return ret;
529
530 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
531 group, func);
532
533 if (has_config) {
534 ret = pinctrl_utils_add_map_configs(pctldev, map,
535 reserved_maps, num_maps, group,
536 configs, num_configs,
537 PIN_MAP_TYPE_CONFIGS_GROUP);
538 if (ret < 0)
539 return ret;
540 }
541 }
542
543 return 0;
544}
545
546static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
547 struct device_node *np_config,
548 struct pinctrl_map **map,
549 unsigned *num_maps)
550{
551 struct device_node *np;
552 unsigned reserved_maps;
553 int ret;
554
555 *map = NULL;
556 *num_maps = 0;
557 reserved_maps = 0;
558
559 /*
560 * If all the pins of a device have the same configuration (or no one),
561 * it is useless to add a subnode, so directly parse node referenced by
562 * phandle.
563 */
564 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
565 &reserved_maps, num_maps);
566 if (ret) {
567 for_each_child_of_node(np_config, np) {
568 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
569 &reserved_maps, num_maps);
570 if (ret < 0)
571 break;
572 }
573 }
574
575 if (ret < 0) {
576 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
577 dev_err(pctldev->dev, "can't create maps for node %s\n",
578 np_config->full_name);
579 }
580
581 return ret;
582}
583
584static const struct pinctrl_ops atmel_pctlops = {
585 .get_groups_count = atmel_pctl_get_groups_count,
586 .get_group_name = atmel_pctl_get_group_name,
587 .get_group_pins = atmel_pctl_get_group_pins,
588 .dt_node_to_map = atmel_pctl_dt_node_to_map,
589 .dt_free_map = pinctrl_utils_dt_free_map,
590};
591
592static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
593{
594 return ARRAY_SIZE(atmel_functions);
595}
596
597static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
598 unsigned selector)
599{
600 return atmel_functions[selector];
601}
602
603static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
604 unsigned selector,
605 const char * const **groups,
606 unsigned * const num_groups)
607{
608 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
609
610 *groups = atmel_pioctrl->group_names;
611 *num_groups = atmel_pioctrl->npins;
612
613 return 0;
614}
615
616static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
617 unsigned function,
618 unsigned group)
619{
620 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
621 unsigned pin;
622 u32 conf;
623
624 dev_dbg(pctldev->dev, "enable function %s group %s\n",
625 atmel_functions[function], atmel_pioctrl->groups[group].name);
626
627 pin = atmel_pioctrl->groups[group].pin;
628 conf = atmel_pin_config_read(pctldev, pin);
629 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
630 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
631 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
632 atmel_pin_config_write(pctldev, pin, conf);
633
634 return 0;
635}
636
637static const struct pinmux_ops atmel_pmxops = {
638 .get_functions_count = atmel_pmx_get_functions_count,
639 .get_function_name = atmel_pmx_get_function_name,
640 .get_function_groups = atmel_pmx_get_function_groups,
641 .set_mux = atmel_pmx_set_mux,
642};
643
644static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
645 unsigned group,
646 unsigned long *config)
647{
648 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
649 unsigned param = pinconf_to_config_param(*config), arg = 0;
650 struct atmel_group *grp = atmel_pioctrl->groups + group;
651 unsigned pin_id = grp->pin;
652 u32 res;
653
654 res = atmel_pin_config_read(pctldev, pin_id);
655
656 switch (param) {
657 case PIN_CONFIG_BIAS_PULL_UP:
658 if (!(res & ATMEL_PIO_PUEN_MASK))
659 return -EINVAL;
660 arg = 1;
661 break;
662 case PIN_CONFIG_BIAS_PULL_DOWN:
663 if ((res & ATMEL_PIO_PUEN_MASK) ||
664 (!(res & ATMEL_PIO_PDEN_MASK)))
665 return -EINVAL;
666 arg = 1;
667 break;
668 case PIN_CONFIG_BIAS_DISABLE:
669 if ((res & ATMEL_PIO_PUEN_MASK) ||
670 ((res & ATMEL_PIO_PDEN_MASK)))
671 return -EINVAL;
672 arg = 1;
673 break;
674 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
675 if (!(res & ATMEL_PIO_OPD_MASK))
676 return -EINVAL;
677 arg = 1;
678 break;
679 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
680 if (!(res & ATMEL_PIO_SCHMITT_MASK))
681 return -EINVAL;
682 arg = 1;
683 break;
684 default:
685 return -ENOTSUPP;
686 }
687
688 *config = pinconf_to_config_packed(param, arg);
689 return 0;
690}
691
692static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
693 unsigned group,
694 unsigned long *configs,
695 unsigned num_configs)
696{
697 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
698 struct atmel_group *grp = atmel_pioctrl->groups + group;
699 unsigned bank, pin, pin_id = grp->pin;
700 u32 mask, conf = 0;
701 int i;
702
703 conf = atmel_pin_config_read(pctldev, pin_id);
704
705 for (i = 0; i < num_configs; i++) {
706 unsigned param = pinconf_to_config_param(configs[i]);
707 unsigned arg = pinconf_to_config_argument(configs[i]);
708
709 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
710 __func__, pin_id, configs[i]);
711
712 switch (param) {
713 case PIN_CONFIG_BIAS_DISABLE:
714 conf &= (~ATMEL_PIO_PUEN_MASK);
715 conf &= (~ATMEL_PIO_PDEN_MASK);
716 break;
717 case PIN_CONFIG_BIAS_PULL_UP:
718 conf |= ATMEL_PIO_PUEN_MASK;
719 break;
720 case PIN_CONFIG_BIAS_PULL_DOWN:
721 conf |= ATMEL_PIO_PDEN_MASK;
722 break;
723 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
724 if (arg == 0)
725 conf &= (~ATMEL_PIO_OPD_MASK);
726 else
727 conf |= ATMEL_PIO_OPD_MASK;
728 break;
729 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
730 if (arg == 0)
731 conf |= ATMEL_PIO_SCHMITT_MASK;
732 else
733 conf &= (~ATMEL_PIO_SCHMITT_MASK);
734 break;
735 case PIN_CONFIG_INPUT_DEBOUNCE:
736 if (arg == 0) {
737 conf &= (~ATMEL_PIO_IFEN_MASK);
738 conf &= (~ATMEL_PIO_IFSCEN_MASK);
739 } else {
740 /*
741 * We don't care about the debounce value for several reasons:
742 * - can't have different debounce periods inside a same group,
743 * - the register to configure this period is a secure register.
744 * The debouncing filter can filter a pulse with a duration of less
745 * than 1/2 slow clock period.
746 */
747 conf |= ATMEL_PIO_IFEN_MASK;
748 conf |= ATMEL_PIO_IFSCEN_MASK;
749 }
750 break;
751 case PIN_CONFIG_OUTPUT:
752 conf |= ATMEL_PIO_DIR_MASK;
753 bank = ATMEL_PIO_BANK(pin_id);
754 pin = ATMEL_PIO_LINE(pin_id);
755 mask = 1 << pin;
756
757 if (arg == 0) {
758 writel_relaxed(mask, atmel_pioctrl->reg_base +
759 bank * ATMEL_PIO_BANK_OFFSET +
760 ATMEL_PIO_CODR);
761 } else {
762 writel_relaxed(mask, atmel_pioctrl->reg_base +
763 bank * ATMEL_PIO_BANK_OFFSET +
764 ATMEL_PIO_SODR);
765 }
766 break;
767 default:
768 dev_warn(pctldev->dev,
769 "unsupported configuration parameter: %u\n",
770 param);
771 continue;
772 }
773 }
774
775 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
776 atmel_pin_config_write(pctldev, pin_id, conf);
777
778 return 0;
779}
780
781static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
782 struct seq_file *s, unsigned pin_id)
783{
784 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
785 u32 conf;
786
787 if (!atmel_pioctrl->pins[pin_id]->device)
788 return;
789
790 if (atmel_pioctrl->pins[pin_id])
791 seq_printf(s, " (%s, ioset %u) ",
792 atmel_pioctrl->pins[pin_id]->device,
793 atmel_pioctrl->pins[pin_id]->ioset);
794
795 conf = atmel_pin_config_read(pctldev, pin_id);
796 if (conf & ATMEL_PIO_PUEN_MASK)
797 seq_printf(s, "%s ", "pull-up");
798 if (conf & ATMEL_PIO_PDEN_MASK)
799 seq_printf(s, "%s ", "pull-down");
800 if (conf & ATMEL_PIO_IFEN_MASK)
801 seq_printf(s, "%s ", "debounce");
802 if (conf & ATMEL_PIO_OPD_MASK)
803 seq_printf(s, "%s ", "open-drain");
804 if (conf & ATMEL_PIO_SCHMITT_MASK)
805 seq_printf(s, "%s ", "schmitt");
806}
807
808static const struct pinconf_ops atmel_confops = {
809 .pin_config_group_get = atmel_conf_pin_config_group_get,
810 .pin_config_group_set = atmel_conf_pin_config_group_set,
811 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
812};
813
814static struct pinctrl_desc atmel_pinctrl_desc = {
815 .name = "atmel_pinctrl",
816 .confops = &atmel_confops,
817 .pctlops = &atmel_pctlops,
818 .pmxops = &atmel_pmxops,
819};
820
de4e882f
LD		 821static int atmel_pctrl_suspend(struct device *dev)
822{
823 struct platform_device *pdev = to_platform_device(dev);
824 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
825 int i;
826
827 /*
828 * For each bank, save IMR to restore it later and disable all GPIO
829 * interrupts excepting the ones marked as wakeup sources.
830 */
831 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
832 atmel_pioctrl->pm_suspend_backup[i] =
833 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
834 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
835 ~atmel_pioctrl->pm_wakeup_sources[i]);
836 }
837
838 return 0;
839}
840
841static int atmel_pctrl_resume(struct device *dev)
842{
843 struct platform_device *pdev = to_platform_device(dev);
844 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
845 int i;
846
847 for (i = 0; i < atmel_pioctrl->nbanks; i++)
848 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
849 atmel_pioctrl->pm_suspend_backup[i]);
850
851 return 0;
852}
853
854static const struct dev_pm_ops atmel_pctrl_pm_ops = {
855 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
856};
857
77618084
LD		 858/*
859 * The number of banks can be different from a SoC to another one.
860 * We can have up to 16 banks.
861 */
862static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
863 .nbanks = 4,
864};
865
866static const struct of_device_id atmel_pctrl_of_match[] = {
867 {
868 .compatible = "atmel,sama5d2-pinctrl",
869 .data = &atmel_sama5d2_pioctrl_data,
870 }, {
871 /* sentinel */
872 }
873};
874MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match);
875
876static int atmel_pinctrl_probe(struct platform_device *pdev)
877{
878 struct device *dev = &pdev->dev;
879 struct pinctrl_pin_desc *pin_desc;
880 const char **group_names;
881 const struct of_device_id *match;
882 int i, ret;
883 struct resource *res;
884 struct atmel_pioctrl *atmel_pioctrl;
885 struct atmel_pioctrl_data *atmel_pioctrl_data;
886
887 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
888 if (!atmel_pioctrl)
889 return -ENOMEM;
890 atmel_pioctrl->dev = dev;
891 atmel_pioctrl->node = dev->of_node;
892 platform_set_drvdata(pdev, atmel_pioctrl);
893
894 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
895 if (!match) {
896 dev_err(dev, "unknown compatible string\n");
897 return -ENODEV;
898 }
899 atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data;
900 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
901 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
902
903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
904 if (!res) {
905 dev_err(dev, "unable to get atmel pinctrl resource\n");
906 return -EINVAL;
907 }
908 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
909 if (IS_ERR(atmel_pioctrl->reg_base))
910 return -EINVAL;
911
912 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
913 if (IS_ERR(atmel_pioctrl->clk)) {
914 dev_err(dev, "failed to get clock\n");
915 return PTR_ERR(atmel_pioctrl->clk);
916 }
917
918 atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins)
919 * atmel_pioctrl->npins, GFP_KERNEL);
920 if (!atmel_pioctrl->pins)
921 return -ENOMEM;
922
923 pin_desc = devm_kzalloc(dev, sizeof(*pin_desc)
924 * atmel_pioctrl->npins, GFP_KERNEL);
925 if (!pin_desc)
926 return -ENOMEM;
927 atmel_pinctrl_desc.pins = pin_desc;
928 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
929
930 /* One pin is one group since a pin can achieve all functions. */
931 group_names = devm_kzalloc(dev, sizeof(*group_names)
932 * atmel_pioctrl->npins, GFP_KERNEL);
933 if (!group_names)
934 return -ENOMEM;
935 atmel_pioctrl->group_names = group_names;
936
937 atmel_pioctrl->groups = devm_kzalloc(&pdev->dev,
938 sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins,
939 GFP_KERNEL);
940 if (!atmel_pioctrl->groups)
941 return -ENOMEM;
942 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
943 struct atmel_group *group = atmel_pioctrl->groups + i;
944 unsigned bank = ATMEL_PIO_BANK(i);
945 unsigned line = ATMEL_PIO_LINE(i);
946
947 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
948 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
949 if (!atmel_pioctrl->pins[i])
950 return -ENOMEM;
951
952 atmel_pioctrl->pins[i]->pin_id = i;
953 atmel_pioctrl->pins[i]->bank = bank;
954 atmel_pioctrl->pins[i]->line = line;
955
956 pin_desc[i].number = i;
957 /* Pin naming convention: P(bank_name)(bank_pin_number). */
958 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
959 bank + 'A', line);
960
961 group->name = group_names[i] = pin_desc[i].name;
962 group->pin = pin_desc[i].number;
963
964 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
965 }
966
967 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
968 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
969 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
970 atmel_pioctrl->gpio_chip->label = dev_name(dev);
971 atmel_pioctrl->gpio_chip->dev = dev;
972 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
973
de4e882f
LD		 974 atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev,
975 sizeof(*atmel_pioctrl->pm_wakeup_sources)
976 * atmel_pioctrl->nbanks, GFP_KERNEL);
977 if (!atmel_pioctrl->pm_wakeup_sources)
978 return -ENOMEM;
979
980 atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev,
981 sizeof(*atmel_pioctrl->pm_suspend_backup)
982 * atmel_pioctrl->nbanks, GFP_KERNEL);
983 if (!atmel_pioctrl->pm_suspend_backup)
984 return -ENOMEM;
985
77618084
LD		 986 atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs)
987 * atmel_pioctrl->nbanks, GFP_KERNEL);
988 if (!atmel_pioctrl->irqs)
989 return -ENOMEM;
990
991 /* There is one controller but each bank has its own irq line. */
992 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
993 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
994 if (!res) {
995 dev_err(dev, "missing irq resource for group %c\n",
996 'A' + i);
997 return -EINVAL;
998 }
999 atmel_pioctrl->irqs[i] = res->start;
1000 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1001 irq_set_handler_data(res->start, atmel_pioctrl);
1002 dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
1003 }
1004
1005 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1006 atmel_pioctrl->gpio_chip->ngpio,
1007 &irq_domain_simple_ops, NULL);
1008 if (!atmel_pioctrl->irq_domain) {
1009 dev_err(dev, "can't add the irq domain\n");
1010 return -ENODEV;
1011 }
1012 atmel_pioctrl->irq_domain->name = "atmel gpio";
1013
1014 for (i = 0; i < atmel_pioctrl->npins; i++) {
1015 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1016
1017 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1018 handle_simple_irq);
1019 irq_set_chip_data(irq, atmel_pioctrl);
1020 dev_dbg(dev,
1021 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1022 i, irq);
1023 }
1024
1025 ret = clk_prepare_enable(atmel_pioctrl->clk);
1026 if (ret) {
1027 dev_err(dev, "failed to prepare and enable clock\n");
1028 goto clk_prepare_enable_error;
1029 }
1030
1031 atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc,
1032 &pdev->dev,
1033 atmel_pioctrl);
1034 if (!atmel_pioctrl->pinctrl_dev) {
1035 dev_err(dev, "pinctrl registration failed\n");
1036 goto pinctrl_register_error;
1037 }
1038
1039 ret = gpiochip_add(atmel_pioctrl->gpio_chip);
1040 if (ret) {
1041 dev_err(dev, "failed to add gpiochip\n");
1042 goto gpiochip_add_error;
1043 }
1044
1045 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1046 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1047 if (ret) {
1048 dev_err(dev, "failed to add gpio pin range\n");
1049 goto gpiochip_add_pin_range_error;
1050 }
1051
1052 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1053
1054 return 0;
1055
1056clk_prepare_enable_error:
1057 irq_domain_remove(atmel_pioctrl->irq_domain);
1058pinctrl_register_error:
1059 clk_disable_unprepare(atmel_pioctrl->clk);
1060gpiochip_add_error:
1061 pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1062gpiochip_add_pin_range_error:
1063 gpiochip_remove(atmel_pioctrl->gpio_chip);
1064
1065 return ret;
1066}
1067
1068int atmel_pinctrl_remove(struct platform_device *pdev)
1069{
1070 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
1071
1072 irq_domain_remove(atmel_pioctrl->irq_domain);
1073 clk_disable_unprepare(atmel_pioctrl->clk);
1074 pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1075 gpiochip_remove(atmel_pioctrl->gpio_chip);
1076
1077 return 0;
1078}
1079
1080static struct platform_driver atmel_pinctrl_driver = {
1081 .driver = {
1082 .name = "pinctrl-at91-pio4",
1083 .of_match_table = atmel_pctrl_of_match,
de4e882f 1084 .pm = &atmel_pctrl_pm_ops,
77618084
LD		 1085 },
1086 .probe = atmel_pinctrl_probe,
1087 .remove = atmel_pinctrl_remove,
1088};
1089module_platform_driver(atmel_pinctrl_driver);
1090
1091MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>);
1092MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver");
1093MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.063772 seconds and 5 git commands to generate.