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6732ae5c JCPV |
1 | /* |
2 | * at91 pinctrl driver based on at91 pinmux core | |
3 | * | |
4 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
6732ae5c JCPV |
19 | #include <linux/io.h> |
20 | #include <linux/gpio.h> | |
6732ae5c JCPV |
21 | #include <linux/pinctrl/machine.h> |
22 | #include <linux/pinctrl/pinconf.h> | |
23 | #include <linux/pinctrl/pinctrl.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | /* Since we request GPIOs from ourself */ | |
26 | #include <linux/pinctrl/consumer.h> | |
27 | ||
c654b6bf | 28 | #include "pinctrl-at91.h" |
6732ae5c JCPV |
29 | #include "core.h" |
30 | ||
94daf85e | 31 | #define MAX_GPIO_BANKS 5 |
6732ae5c JCPV |
32 | #define MAX_NB_GPIO_PER_BANK 32 |
33 | ||
34 | struct at91_pinctrl_mux_ops; | |
35 | ||
36 | struct at91_gpio_chip { | |
37 | struct gpio_chip chip; | |
38 | struct pinctrl_gpio_range range; | |
39 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
40 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
41 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
42 | int pioc_idx; /* PIO bank index */ | |
43 | void __iomem *regbase; /* PIO bank virtual address */ | |
44 | struct clk *clock; /* associated clock */ | |
6732ae5c JCPV |
45 | struct at91_pinctrl_mux_ops *ops; /* ops */ |
46 | }; | |
47 | ||
6732ae5c JCPV |
48 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; |
49 | ||
50 | static int gpio_banks; | |
51 | ||
525fae21 | 52 | #define PULL_UP (1 << 0) |
6732ae5c | 53 | #define MULTI_DRIVE (1 << 1) |
7ebd7a3a JCPV |
54 | #define DEGLITCH (1 << 2) |
55 | #define PULL_DOWN (1 << 3) | |
56 | #define DIS_SCHMIT (1 << 4) | |
4334ac2d MR |
57 | #define DRIVE_STRENGTH_SHIFT 5 |
58 | #define DRIVE_STRENGTH_MASK 0x3 | |
59 | #define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT) | |
7ebd7a3a JCPV |
60 | #define DEBOUNCE (1 << 16) |
61 | #define DEBOUNCE_VAL_SHIFT 17 | |
62 | #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) | |
6732ae5c | 63 | |
4334ac2d MR |
64 | /** |
65 | * These defines will translated the dt binding settings to our internal | |
66 | * settings. They are not necessarily the same value as the register setting. | |
67 | * The actual drive strength current of low, medium and high must be looked up | |
68 | * from the corresponding device datasheet. This value is different for pins | |
69 | * that are even in the same banks. It is also dependent on VCC. | |
70 | * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive | |
71 | * strength when there is no dt config for it. | |
72 | */ | |
73 | #define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT) | |
74 | #define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT) | |
75 | #define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT) | |
76 | #define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT) | |
77 | ||
6732ae5c JCPV |
78 | /** |
79 | * struct at91_pmx_func - describes AT91 pinmux functions | |
80 | * @name: the name of this specific function | |
81 | * @groups: corresponding pin groups | |
82 | * @ngroups: the number of groups | |
83 | */ | |
84 | struct at91_pmx_func { | |
85 | const char *name; | |
86 | const char **groups; | |
87 | unsigned ngroups; | |
88 | }; | |
89 | ||
90 | enum at91_mux { | |
91 | AT91_MUX_GPIO = 0, | |
92 | AT91_MUX_PERIPH_A = 1, | |
93 | AT91_MUX_PERIPH_B = 2, | |
94 | AT91_MUX_PERIPH_C = 3, | |
95 | AT91_MUX_PERIPH_D = 4, | |
96 | }; | |
97 | ||
98 | /** | |
99 | * struct at91_pmx_pin - describes an At91 pin mux | |
100 | * @bank: the bank of the pin | |
101 | * @pin: the pin number in the @bank | |
102 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
103 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
104 | */ | |
105 | struct at91_pmx_pin { | |
106 | uint32_t bank; | |
107 | uint32_t pin; | |
108 | enum at91_mux mux; | |
109 | unsigned long conf; | |
110 | }; | |
111 | ||
112 | /** | |
113 | * struct at91_pin_group - describes an At91 pin group | |
114 | * @name: the name of this specific pin group | |
115 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
116 | * array is the same as pins. | |
117 | * @pins: an array of discrete physical pins used in this group, taken | |
118 | * from the driver-local pin enumeration space | |
119 | * @npins: the number of pins in this group array, i.e. the number of | |
120 | * elements in .pins so we can iterate over that array | |
121 | */ | |
122 | struct at91_pin_group { | |
123 | const char *name; | |
124 | struct at91_pmx_pin *pins_conf; | |
125 | unsigned int *pins; | |
126 | unsigned npins; | |
127 | }; | |
128 | ||
129 | /** | |
c2eb9e7f | 130 | * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group |
6732ae5c JCPV |
131 | * on new IP with support for periph C and D the way to mux in |
132 | * periph A and B has changed | |
133 | * So provide the right call back | |
134 | * if not present means the IP does not support it | |
135 | * @get_periph: return the periph mode configured | |
136 | * @mux_A_periph: mux as periph A | |
137 | * @mux_B_periph: mux as periph B | |
138 | * @mux_C_periph: mux as periph C | |
139 | * @mux_D_periph: mux as periph D | |
7ebd7a3a JCPV |
140 | * @get_deglitch: get deglitch status |
141 | * @set_deglitch: enable/disable deglitch | |
142 | * @get_debounce: get debounce status | |
143 | * @set_debounce: enable/disable debounce | |
144 | * @get_pulldown: get pulldown status | |
145 | * @set_pulldown: enable/disable pulldown | |
146 | * @get_schmitt_trig: get schmitt trigger status | |
147 | * @disable_schmitt_trig: disable schmitt trigger | |
6732ae5c JCPV |
148 | * @irq_type: return irq type |
149 | */ | |
150 | struct at91_pinctrl_mux_ops { | |
151 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
152 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
153 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
154 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
155 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
7ebd7a3a | 156 | bool (*get_deglitch)(void __iomem *pio, unsigned pin); |
77966ad7 | 157 | void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a | 158 | bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); |
77966ad7 | 159 | void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); |
7ebd7a3a | 160 | bool (*get_pulldown)(void __iomem *pio, unsigned pin); |
77966ad7 | 161 | void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a JCPV |
162 | bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); |
163 | void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); | |
4334ac2d MR |
164 | unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin); |
165 | void (*set_drivestrength)(void __iomem *pio, unsigned pin, | |
166 | u32 strength); | |
6732ae5c JCPV |
167 | /* irq */ |
168 | int (*irq_type)(struct irq_data *d, unsigned type); | |
169 | }; | |
170 | ||
171 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
172 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
173 | ||
174 | struct at91_pinctrl { | |
175 | struct device *dev; | |
176 | struct pinctrl_dev *pctl; | |
177 | ||
a0b957f3 | 178 | int nactive_banks; |
6732ae5c JCPV |
179 | |
180 | uint32_t *mux_mask; | |
181 | int nmux; | |
182 | ||
183 | struct at91_pmx_func *functions; | |
184 | int nfunctions; | |
185 | ||
186 | struct at91_pin_group *groups; | |
187 | int ngroups; | |
188 | ||
189 | struct at91_pinctrl_mux_ops *ops; | |
190 | }; | |
191 | ||
192 | static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( | |
193 | const struct at91_pinctrl *info, | |
194 | const char *name) | |
195 | { | |
196 | const struct at91_pin_group *grp = NULL; | |
197 | int i; | |
198 | ||
199 | for (i = 0; i < info->ngroups; i++) { | |
200 | if (strcmp(info->groups[i].name, name)) | |
201 | continue; | |
202 | ||
203 | grp = &info->groups[i]; | |
204 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
205 | break; | |
206 | } | |
207 | ||
208 | return grp; | |
209 | } | |
210 | ||
211 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
212 | { | |
213 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
214 | ||
215 | return info->ngroups; | |
216 | } | |
217 | ||
218 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
219 | unsigned selector) | |
220 | { | |
221 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
222 | ||
223 | return info->groups[selector].name; | |
224 | } | |
225 | ||
226 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
227 | const unsigned **pins, | |
228 | unsigned *npins) | |
229 | { | |
230 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
231 | ||
232 | if (selector >= info->ngroups) | |
233 | return -EINVAL; | |
234 | ||
235 | *pins = info->groups[selector].pins; | |
236 | *npins = info->groups[selector].npins; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
241 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
242 | unsigned offset) | |
243 | { | |
244 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
245 | } | |
246 | ||
247 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
248 | struct device_node *np, | |
249 | struct pinctrl_map **map, unsigned *num_maps) | |
250 | { | |
251 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
252 | const struct at91_pin_group *grp; | |
253 | struct pinctrl_map *new_map; | |
254 | struct device_node *parent; | |
255 | int map_num = 1; | |
256 | int i; | |
6732ae5c JCPV |
257 | |
258 | /* | |
61e310a1 | 259 | * first find the group of this node and check if we need to create |
6732ae5c JCPV |
260 | * config maps for pins |
261 | */ | |
262 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
263 | if (!grp) { | |
264 | dev_err(info->dev, "unable to find group for node %s\n", | |
265 | np->name); | |
266 | return -EINVAL; | |
267 | } | |
268 | ||
269 | map_num += grp->npins; | |
270 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); | |
271 | if (!new_map) | |
272 | return -ENOMEM; | |
273 | ||
274 | *map = new_map; | |
275 | *num_maps = map_num; | |
276 | ||
277 | /* create mux map */ | |
278 | parent = of_get_parent(np); | |
279 | if (!parent) { | |
c62b2b34 | 280 | devm_kfree(pctldev->dev, new_map); |
6732ae5c JCPV |
281 | return -EINVAL; |
282 | } | |
283 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
284 | new_map[0].data.mux.function = parent->name; | |
285 | new_map[0].data.mux.group = np->name; | |
286 | of_node_put(parent); | |
287 | ||
288 | /* create config map */ | |
289 | new_map++; | |
290 | for (i = 0; i < grp->npins; i++) { | |
6732ae5c JCPV |
291 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
292 | new_map[i].data.configs.group_or_pin = | |
293 | pin_get_name(pctldev, grp->pins[i]); | |
294 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
295 | new_map[i].data.configs.num_configs = 1; | |
296 | } | |
297 | ||
298 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
299 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
305 | struct pinctrl_map *map, unsigned num_maps) | |
306 | { | |
307 | } | |
308 | ||
022ab148 | 309 | static const struct pinctrl_ops at91_pctrl_ops = { |
6732ae5c JCPV |
310 | .get_groups_count = at91_get_groups_count, |
311 | .get_group_name = at91_get_group_name, | |
312 | .get_group_pins = at91_get_group_pins, | |
313 | .pin_dbg_show = at91_pin_dbg_show, | |
314 | .dt_node_to_map = at91_dt_node_to_map, | |
315 | .dt_free_map = at91_dt_free_map, | |
316 | }; | |
317 | ||
3c93600d | 318 | static void __iomem *pin_to_controller(struct at91_pinctrl *info, |
6732ae5c JCPV |
319 | unsigned int bank) |
320 | { | |
1ab36387 DD |
321 | if (!gpio_chips[bank]) |
322 | return NULL; | |
323 | ||
6732ae5c JCPV |
324 | return gpio_chips[bank]->regbase; |
325 | } | |
326 | ||
327 | static inline int pin_to_bank(unsigned pin) | |
328 | { | |
329 | return pin /= MAX_NB_GPIO_PER_BANK; | |
330 | } | |
331 | ||
332 | static unsigned pin_to_mask(unsigned int pin) | |
333 | { | |
334 | return 1 << pin; | |
335 | } | |
336 | ||
4334ac2d MR |
337 | static unsigned two_bit_pin_value_shift_amount(unsigned int pin) |
338 | { | |
339 | /* return the shift value for a pin for "two bit" per pin registers, | |
340 | * i.e. drive strength */ | |
341 | return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) | |
342 | ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); | |
343 | } | |
344 | ||
345 | static unsigned sama5d3_get_drive_register(unsigned int pin) | |
346 | { | |
347 | /* drive strength is split between two registers | |
348 | * with two bits per pin */ | |
349 | return (pin >= MAX_NB_GPIO_PER_BANK/2) | |
350 | ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1; | |
351 | } | |
352 | ||
353 | static unsigned at91sam9x5_get_drive_register(unsigned int pin) | |
354 | { | |
355 | /* drive strength is split between two registers | |
356 | * with two bits per pin */ | |
357 | return (pin >= MAX_NB_GPIO_PER_BANK/2) | |
358 | ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1; | |
359 | } | |
360 | ||
6732ae5c JCPV |
361 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) |
362 | { | |
363 | writel_relaxed(mask, pio + PIO_IDR); | |
364 | } | |
365 | ||
366 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
367 | { | |
05d3534a | 368 | return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); |
6732ae5c JCPV |
369 | } |
370 | ||
371 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
372 | { | |
3d784273 WY |
373 | if (on) |
374 | writel_relaxed(mask, pio + PIO_PPDDR); | |
375 | ||
6732ae5c JCPV |
376 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); |
377 | } | |
378 | ||
379 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) | |
380 | { | |
381 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
382 | } | |
383 | ||
384 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
385 | { | |
386 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
387 | } | |
388 | ||
389 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
390 | { | |
391 | writel_relaxed(mask, pio + PIO_ASR); | |
392 | } | |
393 | ||
394 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
395 | { | |
396 | writel_relaxed(mask, pio + PIO_BSR); | |
397 | } | |
398 | ||
399 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
400 | { | |
401 | ||
402 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
403 | pio + PIO_ABCDSR1); | |
404 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
405 | pio + PIO_ABCDSR2); | |
406 | } | |
407 | ||
408 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
409 | { | |
410 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
411 | pio + PIO_ABCDSR1); | |
412 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
413 | pio + PIO_ABCDSR2); | |
414 | } | |
415 | ||
416 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
417 | { | |
418 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
419 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
420 | } | |
421 | ||
422 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
423 | { | |
424 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
425 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
426 | } | |
427 | ||
428 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
429 | { | |
430 | unsigned select; | |
431 | ||
432 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
433 | return AT91_MUX_GPIO; | |
434 | ||
435 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
436 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
437 | ||
438 | return select + 1; | |
439 | } | |
440 | ||
441 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
442 | { | |
443 | unsigned select; | |
444 | ||
445 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
446 | return AT91_MUX_GPIO; | |
447 | ||
448 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
449 | ||
450 | return select + 1; | |
451 | } | |
452 | ||
7ebd7a3a JCPV |
453 | static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) |
454 | { | |
d480239b | 455 | return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; |
7ebd7a3a JCPV |
456 | } |
457 | ||
458 | static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) | |
459 | { | |
d480239b | 460 | writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); |
7ebd7a3a JCPV |
461 | } |
462 | ||
c8dba02e BB |
463 | static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) |
464 | { | |
d480239b BD |
465 | if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) |
466 | return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); | |
c8dba02e BB |
467 | |
468 | return false; | |
469 | } | |
470 | ||
7ebd7a3a JCPV |
471 | static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
472 | { | |
473 | if (is_on) | |
d480239b | 474 | writel_relaxed(mask, pio + PIO_IFSCDR); |
7ebd7a3a JCPV |
475 | at91_mux_set_deglitch(pio, mask, is_on); |
476 | } | |
477 | ||
478 | static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) | |
479 | { | |
d480239b | 480 | *div = readl_relaxed(pio + PIO_SCDR); |
7ebd7a3a | 481 | |
d480239b BD |
482 | return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && |
483 | ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); | |
7ebd7a3a JCPV |
484 | } |
485 | ||
486 | static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, | |
487 | bool is_on, u32 div) | |
488 | { | |
489 | if (is_on) { | |
d480239b BD |
490 | writel_relaxed(mask, pio + PIO_IFSCER); |
491 | writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); | |
492 | writel_relaxed(mask, pio + PIO_IFER); | |
c8dba02e | 493 | } else |
d480239b | 494 | writel_relaxed(mask, pio + PIO_IFSCDR); |
7ebd7a3a JCPV |
495 | } |
496 | ||
497 | static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) | |
498 | { | |
d480239b | 499 | return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); |
7ebd7a3a JCPV |
500 | } |
501 | ||
502 | static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) | |
503 | { | |
3d784273 | 504 | if (is_on) |
d480239b | 505 | writel_relaxed(mask, pio + PIO_PUDR); |
3d784273 | 506 | |
d480239b | 507 | writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); |
7ebd7a3a JCPV |
508 | } |
509 | ||
510 | static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) | |
511 | { | |
d480239b | 512 | writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); |
7ebd7a3a JCPV |
513 | } |
514 | ||
515 | static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) | |
516 | { | |
d480239b | 517 | return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; |
7ebd7a3a JCPV |
518 | } |
519 | ||
4334ac2d MR |
520 | static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) |
521 | { | |
d480239b | 522 | unsigned tmp = readl_relaxed(reg); |
4334ac2d MR |
523 | |
524 | tmp = tmp >> two_bit_pin_value_shift_amount(pin); | |
525 | ||
526 | return tmp & DRIVE_STRENGTH_MASK; | |
527 | } | |
528 | ||
529 | static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, | |
530 | unsigned pin) | |
531 | { | |
532 | unsigned tmp = read_drive_strength(pio + | |
533 | sama5d3_get_drive_register(pin), pin); | |
534 | ||
535 | /* SAMA5 strength is 1:1 with our defines, | |
536 | * except 0 is equivalent to low per datasheet */ | |
537 | if (!tmp) | |
538 | tmp = DRIVE_STRENGTH_LOW; | |
539 | ||
540 | return tmp; | |
541 | } | |
542 | ||
543 | static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, | |
544 | unsigned pin) | |
545 | { | |
546 | unsigned tmp = read_drive_strength(pio + | |
547 | at91sam9x5_get_drive_register(pin), pin); | |
548 | ||
549 | /* strength is inverse in SAM9x5s hardware with the pinctrl defines | |
550 | * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */ | |
551 | tmp = DRIVE_STRENGTH_HI - tmp; | |
552 | ||
553 | return tmp; | |
554 | } | |
555 | ||
556 | static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) | |
557 | { | |
d480239b | 558 | unsigned tmp = readl_relaxed(reg); |
4334ac2d MR |
559 | unsigned shift = two_bit_pin_value_shift_amount(pin); |
560 | ||
561 | tmp &= ~(DRIVE_STRENGTH_MASK << shift); | |
562 | tmp |= strength << shift; | |
563 | ||
d480239b | 564 | writel_relaxed(tmp, reg); |
4334ac2d MR |
565 | } |
566 | ||
567 | static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, | |
568 | u32 setting) | |
569 | { | |
570 | /* do nothing if setting is zero */ | |
571 | if (!setting) | |
572 | return; | |
573 | ||
574 | /* strength is 1 to 1 with setting for SAMA5 */ | |
575 | set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); | |
576 | } | |
577 | ||
578 | static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, | |
579 | u32 setting) | |
580 | { | |
581 | /* do nothing if setting is zero */ | |
582 | if (!setting) | |
583 | return; | |
584 | ||
585 | /* strength is inverse on SAM9x5s with our defines | |
586 | * 0 = hi, 1 = med, 2 = low, 3 = rsvd */ | |
587 | setting = DRIVE_STRENGTH_HI - setting; | |
588 | ||
589 | set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, | |
590 | setting); | |
591 | } | |
592 | ||
6732ae5c JCPV |
593 | static struct at91_pinctrl_mux_ops at91rm9200_ops = { |
594 | .get_periph = at91_mux_get_periph, | |
595 | .mux_A_periph = at91_mux_set_A_periph, | |
596 | .mux_B_periph = at91_mux_set_B_periph, | |
7ebd7a3a JCPV |
597 | .get_deglitch = at91_mux_get_deglitch, |
598 | .set_deglitch = at91_mux_set_deglitch, | |
6732ae5c JCPV |
599 | .irq_type = gpio_irq_type, |
600 | }; | |
601 | ||
602 | static struct at91_pinctrl_mux_ops at91sam9x5_ops = { | |
603 | .get_periph = at91_mux_pio3_get_periph, | |
604 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
605 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
606 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
607 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
c8dba02e | 608 | .get_deglitch = at91_mux_pio3_get_deglitch, |
7ebd7a3a JCPV |
609 | .set_deglitch = at91_mux_pio3_set_deglitch, |
610 | .get_debounce = at91_mux_pio3_get_debounce, | |
611 | .set_debounce = at91_mux_pio3_set_debounce, | |
612 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
613 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
614 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
615 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
4334ac2d MR |
616 | .get_drivestrength = at91_mux_sam9x5_get_drivestrength, |
617 | .set_drivestrength = at91_mux_sam9x5_set_drivestrength, | |
618 | .irq_type = alt_gpio_irq_type, | |
619 | }; | |
620 | ||
621 | static struct at91_pinctrl_mux_ops sama5d3_ops = { | |
622 | .get_periph = at91_mux_pio3_get_periph, | |
623 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
624 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
625 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
626 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
627 | .get_deglitch = at91_mux_pio3_get_deglitch, | |
628 | .set_deglitch = at91_mux_pio3_set_deglitch, | |
629 | .get_debounce = at91_mux_pio3_get_debounce, | |
630 | .set_debounce = at91_mux_pio3_set_debounce, | |
631 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
632 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
633 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
634 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
635 | .get_drivestrength = at91_mux_sama5d3_get_drivestrength, | |
636 | .set_drivestrength = at91_mux_sama5d3_set_drivestrength, | |
6732ae5c JCPV |
637 | .irq_type = alt_gpio_irq_type, |
638 | }; | |
639 | ||
640 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
641 | { | |
642 | if (pin->mux) { | |
4b6fe45a | 643 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", |
6732ae5c JCPV |
644 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); |
645 | } else { | |
4b6fe45a | 646 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", |
6732ae5c JCPV |
647 | pin->bank + 'A', pin->pin, pin->conf); |
648 | } | |
649 | } | |
650 | ||
3c93600d | 651 | static int pin_check_config(struct at91_pinctrl *info, const char *name, |
6732ae5c JCPV |
652 | int index, const struct at91_pmx_pin *pin) |
653 | { | |
654 | int mux; | |
655 | ||
656 | /* check if it's a valid config */ | |
a0b957f3 | 657 | if (pin->bank >= gpio_banks) { |
6732ae5c | 658 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", |
a0b957f3 | 659 | name, index, pin->bank, gpio_banks); |
6732ae5c JCPV |
660 | return -EINVAL; |
661 | } | |
662 | ||
a0b957f3 JCPV |
663 | if (!gpio_chips[pin->bank]) { |
664 | dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", | |
665 | name, index, pin->bank); | |
666 | return -ENXIO; | |
667 | } | |
668 | ||
6732ae5c JCPV |
669 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { |
670 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
671 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
672 | return -EINVAL; | |
673 | } | |
674 | ||
675 | if (!pin->mux) | |
676 | return 0; | |
677 | ||
678 | mux = pin->mux - 1; | |
679 | ||
680 | if (mux >= info->nmux) { | |
681 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
682 | name, index, mux, info->nmux); | |
683 | return -EINVAL; | |
684 | } | |
685 | ||
686 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
687 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
688 | name, index, mux, pin->bank + 'A', pin->pin); | |
689 | return -EINVAL; | |
690 | } | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
696 | { | |
697 | writel_relaxed(mask, pio + PIO_PDR); | |
698 | } | |
699 | ||
700 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
701 | { | |
702 | writel_relaxed(mask, pio + PIO_PER); | |
703 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
704 | } | |
705 | ||
03e9f0ca LW |
706 | static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
707 | unsigned group) | |
6732ae5c JCPV |
708 | { |
709 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
710 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
711 | const struct at91_pmx_pin *pin; | |
712 | uint32_t npins = info->groups[group].npins; | |
713 | int i, ret; | |
714 | unsigned mask; | |
715 | void __iomem *pio; | |
716 | ||
717 | dev_dbg(info->dev, "enable function %s group %s\n", | |
718 | info->functions[selector].name, info->groups[group].name); | |
719 | ||
720 | /* first check that all the pins of the group are valid with a valid | |
61e310a1 | 721 | * parameter */ |
6732ae5c JCPV |
722 | for (i = 0; i < npins; i++) { |
723 | pin = &pins_conf[i]; | |
724 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
725 | if (ret) | |
726 | return ret; | |
727 | } | |
728 | ||
729 | for (i = 0; i < npins; i++) { | |
730 | pin = &pins_conf[i]; | |
731 | at91_pin_dbg(info->dev, pin); | |
732 | pio = pin_to_controller(info, pin->bank); | |
1ab36387 DD |
733 | |
734 | if (!pio) | |
735 | continue; | |
736 | ||
6732ae5c JCPV |
737 | mask = pin_to_mask(pin->pin); |
738 | at91_mux_disable_interrupt(pio, mask); | |
3c93600d | 739 | switch (pin->mux) { |
6732ae5c JCPV |
740 | case AT91_MUX_GPIO: |
741 | at91_mux_gpio_enable(pio, mask, 1); | |
742 | break; | |
743 | case AT91_MUX_PERIPH_A: | |
744 | info->ops->mux_A_periph(pio, mask); | |
745 | break; | |
746 | case AT91_MUX_PERIPH_B: | |
747 | info->ops->mux_B_periph(pio, mask); | |
748 | break; | |
749 | case AT91_MUX_PERIPH_C: | |
750 | if (!info->ops->mux_C_periph) | |
751 | return -EINVAL; | |
752 | info->ops->mux_C_periph(pio, mask); | |
753 | break; | |
754 | case AT91_MUX_PERIPH_D: | |
755 | if (!info->ops->mux_D_periph) | |
756 | return -EINVAL; | |
757 | info->ops->mux_D_periph(pio, mask); | |
758 | break; | |
759 | } | |
760 | if (pin->mux) | |
761 | at91_mux_gpio_disable(pio, mask); | |
762 | } | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
6732ae5c JCPV |
767 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
768 | { | |
769 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
770 | ||
771 | return info->nfunctions; | |
772 | } | |
773 | ||
774 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
775 | unsigned selector) | |
776 | { | |
777 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
778 | ||
779 | return info->functions[selector].name; | |
780 | } | |
781 | ||
782 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
783 | const char * const **groups, | |
784 | unsigned * const num_groups) | |
785 | { | |
786 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
787 | ||
788 | *groups = info->functions[selector].groups; | |
789 | *num_groups = info->functions[selector].ngroups; | |
790 | ||
791 | return 0; | |
792 | } | |
793 | ||
f6f94f66 AL |
794 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
795 | struct pinctrl_gpio_range *range, | |
796 | unsigned offset) | |
6732ae5c JCPV |
797 | { |
798 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
799 | struct at91_gpio_chip *at91_chip; | |
800 | struct gpio_chip *chip; | |
801 | unsigned mask; | |
802 | ||
803 | if (!range) { | |
804 | dev_err(npct->dev, "invalid range\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | if (!range->gc) { | |
808 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
809 | return -EINVAL; | |
810 | } | |
811 | chip = range->gc; | |
370ea611 | 812 | at91_chip = gpiochip_get_data(chip); |
6732ae5c JCPV |
813 | |
814 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
815 | ||
816 | mask = 1 << (offset - chip->base); | |
817 | ||
818 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
819 | offset, 'A' + range->id, offset - chip->base, mask); | |
820 | ||
821 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
f6f94f66 AL |
826 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
827 | struct pinctrl_gpio_range *range, | |
828 | unsigned offset) | |
6732ae5c JCPV |
829 | { |
830 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
831 | ||
832 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
833 | /* Set the pin to some default state, GPIO is usually default */ | |
834 | } | |
835 | ||
022ab148 | 836 | static const struct pinmux_ops at91_pmx_ops = { |
6732ae5c JCPV |
837 | .get_functions_count = at91_pmx_get_funcs_count, |
838 | .get_function_name = at91_pmx_get_func_name, | |
839 | .get_function_groups = at91_pmx_get_groups, | |
03e9f0ca | 840 | .set_mux = at91_pmx_set, |
6732ae5c JCPV |
841 | .gpio_request_enable = at91_gpio_request_enable, |
842 | .gpio_disable_free = at91_gpio_disable_free, | |
843 | }; | |
844 | ||
845 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
846 | unsigned pin_id, unsigned long *config) | |
847 | { | |
848 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
849 | void __iomem *pio; | |
850 | unsigned pin; | |
7ebd7a3a | 851 | int div; |
6732ae5c | 852 | |
1292e693 AB |
853 | *config = 0; |
854 | dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); | |
6732ae5c | 855 | pio = pin_to_controller(info, pin_to_bank(pin_id)); |
1ab36387 DD |
856 | |
857 | if (!pio) | |
858 | return -EINVAL; | |
859 | ||
6732ae5c JCPV |
860 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
861 | ||
862 | if (at91_mux_get_multidrive(pio, pin)) | |
863 | *config |= MULTI_DRIVE; | |
864 | ||
865 | if (at91_mux_get_pullup(pio, pin)) | |
866 | *config |= PULL_UP; | |
867 | ||
7ebd7a3a JCPV |
868 | if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) |
869 | *config |= DEGLITCH; | |
870 | if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) | |
871 | *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); | |
872 | if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) | |
873 | *config |= PULL_DOWN; | |
874 | if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) | |
875 | *config |= DIS_SCHMIT; | |
4334ac2d MR |
876 | if (info->ops->get_drivestrength) |
877 | *config |= (info->ops->get_drivestrength(pio, pin) | |
878 | << DRIVE_STRENGTH_SHIFT); | |
7ebd7a3a | 879 | |
6732ae5c JCPV |
880 | return 0; |
881 | } | |
882 | ||
883 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
884 | unsigned pin_id, unsigned long *configs, |
885 | unsigned num_configs) | |
6732ae5c JCPV |
886 | { |
887 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
888 | unsigned mask; | |
889 | void __iomem *pio; | |
03b054e9 SY |
890 | int i; |
891 | unsigned long config; | |
4334ac2d | 892 | unsigned pin; |
03b054e9 SY |
893 | |
894 | for (i = 0; i < num_configs; i++) { | |
895 | config = configs[i]; | |
896 | ||
897 | dev_dbg(info->dev, | |
898 | "%s:%d, pin_id=%d, config=0x%lx", | |
899 | __func__, __LINE__, pin_id, config); | |
900 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
1ab36387 DD |
901 | |
902 | if (!pio) | |
903 | return -EINVAL; | |
904 | ||
4334ac2d MR |
905 | pin = pin_id % MAX_NB_GPIO_PER_BANK; |
906 | mask = pin_to_mask(pin); | |
03b054e9 SY |
907 | |
908 | if (config & PULL_UP && config & PULL_DOWN) | |
909 | return -EINVAL; | |
910 | ||
911 | at91_mux_set_pullup(pio, mask, config & PULL_UP); | |
912 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
913 | if (info->ops->set_deglitch) | |
914 | info->ops->set_deglitch(pio, mask, config & DEGLITCH); | |
915 | if (info->ops->set_debounce) | |
916 | info->ops->set_debounce(pio, mask, config & DEBOUNCE, | |
7ebd7a3a | 917 | (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); |
03b054e9 SY |
918 | if (info->ops->set_pulldown) |
919 | info->ops->set_pulldown(pio, mask, config & PULL_DOWN); | |
920 | if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) | |
921 | info->ops->disable_schmitt_trig(pio, mask); | |
4334ac2d MR |
922 | if (info->ops->set_drivestrength) |
923 | info->ops->set_drivestrength(pio, pin, | |
924 | (config & DRIVE_STRENGTH) | |
925 | >> DRIVE_STRENGTH_SHIFT); | |
03b054e9 SY |
926 | |
927 | } /* for each config */ | |
7ebd7a3a | 928 | |
6732ae5c JCPV |
929 | return 0; |
930 | } | |
931 | ||
4d9b8a8e AB |
932 | #define DBG_SHOW_FLAG(flag) do { \ |
933 | if (config & flag) { \ | |
934 | if (num_conf) \ | |
935 | seq_puts(s, "|"); \ | |
936 | seq_puts(s, #flag); \ | |
937 | num_conf++; \ | |
938 | } \ | |
939 | } while (0) | |
940 | ||
4334ac2d MR |
941 | #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \ |
942 | if ((config & mask) == flag) { \ | |
943 | if (num_conf) \ | |
944 | seq_puts(s, "|"); \ | |
945 | seq_puts(s, #flag); \ | |
946 | num_conf++; \ | |
947 | } \ | |
948 | } while (0) | |
949 | ||
6732ae5c JCPV |
950 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
951 | struct seq_file *s, unsigned pin_id) | |
952 | { | |
4d9b8a8e | 953 | unsigned long config; |
445d2026 | 954 | int val, num_conf = 0; |
4d9b8a8e | 955 | |
445d2026 | 956 | at91_pinconf_get(pctldev, pin_id, &config); |
4d9b8a8e AB |
957 | |
958 | DBG_SHOW_FLAG(MULTI_DRIVE); | |
959 | DBG_SHOW_FLAG(PULL_UP); | |
960 | DBG_SHOW_FLAG(PULL_DOWN); | |
961 | DBG_SHOW_FLAG(DIS_SCHMIT); | |
962 | DBG_SHOW_FLAG(DEGLITCH); | |
4334ac2d MR |
963 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW); |
964 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED); | |
965 | DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI); | |
4d9b8a8e AB |
966 | DBG_SHOW_FLAG(DEBOUNCE); |
967 | if (config & DEBOUNCE) { | |
968 | val = config >> DEBOUNCE_VAL_SHIFT; | |
969 | seq_printf(s, "(%d)", val); | |
970 | } | |
6732ae5c | 971 | |
4d9b8a8e | 972 | return; |
6732ae5c JCPV |
973 | } |
974 | ||
975 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
976 | struct seq_file *s, unsigned group) | |
977 | { | |
978 | } | |
979 | ||
022ab148 | 980 | static const struct pinconf_ops at91_pinconf_ops = { |
6732ae5c JCPV |
981 | .pin_config_get = at91_pinconf_get, |
982 | .pin_config_set = at91_pinconf_set, | |
983 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
984 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
985 | }; | |
986 | ||
987 | static struct pinctrl_desc at91_pinctrl_desc = { | |
988 | .pctlops = &at91_pctrl_ops, | |
989 | .pmxops = &at91_pmx_ops, | |
990 | .confops = &at91_pinconf_ops, | |
991 | .owner = THIS_MODULE, | |
992 | }; | |
993 | ||
994 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
995 | ||
150632b0 GKH |
996 | static void at91_pinctrl_child_count(struct at91_pinctrl *info, |
997 | struct device_node *np) | |
6732ae5c JCPV |
998 | { |
999 | struct device_node *child; | |
1000 | ||
1001 | for_each_child_of_node(np, child) { | |
1002 | if (of_device_is_compatible(child, gpio_compat)) { | |
a0b957f3 JCPV |
1003 | if (of_device_is_available(child)) |
1004 | info->nactive_banks++; | |
6732ae5c JCPV |
1005 | } else { |
1006 | info->nfunctions++; | |
1007 | info->ngroups += of_get_child_count(child); | |
1008 | } | |
1009 | } | |
1010 | } | |
1011 | ||
150632b0 GKH |
1012 | static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, |
1013 | struct device_node *np) | |
6732ae5c JCPV |
1014 | { |
1015 | int ret = 0; | |
1016 | int size; | |
1164d73a | 1017 | const __be32 *list; |
6732ae5c JCPV |
1018 | |
1019 | list = of_get_property(np, "atmel,mux-mask", &size); | |
1020 | if (!list) { | |
1021 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
1025 | size /= sizeof(*list); | |
a0b957f3 JCPV |
1026 | if (!size || size % gpio_banks) { |
1027 | dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); | |
6732ae5c JCPV |
1028 | return -EINVAL; |
1029 | } | |
a0b957f3 | 1030 | info->nmux = size / gpio_banks; |
6732ae5c JCPV |
1031 | |
1032 | info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); | |
1033 | if (!info->mux_mask) { | |
1034 | dev_err(info->dev, "could not alloc mux_mask\n"); | |
1035 | return -ENOMEM; | |
1036 | } | |
1037 | ||
1038 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
1039 | info->mux_mask, size); | |
1040 | if (ret) | |
1041 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
1042 | return ret; | |
1043 | } | |
1044 | ||
150632b0 GKH |
1045 | static int at91_pinctrl_parse_groups(struct device_node *np, |
1046 | struct at91_pin_group *grp, | |
1047 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
1048 | { |
1049 | struct at91_pmx_pin *pin; | |
1050 | int size; | |
1164d73a | 1051 | const __be32 *list; |
6732ae5c JCPV |
1052 | int i, j; |
1053 | ||
1054 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
1055 | ||
1056 | /* Initialise group */ | |
1057 | grp->name = np->name; | |
1058 | ||
1059 | /* | |
1060 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
1061 | * do sanity check and calculate pins number | |
1062 | */ | |
1063 | list = of_get_property(np, "atmel,pins", &size); | |
1064 | /* we do not check return since it's safe node passed down */ | |
1065 | size /= sizeof(*list); | |
1066 | if (!size || size % 4) { | |
1067 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | grp->npins = size / 4; | |
1072 | pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), | |
1073 | GFP_KERNEL); | |
1074 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
1075 | GFP_KERNEL); | |
1076 | if (!grp->pins_conf || !grp->pins) | |
1077 | return -ENOMEM; | |
1078 | ||
1079 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
1080 | pin->bank = be32_to_cpu(*list++); | |
1081 | pin->pin = be32_to_cpu(*list++); | |
1082 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
1083 | pin->mux = be32_to_cpu(*list++); | |
1084 | pin->conf = be32_to_cpu(*list++); | |
1085 | ||
1086 | at91_pin_dbg(info->dev, pin); | |
1087 | pin++; | |
1088 | } | |
1089 | ||
1090 | return 0; | |
1091 | } | |
1092 | ||
150632b0 GKH |
1093 | static int at91_pinctrl_parse_functions(struct device_node *np, |
1094 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
1095 | { |
1096 | struct device_node *child; | |
1097 | struct at91_pmx_func *func; | |
1098 | struct at91_pin_group *grp; | |
1099 | int ret; | |
1100 | static u32 grp_index; | |
1101 | u32 i = 0; | |
1102 | ||
1103 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
1104 | ||
1105 | func = &info->functions[index]; | |
1106 | ||
1107 | /* Initialise function */ | |
1108 | func->name = np->name; | |
1109 | func->ngroups = of_get_child_count(np); | |
ca7162ad | 1110 | if (func->ngroups == 0) { |
6732ae5c JCPV |
1111 | dev_err(info->dev, "no groups defined\n"); |
1112 | return -EINVAL; | |
1113 | } | |
1114 | func->groups = devm_kzalloc(info->dev, | |
1115 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1116 | if (!func->groups) | |
1117 | return -ENOMEM; | |
1118 | ||
1119 | for_each_child_of_node(np, child) { | |
1120 | func->groups[i] = child->name; | |
1121 | grp = &info->groups[grp_index++]; | |
1122 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
d94b986a JL |
1123 | if (ret) { |
1124 | of_node_put(child); | |
6732ae5c | 1125 | return ret; |
d94b986a | 1126 | } |
6732ae5c JCPV |
1127 | } |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
baa9946e | 1132 | static const struct of_device_id at91_pinctrl_of_match[] = { |
4334ac2d | 1133 | { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, |
6732ae5c JCPV |
1134 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, |
1135 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
1136 | { /* sentinel */ } | |
1137 | }; | |
1138 | ||
150632b0 GKH |
1139 | static int at91_pinctrl_probe_dt(struct platform_device *pdev, |
1140 | struct at91_pinctrl *info) | |
6732ae5c JCPV |
1141 | { |
1142 | int ret = 0; | |
1143 | int i, j; | |
1144 | uint32_t *tmp; | |
1145 | struct device_node *np = pdev->dev.of_node; | |
1146 | struct device_node *child; | |
1147 | ||
1148 | if (!np) | |
1149 | return -ENODEV; | |
1150 | ||
1151 | info->dev = &pdev->dev; | |
3c93600d | 1152 | info->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1153 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
1154 | at91_pinctrl_child_count(info, np); | |
1155 | ||
a0b957f3 | 1156 | if (gpio_banks < 1) { |
61e310a1 | 1157 | dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); |
6732ae5c JCPV |
1158 | return -EINVAL; |
1159 | } | |
1160 | ||
1161 | ret = at91_pinctrl_mux_mask(info, np); | |
1162 | if (ret) | |
1163 | return ret; | |
1164 | ||
1165 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
1166 | ||
1167 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
1168 | tmp = info->mux_mask; | |
a0b957f3 | 1169 | for (i = 0; i < gpio_banks; i++) { |
6732ae5c JCPV |
1170 | for (j = 0; j < info->nmux; j++, tmp++) { |
1171 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1176 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1177 | info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), | |
1178 | GFP_KERNEL); | |
1179 | if (!info->functions) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), | |
1183 | GFP_KERNEL); | |
1184 | if (!info->groups) | |
1185 | return -ENOMEM; | |
1186 | ||
a0b957f3 | 1187 | dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); |
6732ae5c JCPV |
1188 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); |
1189 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1190 | ||
1191 | i = 0; | |
1192 | ||
1193 | for_each_child_of_node(np, child) { | |
1194 | if (of_device_is_compatible(child, gpio_compat)) | |
1195 | continue; | |
1196 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
1197 | if (ret) { | |
1198 | dev_err(&pdev->dev, "failed to parse function\n"); | |
d94b986a | 1199 | of_node_put(child); |
6732ae5c JCPV |
1200 | return ret; |
1201 | } | |
1202 | } | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
150632b0 | 1207 | static int at91_pinctrl_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1208 | { |
1209 | struct at91_pinctrl *info; | |
1210 | struct pinctrl_pin_desc *pdesc; | |
a0b957f3 | 1211 | int ret, i, j, k, ngpio_chips_enabled = 0; |
6732ae5c JCPV |
1212 | |
1213 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1214 | if (!info) | |
1215 | return -ENOMEM; | |
1216 | ||
1217 | ret = at91_pinctrl_probe_dt(pdev, info); | |
1218 | if (ret) | |
1219 | return ret; | |
1220 | ||
1221 | /* | |
1222 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1223 | * to obtain references to the struct gpio_chip * for them, and we | |
1224 | * need this to proceed. | |
1225 | */ | |
a0b957f3 JCPV |
1226 | for (i = 0; i < gpio_banks; i++) |
1227 | if (gpio_chips[i]) | |
1228 | ngpio_chips_enabled++; | |
1229 | ||
1230 | if (ngpio_chips_enabled < info->nactive_banks) { | |
1231 | dev_warn(&pdev->dev, | |
1232 | "All GPIO chips are not registered yet (%d/%d)\n", | |
1233 | ngpio_chips_enabled, info->nactive_banks); | |
1234 | devm_kfree(&pdev->dev, info); | |
1235 | return -EPROBE_DEFER; | |
6732ae5c JCPV |
1236 | } |
1237 | ||
1238 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
a0b957f3 | 1239 | at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK; |
6732ae5c JCPV |
1240 | at91_pinctrl_desc.pins = pdesc = |
1241 | devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); | |
1242 | ||
1243 | if (!at91_pinctrl_desc.pins) | |
1244 | return -ENOMEM; | |
1245 | ||
a0b957f3 | 1246 | for (i = 0, k = 0; i < gpio_banks; i++) { |
6732ae5c JCPV |
1247 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { |
1248 | pdesc->number = k; | |
1249 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
1250 | pdesc++; | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | platform_set_drvdata(pdev, info); | |
1255 | info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); | |
1256 | ||
323de9ef | 1257 | if (IS_ERR(info->pctl)) { |
6732ae5c | 1258 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); |
323de9ef | 1259 | return PTR_ERR(info->pctl); |
6732ae5c JCPV |
1260 | } |
1261 | ||
1262 | /* We will handle a range of GPIO pins */ | |
a0b957f3 JCPV |
1263 | for (i = 0; i < gpio_banks; i++) |
1264 | if (gpio_chips[i]) | |
1265 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
6732ae5c JCPV |
1266 | |
1267 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
1268 | ||
1269 | return 0; | |
6732ae5c JCPV |
1270 | } |
1271 | ||
150632b0 | 1272 | static int at91_pinctrl_remove(struct platform_device *pdev) |
6732ae5c JCPV |
1273 | { |
1274 | struct at91_pinctrl *info = platform_get_drvdata(pdev); | |
1275 | ||
1276 | pinctrl_unregister(info->pctl); | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
8af584b8 RG |
1281 | static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
1282 | { | |
370ea611 | 1283 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
8af584b8 RG |
1284 | void __iomem *pio = at91_gpio->regbase; |
1285 | unsigned mask = 1 << offset; | |
1286 | u32 osr; | |
1287 | ||
1288 | osr = readl_relaxed(pio + PIO_OSR); | |
1289 | return !(osr & mask); | |
1290 | } | |
1291 | ||
6732ae5c JCPV |
1292 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
1293 | { | |
370ea611 | 1294 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1295 | void __iomem *pio = at91_gpio->regbase; |
1296 | unsigned mask = 1 << offset; | |
1297 | ||
1298 | writel_relaxed(mask, pio + PIO_ODR); | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1303 | { | |
370ea611 | 1304 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1305 | void __iomem *pio = at91_gpio->regbase; |
1306 | unsigned mask = 1 << offset; | |
1307 | u32 pdsr; | |
1308 | ||
1309 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1310 | return (pdsr & mask) != 0; | |
1311 | } | |
1312 | ||
1313 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1314 | int val) | |
1315 | { | |
370ea611 | 1316 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1317 | void __iomem *pio = at91_gpio->regbase; |
1318 | unsigned mask = 1 << offset; | |
1319 | ||
1320 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1321 | } | |
1322 | ||
1893b2cf AS |
1323 | static void at91_gpio_set_multiple(struct gpio_chip *chip, |
1324 | unsigned long *mask, unsigned long *bits) | |
1325 | { | |
370ea611 | 1326 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
1893b2cf AS |
1327 | void __iomem *pio = at91_gpio->regbase; |
1328 | ||
1329 | #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) | |
1330 | /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ | |
1331 | uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); | |
1332 | uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); | |
1333 | ||
1334 | writel_relaxed(set_mask, pio + PIO_SODR); | |
1335 | writel_relaxed(clear_mask, pio + PIO_CODR); | |
1336 | } | |
1337 | ||
6732ae5c JCPV |
1338 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
1339 | int val) | |
1340 | { | |
370ea611 | 1341 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1342 | void __iomem *pio = at91_gpio->regbase; |
1343 | unsigned mask = 1 << offset; | |
1344 | ||
1345 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1346 | writel_relaxed(mask, pio + PIO_OER); | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
6732ae5c JCPV |
1351 | #ifdef CONFIG_DEBUG_FS |
1352 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1353 | { | |
1354 | enum at91_mux mode; | |
1355 | int i; | |
370ea611 | 1356 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip); |
6732ae5c JCPV |
1357 | void __iomem *pio = at91_gpio->regbase; |
1358 | ||
1359 | for (i = 0; i < chip->ngpio; i++) { | |
47f22716 | 1360 | unsigned mask = pin_to_mask(i); |
6732ae5c | 1361 | const char *gpio_label; |
6732ae5c JCPV |
1362 | |
1363 | gpio_label = gpiochip_is_requested(chip, i); | |
1364 | if (!gpio_label) | |
1365 | continue; | |
1366 | mode = at91_gpio->ops->get_periph(pio, mask); | |
1367 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1368 | gpio_label, chip->label, i); | |
1369 | if (mode == AT91_MUX_GPIO) { | |
853b6bf0 MC |
1370 | seq_printf(s, "[gpio] "); |
1371 | seq_printf(s, "%s ", | |
1372 | readl_relaxed(pio + PIO_OSR) & mask ? | |
1373 | "output" : "input"); | |
1374 | seq_printf(s, "%s\n", | |
1375 | readl_relaxed(pio + PIO_PDSR) & mask ? | |
1376 | "set" : "clear"); | |
6732ae5c JCPV |
1377 | } else { |
1378 | seq_printf(s, "[periph %c]\n", | |
1379 | mode + 'A' - 1); | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | #else | |
1384 | #define at91_gpio_dbg_show NULL | |
1385 | #endif | |
1386 | ||
1387 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1388 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1389 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1390 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1391 | * handler. | |
1392 | * First implementation always triggers on rising and falling edges | |
1393 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1394 | * level, edge with any polarity. | |
1395 | * | |
1396 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1397 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1398 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1399 | */ | |
1400 | ||
1401 | static void gpio_irq_mask(struct irq_data *d) | |
1402 | { | |
1403 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1404 | void __iomem *pio = at91_gpio->regbase; | |
1405 | unsigned mask = 1 << d->hwirq; | |
1406 | ||
1407 | if (pio) | |
1408 | writel_relaxed(mask, pio + PIO_IDR); | |
1409 | } | |
1410 | ||
1411 | static void gpio_irq_unmask(struct irq_data *d) | |
1412 | { | |
1413 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1414 | void __iomem *pio = at91_gpio->regbase; | |
1415 | unsigned mask = 1 << d->hwirq; | |
1416 | ||
1417 | if (pio) | |
1418 | writel_relaxed(mask, pio + PIO_IER); | |
1419 | } | |
1420 | ||
1421 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1422 | { | |
1423 | switch (type) { | |
1424 | case IRQ_TYPE_NONE: | |
1425 | case IRQ_TYPE_EDGE_BOTH: | |
1426 | return 0; | |
1427 | default: | |
1428 | return -EINVAL; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | /* Alternate irq type for PIO3 support */ | |
1433 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1434 | { | |
1435 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1436 | void __iomem *pio = at91_gpio->regbase; | |
1437 | unsigned mask = 1 << d->hwirq; | |
1438 | ||
1439 | switch (type) { | |
1440 | case IRQ_TYPE_EDGE_RISING: | |
c639845b | 1441 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1442 | writel_relaxed(mask, pio + PIO_ESR); |
1443 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1444 | break; | |
1445 | case IRQ_TYPE_EDGE_FALLING: | |
c639845b | 1446 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1447 | writel_relaxed(mask, pio + PIO_ESR); |
1448 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1449 | break; | |
1450 | case IRQ_TYPE_LEVEL_LOW: | |
c639845b | 1451 | irq_set_handler_locked(d, handle_level_irq); |
6732ae5c JCPV |
1452 | writel_relaxed(mask, pio + PIO_LSR); |
1453 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1454 | break; | |
1455 | case IRQ_TYPE_LEVEL_HIGH: | |
c639845b | 1456 | irq_set_handler_locked(d, handle_level_irq); |
6732ae5c JCPV |
1457 | writel_relaxed(mask, pio + PIO_LSR); |
1458 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1459 | break; | |
1460 | case IRQ_TYPE_EDGE_BOTH: | |
1461 | /* | |
1462 | * disable additional interrupt modes: | |
1463 | * fall back to default behavior | |
1464 | */ | |
c639845b | 1465 | irq_set_handler_locked(d, handle_simple_irq); |
6732ae5c JCPV |
1466 | writel_relaxed(mask, pio + PIO_AIMDR); |
1467 | return 0; | |
1468 | case IRQ_TYPE_NONE: | |
1469 | default: | |
1470 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
1471 | return -EINVAL; | |
1472 | } | |
1473 | ||
1474 | /* enable additional interrupt modes */ | |
1475 | writel_relaxed(mask, pio + PIO_AIMER); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
80cc3732 AS |
1480 | static void gpio_irq_ack(struct irq_data *d) |
1481 | { | |
1482 | /* the interrupt is already cleared before by reading ISR */ | |
1483 | } | |
1484 | ||
6732ae5c | 1485 | #ifdef CONFIG_PM |
647f8d94 LD |
1486 | |
1487 | static u32 wakeups[MAX_GPIO_BANKS]; | |
1488 | static u32 backups[MAX_GPIO_BANKS]; | |
1489 | ||
6732ae5c JCPV |
1490 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
1491 | { | |
1492 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1493 | unsigned bank = at91_gpio->pioc_idx; | |
647f8d94 | 1494 | unsigned mask = 1 << d->hwirq; |
6732ae5c JCPV |
1495 | |
1496 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1497 | return -EINVAL; | |
1498 | ||
647f8d94 LD |
1499 | if (state) |
1500 | wakeups[bank] |= mask; | |
1501 | else | |
1502 | wakeups[bank] &= ~mask; | |
1503 | ||
6732ae5c JCPV |
1504 | irq_set_irq_wake(at91_gpio->pioc_virq, state); |
1505 | ||
1506 | return 0; | |
1507 | } | |
647f8d94 LD |
1508 | |
1509 | void at91_pinctrl_gpio_suspend(void) | |
1510 | { | |
1511 | int i; | |
1512 | ||
1513 | for (i = 0; i < gpio_banks; i++) { | |
1514 | void __iomem *pio; | |
1515 | ||
1516 | if (!gpio_chips[i]) | |
1517 | continue; | |
1518 | ||
1519 | pio = gpio_chips[i]->regbase; | |
1520 | ||
d480239b BD |
1521 | backups[i] = readl_relaxed(pio + PIO_IMR); |
1522 | writel_relaxed(backups[i], pio + PIO_IDR); | |
1523 | writel_relaxed(wakeups[i], pio + PIO_IER); | |
647f8d94 | 1524 | |
795f9953 BB |
1525 | if (!wakeups[i]) |
1526 | clk_disable_unprepare(gpio_chips[i]->clock); | |
1527 | else | |
647f8d94 LD |
1528 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", |
1529 | 'A'+i, wakeups[i]); | |
647f8d94 LD |
1530 | } |
1531 | } | |
1532 | ||
1533 | void at91_pinctrl_gpio_resume(void) | |
1534 | { | |
1535 | int i; | |
1536 | ||
1537 | for (i = 0; i < gpio_banks; i++) { | |
1538 | void __iomem *pio; | |
1539 | ||
1540 | if (!gpio_chips[i]) | |
1541 | continue; | |
1542 | ||
1543 | pio = gpio_chips[i]->regbase; | |
1544 | ||
37ef1d92 BB |
1545 | if (!wakeups[i]) |
1546 | clk_prepare_enable(gpio_chips[i]->clock); | |
647f8d94 | 1547 | |
d480239b BD |
1548 | writel_relaxed(wakeups[i], pio + PIO_IDR); |
1549 | writel_relaxed(backups[i], pio + PIO_IER); | |
647f8d94 LD |
1550 | } |
1551 | } | |
1552 | ||
6732ae5c JCPV |
1553 | #else |
1554 | #define gpio_irq_set_wake NULL | |
647f8d94 | 1555 | #endif /* CONFIG_PM */ |
6732ae5c JCPV |
1556 | |
1557 | static struct irq_chip gpio_irqchip = { | |
1558 | .name = "GPIO", | |
80cc3732 | 1559 | .irq_ack = gpio_irq_ack, |
6732ae5c JCPV |
1560 | .irq_disable = gpio_irq_mask, |
1561 | .irq_mask = gpio_irq_mask, | |
1562 | .irq_unmask = gpio_irq_unmask, | |
1563 | /* .irq_set_type is set dynamically */ | |
1564 | .irq_set_wake = gpio_irq_set_wake, | |
1565 | }; | |
1566 | ||
bd0b9ac4 | 1567 | static void gpio_irq_handler(struct irq_desc *desc) |
6732ae5c | 1568 | { |
5663bb27 | 1569 | struct irq_chip *chip = irq_desc_get_chip(desc); |
80cc3732 | 1570 | struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); |
370ea611 | 1571 | struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip); |
6732ae5c JCPV |
1572 | void __iomem *pio = at91_gpio->regbase; |
1573 | unsigned long isr; | |
1574 | int n; | |
1575 | ||
1576 | chained_irq_enter(chip, desc); | |
1577 | for (;;) { | |
1578 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
c2eb9e7f | 1579 | * When there are none pending, we're finished unless we need |
6732ae5c JCPV |
1580 | * to process multiple banks (like ID_PIOCDE on sam9263). |
1581 | */ | |
1582 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1583 | if (!isr) { | |
1584 | if (!at91_gpio->next) | |
1585 | break; | |
1586 | at91_gpio = at91_gpio->next; | |
1587 | pio = at91_gpio->regbase; | |
cccb0c3e | 1588 | gpio_chip = &at91_gpio->chip; |
6732ae5c JCPV |
1589 | continue; |
1590 | } | |
1591 | ||
05daa16a | 1592 | for_each_set_bit(n, &isr, BITS_PER_LONG) { |
80cc3732 AS |
1593 | generic_handle_irq(irq_find_mapping( |
1594 | gpio_chip->irqdomain, n)); | |
6732ae5c JCPV |
1595 | } |
1596 | } | |
1597 | chained_irq_exit(chip, desc); | |
1598 | /* now it may re-trigger */ | |
1599 | } | |
1600 | ||
834e1678 | 1601 | static int at91_gpio_of_irq_setup(struct platform_device *pdev, |
6732ae5c JCPV |
1602 | struct at91_gpio_chip *at91_gpio) |
1603 | { | |
a0b957f3 | 1604 | struct gpio_chip *gpiochip_prev = NULL; |
cccb0c3e | 1605 | struct at91_gpio_chip *prev = NULL; |
6732ae5c | 1606 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); |
a0b957f3 | 1607 | int ret, i; |
6732ae5c JCPV |
1608 | |
1609 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); | |
1610 | ||
1611 | /* Setup proper .irq_set_type function */ | |
1612 | gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; | |
1613 | ||
1614 | /* Disable irqs of this PIO controller */ | |
1615 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1616 | ||
80cc3732 AS |
1617 | /* |
1618 | * Let the generic code handle this edge IRQ, the the chained | |
1619 | * handler will perform the actual work of handling the parent | |
1620 | * interrupt. | |
1621 | */ | |
1622 | ret = gpiochip_irqchip_add(&at91_gpio->chip, | |
1623 | &gpio_irqchip, | |
1624 | 0, | |
1625 | handle_edge_irq, | |
1626 | IRQ_TYPE_EDGE_BOTH); | |
834e1678 PG |
1627 | if (ret) { |
1628 | dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n", | |
6732ae5c | 1629 | at91_gpio->pioc_idx); |
834e1678 PG |
1630 | return ret; |
1631 | } | |
6732ae5c | 1632 | |
cccb0c3e AS |
1633 | /* The top level handler handles one bank of GPIOs, except |
1634 | * on some SoC it can handle up to three... | |
1635 | * We only set up the handler for the first of the list. | |
1636 | */ | |
a0b957f3 JCPV |
1637 | gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); |
1638 | if (!gpiochip_prev) { | |
1639 | /* Then register the chain on the parent IRQ */ | |
1640 | gpiochip_set_chained_irqchip(&at91_gpio->chip, | |
1641 | &gpio_irqchip, | |
1642 | at91_gpio->pioc_virq, | |
1643 | gpio_irq_handler); | |
cccb0c3e | 1644 | return 0; |
a0b957f3 | 1645 | } |
cccb0c3e | 1646 | |
370ea611 | 1647 | prev = gpiochip_get_data(gpiochip_prev); |
6732ae5c | 1648 | |
a0b957f3 JCPV |
1649 | /* we can only have 2 banks before */ |
1650 | for (i = 0; i < 2; i++) { | |
1651 | if (prev->next) { | |
1652 | prev = prev->next; | |
1653 | } else { | |
1654 | prev->next = at91_gpio; | |
1655 | return 0; | |
1656 | } | |
1657 | } | |
1658 | ||
1659 | return -EINVAL; | |
6732ae5c JCPV |
1660 | } |
1661 | ||
1662 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
1663 | static struct gpio_chip at91_gpio_template = { | |
98c85d58 JG |
1664 | .request = gpiochip_generic_request, |
1665 | .free = gpiochip_generic_free, | |
8af584b8 | 1666 | .get_direction = at91_gpio_get_direction, |
6732ae5c JCPV |
1667 | .direction_input = at91_gpio_direction_input, |
1668 | .get = at91_gpio_get, | |
1669 | .direction_output = at91_gpio_direction_output, | |
1670 | .set = at91_gpio_set, | |
1893b2cf | 1671 | .set_multiple = at91_gpio_set_multiple, |
6732ae5c | 1672 | .dbg_show = at91_gpio_dbg_show, |
9fb1f39e | 1673 | .can_sleep = false, |
6732ae5c JCPV |
1674 | .ngpio = MAX_NB_GPIO_PER_BANK, |
1675 | }; | |
1676 | ||
baa9946e | 1677 | static const struct of_device_id at91_gpio_of_match[] = { |
6732ae5c JCPV |
1678 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, |
1679 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
1680 | { /* sentinel */ } | |
1681 | }; | |
1682 | ||
150632b0 | 1683 | static int at91_gpio_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1684 | { |
1685 | struct device_node *np = pdev->dev.of_node; | |
1686 | struct resource *res; | |
1687 | struct at91_gpio_chip *at91_chip = NULL; | |
1688 | struct gpio_chip *chip; | |
1689 | struct pinctrl_gpio_range *range; | |
1690 | int ret = 0; | |
32b01a36 | 1691 | int irq, i; |
6732ae5c JCPV |
1692 | int alias_idx = of_alias_get_id(np, "gpio"); |
1693 | uint32_t ngpio; | |
32b01a36 | 1694 | char **names; |
6732ae5c JCPV |
1695 | |
1696 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1697 | if (gpio_chips[alias_idx]) { | |
1698 | ret = -EBUSY; | |
1699 | goto err; | |
1700 | } | |
1701 | ||
6732ae5c JCPV |
1702 | irq = platform_get_irq(pdev, 0); |
1703 | if (irq < 0) { | |
1704 | ret = irq; | |
1705 | goto err; | |
1706 | } | |
1707 | ||
1708 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1709 | if (!at91_chip) { | |
1710 | ret = -ENOMEM; | |
1711 | goto err; | |
1712 | } | |
1713 | ||
f50b9e12 | 1714 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
1715 | at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); |
1716 | if (IS_ERR(at91_chip->regbase)) { | |
1717 | ret = PTR_ERR(at91_chip->regbase); | |
6732ae5c JCPV |
1718 | goto err; |
1719 | } | |
1720 | ||
3c93600d | 1721 | at91_chip->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1722 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1723 | at91_chip->pioc_virq = irq; | |
1724 | at91_chip->pioc_idx = alias_idx; | |
1725 | ||
02b837ff | 1726 | at91_chip->clock = devm_clk_get(&pdev->dev, NULL); |
6732ae5c JCPV |
1727 | if (IS_ERR(at91_chip->clock)) { |
1728 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
70e41974 | 1729 | ret = PTR_ERR(at91_chip->clock); |
6732ae5c JCPV |
1730 | goto err; |
1731 | } | |
1732 | ||
70e41974 PG |
1733 | ret = clk_prepare(at91_chip->clock); |
1734 | if (ret) | |
1735 | goto clk_prepare_err; | |
6732ae5c JCPV |
1736 | |
1737 | /* enable PIO controller's clock */ | |
70e41974 PG |
1738 | ret = clk_enable(at91_chip->clock); |
1739 | if (ret) { | |
6732ae5c | 1740 | dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); |
70e41974 | 1741 | goto clk_enable_err; |
6732ae5c JCPV |
1742 | } |
1743 | ||
1744 | at91_chip->chip = at91_gpio_template; | |
1745 | ||
1746 | chip = &at91_chip->chip; | |
1747 | chip->of_node = np; | |
1748 | chip->label = dev_name(&pdev->dev); | |
58383c78 | 1749 | chip->parent = &pdev->dev; |
6732ae5c JCPV |
1750 | chip->owner = THIS_MODULE; |
1751 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1752 | ||
1753 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1754 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1755 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1756 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1757 | else | |
1758 | chip->ngpio = ngpio; | |
1759 | } | |
1760 | ||
3c93600d SK |
1761 | names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, |
1762 | GFP_KERNEL); | |
32b01a36 JCPV |
1763 | |
1764 | if (!names) { | |
1765 | ret = -ENOMEM; | |
70e41974 | 1766 | goto clk_enable_err; |
32b01a36 JCPV |
1767 | } |
1768 | ||
1769 | for (i = 0; i < chip->ngpio; i++) | |
1770 | names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); | |
1771 | ||
3c93600d | 1772 | chip->names = (const char *const *)names; |
32b01a36 | 1773 | |
6732ae5c JCPV |
1774 | range = &at91_chip->range; |
1775 | range->name = chip->label; | |
1776 | range->id = alias_idx; | |
1777 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1778 | ||
1779 | range->npins = chip->ngpio; | |
1780 | range->gc = chip; | |
1781 | ||
370ea611 | 1782 | ret = gpiochip_add_data(chip, at91_chip); |
6732ae5c | 1783 | if (ret) |
70e41974 | 1784 | goto gpiochip_add_err; |
6732ae5c JCPV |
1785 | |
1786 | gpio_chips[alias_idx] = at91_chip; | |
1787 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1788 | ||
834e1678 PG |
1789 | ret = at91_gpio_of_irq_setup(pdev, at91_chip); |
1790 | if (ret) | |
1791 | goto irq_setup_err; | |
6732ae5c JCPV |
1792 | |
1793 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); | |
1794 | ||
1795 | return 0; | |
1796 | ||
834e1678 PG |
1797 | irq_setup_err: |
1798 | gpiochip_remove(chip); | |
70e41974 PG |
1799 | gpiochip_add_err: |
1800 | clk_disable(at91_chip->clock); | |
1801 | clk_enable_err: | |
6732ae5c | 1802 | clk_unprepare(at91_chip->clock); |
70e41974 | 1803 | clk_prepare_err: |
6732ae5c JCPV |
1804 | err: |
1805 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1806 | ||
1807 | return ret; | |
1808 | } | |
1809 | ||
1810 | static struct platform_driver at91_gpio_driver = { | |
1811 | .driver = { | |
1812 | .name = "gpio-at91", | |
606fca94 | 1813 | .of_match_table = at91_gpio_of_match, |
6732ae5c JCPV |
1814 | }, |
1815 | .probe = at91_gpio_probe, | |
1816 | }; | |
1817 | ||
1818 | static struct platform_driver at91_pinctrl_driver = { | |
1819 | .driver = { | |
1820 | .name = "pinctrl-at91", | |
606fca94 | 1821 | .of_match_table = at91_pinctrl_of_match, |
6732ae5c JCPV |
1822 | }, |
1823 | .probe = at91_pinctrl_probe, | |
150632b0 | 1824 | .remove = at91_pinctrl_remove, |
6732ae5c JCPV |
1825 | }; |
1826 | ||
bab7f5a4 TR |
1827 | static struct platform_driver * const drivers[] = { |
1828 | &at91_gpio_driver, | |
1829 | &at91_pinctrl_driver, | |
1830 | }; | |
1831 | ||
6732ae5c JCPV |
1832 | static int __init at91_pinctrl_init(void) |
1833 | { | |
bab7f5a4 | 1834 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
6732ae5c JCPV |
1835 | } |
1836 | arch_initcall(at91_pinctrl_init); | |
1837 | ||
1838 | static void __exit at91_pinctrl_exit(void) | |
1839 | { | |
bab7f5a4 | 1840 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
6732ae5c JCPV |
1841 | } |
1842 | ||
1843 | module_exit(at91_pinctrl_exit); | |
1844 | MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); | |
1845 | MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); | |
1846 | MODULE_LICENSE("GPL v2"); |