Commit | Line | Data |
---|---|---|
6732ae5c JCPV |
1 | /* |
2 | * at91 pinctrl driver based on at91 pinmux core | |
3 | * | |
4 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
5 | * | |
6 | * Under GPLv2 only | |
7 | */ | |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/irqdomain.h> | |
de88cbb7 | 21 | #include <linux/irqchip/chained_irq.h> |
6732ae5c JCPV |
22 | #include <linux/io.h> |
23 | #include <linux/gpio.h> | |
6732ae5c JCPV |
24 | #include <linux/pinctrl/machine.h> |
25 | #include <linux/pinctrl/pinconf.h> | |
26 | #include <linux/pinctrl/pinctrl.h> | |
27 | #include <linux/pinctrl/pinmux.h> | |
28 | /* Since we request GPIOs from ourself */ | |
29 | #include <linux/pinctrl/consumer.h> | |
30 | ||
6732ae5c JCPV |
31 | #include <mach/hardware.h> |
32 | #include <mach/at91_pio.h> | |
33 | ||
34 | #include "core.h" | |
35 | ||
94daf85e | 36 | #define MAX_GPIO_BANKS 5 |
6732ae5c JCPV |
37 | #define MAX_NB_GPIO_PER_BANK 32 |
38 | ||
39 | struct at91_pinctrl_mux_ops; | |
40 | ||
41 | struct at91_gpio_chip { | |
42 | struct gpio_chip chip; | |
43 | struct pinctrl_gpio_range range; | |
44 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | |
45 | int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ | |
46 | int pioc_virq; /* PIO bank Linux virtual interrupt */ | |
47 | int pioc_idx; /* PIO bank index */ | |
48 | void __iomem *regbase; /* PIO bank virtual address */ | |
49 | struct clk *clock; /* associated clock */ | |
50 | struct irq_domain *domain; /* associated irq domain */ | |
51 | struct at91_pinctrl_mux_ops *ops; /* ops */ | |
52 | }; | |
53 | ||
54 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) | |
55 | ||
56 | static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; | |
57 | ||
58 | static int gpio_banks; | |
59 | ||
525fae21 | 60 | #define PULL_UP (1 << 0) |
6732ae5c | 61 | #define MULTI_DRIVE (1 << 1) |
7ebd7a3a JCPV |
62 | #define DEGLITCH (1 << 2) |
63 | #define PULL_DOWN (1 << 3) | |
64 | #define DIS_SCHMIT (1 << 4) | |
65 | #define DEBOUNCE (1 << 16) | |
66 | #define DEBOUNCE_VAL_SHIFT 17 | |
67 | #define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) | |
6732ae5c JCPV |
68 | |
69 | /** | |
70 | * struct at91_pmx_func - describes AT91 pinmux functions | |
71 | * @name: the name of this specific function | |
72 | * @groups: corresponding pin groups | |
73 | * @ngroups: the number of groups | |
74 | */ | |
75 | struct at91_pmx_func { | |
76 | const char *name; | |
77 | const char **groups; | |
78 | unsigned ngroups; | |
79 | }; | |
80 | ||
81 | enum at91_mux { | |
82 | AT91_MUX_GPIO = 0, | |
83 | AT91_MUX_PERIPH_A = 1, | |
84 | AT91_MUX_PERIPH_B = 2, | |
85 | AT91_MUX_PERIPH_C = 3, | |
86 | AT91_MUX_PERIPH_D = 4, | |
87 | }; | |
88 | ||
89 | /** | |
90 | * struct at91_pmx_pin - describes an At91 pin mux | |
91 | * @bank: the bank of the pin | |
92 | * @pin: the pin number in the @bank | |
93 | * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. | |
94 | * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc... | |
95 | */ | |
96 | struct at91_pmx_pin { | |
97 | uint32_t bank; | |
98 | uint32_t pin; | |
99 | enum at91_mux mux; | |
100 | unsigned long conf; | |
101 | }; | |
102 | ||
103 | /** | |
104 | * struct at91_pin_group - describes an At91 pin group | |
105 | * @name: the name of this specific pin group | |
106 | * @pins_conf: the mux mode for each pin in this group. The size of this | |
107 | * array is the same as pins. | |
108 | * @pins: an array of discrete physical pins used in this group, taken | |
109 | * from the driver-local pin enumeration space | |
110 | * @npins: the number of pins in this group array, i.e. the number of | |
111 | * elements in .pins so we can iterate over that array | |
112 | */ | |
113 | struct at91_pin_group { | |
114 | const char *name; | |
115 | struct at91_pmx_pin *pins_conf; | |
116 | unsigned int *pins; | |
117 | unsigned npins; | |
118 | }; | |
119 | ||
120 | /** | |
121 | * struct at91_pinctrl_mux_ops - describes an At91 mux ops group | |
122 | * on new IP with support for periph C and D the way to mux in | |
123 | * periph A and B has changed | |
124 | * So provide the right call back | |
125 | * if not present means the IP does not support it | |
126 | * @get_periph: return the periph mode configured | |
127 | * @mux_A_periph: mux as periph A | |
128 | * @mux_B_periph: mux as periph B | |
129 | * @mux_C_periph: mux as periph C | |
130 | * @mux_D_periph: mux as periph D | |
7ebd7a3a JCPV |
131 | * @get_deglitch: get deglitch status |
132 | * @set_deglitch: enable/disable deglitch | |
133 | * @get_debounce: get debounce status | |
134 | * @set_debounce: enable/disable debounce | |
135 | * @get_pulldown: get pulldown status | |
136 | * @set_pulldown: enable/disable pulldown | |
137 | * @get_schmitt_trig: get schmitt trigger status | |
138 | * @disable_schmitt_trig: disable schmitt trigger | |
6732ae5c JCPV |
139 | * @irq_type: return irq type |
140 | */ | |
141 | struct at91_pinctrl_mux_ops { | |
142 | enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask); | |
143 | void (*mux_A_periph)(void __iomem *pio, unsigned mask); | |
144 | void (*mux_B_periph)(void __iomem *pio, unsigned mask); | |
145 | void (*mux_C_periph)(void __iomem *pio, unsigned mask); | |
146 | void (*mux_D_periph)(void __iomem *pio, unsigned mask); | |
7ebd7a3a | 147 | bool (*get_deglitch)(void __iomem *pio, unsigned pin); |
77966ad7 | 148 | void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a | 149 | bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); |
77966ad7 | 150 | void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); |
7ebd7a3a | 151 | bool (*get_pulldown)(void __iomem *pio, unsigned pin); |
77966ad7 | 152 | void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); |
7ebd7a3a JCPV |
153 | bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); |
154 | void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); | |
6732ae5c JCPV |
155 | /* irq */ |
156 | int (*irq_type)(struct irq_data *d, unsigned type); | |
157 | }; | |
158 | ||
159 | static int gpio_irq_type(struct irq_data *d, unsigned type); | |
160 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type); | |
161 | ||
162 | struct at91_pinctrl { | |
163 | struct device *dev; | |
164 | struct pinctrl_dev *pctl; | |
165 | ||
166 | int nbanks; | |
167 | ||
168 | uint32_t *mux_mask; | |
169 | int nmux; | |
170 | ||
171 | struct at91_pmx_func *functions; | |
172 | int nfunctions; | |
173 | ||
174 | struct at91_pin_group *groups; | |
175 | int ngroups; | |
176 | ||
177 | struct at91_pinctrl_mux_ops *ops; | |
178 | }; | |
179 | ||
180 | static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name( | |
181 | const struct at91_pinctrl *info, | |
182 | const char *name) | |
183 | { | |
184 | const struct at91_pin_group *grp = NULL; | |
185 | int i; | |
186 | ||
187 | for (i = 0; i < info->ngroups; i++) { | |
188 | if (strcmp(info->groups[i].name, name)) | |
189 | continue; | |
190 | ||
191 | grp = &info->groups[i]; | |
192 | dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); | |
193 | break; | |
194 | } | |
195 | ||
196 | return grp; | |
197 | } | |
198 | ||
199 | static int at91_get_groups_count(struct pinctrl_dev *pctldev) | |
200 | { | |
201 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
202 | ||
203 | return info->ngroups; | |
204 | } | |
205 | ||
206 | static const char *at91_get_group_name(struct pinctrl_dev *pctldev, | |
207 | unsigned selector) | |
208 | { | |
209 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
210 | ||
211 | return info->groups[selector].name; | |
212 | } | |
213 | ||
214 | static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
215 | const unsigned **pins, | |
216 | unsigned *npins) | |
217 | { | |
218 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
219 | ||
220 | if (selector >= info->ngroups) | |
221 | return -EINVAL; | |
222 | ||
223 | *pins = info->groups[selector].pins; | |
224 | *npins = info->groups[selector].npins; | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
229 | static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
230 | unsigned offset) | |
231 | { | |
232 | seq_printf(s, "%s", dev_name(pctldev->dev)); | |
233 | } | |
234 | ||
235 | static int at91_dt_node_to_map(struct pinctrl_dev *pctldev, | |
236 | struct device_node *np, | |
237 | struct pinctrl_map **map, unsigned *num_maps) | |
238 | { | |
239 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
240 | const struct at91_pin_group *grp; | |
241 | struct pinctrl_map *new_map; | |
242 | struct device_node *parent; | |
243 | int map_num = 1; | |
244 | int i; | |
6732ae5c JCPV |
245 | |
246 | /* | |
61e310a1 | 247 | * first find the group of this node and check if we need to create |
6732ae5c JCPV |
248 | * config maps for pins |
249 | */ | |
250 | grp = at91_pinctrl_find_group_by_name(info, np->name); | |
251 | if (!grp) { | |
252 | dev_err(info->dev, "unable to find group for node %s\n", | |
253 | np->name); | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | map_num += grp->npins; | |
258 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, GFP_KERNEL); | |
259 | if (!new_map) | |
260 | return -ENOMEM; | |
261 | ||
262 | *map = new_map; | |
263 | *num_maps = map_num; | |
264 | ||
265 | /* create mux map */ | |
266 | parent = of_get_parent(np); | |
267 | if (!parent) { | |
c62b2b34 | 268 | devm_kfree(pctldev->dev, new_map); |
6732ae5c JCPV |
269 | return -EINVAL; |
270 | } | |
271 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
272 | new_map[0].data.mux.function = parent->name; | |
273 | new_map[0].data.mux.group = np->name; | |
274 | of_node_put(parent); | |
275 | ||
276 | /* create config map */ | |
277 | new_map++; | |
278 | for (i = 0; i < grp->npins; i++) { | |
6732ae5c JCPV |
279 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
280 | new_map[i].data.configs.group_or_pin = | |
281 | pin_get_name(pctldev, grp->pins[i]); | |
282 | new_map[i].data.configs.configs = &grp->pins_conf[i].conf; | |
283 | new_map[i].data.configs.num_configs = 1; | |
284 | } | |
285 | ||
286 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
287 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static void at91_dt_free_map(struct pinctrl_dev *pctldev, | |
293 | struct pinctrl_map *map, unsigned num_maps) | |
294 | { | |
295 | } | |
296 | ||
022ab148 | 297 | static const struct pinctrl_ops at91_pctrl_ops = { |
6732ae5c JCPV |
298 | .get_groups_count = at91_get_groups_count, |
299 | .get_group_name = at91_get_group_name, | |
300 | .get_group_pins = at91_get_group_pins, | |
301 | .pin_dbg_show = at91_pin_dbg_show, | |
302 | .dt_node_to_map = at91_dt_node_to_map, | |
303 | .dt_free_map = at91_dt_free_map, | |
304 | }; | |
305 | ||
3c93600d | 306 | static void __iomem *pin_to_controller(struct at91_pinctrl *info, |
6732ae5c JCPV |
307 | unsigned int bank) |
308 | { | |
309 | return gpio_chips[bank]->regbase; | |
310 | } | |
311 | ||
312 | static inline int pin_to_bank(unsigned pin) | |
313 | { | |
314 | return pin /= MAX_NB_GPIO_PER_BANK; | |
315 | } | |
316 | ||
317 | static unsigned pin_to_mask(unsigned int pin) | |
318 | { | |
319 | return 1 << pin; | |
320 | } | |
321 | ||
322 | static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) | |
323 | { | |
324 | writel_relaxed(mask, pio + PIO_IDR); | |
325 | } | |
326 | ||
327 | static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) | |
328 | { | |
05d3534a | 329 | return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); |
6732ae5c JCPV |
330 | } |
331 | ||
332 | static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) | |
333 | { | |
334 | writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); | |
335 | } | |
336 | ||
337 | static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) | |
338 | { | |
339 | return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; | |
340 | } | |
341 | ||
342 | static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) | |
343 | { | |
344 | writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); | |
345 | } | |
346 | ||
347 | static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) | |
348 | { | |
349 | writel_relaxed(mask, pio + PIO_ASR); | |
350 | } | |
351 | ||
352 | static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) | |
353 | { | |
354 | writel_relaxed(mask, pio + PIO_BSR); | |
355 | } | |
356 | ||
357 | static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) | |
358 | { | |
359 | ||
360 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, | |
361 | pio + PIO_ABCDSR1); | |
362 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
363 | pio + PIO_ABCDSR2); | |
364 | } | |
365 | ||
366 | static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) | |
367 | { | |
368 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, | |
369 | pio + PIO_ABCDSR1); | |
370 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, | |
371 | pio + PIO_ABCDSR2); | |
372 | } | |
373 | ||
374 | static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) | |
375 | { | |
376 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); | |
377 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
378 | } | |
379 | ||
380 | static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) | |
381 | { | |
382 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); | |
383 | writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); | |
384 | } | |
385 | ||
386 | static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) | |
387 | { | |
388 | unsigned select; | |
389 | ||
390 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
391 | return AT91_MUX_GPIO; | |
392 | ||
393 | select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); | |
394 | select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); | |
395 | ||
396 | return select + 1; | |
397 | } | |
398 | ||
399 | static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) | |
400 | { | |
401 | unsigned select; | |
402 | ||
403 | if (readl_relaxed(pio + PIO_PSR) & mask) | |
404 | return AT91_MUX_GPIO; | |
405 | ||
406 | select = readl_relaxed(pio + PIO_ABSR) & mask; | |
407 | ||
408 | return select + 1; | |
409 | } | |
410 | ||
7ebd7a3a JCPV |
411 | static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) |
412 | { | |
413 | return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; | |
414 | } | |
415 | ||
416 | static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) | |
417 | { | |
418 | __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); | |
419 | } | |
420 | ||
c8dba02e BB |
421 | static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) |
422 | { | |
423 | if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) | |
424 | return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); | |
425 | ||
426 | return false; | |
427 | } | |
428 | ||
7ebd7a3a JCPV |
429 | static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) |
430 | { | |
431 | if (is_on) | |
432 | __raw_writel(mask, pio + PIO_IFSCDR); | |
433 | at91_mux_set_deglitch(pio, mask, is_on); | |
434 | } | |
435 | ||
436 | static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) | |
437 | { | |
438 | *div = __raw_readl(pio + PIO_SCDR); | |
439 | ||
c8dba02e BB |
440 | return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && |
441 | ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); | |
7ebd7a3a JCPV |
442 | } |
443 | ||
444 | static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, | |
445 | bool is_on, u32 div) | |
446 | { | |
447 | if (is_on) { | |
448 | __raw_writel(mask, pio + PIO_IFSCER); | |
449 | __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); | |
450 | __raw_writel(mask, pio + PIO_IFER); | |
c8dba02e BB |
451 | } else |
452 | __raw_writel(mask, pio + PIO_IFSCDR); | |
7ebd7a3a JCPV |
453 | } |
454 | ||
455 | static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) | |
456 | { | |
05d3534a | 457 | return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); |
7ebd7a3a JCPV |
458 | } |
459 | ||
460 | static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) | |
461 | { | |
462 | __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); | |
463 | } | |
464 | ||
465 | static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) | |
466 | { | |
467 | __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); | |
468 | } | |
469 | ||
470 | static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) | |
471 | { | |
472 | return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; | |
473 | } | |
474 | ||
6732ae5c JCPV |
475 | static struct at91_pinctrl_mux_ops at91rm9200_ops = { |
476 | .get_periph = at91_mux_get_periph, | |
477 | .mux_A_periph = at91_mux_set_A_periph, | |
478 | .mux_B_periph = at91_mux_set_B_periph, | |
7ebd7a3a JCPV |
479 | .get_deglitch = at91_mux_get_deglitch, |
480 | .set_deglitch = at91_mux_set_deglitch, | |
6732ae5c JCPV |
481 | .irq_type = gpio_irq_type, |
482 | }; | |
483 | ||
484 | static struct at91_pinctrl_mux_ops at91sam9x5_ops = { | |
485 | .get_periph = at91_mux_pio3_get_periph, | |
486 | .mux_A_periph = at91_mux_pio3_set_A_periph, | |
487 | .mux_B_periph = at91_mux_pio3_set_B_periph, | |
488 | .mux_C_periph = at91_mux_pio3_set_C_periph, | |
489 | .mux_D_periph = at91_mux_pio3_set_D_periph, | |
c8dba02e | 490 | .get_deglitch = at91_mux_pio3_get_deglitch, |
7ebd7a3a JCPV |
491 | .set_deglitch = at91_mux_pio3_set_deglitch, |
492 | .get_debounce = at91_mux_pio3_get_debounce, | |
493 | .set_debounce = at91_mux_pio3_set_debounce, | |
494 | .get_pulldown = at91_mux_pio3_get_pulldown, | |
495 | .set_pulldown = at91_mux_pio3_set_pulldown, | |
496 | .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, | |
497 | .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, | |
6732ae5c JCPV |
498 | .irq_type = alt_gpio_irq_type, |
499 | }; | |
500 | ||
501 | static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) | |
502 | { | |
503 | if (pin->mux) { | |
504 | dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lu\n", | |
505 | pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); | |
506 | } else { | |
507 | dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lu\n", | |
508 | pin->bank + 'A', pin->pin, pin->conf); | |
509 | } | |
510 | } | |
511 | ||
3c93600d | 512 | static int pin_check_config(struct at91_pinctrl *info, const char *name, |
6732ae5c JCPV |
513 | int index, const struct at91_pmx_pin *pin) |
514 | { | |
515 | int mux; | |
516 | ||
517 | /* check if it's a valid config */ | |
518 | if (pin->bank >= info->nbanks) { | |
519 | dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", | |
520 | name, index, pin->bank, info->nbanks); | |
521 | return -EINVAL; | |
522 | } | |
523 | ||
524 | if (pin->pin >= MAX_NB_GPIO_PER_BANK) { | |
525 | dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", | |
526 | name, index, pin->pin, MAX_NB_GPIO_PER_BANK); | |
527 | return -EINVAL; | |
528 | } | |
529 | ||
530 | if (!pin->mux) | |
531 | return 0; | |
532 | ||
533 | mux = pin->mux - 1; | |
534 | ||
535 | if (mux >= info->nmux) { | |
536 | dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", | |
537 | name, index, mux, info->nmux); | |
538 | return -EINVAL; | |
539 | } | |
540 | ||
541 | if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { | |
542 | dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", | |
543 | name, index, mux, pin->bank + 'A', pin->pin); | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
547 | return 0; | |
548 | } | |
549 | ||
550 | static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) | |
551 | { | |
552 | writel_relaxed(mask, pio + PIO_PDR); | |
553 | } | |
554 | ||
555 | static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) | |
556 | { | |
557 | writel_relaxed(mask, pio + PIO_PER); | |
558 | writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); | |
559 | } | |
560 | ||
561 | static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
562 | unsigned group) | |
563 | { | |
564 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
565 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
566 | const struct at91_pmx_pin *pin; | |
567 | uint32_t npins = info->groups[group].npins; | |
568 | int i, ret; | |
569 | unsigned mask; | |
570 | void __iomem *pio; | |
571 | ||
572 | dev_dbg(info->dev, "enable function %s group %s\n", | |
573 | info->functions[selector].name, info->groups[group].name); | |
574 | ||
575 | /* first check that all the pins of the group are valid with a valid | |
61e310a1 | 576 | * parameter */ |
6732ae5c JCPV |
577 | for (i = 0; i < npins; i++) { |
578 | pin = &pins_conf[i]; | |
579 | ret = pin_check_config(info, info->groups[group].name, i, pin); | |
580 | if (ret) | |
581 | return ret; | |
582 | } | |
583 | ||
584 | for (i = 0; i < npins; i++) { | |
585 | pin = &pins_conf[i]; | |
586 | at91_pin_dbg(info->dev, pin); | |
587 | pio = pin_to_controller(info, pin->bank); | |
588 | mask = pin_to_mask(pin->pin); | |
589 | at91_mux_disable_interrupt(pio, mask); | |
3c93600d | 590 | switch (pin->mux) { |
6732ae5c JCPV |
591 | case AT91_MUX_GPIO: |
592 | at91_mux_gpio_enable(pio, mask, 1); | |
593 | break; | |
594 | case AT91_MUX_PERIPH_A: | |
595 | info->ops->mux_A_periph(pio, mask); | |
596 | break; | |
597 | case AT91_MUX_PERIPH_B: | |
598 | info->ops->mux_B_periph(pio, mask); | |
599 | break; | |
600 | case AT91_MUX_PERIPH_C: | |
601 | if (!info->ops->mux_C_periph) | |
602 | return -EINVAL; | |
603 | info->ops->mux_C_periph(pio, mask); | |
604 | break; | |
605 | case AT91_MUX_PERIPH_D: | |
606 | if (!info->ops->mux_D_periph) | |
607 | return -EINVAL; | |
608 | info->ops->mux_D_periph(pio, mask); | |
609 | break; | |
610 | } | |
611 | if (pin->mux) | |
612 | at91_mux_gpio_disable(pio, mask); | |
613 | } | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static void at91_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, | |
619 | unsigned group) | |
620 | { | |
621 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
622 | const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; | |
623 | const struct at91_pmx_pin *pin; | |
624 | uint32_t npins = info->groups[group].npins; | |
625 | int i; | |
626 | unsigned mask; | |
627 | void __iomem *pio; | |
628 | ||
629 | for (i = 0; i < npins; i++) { | |
630 | pin = &pins_conf[i]; | |
631 | at91_pin_dbg(info->dev, pin); | |
632 | pio = pin_to_controller(info, pin->bank); | |
633 | mask = pin_to_mask(pin->pin); | |
634 | at91_mux_gpio_enable(pio, mask, 1); | |
635 | } | |
636 | } | |
637 | ||
638 | static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
639 | { | |
640 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
641 | ||
642 | return info->nfunctions; | |
643 | } | |
644 | ||
645 | static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
646 | unsigned selector) | |
647 | { | |
648 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
649 | ||
650 | return info->functions[selector].name; | |
651 | } | |
652 | ||
653 | static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
654 | const char * const **groups, | |
655 | unsigned * const num_groups) | |
656 | { | |
657 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
658 | ||
659 | *groups = info->functions[selector].groups; | |
660 | *num_groups = info->functions[selector].ngroups; | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
f6f94f66 AL |
665 | static int at91_gpio_request_enable(struct pinctrl_dev *pctldev, |
666 | struct pinctrl_gpio_range *range, | |
667 | unsigned offset) | |
6732ae5c JCPV |
668 | { |
669 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
670 | struct at91_gpio_chip *at91_chip; | |
671 | struct gpio_chip *chip; | |
672 | unsigned mask; | |
673 | ||
674 | if (!range) { | |
675 | dev_err(npct->dev, "invalid range\n"); | |
676 | return -EINVAL; | |
677 | } | |
678 | if (!range->gc) { | |
679 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
680 | return -EINVAL; | |
681 | } | |
682 | chip = range->gc; | |
683 | at91_chip = container_of(chip, struct at91_gpio_chip, chip); | |
684 | ||
685 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
686 | ||
687 | mask = 1 << (offset - chip->base); | |
688 | ||
689 | dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", | |
690 | offset, 'A' + range->id, offset - chip->base, mask); | |
691 | ||
692 | writel_relaxed(mask, at91_chip->regbase + PIO_PER); | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
f6f94f66 AL |
697 | static void at91_gpio_disable_free(struct pinctrl_dev *pctldev, |
698 | struct pinctrl_gpio_range *range, | |
699 | unsigned offset) | |
6732ae5c JCPV |
700 | { |
701 | struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
702 | ||
703 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
704 | /* Set the pin to some default state, GPIO is usually default */ | |
705 | } | |
706 | ||
022ab148 | 707 | static const struct pinmux_ops at91_pmx_ops = { |
6732ae5c JCPV |
708 | .get_functions_count = at91_pmx_get_funcs_count, |
709 | .get_function_name = at91_pmx_get_func_name, | |
710 | .get_function_groups = at91_pmx_get_groups, | |
711 | .enable = at91_pmx_enable, | |
712 | .disable = at91_pmx_disable, | |
713 | .gpio_request_enable = at91_gpio_request_enable, | |
714 | .gpio_disable_free = at91_gpio_disable_free, | |
715 | }; | |
716 | ||
717 | static int at91_pinconf_get(struct pinctrl_dev *pctldev, | |
718 | unsigned pin_id, unsigned long *config) | |
719 | { | |
720 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
721 | void __iomem *pio; | |
722 | unsigned pin; | |
7ebd7a3a | 723 | int div; |
6732ae5c JCPV |
724 | |
725 | dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); | |
726 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
727 | pin = pin_id % MAX_NB_GPIO_PER_BANK; | |
728 | ||
729 | if (at91_mux_get_multidrive(pio, pin)) | |
730 | *config |= MULTI_DRIVE; | |
731 | ||
732 | if (at91_mux_get_pullup(pio, pin)) | |
733 | *config |= PULL_UP; | |
734 | ||
7ebd7a3a JCPV |
735 | if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) |
736 | *config |= DEGLITCH; | |
737 | if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) | |
738 | *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); | |
739 | if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) | |
740 | *config |= PULL_DOWN; | |
741 | if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) | |
742 | *config |= DIS_SCHMIT; | |
743 | ||
6732ae5c JCPV |
744 | return 0; |
745 | } | |
746 | ||
747 | static int at91_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
748 | unsigned pin_id, unsigned long *configs, |
749 | unsigned num_configs) | |
6732ae5c JCPV |
750 | { |
751 | struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
752 | unsigned mask; | |
753 | void __iomem *pio; | |
03b054e9 SY |
754 | int i; |
755 | unsigned long config; | |
756 | ||
757 | for (i = 0; i < num_configs; i++) { | |
758 | config = configs[i]; | |
759 | ||
760 | dev_dbg(info->dev, | |
761 | "%s:%d, pin_id=%d, config=0x%lx", | |
762 | __func__, __LINE__, pin_id, config); | |
763 | pio = pin_to_controller(info, pin_to_bank(pin_id)); | |
764 | mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); | |
765 | ||
766 | if (config & PULL_UP && config & PULL_DOWN) | |
767 | return -EINVAL; | |
768 | ||
769 | at91_mux_set_pullup(pio, mask, config & PULL_UP); | |
770 | at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); | |
771 | if (info->ops->set_deglitch) | |
772 | info->ops->set_deglitch(pio, mask, config & DEGLITCH); | |
773 | if (info->ops->set_debounce) | |
774 | info->ops->set_debounce(pio, mask, config & DEBOUNCE, | |
7ebd7a3a | 775 | (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT); |
03b054e9 SY |
776 | if (info->ops->set_pulldown) |
777 | info->ops->set_pulldown(pio, mask, config & PULL_DOWN); | |
778 | if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) | |
779 | info->ops->disable_schmitt_trig(pio, mask); | |
780 | ||
781 | } /* for each config */ | |
7ebd7a3a | 782 | |
6732ae5c JCPV |
783 | return 0; |
784 | } | |
785 | ||
786 | static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
787 | struct seq_file *s, unsigned pin_id) | |
788 | { | |
789 | ||
790 | } | |
791 | ||
792 | static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
793 | struct seq_file *s, unsigned group) | |
794 | { | |
795 | } | |
796 | ||
022ab148 | 797 | static const struct pinconf_ops at91_pinconf_ops = { |
6732ae5c JCPV |
798 | .pin_config_get = at91_pinconf_get, |
799 | .pin_config_set = at91_pinconf_set, | |
800 | .pin_config_dbg_show = at91_pinconf_dbg_show, | |
801 | .pin_config_group_dbg_show = at91_pinconf_group_dbg_show, | |
802 | }; | |
803 | ||
804 | static struct pinctrl_desc at91_pinctrl_desc = { | |
805 | .pctlops = &at91_pctrl_ops, | |
806 | .pmxops = &at91_pmx_ops, | |
807 | .confops = &at91_pinconf_ops, | |
808 | .owner = THIS_MODULE, | |
809 | }; | |
810 | ||
811 | static const char *gpio_compat = "atmel,at91rm9200-gpio"; | |
812 | ||
150632b0 GKH |
813 | static void at91_pinctrl_child_count(struct at91_pinctrl *info, |
814 | struct device_node *np) | |
6732ae5c JCPV |
815 | { |
816 | struct device_node *child; | |
817 | ||
818 | for_each_child_of_node(np, child) { | |
819 | if (of_device_is_compatible(child, gpio_compat)) { | |
820 | info->nbanks++; | |
821 | } else { | |
822 | info->nfunctions++; | |
823 | info->ngroups += of_get_child_count(child); | |
824 | } | |
825 | } | |
826 | } | |
827 | ||
150632b0 GKH |
828 | static int at91_pinctrl_mux_mask(struct at91_pinctrl *info, |
829 | struct device_node *np) | |
6732ae5c JCPV |
830 | { |
831 | int ret = 0; | |
832 | int size; | |
1164d73a | 833 | const __be32 *list; |
6732ae5c JCPV |
834 | |
835 | list = of_get_property(np, "atmel,mux-mask", &size); | |
836 | if (!list) { | |
837 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
838 | return -EINVAL; | |
839 | } | |
840 | ||
841 | size /= sizeof(*list); | |
842 | if (!size || size % info->nbanks) { | |
843 | dev_err(info->dev, "wrong mux mask array should be by %d\n", info->nbanks); | |
844 | return -EINVAL; | |
845 | } | |
846 | info->nmux = size / info->nbanks; | |
847 | ||
848 | info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL); | |
849 | if (!info->mux_mask) { | |
850 | dev_err(info->dev, "could not alloc mux_mask\n"); | |
851 | return -ENOMEM; | |
852 | } | |
853 | ||
854 | ret = of_property_read_u32_array(np, "atmel,mux-mask", | |
855 | info->mux_mask, size); | |
856 | if (ret) | |
857 | dev_err(info->dev, "can not read the mux-mask of %d\n", size); | |
858 | return ret; | |
859 | } | |
860 | ||
150632b0 GKH |
861 | static int at91_pinctrl_parse_groups(struct device_node *np, |
862 | struct at91_pin_group *grp, | |
863 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
864 | { |
865 | struct at91_pmx_pin *pin; | |
866 | int size; | |
1164d73a | 867 | const __be32 *list; |
6732ae5c JCPV |
868 | int i, j; |
869 | ||
870 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
871 | ||
872 | /* Initialise group */ | |
873 | grp->name = np->name; | |
874 | ||
875 | /* | |
876 | * the binding format is atmel,pins = <bank pin mux CONFIG ...>, | |
877 | * do sanity check and calculate pins number | |
878 | */ | |
879 | list = of_get_property(np, "atmel,pins", &size); | |
880 | /* we do not check return since it's safe node passed down */ | |
881 | size /= sizeof(*list); | |
882 | if (!size || size % 4) { | |
883 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
884 | return -EINVAL; | |
885 | } | |
886 | ||
887 | grp->npins = size / 4; | |
888 | pin = grp->pins_conf = devm_kzalloc(info->dev, grp->npins * sizeof(struct at91_pmx_pin), | |
889 | GFP_KERNEL); | |
890 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
891 | GFP_KERNEL); | |
892 | if (!grp->pins_conf || !grp->pins) | |
893 | return -ENOMEM; | |
894 | ||
895 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
896 | pin->bank = be32_to_cpu(*list++); | |
897 | pin->pin = be32_to_cpu(*list++); | |
898 | grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; | |
899 | pin->mux = be32_to_cpu(*list++); | |
900 | pin->conf = be32_to_cpu(*list++); | |
901 | ||
902 | at91_pin_dbg(info->dev, pin); | |
903 | pin++; | |
904 | } | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
150632b0 GKH |
909 | static int at91_pinctrl_parse_functions(struct device_node *np, |
910 | struct at91_pinctrl *info, u32 index) | |
6732ae5c JCPV |
911 | { |
912 | struct device_node *child; | |
913 | struct at91_pmx_func *func; | |
914 | struct at91_pin_group *grp; | |
915 | int ret; | |
916 | static u32 grp_index; | |
917 | u32 i = 0; | |
918 | ||
919 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
920 | ||
921 | func = &info->functions[index]; | |
922 | ||
923 | /* Initialise function */ | |
924 | func->name = np->name; | |
925 | func->ngroups = of_get_child_count(np); | |
926 | if (func->ngroups <= 0) { | |
927 | dev_err(info->dev, "no groups defined\n"); | |
928 | return -EINVAL; | |
929 | } | |
930 | func->groups = devm_kzalloc(info->dev, | |
931 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
932 | if (!func->groups) | |
933 | return -ENOMEM; | |
934 | ||
935 | for_each_child_of_node(np, child) { | |
936 | func->groups[i] = child->name; | |
937 | grp = &info->groups[grp_index++]; | |
938 | ret = at91_pinctrl_parse_groups(child, grp, info, i++); | |
939 | if (ret) | |
940 | return ret; | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
150632b0 | 946 | static struct of_device_id at91_pinctrl_of_match[] = { |
6732ae5c JCPV |
947 | { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, |
948 | { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, | |
949 | { /* sentinel */ } | |
950 | }; | |
951 | ||
150632b0 GKH |
952 | static int at91_pinctrl_probe_dt(struct platform_device *pdev, |
953 | struct at91_pinctrl *info) | |
6732ae5c JCPV |
954 | { |
955 | int ret = 0; | |
956 | int i, j; | |
957 | uint32_t *tmp; | |
958 | struct device_node *np = pdev->dev.of_node; | |
959 | struct device_node *child; | |
960 | ||
961 | if (!np) | |
962 | return -ENODEV; | |
963 | ||
964 | info->dev = &pdev->dev; | |
3c93600d | 965 | info->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
966 | of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; |
967 | at91_pinctrl_child_count(info, np); | |
968 | ||
969 | if (info->nbanks < 1) { | |
61e310a1 | 970 | dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); |
6732ae5c JCPV |
971 | return -EINVAL; |
972 | } | |
973 | ||
974 | ret = at91_pinctrl_mux_mask(info, np); | |
975 | if (ret) | |
976 | return ret; | |
977 | ||
978 | dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); | |
979 | ||
980 | dev_dbg(&pdev->dev, "mux-mask\n"); | |
981 | tmp = info->mux_mask; | |
982 | for (i = 0; i < info->nbanks; i++) { | |
983 | for (j = 0; j < info->nmux; j++, tmp++) { | |
984 | dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); | |
985 | } | |
986 | } | |
987 | ||
988 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
989 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
990 | info->functions = devm_kzalloc(&pdev->dev, info->nfunctions * sizeof(struct at91_pmx_func), | |
991 | GFP_KERNEL); | |
992 | if (!info->functions) | |
993 | return -ENOMEM; | |
994 | ||
995 | info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct at91_pin_group), | |
996 | GFP_KERNEL); | |
997 | if (!info->groups) | |
998 | return -ENOMEM; | |
999 | ||
1000 | dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks); | |
1001 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1002 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1003 | ||
1004 | i = 0; | |
1005 | ||
1006 | for_each_child_of_node(np, child) { | |
1007 | if (of_device_is_compatible(child, gpio_compat)) | |
1008 | continue; | |
1009 | ret = at91_pinctrl_parse_functions(child, info, i++); | |
1010 | if (ret) { | |
1011 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1012 | return ret; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
150632b0 | 1019 | static int at91_pinctrl_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1020 | { |
1021 | struct at91_pinctrl *info; | |
1022 | struct pinctrl_pin_desc *pdesc; | |
3c93600d | 1023 | int ret, i, j, k; |
6732ae5c JCPV |
1024 | |
1025 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
1026 | if (!info) | |
1027 | return -ENOMEM; | |
1028 | ||
1029 | ret = at91_pinctrl_probe_dt(pdev, info); | |
1030 | if (ret) | |
1031 | return ret; | |
1032 | ||
1033 | /* | |
1034 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
1035 | * to obtain references to the struct gpio_chip * for them, and we | |
1036 | * need this to proceed. | |
1037 | */ | |
1038 | for (i = 0; i < info->nbanks; i++) { | |
1039 | if (!gpio_chips[i]) { | |
1040 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | |
1041 | devm_kfree(&pdev->dev, info); | |
1042 | return -EPROBE_DEFER; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | at91_pinctrl_desc.name = dev_name(&pdev->dev); | |
1047 | at91_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK; | |
1048 | at91_pinctrl_desc.pins = pdesc = | |
1049 | devm_kzalloc(&pdev->dev, sizeof(*pdesc) * at91_pinctrl_desc.npins, GFP_KERNEL); | |
1050 | ||
1051 | if (!at91_pinctrl_desc.pins) | |
1052 | return -ENOMEM; | |
1053 | ||
1054 | for (i = 0 , k = 0; i < info->nbanks; i++) { | |
1055 | for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) { | |
1056 | pdesc->number = k; | |
1057 | pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); | |
1058 | pdesc++; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | platform_set_drvdata(pdev, info); | |
1063 | info->pctl = pinctrl_register(&at91_pinctrl_desc, &pdev->dev, info); | |
1064 | ||
1065 | if (!info->pctl) { | |
1066 | dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); | |
1067 | ret = -EINVAL; | |
1068 | goto err; | |
1069 | } | |
1070 | ||
1071 | /* We will handle a range of GPIO pins */ | |
1072 | for (i = 0; i < info->nbanks; i++) | |
1073 | pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); | |
1074 | ||
1075 | dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); | |
1076 | ||
1077 | return 0; | |
1078 | ||
1079 | err: | |
1080 | return ret; | |
1081 | } | |
1082 | ||
150632b0 | 1083 | static int at91_pinctrl_remove(struct platform_device *pdev) |
6732ae5c JCPV |
1084 | { |
1085 | struct at91_pinctrl *info = platform_get_drvdata(pdev); | |
1086 | ||
1087 | pinctrl_unregister(info->pctl); | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static int at91_gpio_request(struct gpio_chip *chip, unsigned offset) | |
1093 | { | |
1094 | /* | |
1095 | * Map back to global GPIO space and request muxing, the direction | |
1096 | * parameter does not matter for this controller. | |
1097 | */ | |
1098 | int gpio = chip->base + offset; | |
1099 | int bank = chip->base / chip->ngpio; | |
1100 | ||
1101 | dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__, | |
1102 | 'A' + bank, offset, gpio); | |
1103 | ||
1104 | return pinctrl_request_gpio(gpio); | |
1105 | } | |
1106 | ||
1107 | static void at91_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1108 | { | |
1109 | int gpio = chip->base + offset; | |
1110 | ||
1111 | pinctrl_free_gpio(gpio); | |
1112 | } | |
1113 | ||
1114 | static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
1115 | { | |
1116 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1117 | void __iomem *pio = at91_gpio->regbase; | |
1118 | unsigned mask = 1 << offset; | |
1119 | ||
1120 | writel_relaxed(mask, pio + PIO_ODR); | |
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static int at91_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1125 | { | |
1126 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1127 | void __iomem *pio = at91_gpio->regbase; | |
1128 | unsigned mask = 1 << offset; | |
1129 | u32 pdsr; | |
1130 | ||
1131 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1132 | return (pdsr & mask) != 0; | |
1133 | } | |
1134 | ||
1135 | static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, | |
1136 | int val) | |
1137 | { | |
1138 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1139 | void __iomem *pio = at91_gpio->regbase; | |
1140 | unsigned mask = 1 << offset; | |
1141 | ||
1142 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1143 | } | |
1144 | ||
1145 | static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
1146 | int val) | |
1147 | { | |
1148 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1149 | void __iomem *pio = at91_gpio->regbase; | |
1150 | unsigned mask = 1 << offset; | |
1151 | ||
1152 | writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); | |
1153 | writel_relaxed(mask, pio + PIO_OER); | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | static int at91_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
1159 | { | |
1160 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1161 | int virq; | |
1162 | ||
1163 | if (offset < chip->ngpio) | |
1164 | virq = irq_create_mapping(at91_gpio->domain, offset); | |
1165 | else | |
1166 | virq = -ENXIO; | |
1167 | ||
1168 | dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", | |
1169 | chip->label, offset + chip->base, virq); | |
1170 | return virq; | |
1171 | } | |
1172 | ||
1173 | #ifdef CONFIG_DEBUG_FS | |
1174 | static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1175 | { | |
1176 | enum at91_mux mode; | |
1177 | int i; | |
1178 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | |
1179 | void __iomem *pio = at91_gpio->regbase; | |
1180 | ||
1181 | for (i = 0; i < chip->ngpio; i++) { | |
1182 | unsigned pin = chip->base + i; | |
1183 | unsigned mask = pin_to_mask(pin); | |
1184 | const char *gpio_label; | |
1185 | u32 pdsr; | |
1186 | ||
1187 | gpio_label = gpiochip_is_requested(chip, i); | |
1188 | if (!gpio_label) | |
1189 | continue; | |
1190 | mode = at91_gpio->ops->get_periph(pio, mask); | |
1191 | seq_printf(s, "[%s] GPIO%s%d: ", | |
1192 | gpio_label, chip->label, i); | |
1193 | if (mode == AT91_MUX_GPIO) { | |
1194 | pdsr = readl_relaxed(pio + PIO_PDSR); | |
1195 | ||
1196 | seq_printf(s, "[gpio] %s\n", | |
1197 | pdsr & mask ? | |
1198 | "set" : "clear"); | |
1199 | } else { | |
1200 | seq_printf(s, "[periph %c]\n", | |
1201 | mode + 'A' - 1); | |
1202 | } | |
1203 | } | |
1204 | } | |
1205 | #else | |
1206 | #define at91_gpio_dbg_show NULL | |
1207 | #endif | |
1208 | ||
1209 | /* Several AIC controller irqs are dispatched through this GPIO handler. | |
1210 | * To use any AT91_PIN_* as an externally triggered IRQ, first call | |
1211 | * at91_set_gpio_input() then maybe enable its glitch filter. | |
1212 | * Then just request_irq() with the pin ID; it works like any ARM IRQ | |
1213 | * handler. | |
1214 | * First implementation always triggers on rising and falling edges | |
1215 | * whereas the newer PIO3 can be additionally configured to trigger on | |
1216 | * level, edge with any polarity. | |
1217 | * | |
1218 | * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after | |
1219 | * configuring them with at91_set_a_periph() or at91_set_b_periph(). | |
1220 | * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. | |
1221 | */ | |
1222 | ||
1223 | static void gpio_irq_mask(struct irq_data *d) | |
1224 | { | |
1225 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1226 | void __iomem *pio = at91_gpio->regbase; | |
1227 | unsigned mask = 1 << d->hwirq; | |
1228 | ||
1229 | if (pio) | |
1230 | writel_relaxed(mask, pio + PIO_IDR); | |
1231 | } | |
1232 | ||
1233 | static void gpio_irq_unmask(struct irq_data *d) | |
1234 | { | |
1235 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1236 | void __iomem *pio = at91_gpio->regbase; | |
1237 | unsigned mask = 1 << d->hwirq; | |
1238 | ||
1239 | if (pio) | |
1240 | writel_relaxed(mask, pio + PIO_IER); | |
1241 | } | |
1242 | ||
1243 | static int gpio_irq_type(struct irq_data *d, unsigned type) | |
1244 | { | |
1245 | switch (type) { | |
1246 | case IRQ_TYPE_NONE: | |
1247 | case IRQ_TYPE_EDGE_BOTH: | |
1248 | return 0; | |
1249 | default: | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | } | |
1253 | ||
1254 | /* Alternate irq type for PIO3 support */ | |
1255 | static int alt_gpio_irq_type(struct irq_data *d, unsigned type) | |
1256 | { | |
1257 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1258 | void __iomem *pio = at91_gpio->regbase; | |
1259 | unsigned mask = 1 << d->hwirq; | |
1260 | ||
1261 | switch (type) { | |
1262 | case IRQ_TYPE_EDGE_RISING: | |
99fce029 | 1263 | irq_set_handler(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1264 | writel_relaxed(mask, pio + PIO_ESR); |
1265 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1266 | break; | |
1267 | case IRQ_TYPE_EDGE_FALLING: | |
99fce029 | 1268 | irq_set_handler(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1269 | writel_relaxed(mask, pio + PIO_ESR); |
1270 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1271 | break; | |
1272 | case IRQ_TYPE_LEVEL_LOW: | |
99fce029 | 1273 | irq_set_handler(d->irq, handle_level_irq); |
6732ae5c JCPV |
1274 | writel_relaxed(mask, pio + PIO_LSR); |
1275 | writel_relaxed(mask, pio + PIO_FELLSR); | |
1276 | break; | |
1277 | case IRQ_TYPE_LEVEL_HIGH: | |
99fce029 | 1278 | irq_set_handler(d->irq, handle_level_irq); |
6732ae5c JCPV |
1279 | writel_relaxed(mask, pio + PIO_LSR); |
1280 | writel_relaxed(mask, pio + PIO_REHLSR); | |
1281 | break; | |
1282 | case IRQ_TYPE_EDGE_BOTH: | |
1283 | /* | |
1284 | * disable additional interrupt modes: | |
1285 | * fall back to default behavior | |
1286 | */ | |
99fce029 | 1287 | irq_set_handler(d->irq, handle_simple_irq); |
6732ae5c JCPV |
1288 | writel_relaxed(mask, pio + PIO_AIMDR); |
1289 | return 0; | |
1290 | case IRQ_TYPE_NONE: | |
1291 | default: | |
1292 | pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); | |
1293 | return -EINVAL; | |
1294 | } | |
1295 | ||
1296 | /* enable additional interrupt modes */ | |
1297 | writel_relaxed(mask, pio + PIO_AIMER); | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | #ifdef CONFIG_PM | |
647f8d94 LD |
1303 | |
1304 | static u32 wakeups[MAX_GPIO_BANKS]; | |
1305 | static u32 backups[MAX_GPIO_BANKS]; | |
1306 | ||
6732ae5c JCPV |
1307 | static int gpio_irq_set_wake(struct irq_data *d, unsigned state) |
1308 | { | |
1309 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); | |
1310 | unsigned bank = at91_gpio->pioc_idx; | |
647f8d94 | 1311 | unsigned mask = 1 << d->hwirq; |
6732ae5c JCPV |
1312 | |
1313 | if (unlikely(bank >= MAX_GPIO_BANKS)) | |
1314 | return -EINVAL; | |
1315 | ||
647f8d94 LD |
1316 | if (state) |
1317 | wakeups[bank] |= mask; | |
1318 | else | |
1319 | wakeups[bank] &= ~mask; | |
1320 | ||
6732ae5c JCPV |
1321 | irq_set_irq_wake(at91_gpio->pioc_virq, state); |
1322 | ||
1323 | return 0; | |
1324 | } | |
647f8d94 LD |
1325 | |
1326 | void at91_pinctrl_gpio_suspend(void) | |
1327 | { | |
1328 | int i; | |
1329 | ||
1330 | for (i = 0; i < gpio_banks; i++) { | |
1331 | void __iomem *pio; | |
1332 | ||
1333 | if (!gpio_chips[i]) | |
1334 | continue; | |
1335 | ||
1336 | pio = gpio_chips[i]->regbase; | |
1337 | ||
1338 | backups[i] = __raw_readl(pio + PIO_IMR); | |
1339 | __raw_writel(backups[i], pio + PIO_IDR); | |
1340 | __raw_writel(wakeups[i], pio + PIO_IER); | |
1341 | ||
1342 | if (!wakeups[i]) { | |
1343 | clk_unprepare(gpio_chips[i]->clock); | |
1344 | clk_disable(gpio_chips[i]->clock); | |
1345 | } else { | |
1346 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", | |
1347 | 'A'+i, wakeups[i]); | |
1348 | } | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | void at91_pinctrl_gpio_resume(void) | |
1353 | { | |
1354 | int i; | |
1355 | ||
1356 | for (i = 0; i < gpio_banks; i++) { | |
1357 | void __iomem *pio; | |
1358 | ||
1359 | if (!gpio_chips[i]) | |
1360 | continue; | |
1361 | ||
1362 | pio = gpio_chips[i]->regbase; | |
1363 | ||
1364 | if (!wakeups[i]) { | |
1365 | if (clk_prepare(gpio_chips[i]->clock) == 0) | |
1366 | clk_enable(gpio_chips[i]->clock); | |
1367 | } | |
1368 | ||
1369 | __raw_writel(wakeups[i], pio + PIO_IDR); | |
1370 | __raw_writel(backups[i], pio + PIO_IER); | |
1371 | } | |
1372 | } | |
1373 | ||
6732ae5c JCPV |
1374 | #else |
1375 | #define gpio_irq_set_wake NULL | |
647f8d94 | 1376 | #endif /* CONFIG_PM */ |
6732ae5c JCPV |
1377 | |
1378 | static struct irq_chip gpio_irqchip = { | |
1379 | .name = "GPIO", | |
1380 | .irq_disable = gpio_irq_mask, | |
1381 | .irq_mask = gpio_irq_mask, | |
1382 | .irq_unmask = gpio_irq_unmask, | |
1383 | /* .irq_set_type is set dynamically */ | |
1384 | .irq_set_wake = gpio_irq_set_wake, | |
1385 | }; | |
1386 | ||
1387 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
1388 | { | |
1389 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
1390 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
1391 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | |
1392 | void __iomem *pio = at91_gpio->regbase; | |
1393 | unsigned long isr; | |
1394 | int n; | |
1395 | ||
1396 | chained_irq_enter(chip, desc); | |
1397 | for (;;) { | |
1398 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | |
1399 | * When there none are pending, we're finished unless we need | |
1400 | * to process multiple banks (like ID_PIOCDE on sam9263). | |
1401 | */ | |
1402 | isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); | |
1403 | if (!isr) { | |
1404 | if (!at91_gpio->next) | |
1405 | break; | |
1406 | at91_gpio = at91_gpio->next; | |
1407 | pio = at91_gpio->regbase; | |
1408 | continue; | |
1409 | } | |
1410 | ||
05daa16a | 1411 | for_each_set_bit(n, &isr, BITS_PER_LONG) { |
6732ae5c | 1412 | generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); |
6732ae5c JCPV |
1413 | } |
1414 | } | |
1415 | chained_irq_exit(chip, desc); | |
1416 | /* now it may re-trigger */ | |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * This lock class tells lockdep that GPIO irqs are in a different | |
1421 | * category than their parents, so it won't report false recursion. | |
1422 | */ | |
1423 | static struct lock_class_key gpio_lock_class; | |
1424 | ||
1425 | static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq, | |
1426 | irq_hw_number_t hw) | |
1427 | { | |
1428 | struct at91_gpio_chip *at91_gpio = h->host_data; | |
99fce029 BB |
1429 | void __iomem *pio = at91_gpio->regbase; |
1430 | u32 mask = 1 << hw; | |
6732ae5c JCPV |
1431 | |
1432 | irq_set_lockdep_class(virq, &gpio_lock_class); | |
1433 | ||
1434 | /* | |
1435 | * Can use the "simple" and not "edge" handler since it's | |
1436 | * shorter, and the AIC handles interrupts sanely. | |
1437 | */ | |
99fce029 BB |
1438 | irq_set_chip(virq, &gpio_irqchip); |
1439 | if ((at91_gpio->ops == &at91sam9x5_ops) && | |
1440 | (readl_relaxed(pio + PIO_AIMMR) & mask) && | |
1441 | (readl_relaxed(pio + PIO_ELSR) & mask)) | |
1442 | irq_set_handler(virq, handle_level_irq); | |
1443 | else | |
1444 | irq_set_handler(virq, handle_simple_irq); | |
6732ae5c JCPV |
1445 | set_irq_flags(virq, IRQF_VALID); |
1446 | irq_set_chip_data(virq, at91_gpio); | |
1447 | ||
1448 | return 0; | |
1449 | } | |
1450 | ||
f6f94f66 AL |
1451 | static int at91_gpio_irq_domain_xlate(struct irq_domain *d, |
1452 | struct device_node *ctrlr, | |
1453 | const u32 *intspec, unsigned int intsize, | |
1454 | irq_hw_number_t *out_hwirq, | |
1455 | unsigned int *out_type) | |
a728c7cd JCPV |
1456 | { |
1457 | struct at91_gpio_chip *at91_gpio = d->host_data; | |
1458 | int ret; | |
1459 | int pin = at91_gpio->chip.base + intspec[0]; | |
1460 | ||
1461 | if (WARN_ON(intsize < 2)) | |
1462 | return -EINVAL; | |
1463 | *out_hwirq = intspec[0]; | |
1464 | *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; | |
1465 | ||
1466 | ret = gpio_request(pin, ctrlr->full_name); | |
1467 | if (ret) | |
1468 | return ret; | |
1469 | ||
1470 | ret = gpio_direction_input(pin); | |
1471 | if (ret) | |
1472 | return ret; | |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | ||
6732ae5c JCPV |
1477 | static struct irq_domain_ops at91_gpio_ops = { |
1478 | .map = at91_gpio_irq_map, | |
a728c7cd | 1479 | .xlate = at91_gpio_irq_domain_xlate, |
6732ae5c JCPV |
1480 | }; |
1481 | ||
1482 | static int at91_gpio_of_irq_setup(struct device_node *node, | |
1483 | struct at91_gpio_chip *at91_gpio) | |
1484 | { | |
1485 | struct at91_gpio_chip *prev = NULL; | |
1486 | struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); | |
1487 | ||
1488 | at91_gpio->pioc_hwirq = irqd_to_hwirq(d); | |
1489 | ||
1490 | /* Setup proper .irq_set_type function */ | |
1491 | gpio_irqchip.irq_set_type = at91_gpio->ops->irq_type; | |
1492 | ||
1493 | /* Disable irqs of this PIO controller */ | |
1494 | writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); | |
1495 | ||
1496 | /* Setup irq domain */ | |
1497 | at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio, | |
1498 | &at91_gpio_ops, at91_gpio); | |
1499 | if (!at91_gpio->domain) | |
1500 | panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", | |
1501 | at91_gpio->pioc_idx); | |
1502 | ||
1503 | /* Setup chained handler */ | |
1504 | if (at91_gpio->pioc_idx) | |
1505 | prev = gpio_chips[at91_gpio->pioc_idx - 1]; | |
1506 | ||
61e310a1 | 1507 | /* The top level handler handles one bank of GPIOs, except |
6732ae5c JCPV |
1508 | * on some SoC it can handles up to three... |
1509 | * We only set up the handler for the first of the list. | |
1510 | */ | |
1511 | if (prev && prev->next == at91_gpio) | |
1512 | return 0; | |
1513 | ||
1514 | irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio); | |
1515 | irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler); | |
1516 | ||
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | /* This structure is replicated for each GPIO block allocated at probe time */ | |
1521 | static struct gpio_chip at91_gpio_template = { | |
1522 | .request = at91_gpio_request, | |
1523 | .free = at91_gpio_free, | |
1524 | .direction_input = at91_gpio_direction_input, | |
1525 | .get = at91_gpio_get, | |
1526 | .direction_output = at91_gpio_direction_output, | |
1527 | .set = at91_gpio_set, | |
1528 | .to_irq = at91_gpio_to_irq, | |
1529 | .dbg_show = at91_gpio_dbg_show, | |
1530 | .can_sleep = 0, | |
1531 | .ngpio = MAX_NB_GPIO_PER_BANK, | |
1532 | }; | |
1533 | ||
150632b0 | 1534 | static void at91_gpio_probe_fixup(void) |
6732ae5c JCPV |
1535 | { |
1536 | unsigned i; | |
1537 | struct at91_gpio_chip *at91_gpio, *last = NULL; | |
1538 | ||
1539 | for (i = 0; i < gpio_banks; i++) { | |
1540 | at91_gpio = gpio_chips[i]; | |
1541 | ||
1542 | /* | |
1543 | * GPIO controller are grouped on some SoC: | |
1544 | * PIOC, PIOD and PIOE can share the same IRQ line | |
1545 | */ | |
1546 | if (last && last->pioc_virq == at91_gpio->pioc_virq) | |
1547 | last->next = at91_gpio; | |
1548 | last = at91_gpio; | |
1549 | } | |
1550 | } | |
1551 | ||
150632b0 | 1552 | static struct of_device_id at91_gpio_of_match[] = { |
6732ae5c JCPV |
1553 | { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, |
1554 | { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, | |
1555 | { /* sentinel */ } | |
1556 | }; | |
1557 | ||
150632b0 | 1558 | static int at91_gpio_probe(struct platform_device *pdev) |
6732ae5c JCPV |
1559 | { |
1560 | struct device_node *np = pdev->dev.of_node; | |
1561 | struct resource *res; | |
1562 | struct at91_gpio_chip *at91_chip = NULL; | |
1563 | struct gpio_chip *chip; | |
1564 | struct pinctrl_gpio_range *range; | |
1565 | int ret = 0; | |
32b01a36 | 1566 | int irq, i; |
6732ae5c JCPV |
1567 | int alias_idx = of_alias_get_id(np, "gpio"); |
1568 | uint32_t ngpio; | |
32b01a36 | 1569 | char **names; |
6732ae5c JCPV |
1570 | |
1571 | BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips)); | |
1572 | if (gpio_chips[alias_idx]) { | |
1573 | ret = -EBUSY; | |
1574 | goto err; | |
1575 | } | |
1576 | ||
6732ae5c JCPV |
1577 | irq = platform_get_irq(pdev, 0); |
1578 | if (irq < 0) { | |
1579 | ret = irq; | |
1580 | goto err; | |
1581 | } | |
1582 | ||
1583 | at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); | |
1584 | if (!at91_chip) { | |
1585 | ret = -ENOMEM; | |
1586 | goto err; | |
1587 | } | |
1588 | ||
f50b9e12 | 1589 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
1590 | at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res); |
1591 | if (IS_ERR(at91_chip->regbase)) { | |
1592 | ret = PTR_ERR(at91_chip->regbase); | |
6732ae5c JCPV |
1593 | goto err; |
1594 | } | |
1595 | ||
3c93600d | 1596 | at91_chip->ops = (struct at91_pinctrl_mux_ops *) |
6732ae5c JCPV |
1597 | of_match_device(at91_gpio_of_match, &pdev->dev)->data; |
1598 | at91_chip->pioc_virq = irq; | |
1599 | at91_chip->pioc_idx = alias_idx; | |
1600 | ||
1601 | at91_chip->clock = clk_get(&pdev->dev, NULL); | |
1602 | if (IS_ERR(at91_chip->clock)) { | |
1603 | dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); | |
1604 | goto err; | |
1605 | } | |
1606 | ||
1607 | if (clk_prepare(at91_chip->clock)) | |
1608 | goto clk_prep_err; | |
1609 | ||
1610 | /* enable PIO controller's clock */ | |
1611 | if (clk_enable(at91_chip->clock)) { | |
1612 | dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); | |
1613 | goto clk_err; | |
1614 | } | |
1615 | ||
1616 | at91_chip->chip = at91_gpio_template; | |
1617 | ||
1618 | chip = &at91_chip->chip; | |
1619 | chip->of_node = np; | |
1620 | chip->label = dev_name(&pdev->dev); | |
1621 | chip->dev = &pdev->dev; | |
1622 | chip->owner = THIS_MODULE; | |
1623 | chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; | |
1624 | ||
1625 | if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { | |
1626 | if (ngpio >= MAX_NB_GPIO_PER_BANK) | |
1627 | pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", | |
1628 | alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK); | |
1629 | else | |
1630 | chip->ngpio = ngpio; | |
1631 | } | |
1632 | ||
3c93600d SK |
1633 | names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio, |
1634 | GFP_KERNEL); | |
32b01a36 JCPV |
1635 | |
1636 | if (!names) { | |
1637 | ret = -ENOMEM; | |
1638 | goto clk_err; | |
1639 | } | |
1640 | ||
1641 | for (i = 0; i < chip->ngpio; i++) | |
1642 | names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); | |
1643 | ||
3c93600d | 1644 | chip->names = (const char *const *)names; |
32b01a36 | 1645 | |
6732ae5c JCPV |
1646 | range = &at91_chip->range; |
1647 | range->name = chip->label; | |
1648 | range->id = alias_idx; | |
1649 | range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; | |
1650 | ||
1651 | range->npins = chip->ngpio; | |
1652 | range->gc = chip; | |
1653 | ||
1654 | ret = gpiochip_add(chip); | |
1655 | if (ret) | |
1656 | goto clk_err; | |
1657 | ||
1658 | gpio_chips[alias_idx] = at91_chip; | |
1659 | gpio_banks = max(gpio_banks, alias_idx + 1); | |
1660 | ||
1661 | at91_gpio_probe_fixup(); | |
1662 | ||
1663 | at91_gpio_of_irq_setup(np, at91_chip); | |
1664 | ||
1665 | dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); | |
1666 | ||
1667 | return 0; | |
1668 | ||
1669 | clk_err: | |
1670 | clk_unprepare(at91_chip->clock); | |
1671 | clk_prep_err: | |
1672 | clk_put(at91_chip->clock); | |
1673 | err: | |
1674 | dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); | |
1675 | ||
1676 | return ret; | |
1677 | } | |
1678 | ||
1679 | static struct platform_driver at91_gpio_driver = { | |
1680 | .driver = { | |
1681 | .name = "gpio-at91", | |
1682 | .owner = THIS_MODULE, | |
606fca94 | 1683 | .of_match_table = at91_gpio_of_match, |
6732ae5c JCPV |
1684 | }, |
1685 | .probe = at91_gpio_probe, | |
1686 | }; | |
1687 | ||
1688 | static struct platform_driver at91_pinctrl_driver = { | |
1689 | .driver = { | |
1690 | .name = "pinctrl-at91", | |
1691 | .owner = THIS_MODULE, | |
606fca94 | 1692 | .of_match_table = at91_pinctrl_of_match, |
6732ae5c JCPV |
1693 | }, |
1694 | .probe = at91_pinctrl_probe, | |
150632b0 | 1695 | .remove = at91_pinctrl_remove, |
6732ae5c JCPV |
1696 | }; |
1697 | ||
1698 | static int __init at91_pinctrl_init(void) | |
1699 | { | |
1700 | int ret; | |
1701 | ||
1702 | ret = platform_driver_register(&at91_gpio_driver); | |
1703 | if (ret) | |
1704 | return ret; | |
1705 | return platform_driver_register(&at91_pinctrl_driver); | |
1706 | } | |
1707 | arch_initcall(at91_pinctrl_init); | |
1708 | ||
1709 | static void __exit at91_pinctrl_exit(void) | |
1710 | { | |
1711 | platform_driver_unregister(&at91_pinctrl_driver); | |
1712 | } | |
1713 | ||
1714 | module_exit(at91_pinctrl_exit); | |
1715 | MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>"); | |
1716 | MODULE_DESCRIPTION("Atmel AT91 pinctrl driver"); | |
1717 | MODULE_LICENSE("GPL v2"); |