Commit | Line | Data |
---|---|---|
bd41b99d | 1 | /* |
c103de24 | 2 | * U300 GPIO module. |
bd41b99d | 3 | * |
04b13de6 | 4 | * Copyright (C) 2007-2012 ST-Ericsson AB |
bd41b99d | 5 | * License terms: GNU General Public License (GPL) version 2 |
bd41b99d | 6 | * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) |
cc890cd7 | 7 | * Author: Linus Walleij <linus.walleij@linaro.org> |
bd41b99d | 8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> |
bd41b99d LW |
9 | */ |
10 | #include <linux/module.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/gpio.h> | |
cc890cd7 | 19 | #include <linux/slab.h> |
28a8d14c | 20 | #include <linux/pinctrl/consumer.h> |
dc0b1aa3 | 21 | #include <linux/pinctrl/pinconf-generic.h> |
dc0b1aa3 | 22 | #include "pinctrl-coh901.h" |
bd41b99d | 23 | |
04b13de6 | 24 | #define U300_GPIO_PORT_STRIDE (0x30) |
cc890cd7 | 25 | /* |
04b13de6 LW |
26 | * Control Register 32bit (R/W) |
27 | * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores | |
28 | * gives the number of GPIO pins. | |
29 | * bit 8-2 (mask 0x000001FC) contains the core version ID. | |
cc890cd7 | 30 | */ |
04b13de6 LW |
31 | #define U300_GPIO_CR (0x00) |
32 | #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) | |
33 | #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) | |
34 | #define U300_GPIO_PXPDIR (0x04) | |
35 | #define U300_GPIO_PXPDOR (0x08) | |
36 | #define U300_GPIO_PXPCR (0x0C) | |
cc890cd7 LW |
37 | #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) |
38 | #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) | |
39 | #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) | |
40 | #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) | |
41 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) | |
42 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) | |
43 | #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) | |
04b13de6 LW |
44 | #define U300_GPIO_PXPER (0x10) |
45 | #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) | |
46 | #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) | |
47 | #define U300_GPIO_PXIEV (0x14) | |
48 | #define U300_GPIO_PXIEN (0x18) | |
49 | #define U300_GPIO_PXIFR (0x1C) | |
50 | #define U300_GPIO_PXICR (0x20) | |
cc890cd7 LW |
51 | #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) |
52 | #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) | |
53 | #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) | |
54 | #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) | |
cc890cd7 LW |
55 | |
56 | /* 8 bits per port, no version has more than 7 ports */ | |
b263e9b8 | 57 | #define U300_GPIO_NUM_PORTS 7 |
cc890cd7 | 58 | #define U300_GPIO_PINS_PER_PORT 8 |
b263e9b8 | 59 | #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) |
cc890cd7 | 60 | |
523dcce7 LW |
61 | struct u300_gpio_port { |
62 | struct u300_gpio *gpio; | |
63 | char name[8]; | |
64 | int irq; | |
65 | int number; | |
66 | u8 toggle_edge_mode; | |
67 | }; | |
68 | ||
cc890cd7 LW |
69 | struct u300_gpio { |
70 | struct gpio_chip chip; | |
523dcce7 | 71 | struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; |
cc890cd7 | 72 | struct clk *clk; |
cc890cd7 LW |
73 | void __iomem *base; |
74 | struct device *dev; | |
cc890cd7 LW |
75 | u32 stride; |
76 | /* Register offsets */ | |
77 | u32 pcr; | |
78 | u32 dor; | |
79 | u32 dir; | |
80 | u32 per; | |
81 | u32 icr; | |
82 | u32 ien; | |
83 | u32 iev; | |
84 | }; | |
bd41b99d | 85 | |
cc890cd7 LW |
86 | /* |
87 | * Macro to expand to read a specific register found in the "gpio" | |
88 | * struct. It requires the struct u300_gpio *gpio variable to exist in | |
89 | * its context. It calculates the port offset from the given pin | |
90 | * offset, muliplies by the port stride and adds the register offset | |
91 | * so it provides a pointer to the desired register. | |
92 | */ | |
93 | #define U300_PIN_REG(pin, reg) \ | |
94 | (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) | |
bd41b99d | 95 | |
cc890cd7 LW |
96 | /* |
97 | * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO | |
98 | * register. | |
99 | */ | |
100 | #define U300_PIN_BIT(pin) \ | |
101 | (1 << (pin & 0x07)) | |
bd41b99d | 102 | |
cc890cd7 LW |
103 | struct u300_gpio_confdata { |
104 | u16 bias_mode; | |
105 | bool output; | |
106 | int outval; | |
bd41b99d LW |
107 | }; |
108 | ||
cc890cd7 | 109 | #define U300_FLOATING_INPUT { \ |
a050b3ee | 110 | .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ |
cc890cd7 LW |
111 | .output = false, \ |
112 | } | |
bd41b99d | 113 | |
cc890cd7 | 114 | #define U300_PULL_UP_INPUT { \ |
a050b3ee | 115 | .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ |
cc890cd7 LW |
116 | .output = false, \ |
117 | } | |
bd41b99d | 118 | |
cc890cd7 LW |
119 | #define U300_OUTPUT_LOW { \ |
120 | .output = true, \ | |
121 | .outval = 0, \ | |
122 | } | |
bd41b99d | 123 | |
cc890cd7 LW |
124 | #define U300_OUTPUT_HIGH { \ |
125 | .output = true, \ | |
126 | .outval = 1, \ | |
127 | } | |
bd41b99d | 128 | |
bd41b99d | 129 | /* Initial configuration */ |
122dbe7e | 130 | static const struct __initconst u300_gpio_confdata |
b263e9b8 | 131 | bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { |
bd41b99d LW |
132 | /* Port 0, pins 0-7 */ |
133 | { | |
cc890cd7 LW |
134 | U300_FLOATING_INPUT, |
135 | U300_OUTPUT_HIGH, | |
136 | U300_FLOATING_INPUT, | |
137 | U300_OUTPUT_LOW, | |
138 | U300_OUTPUT_LOW, | |
139 | U300_OUTPUT_LOW, | |
140 | U300_OUTPUT_LOW, | |
141 | U300_OUTPUT_LOW, | |
bd41b99d LW |
142 | }, |
143 | /* Port 1, pins 0-7 */ | |
144 | { | |
cc890cd7 LW |
145 | U300_OUTPUT_LOW, |
146 | U300_OUTPUT_LOW, | |
147 | U300_OUTPUT_LOW, | |
148 | U300_PULL_UP_INPUT, | |
149 | U300_FLOATING_INPUT, | |
150 | U300_OUTPUT_HIGH, | |
151 | U300_OUTPUT_LOW, | |
152 | U300_OUTPUT_LOW, | |
bd41b99d LW |
153 | }, |
154 | /* Port 2, pins 0-7 */ | |
155 | { | |
cc890cd7 LW |
156 | U300_FLOATING_INPUT, |
157 | U300_FLOATING_INPUT, | |
158 | U300_FLOATING_INPUT, | |
159 | U300_FLOATING_INPUT, | |
160 | U300_OUTPUT_LOW, | |
161 | U300_PULL_UP_INPUT, | |
162 | U300_OUTPUT_LOW, | |
163 | U300_PULL_UP_INPUT, | |
bd41b99d LW |
164 | }, |
165 | /* Port 3, pins 0-7 */ | |
166 | { | |
cc890cd7 LW |
167 | U300_PULL_UP_INPUT, |
168 | U300_OUTPUT_LOW, | |
169 | U300_FLOATING_INPUT, | |
170 | U300_FLOATING_INPUT, | |
171 | U300_FLOATING_INPUT, | |
172 | U300_FLOATING_INPUT, | |
173 | U300_FLOATING_INPUT, | |
174 | U300_FLOATING_INPUT, | |
bd41b99d LW |
175 | }, |
176 | /* Port 4, pins 0-7 */ | |
177 | { | |
cc890cd7 LW |
178 | U300_FLOATING_INPUT, |
179 | U300_FLOATING_INPUT, | |
180 | U300_FLOATING_INPUT, | |
181 | U300_FLOATING_INPUT, | |
182 | U300_FLOATING_INPUT, | |
183 | U300_FLOATING_INPUT, | |
184 | U300_FLOATING_INPUT, | |
185 | U300_FLOATING_INPUT, | |
bd41b99d LW |
186 | }, |
187 | /* Port 5, pins 0-7 */ | |
188 | { | |
cc890cd7 LW |
189 | U300_FLOATING_INPUT, |
190 | U300_FLOATING_INPUT, | |
191 | U300_FLOATING_INPUT, | |
192 | U300_FLOATING_INPUT, | |
193 | U300_FLOATING_INPUT, | |
194 | U300_FLOATING_INPUT, | |
195 | U300_FLOATING_INPUT, | |
196 | U300_FLOATING_INPUT, | |
bd41b99d LW |
197 | }, |
198 | /* Port 6, pind 0-7 */ | |
199 | { | |
cc890cd7 LW |
200 | U300_FLOATING_INPUT, |
201 | U300_FLOATING_INPUT, | |
202 | U300_FLOATING_INPUT, | |
203 | U300_FLOATING_INPUT, | |
204 | U300_FLOATING_INPUT, | |
205 | U300_FLOATING_INPUT, | |
206 | U300_FLOATING_INPUT, | |
207 | U300_FLOATING_INPUT, | |
bd41b99d | 208 | } |
cc890cd7 | 209 | }; |
bd41b99d | 210 | |
cc890cd7 LW |
211 | /** |
212 | * to_u300_gpio() - get the pointer to u300_gpio | |
213 | * @chip: the gpio chip member of the structure u300_gpio | |
bd41b99d | 214 | */ |
cc890cd7 | 215 | static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) |
bd41b99d | 216 | { |
cc890cd7 | 217 | return container_of(chip, struct u300_gpio, chip); |
bd41b99d | 218 | } |
bd41b99d | 219 | |
b4e3ac74 LW |
220 | static int u300_gpio_request(struct gpio_chip *chip, unsigned offset) |
221 | { | |
222 | /* | |
223 | * Map back to global GPIO space and request muxing, the direction | |
224 | * parameter does not matter for this controller. | |
225 | */ | |
226 | int gpio = chip->base + offset; | |
227 | ||
e93bcee0 | 228 | return pinctrl_request_gpio(gpio); |
b4e3ac74 LW |
229 | } |
230 | ||
231 | static void u300_gpio_free(struct gpio_chip *chip, unsigned offset) | |
232 | { | |
233 | int gpio = chip->base + offset; | |
234 | ||
e93bcee0 | 235 | pinctrl_free_gpio(gpio); |
b4e3ac74 LW |
236 | } |
237 | ||
cc890cd7 | 238 | static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 239 | { |
cc890cd7 | 240 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 241 | |
cc890cd7 | 242 | return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); |
bd41b99d | 243 | } |
bd41b99d | 244 | |
cc890cd7 | 245 | static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
ee17962e | 246 | { |
cc890cd7 LW |
247 | struct u300_gpio *gpio = to_u300_gpio(chip); |
248 | unsigned long flags; | |
249 | u32 val; | |
ee17962e | 250 | |
cc890cd7 | 251 | local_irq_save(flags); |
bd41b99d | 252 | |
cc890cd7 LW |
253 | val = readl(U300_PIN_REG(offset, dor)); |
254 | if (value) | |
255 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
256 | else | |
257 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); | |
bd41b99d | 258 | |
cc890cd7 | 259 | local_irq_restore(flags); |
bd41b99d | 260 | } |
bd41b99d | 261 | |
cc890cd7 | 262 | static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
bd41b99d | 263 | { |
cc890cd7 LW |
264 | struct u300_gpio *gpio = to_u300_gpio(chip); |
265 | unsigned long flags; | |
266 | u32 val; | |
bd41b99d | 267 | |
cc890cd7 LW |
268 | local_irq_save(flags); |
269 | val = readl(U300_PIN_REG(offset, pcr)); | |
270 | /* Mask out this pin, note 2 bits per setting */ | |
271 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
272 | writel(val, U300_PIN_REG(offset, pcr)); | |
273 | local_irq_restore(flags); | |
274 | return 0; | |
bd41b99d | 275 | } |
bd41b99d | 276 | |
cc890cd7 LW |
277 | static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
278 | int value) | |
bd41b99d | 279 | { |
cc890cd7 | 280 | struct u300_gpio *gpio = to_u300_gpio(chip); |
bd41b99d | 281 | unsigned long flags; |
cc890cd7 LW |
282 | u32 oldmode; |
283 | u32 val; | |
bd41b99d LW |
284 | |
285 | local_irq_save(flags); | |
cc890cd7 LW |
286 | val = readl(U300_PIN_REG(offset, pcr)); |
287 | /* | |
288 | * Drive mode must be set by the special mode set function, set | |
289 | * push/pull mode by default if no mode has been selected. | |
290 | */ | |
291 | oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << | |
292 | ((offset & 0x07) << 1)); | |
293 | /* mode = 0 means input, else some mode is already set */ | |
294 | if (oldmode == 0) { | |
295 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << | |
296 | ((offset & 0x07) << 1)); | |
297 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
298 | << ((offset & 0x07) << 1)); | |
299 | writel(val, U300_PIN_REG(offset, pcr)); | |
bd41b99d | 300 | } |
cc890cd7 | 301 | u300_gpio_set(chip, offset, value); |
bd41b99d | 302 | local_irq_restore(flags); |
cc890cd7 | 303 | return 0; |
bd41b99d | 304 | } |
bd41b99d | 305 | |
dc0b1aa3 LW |
306 | /* Returning -EINVAL means "supported but not available" */ |
307 | int u300_gpio_config_get(struct gpio_chip *chip, | |
308 | unsigned offset, | |
309 | unsigned long *config) | |
310 | { | |
311 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
312 | enum pin_config_param param = (enum pin_config_param) *config; | |
313 | bool biasmode; | |
314 | u32 drmode; | |
315 | ||
316 | /* One bit per pin, clamp to bool range */ | |
317 | biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); | |
318 | ||
319 | /* Mask out the two bits for this pin and shift to bits 0,1 */ | |
320 | drmode = readl(U300_PIN_REG(offset, pcr)); | |
321 | drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); | |
322 | drmode >>= ((offset & 0x07) << 1); | |
323 | ||
8b0ef258 | 324 | switch (param) { |
dc0b1aa3 LW |
325 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: |
326 | *config = 0; | |
327 | if (biasmode) | |
328 | return 0; | |
329 | else | |
330 | return -EINVAL; | |
331 | break; | |
332 | case PIN_CONFIG_BIAS_PULL_UP: | |
333 | *config = 0; | |
334 | if (!biasmode) | |
335 | return 0; | |
336 | else | |
337 | return -EINVAL; | |
338 | break; | |
339 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
340 | *config = 0; | |
341 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) | |
342 | return 0; | |
343 | else | |
344 | return -EINVAL; | |
345 | break; | |
346 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
347 | *config = 0; | |
348 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) | |
349 | return 0; | |
350 | else | |
351 | return -EINVAL; | |
352 | break; | |
353 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: | |
354 | *config = 0; | |
355 | if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) | |
356 | return 0; | |
357 | else | |
358 | return -EINVAL; | |
359 | break; | |
360 | default: | |
361 | break; | |
362 | } | |
363 | return -ENOTSUPP; | |
364 | } | |
365 | ||
366 | int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, | |
367 | enum pin_config_param param) | |
cc890cd7 LW |
368 | { |
369 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
bd41b99d LW |
370 | unsigned long flags; |
371 | u32 val; | |
372 | ||
bd41b99d | 373 | local_irq_save(flags); |
cc890cd7 | 374 | switch (param) { |
a050b3ee LW |
375 | case PIN_CONFIG_BIAS_DISABLE: |
376 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
cc890cd7 LW |
377 | val = readl(U300_PIN_REG(offset, per)); |
378 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
379 | break; | |
a050b3ee | 380 | case PIN_CONFIG_BIAS_PULL_UP: |
cc890cd7 LW |
381 | val = readl(U300_PIN_REG(offset, per)); |
382 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); | |
383 | break; | |
a050b3ee | 384 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
cc890cd7 LW |
385 | val = readl(U300_PIN_REG(offset, pcr)); |
386 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
387 | << ((offset & 0x07) << 1)); | |
388 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL | |
389 | << ((offset & 0x07) << 1)); | |
390 | writel(val, U300_PIN_REG(offset, pcr)); | |
391 | break; | |
a050b3ee | 392 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: |
cc890cd7 LW |
393 | val = readl(U300_PIN_REG(offset, pcr)); |
394 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
395 | << ((offset & 0x07) << 1)); | |
396 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN | |
397 | << ((offset & 0x07) << 1)); | |
398 | writel(val, U300_PIN_REG(offset, pcr)); | |
399 | break; | |
a050b3ee | 400 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
cc890cd7 LW |
401 | val = readl(U300_PIN_REG(offset, pcr)); |
402 | val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK | |
403 | << ((offset & 0x07) << 1)); | |
404 | val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE | |
405 | << ((offset & 0x07) << 1)); | |
406 | writel(val, U300_PIN_REG(offset, pcr)); | |
407 | break; | |
408 | default: | |
409 | local_irq_restore(flags); | |
410 | dev_err(gpio->dev, "illegal configuration requested\n"); | |
411 | return -EINVAL; | |
412 | } | |
bd41b99d LW |
413 | local_irq_restore(flags); |
414 | return 0; | |
415 | } | |
bd41b99d | 416 | |
cc890cd7 LW |
417 | static struct gpio_chip u300_gpio_chip = { |
418 | .label = "u300-gpio-chip", | |
419 | .owner = THIS_MODULE, | |
b4e3ac74 LW |
420 | .request = u300_gpio_request, |
421 | .free = u300_gpio_free, | |
cc890cd7 LW |
422 | .get = u300_gpio_get, |
423 | .set = u300_gpio_set, | |
424 | .direction_input = u300_gpio_direction_input, | |
425 | .direction_output = u300_gpio_direction_output, | |
cc890cd7 LW |
426 | }; |
427 | ||
428 | static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) | |
bd41b99d | 429 | { |
bd41b99d LW |
430 | u32 val; |
431 | ||
cc890cd7 LW |
432 | val = readl(U300_PIN_REG(offset, icr)); |
433 | /* Set mode depending on state */ | |
434 | if (u300_gpio_get(&gpio->chip, offset)) { | |
435 | /* High now, let's trigger on falling edge next then */ | |
436 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
437 | dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", | |
438 | offset); | |
439 | } else { | |
440 | /* Low now, let's trigger on rising edge next then */ | |
441 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
442 | dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", | |
443 | offset); | |
444 | } | |
bd41b99d | 445 | } |
bd41b99d | 446 | |
cc890cd7 | 447 | static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) |
bd41b99d | 448 | { |
523dcce7 LW |
449 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
450 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
451 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; | |
452 | int offset = d->hwirq; | |
bd41b99d | 453 | u32 val; |
bd41b99d | 454 | |
cc890cd7 LW |
455 | if ((trigger & IRQF_TRIGGER_RISING) && |
456 | (trigger & IRQF_TRIGGER_FALLING)) { | |
457 | /* | |
458 | * The GPIO block can only trigger on falling OR rising edges, | |
459 | * not both. So we need to toggle the mode whenever the pin | |
460 | * goes from one state to the other with a special state flag | |
461 | */ | |
462 | dev_dbg(gpio->dev, | |
463 | "trigger on both rising and falling edge on pin %d\n", | |
464 | offset); | |
465 | port->toggle_edge_mode |= U300_PIN_BIT(offset); | |
466 | u300_toggle_trigger(gpio, offset); | |
467 | } else if (trigger & IRQF_TRIGGER_RISING) { | |
468 | dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", | |
469 | offset); | |
470 | val = readl(U300_PIN_REG(offset, icr)); | |
471 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
472 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
473 | } else if (trigger & IRQF_TRIGGER_FALLING) { | |
474 | dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", | |
475 | offset); | |
476 | val = readl(U300_PIN_REG(offset, icr)); | |
477 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); | |
478 | port->toggle_edge_mode &= ~U300_PIN_BIT(offset); | |
479 | } | |
480 | ||
481 | return 0; | |
bd41b99d | 482 | } |
bd41b99d | 483 | |
cc890cd7 | 484 | static void u300_gpio_irq_enable(struct irq_data *d) |
bd41b99d | 485 | { |
523dcce7 LW |
486 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
487 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
488 | struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; | |
489 | int offset = d->hwirq; | |
bd41b99d LW |
490 | u32 val; |
491 | unsigned long flags; | |
492 | ||
a6c45b99 LW |
493 | dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", |
494 | d->hwirq, port->name, offset); | |
bd41b99d | 495 | local_irq_save(flags); |
cc890cd7 LW |
496 | val = readl(U300_PIN_REG(offset, ien)); |
497 | writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d LW |
498 | local_irq_restore(flags); |
499 | } | |
bd41b99d | 500 | |
cc890cd7 | 501 | static void u300_gpio_irq_disable(struct irq_data *d) |
bd41b99d | 502 | { |
523dcce7 LW |
503 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
504 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
505 | int offset = d->hwirq; | |
bd41b99d LW |
506 | u32 val; |
507 | unsigned long flags; | |
508 | ||
509 | local_irq_save(flags); | |
cc890cd7 LW |
510 | val = readl(U300_PIN_REG(offset, ien)); |
511 | writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); | |
bd41b99d | 512 | local_irq_restore(flags); |
8c1d50a6 LW |
513 | } |
514 | ||
cc890cd7 LW |
515 | static struct irq_chip u300_gpio_irqchip = { |
516 | .name = "u300-gpio-irqchip", | |
517 | .irq_enable = u300_gpio_irq_enable, | |
518 | .irq_disable = u300_gpio_irq_disable, | |
519 | .irq_set_type = u300_gpio_irq_type, | |
cc890cd7 LW |
520 | }; |
521 | ||
522 | static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |
bd41b99d | 523 | { |
523dcce7 LW |
524 | struct irq_chip *parent_chip = irq_get_chip(irq); |
525 | struct gpio_chip *chip = irq_get_handler_data(irq); | |
526 | struct u300_gpio *gpio = to_u300_gpio(chip); | |
527 | struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; | |
cc890cd7 LW |
528 | int pinoffset = port->number << 3; /* get the right stride */ |
529 | unsigned long val; | |
bd41b99d | 530 | |
523dcce7 LW |
531 | chained_irq_enter(parent_chip, desc); |
532 | ||
bd41b99d | 533 | /* Read event register */ |
cc890cd7 | 534 | val = readl(U300_PIN_REG(pinoffset, iev)); |
bd41b99d | 535 | /* Mask relevant bits */ |
cc890cd7 | 536 | val &= 0xFFU; /* 8 bits per port */ |
bd41b99d | 537 | /* ACK IRQ (clear event) */ |
cc890cd7 LW |
538 | writel(val, U300_PIN_REG(pinoffset, iev)); |
539 | ||
540 | /* Call IRQ handler */ | |
541 | if (val != 0) { | |
542 | int irqoffset; | |
543 | ||
544 | for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { | |
cc890cd7 | 545 | int offset = pinoffset + irqoffset; |
523dcce7 | 546 | int pin_irq = irq_find_mapping(chip->irqdomain, offset); |
cc890cd7 LW |
547 | |
548 | dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", | |
549 | pin_irq, offset); | |
550 | generic_handle_irq(pin_irq); | |
551 | /* | |
552 | * Triggering IRQ on both rising and falling edge | |
553 | * needs mockery | |
554 | */ | |
555 | if (port->toggle_edge_mode & U300_PIN_BIT(offset)) | |
556 | u300_toggle_trigger(gpio, offset); | |
557 | } | |
bd41b99d | 558 | } |
cc890cd7 | 559 | |
523dcce7 | 560 | chained_irq_exit(parent_chip, desc); |
bd41b99d LW |
561 | } |
562 | ||
cc890cd7 LW |
563 | static void __init u300_gpio_init_pin(struct u300_gpio *gpio, |
564 | int offset, | |
565 | const struct u300_gpio_confdata *conf) | |
bd41b99d | 566 | { |
cc890cd7 LW |
567 | /* Set mode: input or output */ |
568 | if (conf->output) { | |
569 | u300_gpio_direction_output(&gpio->chip, offset, conf->outval); | |
bd41b99d | 570 | |
cc890cd7 | 571 | /* Deactivate bias mode for output */ |
dc0b1aa3 LW |
572 | u300_gpio_config_set(&gpio->chip, offset, |
573 | PIN_CONFIG_BIAS_HIGH_IMPEDANCE); | |
cc890cd7 LW |
574 | |
575 | /* Set drive mode for output */ | |
dc0b1aa3 LW |
576 | u300_gpio_config_set(&gpio->chip, offset, |
577 | PIN_CONFIG_DRIVE_PUSH_PULL); | |
cc890cd7 LW |
578 | |
579 | dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", | |
580 | offset, conf->outval); | |
581 | } else { | |
582 | u300_gpio_direction_input(&gpio->chip, offset); | |
583 | ||
584 | /* Always set output low on input pins */ | |
585 | u300_gpio_set(&gpio->chip, offset, 0); | |
586 | ||
587 | /* Set bias mode for input */ | |
dc0b1aa3 | 588 | u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); |
cc890cd7 LW |
589 | |
590 | dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", | |
591 | offset, conf->bias_mode); | |
bd41b99d | 592 | } |
cc890cd7 | 593 | } |
bd41b99d | 594 | |
b263e9b8 | 595 | static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) |
cc890cd7 LW |
596 | { |
597 | int i, j; | |
598 | ||
599 | /* Write default config and values to all pins */ | |
b263e9b8 | 600 | for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { |
cc890cd7 LW |
601 | for (j = 0; j < 8; j++) { |
602 | const struct u300_gpio_confdata *conf; | |
603 | int offset = (i*8) + j; | |
604 | ||
04b13de6 | 605 | conf = &bs335_gpio_config[i][j]; |
cc890cd7 | 606 | u300_gpio_init_pin(gpio, offset, conf); |
bd41b99d LW |
607 | } |
608 | } | |
cc890cd7 | 609 | } |
bd41b99d | 610 | |
387923c5 LW |
611 | /* |
612 | * Here we map a GPIO in the local gpio_chip pin space to a pin in | |
613 | * the local pinctrl pin space. The pin controller used is | |
614 | * pinctrl-u300. | |
615 | */ | |
616 | struct coh901_pinpair { | |
617 | unsigned int offset; | |
618 | unsigned int pin_base; | |
619 | }; | |
620 | ||
621 | #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } | |
622 | ||
623 | static struct coh901_pinpair coh901_pintable[] = { | |
624 | COH901_PINRANGE(10, 426), | |
625 | COH901_PINRANGE(11, 180), | |
626 | COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ | |
627 | COH901_PINRANGE(13, 179), | |
628 | COH901_PINRANGE(14, 178), | |
629 | COH901_PINRANGE(16, 194), | |
630 | COH901_PINRANGE(17, 193), | |
631 | COH901_PINRANGE(18, 192), | |
632 | COH901_PINRANGE(19, 191), | |
633 | COH901_PINRANGE(20, 186), | |
634 | COH901_PINRANGE(21, 185), | |
635 | COH901_PINRANGE(22, 184), | |
636 | COH901_PINRANGE(23, 183), | |
637 | COH901_PINRANGE(24, 182), | |
638 | COH901_PINRANGE(25, 181), | |
639 | }; | |
640 | ||
cc890cd7 | 641 | static int __init u300_gpio_probe(struct platform_device *pdev) |
bd41b99d | 642 | { |
cc890cd7 | 643 | struct u300_gpio *gpio; |
585583f5 | 644 | struct resource *memres; |
bd41b99d | 645 | int err = 0; |
cc890cd7 LW |
646 | int portno; |
647 | u32 val; | |
648 | u32 ifr; | |
bd41b99d | 649 | int i; |
bd41b99d | 650 | |
585583f5 LW |
651 | gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); |
652 | if (gpio == NULL) | |
cc890cd7 | 653 | return -ENOMEM; |
cc890cd7 LW |
654 | |
655 | gpio->chip = u300_gpio_chip; | |
b263e9b8 | 656 | gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; |
cc890cd7 | 657 | gpio->chip.dev = &pdev->dev; |
b263e9b8 | 658 | gpio->chip.base = 0; |
cc890cd7 | 659 | gpio->dev = &pdev->dev; |
bd41b99d | 660 | |
585583f5 | 661 | memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
9e0c1fb2 TR |
662 | gpio->base = devm_ioremap_resource(&pdev->dev, memres); |
663 | if (IS_ERR(gpio->base)) | |
664 | return PTR_ERR(gpio->base); | |
585583f5 LW |
665 | |
666 | gpio->clk = devm_clk_get(gpio->dev, NULL); | |
cc890cd7 LW |
667 | if (IS_ERR(gpio->clk)) { |
668 | err = PTR_ERR(gpio->clk); | |
669 | dev_err(gpio->dev, "could not get GPIO clock\n"); | |
585583f5 | 670 | return err; |
bd41b99d | 671 | } |
585583f5 | 672 | |
27e8461c | 673 | err = clk_prepare_enable(gpio->clk); |
bd41b99d | 674 | if (err) { |
cc890cd7 | 675 | dev_err(gpio->dev, "could not enable GPIO clock\n"); |
585583f5 | 676 | return err; |
bd41b99d | 677 | } |
cc890cd7 | 678 | |
04b13de6 LW |
679 | dev_info(gpio->dev, |
680 | "initializing GPIO Controller COH 901 571/3\n"); | |
681 | gpio->stride = U300_GPIO_PORT_STRIDE; | |
682 | gpio->pcr = U300_GPIO_PXPCR; | |
683 | gpio->dor = U300_GPIO_PXPDOR; | |
684 | gpio->dir = U300_GPIO_PXPDIR; | |
685 | gpio->per = U300_GPIO_PXPER; | |
686 | gpio->icr = U300_GPIO_PXICR; | |
687 | gpio->ien = U300_GPIO_PXIEN; | |
688 | gpio->iev = U300_GPIO_PXIEV; | |
689 | ifr = U300_GPIO_PXIFR; | |
690 | ||
691 | val = readl(gpio->base + U300_GPIO_CR); | |
692 | dev_info(gpio->dev, "COH901571/3 block version: %d, " \ | |
693 | "number of cores: %d totalling %d pins\n", | |
694 | ((val & 0x000001FC) >> 2), | |
695 | ((val & 0x0000FE00) >> 9), | |
696 | ((val & 0x0000FE00) >> 9) * 8); | |
697 | writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, | |
698 | gpio->base + U300_GPIO_CR); | |
b263e9b8 | 699 | u300_gpio_init_coh901571(gpio); |
cc890cd7 | 700 | |
523dcce7 LW |
701 | #ifdef CONFIG_OF_GPIO |
702 | gpio->chip.of_node = pdev->dev.of_node; | |
703 | #endif | |
704 | err = gpiochip_add(&gpio->chip); | |
705 | if (err) { | |
706 | dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); | |
707 | goto err_no_chip; | |
708 | } | |
709 | ||
710 | err = gpiochip_irqchip_add(&gpio->chip, | |
711 | &u300_gpio_irqchip, | |
712 | 0, | |
713 | handle_simple_irq, | |
714 | IRQ_TYPE_EDGE_FALLING); | |
715 | if (err) { | |
716 | dev_err(gpio->dev, "no GPIO irqchip\n"); | |
717 | goto err_no_irqchip; | |
718 | } | |
719 | ||
cc890cd7 | 720 | /* Add each port with its IRQ separately */ |
b263e9b8 | 721 | for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { |
523dcce7 | 722 | struct u300_gpio_port *port = &gpio->ports[portno]; |
cc890cd7 LW |
723 | |
724 | snprintf(port->name, 8, "gpio%d", portno); | |
725 | port->number = portno; | |
726 | port->gpio = gpio; | |
727 | ||
351c2163 | 728 | port->irq = platform_get_irq(pdev, portno); |
cc890cd7 | 729 | |
523dcce7 LW |
730 | gpiochip_set_chained_irqchip(&gpio->chip, |
731 | &u300_gpio_irqchip, | |
732 | port->irq, | |
733 | u300_gpio_irq_handler); | |
cc890cd7 LW |
734 | |
735 | /* Turns off irq force (test register) for this port */ | |
736 | writel(0x0, gpio->base + portno * gpio->stride + ifr); | |
bd41b99d | 737 | } |
cc890cd7 LW |
738 | dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); |
739 | ||
387923c5 LW |
740 | /* |
741 | * Add pinctrl pin ranges, the pin controller must be registered | |
742 | * at this point | |
743 | */ | |
744 | for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { | |
745 | struct coh901_pinpair *p = &coh901_pintable[i]; | |
746 | ||
747 | err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", | |
748 | p->offset, p->pin_base, 1); | |
749 | if (err) | |
750 | goto err_no_range; | |
751 | } | |
752 | ||
cc890cd7 | 753 | platform_set_drvdata(pdev, gpio); |
bd41b99d LW |
754 | |
755 | return 0; | |
756 | ||
387923c5 | 757 | err_no_range: |
523dcce7 | 758 | err_no_irqchip: |
b4e7c55d | 759 | gpiochip_remove(&gpio->chip); |
cc890cd7 | 760 | err_no_chip: |
27e8461c | 761 | clk_disable_unprepare(gpio->clk); |
80357203 | 762 | dev_err(&pdev->dev, "module ERROR:%d\n", err); |
bd41b99d LW |
763 | return err; |
764 | } | |
765 | ||
cc890cd7 | 766 | static int __exit u300_gpio_remove(struct platform_device *pdev) |
bd41b99d | 767 | { |
cc890cd7 | 768 | struct u300_gpio *gpio = platform_get_drvdata(pdev); |
bd41b99d LW |
769 | |
770 | /* Turn off the GPIO block */ | |
04b13de6 | 771 | writel(0x00000000U, gpio->base + U300_GPIO_CR); |
cc890cd7 | 772 | |
b4e7c55d | 773 | gpiochip_remove(&gpio->chip); |
27e8461c | 774 | clk_disable_unprepare(gpio->clk); |
bd41b99d LW |
775 | return 0; |
776 | } | |
777 | ||
351c2163 LW |
778 | static const struct of_device_id u300_gpio_match[] = { |
779 | { .compatible = "stericsson,gpio-coh901" }, | |
780 | {}, | |
781 | }; | |
782 | ||
cc890cd7 | 783 | static struct platform_driver u300_gpio_driver = { |
bd41b99d LW |
784 | .driver = { |
785 | .name = "u300-gpio", | |
351c2163 | 786 | .of_match_table = u300_gpio_match, |
bd41b99d | 787 | }, |
cc890cd7 | 788 | .remove = __exit_p(u300_gpio_remove), |
bd41b99d LW |
789 | }; |
790 | ||
bd41b99d LW |
791 | static int __init u300_gpio_init(void) |
792 | { | |
cc890cd7 | 793 | return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); |
bd41b99d LW |
794 | } |
795 | ||
796 | static void __exit u300_gpio_exit(void) | |
797 | { | |
cc890cd7 | 798 | platform_driver_unregister(&u300_gpio_driver); |
bd41b99d LW |
799 | } |
800 | ||
801 | arch_initcall(u300_gpio_init); | |
802 | module_exit(u300_gpio_exit); | |
803 | ||
804 | MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); | |
cc890cd7 | 805 | MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); |
bd41b99d | 806 | MODULE_LICENSE("GPL"); |