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43b169db TA |
1 | /* |
2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This file contains the Samsung Exynos specific information required by the | |
17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of | |
18 | * external gpio and wakeup interrupt support. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/irq.h> | |
de88cbb7 | 26 | #include <linux/irqchip/chained_irq.h> |
43b169db TA |
27 | #include <linux/of_irq.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/slab.h> | |
19846950 | 30 | #include <linux/spinlock.h> |
43b169db TA |
31 | #include <linux/err.h> |
32 | ||
43b169db TA |
33 | #include "pinctrl-samsung.h" |
34 | #include "pinctrl-exynos.h" | |
35 | ||
499147c9 TF |
36 | |
37 | static struct samsung_pin_bank_type bank_type_off = { | |
38 | .fld_width = { 4, 1, 2, 2, 2, 2, }, | |
43fc9e7f | 39 | .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, |
499147c9 TF |
40 | }; |
41 | ||
42 | static struct samsung_pin_bank_type bank_type_alive = { | |
43 | .fld_width = { 4, 1, 2, 2, }, | |
43fc9e7f | 44 | .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, |
499147c9 TF |
45 | }; |
46 | ||
43b169db TA |
47 | /* list of external wakeup controllers supported */ |
48 | static const struct of_device_id exynos_wkup_irq_ids[] = { | |
49 | { .compatible = "samsung,exynos4210-wakeup-eint", }, | |
afa538c2 | 50 | { } |
43b169db TA |
51 | }; |
52 | ||
5ace03fb | 53 | static void exynos_gpio_irq_mask(struct irq_data *irqd) |
43b169db | 54 | { |
595be726 TF |
55 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
56 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
57 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; | |
43b169db | 58 | unsigned long mask; |
5ae8cf79 DA |
59 | unsigned long flags; |
60 | ||
61 | spin_lock_irqsave(&bank->slock, flags); | |
43b169db TA |
62 | |
63 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 64 | mask |= 1 << irqd->hwirq; |
43b169db | 65 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
66 | |
67 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
68 | } |
69 | ||
5ace03fb | 70 | static void exynos_gpio_irq_ack(struct irq_data *irqd) |
43b169db | 71 | { |
595be726 TF |
72 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
73 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
5ace03fb | 74 | unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset; |
43b169db | 75 | |
5ace03fb | 76 | writel(1 << irqd->hwirq, d->virt_base + reg_pend); |
43b169db TA |
77 | } |
78 | ||
5ace03fb | 79 | static void exynos_gpio_irq_unmask(struct irq_data *irqd) |
43b169db | 80 | { |
595be726 TF |
81 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
82 | struct samsung_pinctrl_drv_data *d = bank->drvdata; | |
595be726 | 83 | unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset; |
43b169db | 84 | unsigned long mask; |
5ae8cf79 | 85 | unsigned long flags; |
43b169db | 86 | |
5a68e7a7 DA |
87 | /* |
88 | * Ack level interrupts right before unmask | |
89 | * | |
90 | * If we don't do this we'll get a double-interrupt. Level triggered | |
91 | * interrupts must not fire an interrupt if the level is not | |
92 | * _currently_ active, even if it was active while the interrupt was | |
93 | * masked. | |
94 | */ | |
95 | if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) | |
96 | exynos_gpio_irq_ack(irqd); | |
97 | ||
5ae8cf79 | 98 | spin_lock_irqsave(&bank->slock, flags); |
43b169db TA |
99 | |
100 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 101 | mask &= ~(1 << irqd->hwirq); |
43b169db | 102 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
103 | |
104 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
105 | } |
106 | ||
107 | static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) | |
108 | { | |
595be726 | 109 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
499147c9 | 110 | struct samsung_pin_bank_type *bank_type = bank->type; |
595be726 | 111 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
43b169db | 112 | struct samsung_pin_ctrl *ctrl = d->ctrl; |
595be726 TF |
113 | unsigned int pin = irqd->hwirq; |
114 | unsigned int shift = EXYNOS_EINT_CON_LEN * pin; | |
43b169db | 115 | unsigned int con, trig_type; |
595be726 | 116 | unsigned long reg_con = ctrl->geint_con + bank->eint_offset; |
19846950 | 117 | unsigned long flags; |
ee2f573c | 118 | unsigned int mask; |
43b169db TA |
119 | |
120 | switch (type) { | |
121 | case IRQ_TYPE_EDGE_RISING: | |
122 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
123 | break; | |
124 | case IRQ_TYPE_EDGE_FALLING: | |
125 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
126 | break; | |
127 | case IRQ_TYPE_EDGE_BOTH: | |
128 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
129 | break; | |
130 | case IRQ_TYPE_LEVEL_HIGH: | |
131 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
132 | break; | |
133 | case IRQ_TYPE_LEVEL_LOW: | |
134 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
135 | break; | |
136 | default: | |
137 | pr_err("unsupported external interrupt type\n"); | |
138 | return -EINVAL; | |
139 | } | |
140 | ||
141 | if (type & IRQ_TYPE_EDGE_BOTH) | |
142 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
143 | else | |
144 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
145 | ||
146 | con = readl(d->virt_base + reg_con); | |
147 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
148 | con |= trig_type << shift; | |
149 | writel(con, d->virt_base + reg_con); | |
ee2f573c | 150 | |
43fc9e7f | 151 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; |
499147c9 TF |
152 | shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; |
153 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
ee2f573c | 154 | |
19846950 TF |
155 | spin_lock_irqsave(&bank->slock, flags); |
156 | ||
ee2f573c TF |
157 | con = readl(d->virt_base + reg_con); |
158 | con &= ~(mask << shift); | |
159 | con |= EXYNOS_EINT_FUNC << shift; | |
160 | writel(con, d->virt_base + reg_con); | |
161 | ||
19846950 TF |
162 | spin_unlock_irqrestore(&bank->slock, flags); |
163 | ||
43b169db TA |
164 | return 0; |
165 | } | |
166 | ||
167 | /* | |
168 | * irq_chip for gpio interrupts. | |
169 | */ | |
170 | static struct irq_chip exynos_gpio_irq_chip = { | |
171 | .name = "exynos_gpio_irq_chip", | |
172 | .irq_unmask = exynos_gpio_irq_unmask, | |
173 | .irq_mask = exynos_gpio_irq_mask, | |
174 | .irq_ack = exynos_gpio_irq_ack, | |
175 | .irq_set_type = exynos_gpio_irq_set_type, | |
176 | }; | |
177 | ||
43b169db TA |
178 | static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, |
179 | irq_hw_number_t hw) | |
180 | { | |
595be726 | 181 | struct samsung_pin_bank *b = h->host_data; |
43b169db | 182 | |
595be726 | 183 | irq_set_chip_data(virq, b); |
43b169db TA |
184 | irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip, |
185 | handle_level_irq); | |
186 | set_irq_flags(virq, IRQF_VALID); | |
187 | return 0; | |
188 | } | |
189 | ||
43b169db TA |
190 | /* |
191 | * irq domain callbacks for external gpio interrupt controller. | |
192 | */ | |
193 | static const struct irq_domain_ops exynos_gpio_irqd_ops = { | |
194 | .map = exynos_gpio_irq_map, | |
43b169db TA |
195 | .xlate = irq_domain_xlate_twocell, |
196 | }; | |
197 | ||
198 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) | |
199 | { | |
200 | struct samsung_pinctrl_drv_data *d = data; | |
201 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
202 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
203 | unsigned int svc, group, pin, virq; | |
204 | ||
205 | svc = readl(d->virt_base + ctrl->svc); | |
206 | group = EXYNOS_SVC_GROUP(svc); | |
207 | pin = svc & EXYNOS_SVC_NUM_MASK; | |
208 | ||
209 | if (!group) | |
210 | return IRQ_HANDLED; | |
211 | bank += (group - 1); | |
212 | ||
595be726 | 213 | virq = irq_linear_revmap(bank->irq_domain, pin); |
43b169db TA |
214 | if (!virq) |
215 | return IRQ_NONE; | |
216 | generic_handle_irq(virq); | |
217 | return IRQ_HANDLED; | |
218 | } | |
219 | ||
7ccbc60c TF |
220 | struct exynos_eint_gpio_save { |
221 | u32 eint_con; | |
222 | u32 eint_fltcon0; | |
223 | u32 eint_fltcon1; | |
224 | }; | |
225 | ||
43b169db TA |
226 | /* |
227 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. | |
228 | * @d: driver data of samsung pinctrl driver. | |
229 | */ | |
230 | static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) | |
231 | { | |
595be726 | 232 | struct samsung_pin_bank *bank; |
43b169db | 233 | struct device *dev = d->dev; |
7ccbc60c TF |
234 | int ret; |
235 | int i; | |
43b169db TA |
236 | |
237 | if (!d->irq) { | |
238 | dev_err(dev, "irq number not available\n"); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, | |
243 | 0, dev_name(dev), d); | |
244 | if (ret) { | |
245 | dev_err(dev, "irq request failed\n"); | |
246 | return -ENXIO; | |
247 | } | |
248 | ||
595be726 TF |
249 | bank = d->ctrl->pin_banks; |
250 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
251 | if (bank->eint_type != EINT_TYPE_GPIO) | |
252 | continue; | |
253 | bank->irq_domain = irq_domain_add_linear(bank->of_node, | |
254 | bank->nr_pins, &exynos_gpio_irqd_ops, bank); | |
255 | if (!bank->irq_domain) { | |
256 | dev_err(dev, "gpio irq domain add failed\n"); | |
7ccbc60c TF |
257 | ret = -ENXIO; |
258 | goto err_domains; | |
259 | } | |
260 | ||
261 | bank->soc_priv = devm_kzalloc(d->dev, | |
262 | sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); | |
263 | if (!bank->soc_priv) { | |
264 | irq_domain_remove(bank->irq_domain); | |
265 | ret = -ENOMEM; | |
266 | goto err_domains; | |
595be726 | 267 | } |
43b169db TA |
268 | } |
269 | ||
270 | return 0; | |
7ccbc60c TF |
271 | |
272 | err_domains: | |
273 | for (--i, --bank; i >= 0; --i, --bank) { | |
274 | if (bank->eint_type != EINT_TYPE_GPIO) | |
275 | continue; | |
276 | irq_domain_remove(bank->irq_domain); | |
277 | } | |
278 | ||
279 | return ret; | |
43b169db TA |
280 | } |
281 | ||
5ace03fb | 282 | static void exynos_wkup_irq_mask(struct irq_data *irqd) |
43b169db | 283 | { |
a04b07c0 TF |
284 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
285 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
286 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; | |
43b169db | 287 | unsigned long mask; |
5ae8cf79 DA |
288 | unsigned long flags; |
289 | ||
290 | spin_lock_irqsave(&b->slock, flags); | |
43b169db TA |
291 | |
292 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 293 | mask |= 1 << irqd->hwirq; |
43b169db | 294 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
295 | |
296 | spin_unlock_irqrestore(&b->slock, flags); | |
43b169db TA |
297 | } |
298 | ||
5ace03fb | 299 | static void exynos_wkup_irq_ack(struct irq_data *irqd) |
43b169db | 300 | { |
a04b07c0 TF |
301 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
302 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
5ace03fb | 303 | unsigned long pend = d->ctrl->weint_pend + b->eint_offset; |
43b169db | 304 | |
5ace03fb | 305 | writel(1 << irqd->hwirq, d->virt_base + pend); |
43b169db TA |
306 | } |
307 | ||
5ace03fb | 308 | static void exynos_wkup_irq_unmask(struct irq_data *irqd) |
43b169db | 309 | { |
a04b07c0 TF |
310 | struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd); |
311 | struct samsung_pinctrl_drv_data *d = b->drvdata; | |
a04b07c0 | 312 | unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset; |
43b169db | 313 | unsigned long mask; |
5ae8cf79 | 314 | unsigned long flags; |
43b169db | 315 | |
5a68e7a7 DA |
316 | /* |
317 | * Ack level interrupts right before unmask | |
318 | * | |
319 | * If we don't do this we'll get a double-interrupt. Level triggered | |
320 | * interrupts must not fire an interrupt if the level is not | |
321 | * _currently_ active, even if it was active while the interrupt was | |
322 | * masked. | |
323 | */ | |
324 | if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) | |
325 | exynos_wkup_irq_ack(irqd); | |
326 | ||
5ae8cf79 | 327 | spin_lock_irqsave(&b->slock, flags); |
43b169db TA |
328 | |
329 | mask = readl(d->virt_base + reg_mask); | |
5ace03fb | 330 | mask &= ~(1 << irqd->hwirq); |
43b169db | 331 | writel(mask, d->virt_base + reg_mask); |
5ae8cf79 DA |
332 | |
333 | spin_unlock_irqrestore(&b->slock, flags); | |
43b169db TA |
334 | } |
335 | ||
336 | static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) | |
337 | { | |
a04b07c0 | 338 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
499147c9 | 339 | struct samsung_pin_bank_type *bank_type = bank->type; |
a04b07c0 TF |
340 | struct samsung_pinctrl_drv_data *d = bank->drvdata; |
341 | unsigned int pin = irqd->hwirq; | |
342 | unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; | |
43b169db TA |
343 | unsigned long shift = EXYNOS_EINT_CON_LEN * pin; |
344 | unsigned long con, trig_type; | |
19846950 | 345 | unsigned long flags; |
22b9ba03 | 346 | unsigned int mask; |
43b169db TA |
347 | |
348 | switch (type) { | |
349 | case IRQ_TYPE_EDGE_RISING: | |
350 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
351 | break; | |
352 | case IRQ_TYPE_EDGE_FALLING: | |
353 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
354 | break; | |
355 | case IRQ_TYPE_EDGE_BOTH: | |
356 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
357 | break; | |
358 | case IRQ_TYPE_LEVEL_HIGH: | |
359 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
360 | break; | |
361 | case IRQ_TYPE_LEVEL_LOW: | |
362 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
363 | break; | |
364 | default: | |
365 | pr_err("unsupported external interrupt type\n"); | |
366 | return -EINVAL; | |
367 | } | |
368 | ||
369 | if (type & IRQ_TYPE_EDGE_BOTH) | |
370 | __irq_set_handler_locked(irqd->irq, handle_edge_irq); | |
371 | else | |
372 | __irq_set_handler_locked(irqd->irq, handle_level_irq); | |
373 | ||
374 | con = readl(d->virt_base + reg_con); | |
375 | con &= ~(EXYNOS_EINT_CON_MASK << shift); | |
376 | con |= trig_type << shift; | |
377 | writel(con, d->virt_base + reg_con); | |
22b9ba03 | 378 | |
43fc9e7f | 379 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; |
499147c9 TF |
380 | shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC]; |
381 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
22b9ba03 | 382 | |
19846950 TF |
383 | spin_lock_irqsave(&bank->slock, flags); |
384 | ||
22b9ba03 TF |
385 | con = readl(d->virt_base + reg_con); |
386 | con &= ~(mask << shift); | |
387 | con |= EXYNOS_EINT_FUNC << shift; | |
388 | writel(con, d->virt_base + reg_con); | |
389 | ||
19846950 TF |
390 | spin_unlock_irqrestore(&bank->slock, flags); |
391 | ||
43b169db TA |
392 | return 0; |
393 | } | |
394 | ||
ad350cd9 TF |
395 | static u32 exynos_eint_wake_mask = 0xffffffff; |
396 | ||
397 | u32 exynos_get_eint_wake_mask(void) | |
398 | { | |
399 | return exynos_eint_wake_mask; | |
400 | } | |
401 | ||
402 | static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) | |
403 | { | |
404 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); | |
405 | unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); | |
406 | ||
407 | pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); | |
408 | ||
409 | if (!on) | |
410 | exynos_eint_wake_mask |= bit; | |
411 | else | |
412 | exynos_eint_wake_mask &= ~bit; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
43b169db TA |
417 | /* |
418 | * irq_chip for wakeup interrupts | |
419 | */ | |
420 | static struct irq_chip exynos_wkup_irq_chip = { | |
421 | .name = "exynos_wkup_irq_chip", | |
422 | .irq_unmask = exynos_wkup_irq_unmask, | |
423 | .irq_mask = exynos_wkup_irq_mask, | |
424 | .irq_ack = exynos_wkup_irq_ack, | |
425 | .irq_set_type = exynos_wkup_irq_set_type, | |
ad350cd9 | 426 | .irq_set_wake = exynos_wkup_irq_set_wake, |
43b169db TA |
427 | }; |
428 | ||
429 | /* interrupt handler for wakeup interrupts 0..15 */ | |
430 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | |
431 | { | |
432 | struct exynos_weint_data *eintd = irq_get_handler_data(irq); | |
a04b07c0 | 433 | struct samsung_pin_bank *bank = eintd->bank; |
43b169db TA |
434 | struct irq_chip *chip = irq_get_chip(irq); |
435 | int eint_irq; | |
436 | ||
437 | chained_irq_enter(chip, desc); | |
438 | chip->irq_mask(&desc->irq_data); | |
439 | ||
440 | if (chip->irq_ack) | |
441 | chip->irq_ack(&desc->irq_data); | |
442 | ||
a04b07c0 | 443 | eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); |
43b169db TA |
444 | generic_handle_irq(eint_irq); |
445 | chip->irq_unmask(&desc->irq_data); | |
446 | chained_irq_exit(chip, desc); | |
447 | } | |
448 | ||
a04b07c0 TF |
449 | static inline void exynos_irq_demux_eint(unsigned long pend, |
450 | struct irq_domain *domain) | |
43b169db TA |
451 | { |
452 | unsigned int irq; | |
453 | ||
454 | while (pend) { | |
455 | irq = fls(pend) - 1; | |
a04b07c0 | 456 | generic_handle_irq(irq_find_mapping(domain, irq)); |
43b169db TA |
457 | pend &= ~(1 << irq); |
458 | } | |
459 | } | |
460 | ||
461 | /* interrupt handler for wakeup interrupt 16 */ | |
462 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |
463 | { | |
464 | struct irq_chip *chip = irq_get_chip(irq); | |
a04b07c0 TF |
465 | struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); |
466 | struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; | |
467 | struct samsung_pin_ctrl *ctrl = d->ctrl; | |
43b169db | 468 | unsigned long pend; |
de59049b | 469 | unsigned long mask; |
a04b07c0 | 470 | int i; |
43b169db TA |
471 | |
472 | chained_irq_enter(chip, desc); | |
a04b07c0 TF |
473 | |
474 | for (i = 0; i < eintd->nr_banks; ++i) { | |
475 | struct samsung_pin_bank *b = eintd->banks[i]; | |
476 | pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset); | |
477 | mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset); | |
478 | exynos_irq_demux_eint(pend & ~mask, b->irq_domain); | |
479 | } | |
480 | ||
43b169db TA |
481 | chained_irq_exit(chip, desc); |
482 | } | |
483 | ||
484 | static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq, | |
485 | irq_hw_number_t hw) | |
486 | { | |
487 | irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq); | |
488 | irq_set_chip_data(virq, h->host_data); | |
489 | set_irq_flags(virq, IRQF_VALID); | |
490 | return 0; | |
491 | } | |
492 | ||
493 | /* | |
494 | * irq domain callbacks for external wakeup interrupt controller. | |
495 | */ | |
496 | static const struct irq_domain_ops exynos_wkup_irqd_ops = { | |
497 | .map = exynos_wkup_irq_map, | |
498 | .xlate = irq_domain_xlate_twocell, | |
499 | }; | |
500 | ||
501 | /* | |
502 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. | |
503 | * @d: driver data of samsung pinctrl driver. | |
504 | */ | |
505 | static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) | |
506 | { | |
507 | struct device *dev = d->dev; | |
c3ad056b TF |
508 | struct device_node *wkup_np = NULL; |
509 | struct device_node *np; | |
a04b07c0 | 510 | struct samsung_pin_bank *bank; |
43b169db | 511 | struct exynos_weint_data *weint_data; |
a04b07c0 TF |
512 | struct exynos_muxed_weint_data *muxed_data; |
513 | unsigned int muxed_banks = 0; | |
514 | unsigned int i; | |
43b169db TA |
515 | int idx, irq; |
516 | ||
c3ad056b TF |
517 | for_each_child_of_node(dev->of_node, np) { |
518 | if (of_match_node(exynos_wkup_irq_ids, np)) { | |
519 | wkup_np = np; | |
520 | break; | |
521 | } | |
43b169db | 522 | } |
c3ad056b TF |
523 | if (!wkup_np) |
524 | return -ENODEV; | |
43b169db | 525 | |
a04b07c0 TF |
526 | bank = d->ctrl->pin_banks; |
527 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
528 | if (bank->eint_type != EINT_TYPE_WKUP) | |
529 | continue; | |
43b169db | 530 | |
a04b07c0 TF |
531 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
532 | bank->nr_pins, &exynos_wkup_irqd_ops, bank); | |
533 | if (!bank->irq_domain) { | |
534 | dev_err(dev, "wkup irq domain add failed\n"); | |
535 | return -ENXIO; | |
536 | } | |
43b169db | 537 | |
a04b07c0 TF |
538 | if (!of_find_property(bank->of_node, "interrupts", NULL)) { |
539 | bank->eint_type = EINT_TYPE_WKUP_MUX; | |
540 | ++muxed_banks; | |
541 | continue; | |
542 | } | |
43b169db | 543 | |
a04b07c0 TF |
544 | weint_data = devm_kzalloc(dev, bank->nr_pins |
545 | * sizeof(*weint_data), GFP_KERNEL); | |
546 | if (!weint_data) { | |
547 | dev_err(dev, "could not allocate memory for weint_data\n"); | |
548 | return -ENOMEM; | |
549 | } | |
43b169db | 550 | |
a04b07c0 TF |
551 | for (idx = 0; idx < bank->nr_pins; ++idx) { |
552 | irq = irq_of_parse_and_map(bank->of_node, idx); | |
553 | if (!irq) { | |
554 | dev_err(dev, "irq number for eint-%s-%d not found\n", | |
555 | bank->name, idx); | |
556 | continue; | |
557 | } | |
558 | weint_data[idx].irq = idx; | |
559 | weint_data[idx].bank = bank; | |
43b169db TA |
560 | irq_set_handler_data(irq, &weint_data[idx]); |
561 | irq_set_chained_handler(irq, exynos_irq_eint0_15); | |
43b169db TA |
562 | } |
563 | } | |
a04b07c0 TF |
564 | |
565 | if (!muxed_banks) | |
566 | return 0; | |
567 | ||
568 | irq = irq_of_parse_and_map(wkup_np, 0); | |
569 | if (!irq) { | |
570 | dev_err(dev, "irq number for muxed EINTs not found\n"); | |
571 | return 0; | |
572 | } | |
573 | ||
574 | muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) | |
575 | + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); | |
576 | if (!muxed_data) { | |
577 | dev_err(dev, "could not allocate memory for muxed_data\n"); | |
578 | return -ENOMEM; | |
579 | } | |
580 | ||
581 | irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); | |
582 | irq_set_handler_data(irq, muxed_data); | |
583 | ||
584 | bank = d->ctrl->pin_banks; | |
585 | idx = 0; | |
586 | for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { | |
587 | if (bank->eint_type != EINT_TYPE_WKUP_MUX) | |
588 | continue; | |
589 | ||
590 | muxed_data->banks[idx++] = bank; | |
591 | } | |
592 | muxed_data->nr_banks = muxed_banks; | |
593 | ||
43b169db TA |
594 | return 0; |
595 | } | |
596 | ||
7ccbc60c TF |
597 | static void exynos_pinctrl_suspend_bank( |
598 | struct samsung_pinctrl_drv_data *drvdata, | |
599 | struct samsung_pin_bank *bank) | |
600 | { | |
601 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
602 | void __iomem *regs = drvdata->virt_base; | |
603 | ||
604 | save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
605 | + bank->eint_offset); | |
606 | save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
607 | + 2 * bank->eint_offset); | |
608 | save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
609 | + 2 * bank->eint_offset + 4); | |
610 | ||
611 | pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); | |
612 | pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); | |
613 | pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); | |
614 | } | |
615 | ||
616 | static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) | |
617 | { | |
618 | struct samsung_pin_ctrl *ctrl = drvdata->ctrl; | |
619 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
620 | int i; | |
621 | ||
622 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) | |
623 | if (bank->eint_type == EINT_TYPE_GPIO) | |
624 | exynos_pinctrl_suspend_bank(drvdata, bank); | |
625 | } | |
626 | ||
627 | static void exynos_pinctrl_resume_bank( | |
628 | struct samsung_pinctrl_drv_data *drvdata, | |
629 | struct samsung_pin_bank *bank) | |
630 | { | |
631 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
632 | void __iomem *regs = drvdata->virt_base; | |
633 | ||
634 | pr_debug("%s: con %#010x => %#010x\n", bank->name, | |
635 | readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
636 | + bank->eint_offset), save->eint_con); | |
637 | pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, | |
638 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
639 | + 2 * bank->eint_offset), save->eint_fltcon0); | |
640 | pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, | |
641 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
642 | + 2 * bank->eint_offset + 4), save->eint_fltcon1); | |
643 | ||
644 | writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET | |
645 | + bank->eint_offset); | |
646 | writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
647 | + 2 * bank->eint_offset); | |
648 | writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
649 | + 2 * bank->eint_offset + 4); | |
650 | } | |
651 | ||
652 | static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) | |
653 | { | |
654 | struct samsung_pin_ctrl *ctrl = drvdata->ctrl; | |
655 | struct samsung_pin_bank *bank = ctrl->pin_banks; | |
656 | int i; | |
657 | ||
658 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) | |
659 | if (bank->eint_type == EINT_TYPE_GPIO) | |
660 | exynos_pinctrl_resume_bank(drvdata, bank); | |
661 | } | |
662 | ||
43b169db TA |
663 | /* pin banks of exynos4210 pin-controller 0 */ |
664 | static struct samsung_pin_bank exynos4210_pin_banks0[] = { | |
1b6056d6 TF |
665 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), |
666 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
667 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
668 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
669 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
670 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
671 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
672 | EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), | |
673 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), | |
674 | EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), | |
675 | EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), | |
676 | EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), | |
677 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
678 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
679 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
680 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
43b169db TA |
681 | }; |
682 | ||
683 | /* pin banks of exynos4210 pin-controller 1 */ | |
684 | static struct samsung_pin_bank exynos4210_pin_banks1[] = { | |
1b6056d6 TF |
685 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), |
686 | EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), | |
687 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
688 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
689 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
690 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
691 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), | |
692 | EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), | |
693 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
40ba6227 TF |
694 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), |
695 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
696 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
697 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
698 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
699 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
700 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
a04b07c0 TF |
701 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), |
702 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
703 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
704 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
43b169db TA |
705 | }; |
706 | ||
707 | /* pin banks of exynos4210 pin-controller 2 */ | |
708 | static struct samsung_pin_bank exynos4210_pin_banks2[] = { | |
40ba6227 | 709 | EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), |
43b169db TA |
710 | }; |
711 | ||
712 | /* | |
713 | * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes | |
714 | * three gpio/pin-mux/pinconfig controllers. | |
715 | */ | |
716 | struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { | |
717 | { | |
718 | /* pin-controller instance 0 data */ | |
719 | .pin_banks = exynos4210_pin_banks0, | |
720 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), | |
43b169db TA |
721 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
722 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
723 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
724 | .svc = EXYNOS_SVC_OFFSET, | |
725 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
726 | .suspend = exynos_pinctrl_suspend, |
727 | .resume = exynos_pinctrl_resume, | |
43b169db TA |
728 | .label = "exynos4210-gpio-ctrl0", |
729 | }, { | |
730 | /* pin-controller instance 1 data */ | |
731 | .pin_banks = exynos4210_pin_banks1, | |
732 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), | |
43b169db TA |
733 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, |
734 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
735 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
736 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
737 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
738 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
739 | .svc = EXYNOS_SVC_OFFSET, | |
740 | .eint_gpio_init = exynos_eint_gpio_init, | |
741 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
742 | .suspend = exynos_pinctrl_suspend, |
743 | .resume = exynos_pinctrl_resume, | |
43b169db TA |
744 | .label = "exynos4210-gpio-ctrl1", |
745 | }, { | |
746 | /* pin-controller instance 2 data */ | |
747 | .pin_banks = exynos4210_pin_banks2, | |
748 | .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), | |
43b169db TA |
749 | .label = "exynos4210-gpio-ctrl2", |
750 | }, | |
751 | }; | |
6edc794a TF |
752 | |
753 | /* pin banks of exynos4x12 pin-controller 0 */ | |
754 | static struct samsung_pin_bank exynos4x12_pin_banks0[] = { | |
755 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | |
756 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
757 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), | |
758 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), | |
759 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), | |
760 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), | |
761 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), | |
762 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), | |
763 | EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), | |
764 | EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), | |
765 | EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), | |
766 | EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), | |
767 | EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), | |
768 | }; | |
769 | ||
770 | /* pin banks of exynos4x12 pin-controller 1 */ | |
771 | static struct samsung_pin_bank exynos4x12_pin_banks1[] = { | |
772 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), | |
773 | EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), | |
774 | EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), | |
775 | EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), | |
776 | EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), | |
777 | EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), | |
778 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), | |
779 | EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), | |
780 | EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), | |
781 | EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), | |
782 | EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), | |
783 | EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), | |
784 | EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), | |
785 | EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), | |
786 | EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), | |
787 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), | |
788 | EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), | |
789 | EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), | |
790 | EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), | |
791 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), | |
792 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
793 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
794 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
795 | }; | |
796 | ||
797 | /* pin banks of exynos4x12 pin-controller 2 */ | |
798 | static struct samsung_pin_bank exynos4x12_pin_banks2[] = { | |
799 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), | |
800 | }; | |
801 | ||
802 | /* pin banks of exynos4x12 pin-controller 3 */ | |
803 | static struct samsung_pin_bank exynos4x12_pin_banks3[] = { | |
804 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), | |
805 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), | |
806 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), | |
807 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), | |
808 | EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), | |
809 | }; | |
810 | ||
811 | /* | |
812 | * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes | |
813 | * four gpio/pin-mux/pinconfig controllers. | |
814 | */ | |
815 | struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { | |
816 | { | |
817 | /* pin-controller instance 0 data */ | |
818 | .pin_banks = exynos4x12_pin_banks0, | |
819 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), | |
820 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
821 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
822 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
823 | .svc = EXYNOS_SVC_OFFSET, | |
824 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
825 | .suspend = exynos_pinctrl_suspend, |
826 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
827 | .label = "exynos4x12-gpio-ctrl0", |
828 | }, { | |
829 | /* pin-controller instance 1 data */ | |
830 | .pin_banks = exynos4x12_pin_banks1, | |
831 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), | |
832 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
833 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
834 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
835 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
836 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
837 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
838 | .svc = EXYNOS_SVC_OFFSET, | |
839 | .eint_gpio_init = exynos_eint_gpio_init, | |
840 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
841 | .suspend = exynos_pinctrl_suspend, |
842 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
843 | .label = "exynos4x12-gpio-ctrl1", |
844 | }, { | |
845 | /* pin-controller instance 2 data */ | |
846 | .pin_banks = exynos4x12_pin_banks2, | |
847 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), | |
848 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
849 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
850 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
851 | .svc = EXYNOS_SVC_OFFSET, | |
852 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
853 | .suspend = exynos_pinctrl_suspend, |
854 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
855 | .label = "exynos4x12-gpio-ctrl2", |
856 | }, { | |
857 | /* pin-controller instance 3 data */ | |
858 | .pin_banks = exynos4x12_pin_banks3, | |
859 | .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), | |
860 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
861 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
862 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
863 | .svc = EXYNOS_SVC_OFFSET, | |
864 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
865 | .suspend = exynos_pinctrl_suspend, |
866 | .resume = exynos_pinctrl_resume, | |
6edc794a TF |
867 | .label = "exynos4x12-gpio-ctrl3", |
868 | }, | |
869 | }; | |
f67faf48 TA |
870 | |
871 | /* pin banks of exynos5250 pin-controller 0 */ | |
872 | static struct samsung_pin_bank exynos5250_pin_banks0[] = { | |
873 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | |
874 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
875 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), | |
876 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), | |
877 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), | |
878 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), | |
879 | EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), | |
880 | EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), | |
881 | EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), | |
882 | EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), | |
883 | EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), | |
884 | EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), | |
885 | EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), | |
886 | EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), | |
887 | EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), | |
888 | EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), | |
889 | EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), | |
890 | EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), | |
891 | EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), | |
892 | EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), | |
893 | EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), | |
894 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), | |
895 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
896 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
897 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
898 | }; | |
899 | ||
900 | /* pin banks of exynos5250 pin-controller 1 */ | |
901 | static struct samsung_pin_bank exynos5250_pin_banks1[] = { | |
902 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), | |
903 | EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), | |
904 | EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), | |
905 | EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), | |
906 | EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), | |
907 | EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), | |
908 | EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), | |
909 | EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), | |
910 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), | |
911 | }; | |
912 | ||
913 | /* pin banks of exynos5250 pin-controller 2 */ | |
914 | static struct samsung_pin_bank exynos5250_pin_banks2[] = { | |
915 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), | |
916 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), | |
917 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), | |
918 | EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), | |
919 | EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), | |
920 | }; | |
921 | ||
922 | /* pin banks of exynos5250 pin-controller 3 */ | |
923 | static struct samsung_pin_bank exynos5250_pin_banks3[] = { | |
924 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), | |
925 | }; | |
926 | ||
927 | /* | |
928 | * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes | |
929 | * four gpio/pin-mux/pinconfig controllers. | |
930 | */ | |
931 | struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { | |
932 | { | |
933 | /* pin-controller instance 0 data */ | |
934 | .pin_banks = exynos5250_pin_banks0, | |
935 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), | |
936 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
937 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
938 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
939 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
940 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
941 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
942 | .svc = EXYNOS_SVC_OFFSET, | |
943 | .eint_gpio_init = exynos_eint_gpio_init, | |
944 | .eint_wkup_init = exynos_eint_wkup_init, | |
7ccbc60c TF |
945 | .suspend = exynos_pinctrl_suspend, |
946 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
947 | .label = "exynos5250-gpio-ctrl0", |
948 | }, { | |
949 | /* pin-controller instance 1 data */ | |
950 | .pin_banks = exynos5250_pin_banks1, | |
951 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), | |
952 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
953 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
954 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
955 | .svc = EXYNOS_SVC_OFFSET, | |
956 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
957 | .suspend = exynos_pinctrl_suspend, |
958 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
959 | .label = "exynos5250-gpio-ctrl1", |
960 | }, { | |
961 | /* pin-controller instance 2 data */ | |
962 | .pin_banks = exynos5250_pin_banks2, | |
963 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), | |
964 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
965 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
966 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
967 | .svc = EXYNOS_SVC_OFFSET, | |
968 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
969 | .suspend = exynos_pinctrl_suspend, |
970 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
971 | .label = "exynos5250-gpio-ctrl2", |
972 | }, { | |
973 | /* pin-controller instance 3 data */ | |
974 | .pin_banks = exynos5250_pin_banks3, | |
975 | .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), | |
976 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
977 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
978 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
979 | .svc = EXYNOS_SVC_OFFSET, | |
980 | .eint_gpio_init = exynos_eint_gpio_init, | |
7ccbc60c TF |
981 | .suspend = exynos_pinctrl_suspend, |
982 | .resume = exynos_pinctrl_resume, | |
f67faf48 TA |
983 | .label = "exynos5250-gpio-ctrl3", |
984 | }, | |
985 | }; | |
983dbeb3 LKA |
986 | |
987 | /* pin banks of exynos5420 pin-controller 0 */ | |
988 | static struct samsung_pin_bank exynos5420_pin_banks0[] = { | |
989 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), | |
990 | EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), | |
991 | EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), | |
992 | EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), | |
993 | EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), | |
994 | }; | |
995 | ||
996 | /* pin banks of exynos5420 pin-controller 1 */ | |
997 | static struct samsung_pin_bank exynos5420_pin_banks1[] = { | |
998 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), | |
999 | EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), | |
1000 | EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), | |
1001 | EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), | |
1002 | EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), | |
1003 | EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), | |
1004 | EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), | |
1005 | EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), | |
1006 | EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), | |
1007 | EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), | |
1008 | EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), | |
1009 | EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), | |
1010 | EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), | |
1011 | }; | |
1012 | ||
1013 | /* pin banks of exynos5420 pin-controller 2 */ | |
1014 | static struct samsung_pin_bank exynos5420_pin_banks2[] = { | |
1015 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), | |
1016 | EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), | |
1017 | EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), | |
1018 | EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), | |
1019 | EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), | |
1020 | EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), | |
1021 | EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), | |
1022 | EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), | |
1023 | }; | |
1024 | ||
1025 | /* pin banks of exynos5420 pin-controller 3 */ | |
1026 | static struct samsung_pin_bank exynos5420_pin_banks3[] = { | |
1027 | EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), | |
1028 | EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), | |
1029 | EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), | |
1030 | EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), | |
1031 | EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), | |
1032 | EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), | |
1033 | EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), | |
1034 | EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), | |
1035 | EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), | |
1036 | }; | |
1037 | ||
1038 | /* pin banks of exynos5420 pin-controller 4 */ | |
1039 | static struct samsung_pin_bank exynos5420_pin_banks4[] = { | |
1040 | EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), | |
1041 | }; | |
1042 | ||
1043 | /* | |
1044 | * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes | |
1045 | * four gpio/pin-mux/pinconfig controllers. | |
1046 | */ | |
1047 | struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { | |
1048 | { | |
1049 | /* pin-controller instance 0 data */ | |
1050 | .pin_banks = exynos5420_pin_banks0, | |
1051 | .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), | |
1052 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
1053 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
1054 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
1055 | .weint_con = EXYNOS_WKUP_ECON_OFFSET, | |
1056 | .weint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
1057 | .weint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
1058 | .svc = EXYNOS_SVC_OFFSET, | |
1059 | .eint_gpio_init = exynos_eint_gpio_init, | |
1060 | .eint_wkup_init = exynos_eint_wkup_init, | |
1061 | .label = "exynos5420-gpio-ctrl0", | |
1062 | }, { | |
1063 | /* pin-controller instance 1 data */ | |
1064 | .pin_banks = exynos5420_pin_banks1, | |
1065 | .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), | |
1066 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
1067 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
1068 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
1069 | .svc = EXYNOS_SVC_OFFSET, | |
1070 | .eint_gpio_init = exynos_eint_gpio_init, | |
1071 | .label = "exynos5420-gpio-ctrl1", | |
1072 | }, { | |
1073 | /* pin-controller instance 2 data */ | |
1074 | .pin_banks = exynos5420_pin_banks2, | |
1075 | .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), | |
1076 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
1077 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
1078 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
1079 | .svc = EXYNOS_SVC_OFFSET, | |
1080 | .eint_gpio_init = exynos_eint_gpio_init, | |
1081 | .label = "exynos5420-gpio-ctrl2", | |
1082 | }, { | |
1083 | /* pin-controller instance 3 data */ | |
1084 | .pin_banks = exynos5420_pin_banks3, | |
1085 | .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), | |
1086 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
1087 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
1088 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
1089 | .svc = EXYNOS_SVC_OFFSET, | |
1090 | .eint_gpio_init = exynos_eint_gpio_init, | |
1091 | .label = "exynos5420-gpio-ctrl3", | |
1092 | }, { | |
1093 | /* pin-controller instance 4 data */ | |
1094 | .pin_banks = exynos5420_pin_banks4, | |
1095 | .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), | |
1096 | .geint_con = EXYNOS_GPIO_ECON_OFFSET, | |
1097 | .geint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
1098 | .geint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
1099 | .svc = EXYNOS_SVC_OFFSET, | |
1100 | .eint_gpio_init = exynos_eint_gpio_init, | |
1101 | .label = "exynos5420-gpio-ctrl4", | |
1102 | }, | |
1103 | }; |