Commit | Line | Data |
---|---|---|
43b169db TA |
1 | /* |
2 | * Exynos specific definitions for Samsung pinctrl and gpiolib driver. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * This file contains the Exynos specific definitions for the Samsung | |
10 | * pinctrl/gpiolib interface drivers. | |
11 | * | |
12 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or | |
17 | * (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #define EXYNOS_GPIO_START(__gpio) ((__gpio##_START) + (__gpio##_NR)) | |
21 | ||
22 | #define EXYNOS4210_GPIO_A0_NR (8) | |
23 | #define EXYNOS4210_GPIO_A1_NR (6) | |
24 | #define EXYNOS4210_GPIO_B_NR (8) | |
25 | #define EXYNOS4210_GPIO_C0_NR (5) | |
26 | #define EXYNOS4210_GPIO_C1_NR (5) | |
27 | #define EXYNOS4210_GPIO_D0_NR (4) | |
28 | #define EXYNOS4210_GPIO_D1_NR (4) | |
29 | #define EXYNOS4210_GPIO_E0_NR (5) | |
30 | #define EXYNOS4210_GPIO_E1_NR (8) | |
31 | #define EXYNOS4210_GPIO_E2_NR (6) | |
32 | #define EXYNOS4210_GPIO_E3_NR (8) | |
33 | #define EXYNOS4210_GPIO_E4_NR (8) | |
34 | #define EXYNOS4210_GPIO_F0_NR (8) | |
35 | #define EXYNOS4210_GPIO_F1_NR (8) | |
36 | #define EXYNOS4210_GPIO_F2_NR (8) | |
37 | #define EXYNOS4210_GPIO_F3_NR (6) | |
38 | #define EXYNOS4210_GPIO_J0_NR (8) | |
39 | #define EXYNOS4210_GPIO_J1_NR (5) | |
40 | #define EXYNOS4210_GPIO_K0_NR (7) | |
41 | #define EXYNOS4210_GPIO_K1_NR (7) | |
42 | #define EXYNOS4210_GPIO_K2_NR (7) | |
43 | #define EXYNOS4210_GPIO_K3_NR (7) | |
44 | #define EXYNOS4210_GPIO_L0_NR (8) | |
45 | #define EXYNOS4210_GPIO_L1_NR (3) | |
46 | #define EXYNOS4210_GPIO_L2_NR (8) | |
47 | #define EXYNOS4210_GPIO_Y0_NR (6) | |
48 | #define EXYNOS4210_GPIO_Y1_NR (4) | |
49 | #define EXYNOS4210_GPIO_Y2_NR (6) | |
50 | #define EXYNOS4210_GPIO_Y3_NR (8) | |
51 | #define EXYNOS4210_GPIO_Y4_NR (8) | |
52 | #define EXYNOS4210_GPIO_Y5_NR (8) | |
53 | #define EXYNOS4210_GPIO_Y6_NR (8) | |
54 | #define EXYNOS4210_GPIO_X0_NR (8) | |
55 | #define EXYNOS4210_GPIO_X1_NR (8) | |
56 | #define EXYNOS4210_GPIO_X2_NR (8) | |
57 | #define EXYNOS4210_GPIO_X3_NR (8) | |
58 | #define EXYNOS4210_GPIO_Z_NR (7) | |
59 | ||
60 | enum exynos4210_gpio_xa_start { | |
61 | EXYNOS4210_GPIO_A0_START = 0, | |
62 | EXYNOS4210_GPIO_A1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A0), | |
63 | EXYNOS4210_GPIO_B_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_A1), | |
64 | EXYNOS4210_GPIO_C0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_B), | |
65 | EXYNOS4210_GPIO_C1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C0), | |
66 | EXYNOS4210_GPIO_D0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_C1), | |
67 | EXYNOS4210_GPIO_D1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D0), | |
68 | EXYNOS4210_GPIO_E0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_D1), | |
69 | EXYNOS4210_GPIO_E1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E0), | |
70 | EXYNOS4210_GPIO_E2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E1), | |
71 | EXYNOS4210_GPIO_E3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E2), | |
72 | EXYNOS4210_GPIO_E4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E3), | |
73 | EXYNOS4210_GPIO_F0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_E4), | |
74 | EXYNOS4210_GPIO_F1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F0), | |
75 | EXYNOS4210_GPIO_F2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F1), | |
76 | EXYNOS4210_GPIO_F3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_F2), | |
77 | }; | |
78 | ||
79 | enum exynos4210_gpio_xb_start { | |
80 | EXYNOS4210_GPIO_J0_START = 0, | |
81 | EXYNOS4210_GPIO_J1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J0), | |
82 | EXYNOS4210_GPIO_K0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_J1), | |
83 | EXYNOS4210_GPIO_K1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K0), | |
84 | EXYNOS4210_GPIO_K2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K1), | |
85 | EXYNOS4210_GPIO_K3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K2), | |
86 | EXYNOS4210_GPIO_L0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_K3), | |
87 | EXYNOS4210_GPIO_L1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L0), | |
88 | EXYNOS4210_GPIO_L2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L1), | |
89 | EXYNOS4210_GPIO_Y0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2), | |
90 | EXYNOS4210_GPIO_Y1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y0), | |
91 | EXYNOS4210_GPIO_Y2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y1), | |
92 | EXYNOS4210_GPIO_Y3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y2), | |
93 | EXYNOS4210_GPIO_Y4_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y3), | |
94 | EXYNOS4210_GPIO_Y5_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y4), | |
95 | EXYNOS4210_GPIO_Y6_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y5), | |
96 | EXYNOS4210_GPIO_X0_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_Y6), | |
97 | EXYNOS4210_GPIO_X1_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X0), | |
98 | EXYNOS4210_GPIO_X2_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X1), | |
99 | EXYNOS4210_GPIO_X3_START = EXYNOS_GPIO_START(EXYNOS4210_GPIO_X2), | |
100 | }; | |
101 | ||
102 | enum exynos4210_gpio_xc_start { | |
103 | EXYNOS4210_GPIO_Z_START = 0, | |
104 | }; | |
105 | ||
106 | #define EXYNOS4210_GPIO_A0_IRQ EXYNOS4210_GPIO_A0_START | |
107 | #define EXYNOS4210_GPIO_A1_IRQ EXYNOS4210_GPIO_A1_START | |
108 | #define EXYNOS4210_GPIO_B_IRQ EXYNOS4210_GPIO_B_START | |
109 | #define EXYNOS4210_GPIO_C0_IRQ EXYNOS4210_GPIO_C0_START | |
110 | #define EXYNOS4210_GPIO_C1_IRQ EXYNOS4210_GPIO_C1_START | |
111 | #define EXYNOS4210_GPIO_D0_IRQ EXYNOS4210_GPIO_D0_START | |
112 | #define EXYNOS4210_GPIO_D1_IRQ EXYNOS4210_GPIO_D1_START | |
113 | #define EXYNOS4210_GPIO_E0_IRQ EXYNOS4210_GPIO_E0_START | |
114 | #define EXYNOS4210_GPIO_E1_IRQ EXYNOS4210_GPIO_E1_START | |
115 | #define EXYNOS4210_GPIO_E2_IRQ EXYNOS4210_GPIO_E2_START | |
116 | #define EXYNOS4210_GPIO_E3_IRQ EXYNOS4210_GPIO_E3_START | |
117 | #define EXYNOS4210_GPIO_E4_IRQ EXYNOS4210_GPIO_E4_START | |
118 | #define EXYNOS4210_GPIO_F0_IRQ EXYNOS4210_GPIO_F0_START | |
119 | #define EXYNOS4210_GPIO_F1_IRQ EXYNOS4210_GPIO_F1_START | |
120 | #define EXYNOS4210_GPIO_F2_IRQ EXYNOS4210_GPIO_F2_START | |
121 | #define EXYNOS4210_GPIO_F3_IRQ EXYNOS4210_GPIO_F3_START | |
122 | #define EXYNOS4210_GPIO_J0_IRQ EXYNOS4210_GPIO_J0_START | |
123 | #define EXYNOS4210_GPIO_J1_IRQ EXYNOS4210_GPIO_J1_START | |
124 | #define EXYNOS4210_GPIO_K0_IRQ EXYNOS4210_GPIO_K0_START | |
125 | #define EXYNOS4210_GPIO_K1_IRQ EXYNOS4210_GPIO_K1_START | |
126 | #define EXYNOS4210_GPIO_K2_IRQ EXYNOS4210_GPIO_K2_START | |
127 | #define EXYNOS4210_GPIO_K3_IRQ EXYNOS4210_GPIO_K3_START | |
128 | #define EXYNOS4210_GPIO_L0_IRQ EXYNOS4210_GPIO_L0_START | |
129 | #define EXYNOS4210_GPIO_L1_IRQ EXYNOS4210_GPIO_L1_START | |
130 | #define EXYNOS4210_GPIO_L2_IRQ EXYNOS4210_GPIO_L2_START | |
131 | #define EXYNOS4210_GPIO_Z_IRQ EXYNOS4210_GPIO_Z_START | |
132 | ||
133 | #define EXYNOS4210_GPIOA_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3) | |
134 | #define EXYNOS4210_GPIOA_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_F3) | |
135 | #define EXYNOS4210_GPIOB_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_X3) | |
136 | #define EXYNOS4210_GPIOB_NR_GINT EXYNOS_GPIO_START(EXYNOS4210_GPIO_L2) | |
137 | #define EXYNOS4210_GPIOC_NR_PINS EXYNOS_GPIO_START(EXYNOS4210_GPIO_Z) | |
138 | ||
139 | /* External GPIO and wakeup interrupt related definitions */ | |
140 | #define EXYNOS_GPIO_ECON_OFFSET 0x700 | |
141 | #define EXYNOS_GPIO_EMASK_OFFSET 0x900 | |
142 | #define EXYNOS_GPIO_EPEND_OFFSET 0xA00 | |
143 | #define EXYNOS_WKUP_ECON_OFFSET 0xE00 | |
144 | #define EXYNOS_WKUP_EMASK_OFFSET 0xF00 | |
145 | #define EXYNOS_WKUP_EPEND_OFFSET 0xF40 | |
146 | #define EXYNOS_SVC_OFFSET 0xB08 | |
ee2f573c | 147 | #define EXYNOS_EINT_FUNC 0xF |
43b169db TA |
148 | |
149 | /* helpers to access interrupt service register */ | |
150 | #define EXYNOS_SVC_GROUP_SHIFT 3 | |
151 | #define EXYNOS_SVC_GROUP_MASK 0x1f | |
152 | #define EXYNOS_SVC_NUM_MASK 7 | |
153 | #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \ | |
154 | EXYNOS_SVC_GROUP_MASK) | |
155 | ||
156 | /* Exynos specific external interrupt trigger types */ | |
157 | #define EXYNOS_EINT_LEVEL_LOW 0 | |
158 | #define EXYNOS_EINT_LEVEL_HIGH 1 | |
159 | #define EXYNOS_EINT_EDGE_FALLING 2 | |
160 | #define EXYNOS_EINT_EDGE_RISING 3 | |
161 | #define EXYNOS_EINT_EDGE_BOTH 4 | |
162 | #define EXYNOS_EINT_CON_MASK 0xF | |
163 | #define EXYNOS_EINT_CON_LEN 4 | |
164 | ||
165 | #define EXYNOS_EINT_MAX_PER_BANK 8 | |
166 | #define EXYNOS_EINT_NR_WKUP_EINT | |
167 | ||
168 | #define EXYNOS_PIN_BANK_EINTN(reg, __gpio, id) \ | |
169 | { \ | |
170 | .pctl_offset = reg, \ | |
171 | .pin_base = (__gpio##_START), \ | |
172 | .nr_pins = (__gpio##_NR), \ | |
173 | .func_width = 4, \ | |
174 | .pud_width = 2, \ | |
175 | .drv_width = 2, \ | |
176 | .conpdn_width = 2, \ | |
177 | .pudpdn_width = 2, \ | |
178 | .eint_type = EINT_TYPE_NONE, \ | |
179 | .name = id \ | |
180 | } | |
181 | ||
182 | #define EXYNOS_PIN_BANK_EINTG(reg, __gpio, id) \ | |
183 | { \ | |
184 | .pctl_offset = reg, \ | |
185 | .pin_base = (__gpio##_START), \ | |
186 | .nr_pins = (__gpio##_NR), \ | |
187 | .func_width = 4, \ | |
188 | .pud_width = 2, \ | |
189 | .drv_width = 2, \ | |
190 | .conpdn_width = 2, \ | |
191 | .pudpdn_width = 2, \ | |
192 | .eint_type = EINT_TYPE_GPIO, \ | |
193 | .irq_base = (__gpio##_IRQ), \ | |
194 | .name = id \ | |
195 | } | |
196 | ||
197 | /** | |
198 | * struct exynos_geint_data: gpio eint specific data for irq_chip callbacks. | |
199 | * @bank: pin bank from which this gpio interrupt originates. | |
200 | * @pin: pin number within the bank. | |
201 | * @eint_offset: offset to be added to the con/pend/mask register bank base. | |
202 | */ | |
203 | struct exynos_geint_data { | |
204 | struct samsung_pin_bank *bank; | |
205 | u32 pin; | |
206 | u32 eint_offset; | |
207 | }; | |
208 | ||
209 | /** | |
210 | * struct exynos_weint_data: irq specific data for all the wakeup interrupts | |
211 | * generated by the external wakeup interrupt controller. | |
212 | * @domain: irq domain representing the external wakeup interrupts | |
213 | * @irq: interrupt number within the domain. | |
214 | */ | |
215 | struct exynos_weint_data { | |
216 | struct irq_domain *domain; | |
217 | u32 irq; | |
218 | }; |