[deliverable/linux.git] / drivers / pinctrl / pinctrl-imx.c

/*
 * Core driver for the imx pin controller
 *
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Linaro Ltd.
 *
 * Author: Dong Aisheng <dong.aisheng@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>

#include "core.h"
#include "pinctrl-imx.h"

#define IMX_PMX_DUMP(info, p, m, c, n)			\
{							\
	int i, j;					\
	printk(KERN_DEBUG "Format: Pin Mux Config\n");	\
	for (i = 0; i < n; i++) {			\
		j = p[i];				\
		printk(KERN_DEBUG "%s %d 0x%lx\n",	\
			info->pins[j].name,		\
			m[i], c[i]);			\
	}						\
}

/* The bits in CONFIG cell defined in binding doc*/
#define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
#define IMX_PAD_SION 0x40000000		/* set SION */

/**
 * @dev: a pointer back to containing device
 * @base: the offset to the controller in virtual memory
 */
struct imx_pinctrl {
	struct device *dev;
	struct pinctrl_dev *pctl;
	void __iomem *base;
	const struct imx_pinctrl_soc_info *info;
};

static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
				const struct imx_pinctrl_soc_info *info,
				const char *name)
{
	const struct imx_pin_group *grp = NULL;
	int i;

	for (i = 0; i < info->ngroups; i++) {
		if (!strcmp(info->groups[i].name, name)) {
			grp = &info->groups[i];
			break;
		}
	}

	return grp;
}

static int imx_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->ngroups;
}

static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
				       unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->groups[selector].name;
}

static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
			       const unsigned **pins,
			       unsigned *npins)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	if (selector >= info->ngroups)
		return -EINVAL;

	*pins = info->groups[selector].pins;
	*npins = info->groups[selector].npins;

	return 0;
}

static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
		   unsigned offset)
{
	seq_printf(s, "%s", dev_name(pctldev->dev));
}

static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
			struct device_node *np,
			struct pinctrl_map **map, unsigned *num_maps)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_group *grp;
	struct pinctrl_map *new_map;
	struct device_node *parent;
	int map_num = 1;
	int i, j;

	/*
	 * first find the group of this node and check if we need create
	 * config maps for pins
	 */
	grp = imx_pinctrl_find_group_by_name(info, np->name);
	if (!grp) {
		dev_err(info->dev, "unable to find group for node %s\n",
			np->name);
		return -EINVAL;
	}

	for (i = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL))
			map_num++;
	}

	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	if (!new_map)
		return -ENOMEM;

	*map = new_map;
	*num_maps = map_num;

	/* create mux map */
	parent = of_get_parent(np);
	if (!parent) {
		kfree(new_map);
		return -EINVAL;
	}
	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	new_map[0].data.mux.function = parent->name;
	new_map[0].data.mux.group = np->name;
	of_node_put(parent);

	/* create config map */
	new_map++;
	for (i = j = 0; i < grp->npins; i++) {
		if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
			new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
			new_map[j].data.configs.group_or_pin =
					pin_get_name(pctldev, grp->pins[i]);
			new_map[j].data.configs.configs = &grp->configs[i];
			new_map[j].data.configs.num_configs = 1;
			j++;
		}
	}

	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
		(*map)->data.mux.function, (*map)->data.mux.group, map_num);

	return 0;
}

static void imx_dt_free_map(struct pinctrl_dev *pctldev,
				struct pinctrl_map *map, unsigned num_maps)
{
	kfree(map);
}

static const struct pinctrl_ops imx_pctrl_ops = {
	.get_groups_count = imx_get_groups_count,
	.get_group_name = imx_get_group_name,
	.get_group_pins = imx_get_group_pins,
	.pin_dbg_show = imx_pin_dbg_show,
	.dt_node_to_map = imx_dt_node_to_map,
	.dt_free_map = imx_dt_free_map,

};

static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
			   unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg;
	const unsigned *pins, *mux, *input_val;
	u16 *input_reg;
	unsigned int npins, pin_id;
	int i;

	/*
	 * Configure the mux mode for each pin in the group for a specific
	 * function.
	 */
	pins = info->groups[group].pins;
	npins = info->groups[group].npins;
	mux = info->groups[group].mux_mode;
	input_val = info->groups[group].input_val;
	input_reg = info->groups[group].input_reg;

	WARN_ON(!pins || !npins || !mux || !input_val || !input_reg);

	dev_dbg(ipctl->dev, "enable function %s group %s\n",
		info->functions[selector].name, info->groups[group].name);

	for (i = 0; i < npins; i++) {
		pin_id = pins[i];
		pin_reg = &info->pin_regs[pin_id];

		if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
			dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
				info->pins[pin_id].name);
			return -EINVAL;
		}

		if (info->flags & SHARE_MUX_CONF_REG) {
			u32 reg;
			reg = readl(ipctl->base + pin_reg->mux_reg);
			reg &= ~(0x7 << 20);
			reg |= (mux[i] << 20);
			writel(reg, ipctl->base + pin_reg->mux_reg);
		} else {
			writel(mux[i], ipctl->base + pin_reg->mux_reg);
		}
		dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
			pin_reg->mux_reg, mux[i]);

		/*
		 * If the select input value begins with 0xff, it's a quirky
		 * select input and the value should be interpreted as below.
		 *     31     23      15      7        0
		 *     | 0xff | shift | width | select |
		 * It's used to work around the problem that the select
		 * input for some pin is not implemented in the select
		 * input register but in some general purpose register.
		 * We encode the select input value, width and shift of
		 * the bit field into input_val cell of pin function ID
		 * in device tree, and then decode them here for setting
		 * up the select input bits in general purpose register.
		 */
		if (input_val[i] >> 24 == 0xff) {
			u32 val = input_val[i];
			u8 select = val & 0xff;
			u8 width = (val >> 8) & 0xff;
			u8 shift = (val >> 16) & 0xff;
			u32 mask = ((1 << width) - 1) << shift;
			/*
			 * The input_reg[i] here is actually some IOMUXC general
			 * purpose register, not regular select input register.
			 */
			val = readl(ipctl->base + input_reg[i]);
			val &= ~mask;
			val |= select << shift;
			writel(val, ipctl->base + input_reg[i]);
		} else if (input_reg[i]) {
			/*
			 * Regular select input register can never be at offset
			 * 0, and we only print register value for regular case.
			 */
			writel(input_val[i], ipctl->base + input_reg[i]);
			dev_dbg(ipctl->dev,
				"==>select_input: offset 0x%x val 0x%x\n",
				input_reg[i], input_val[i]);
		}
	}

	return 0;
}

static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->nfunctions;
}

static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
					  unsigned selector)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	return info->functions[selector].name;
}

static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
			       const char * const **groups,
			       unsigned * const num_groups)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;

	*groups = info->functions[selector].groups;
	*num_groups = info->functions[selector].num_groups;

	return 0;
}

static const struct pinmux_ops imx_pmx_ops = {
	.get_functions_count = imx_pmx_get_funcs_count,
	.get_function_name = imx_pmx_get_func_name,
	.get_function_groups = imx_pmx_get_groups,
	.enable = imx_pmx_enable,
};

static int imx_pinconf_get(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long *config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	*config = readl(ipctl->base + pin_reg->conf_reg);

	if (info->flags & SHARE_MUX_CONF_REG)
		*config &= 0xffff;

	return 0;
}

static int imx_pinconf_set(struct pinctrl_dev *pctldev,
			     unsigned pin_id, unsigned long config)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];

	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
		dev_err(info->dev, "Pin(%s) does not support config function\n",
			info->pins[pin_id].name);
		return -EINVAL;
	}

	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
		info->pins[pin_id].name);

	if (info->flags & SHARE_MUX_CONF_REG) {
		u32 reg;
		reg = readl(ipctl->base + pin_reg->conf_reg);
		reg &= ~0xffff;
		reg |= config;
		writel(reg, ipctl->base + pin_reg->conf_reg);
	} else {
		writel(config, ipctl->base + pin_reg->conf_reg);
	}
	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
		pin_reg->conf_reg, config);

	return 0;
}

static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
				   struct seq_file *s, unsigned pin_id)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
	unsigned long config;

	if (!pin_reg || !pin_reg->conf_reg) {
		seq_printf(s, "N/A");
		return;
	}

	config = readl(ipctl->base + pin_reg->conf_reg);
	seq_printf(s, "0x%lx", config);
}

static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
					 struct seq_file *s, unsigned group)
{
	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	const struct imx_pinctrl_soc_info *info = ipctl->info;
	struct imx_pin_group *grp;
	unsigned long config;
	const char *name;
	int i, ret;

	if (group > info->ngroups)
		return;

	seq_printf(s, "\n");
	grp = &info->groups[group];
	for (i = 0; i < grp->npins; i++) {
		name = pin_get_name(pctldev, grp->pins[i]);
		ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
		if (ret)
			return;
		seq_printf(s, "%s: 0x%lx", name, config);
	}
}

static const struct pinconf_ops imx_pinconf_ops = {
	.pin_config_get = imx_pinconf_get,
	.pin_config_set = imx_pinconf_set,
	.pin_config_dbg_show = imx_pinconf_dbg_show,
	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};

static struct pinctrl_desc imx_pinctrl_desc = {
	.pctlops = &imx_pctrl_ops,
	.pmxops = &imx_pmx_ops,
	.confops = &imx_pinconf_ops,
	.owner = THIS_MODULE,
};

/*
 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
 * 1 u32 CONFIG, so 24 types in total for each pin.
 */
#define FSL_PIN_SIZE 24
#define SHARE_FSL_PIN_SIZE 20

static int imx_pinctrl_parse_groups(struct device_node *np,
				    struct imx_pin_group *grp,
				    struct imx_pinctrl_soc_info *info,
				    u32 index)
{
	int size, pin_size;
	const __be32 *list;
	int i;
	u32 config;

	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);

	if (info->flags & SHARE_MUX_CONF_REG)
		pin_size = SHARE_FSL_PIN_SIZE;
	else
		pin_size = FSL_PIN_SIZE;
	/* Initialise group */
	grp->name = np->name;

	/*
	 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	 * do sanity check and calculate pins number
	 */
	list = of_get_property(np, "fsl,pins", &size);
	if (!list) {
		dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
		return -EINVAL;
	}

	/* we do not check return since it's safe node passed down */
	if (!size || size % pin_size) {
		dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
		return -EINVAL;
	}

	grp->npins = size / pin_size;
	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
				GFP_KERNEL);
	grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
				GFP_KERNEL);
	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
				GFP_KERNEL);
	for (i = 0; i < grp->npins; i++) {
		u32 mux_reg = be32_to_cpu(*list++);
		u32 conf_reg;
		unsigned int pin_id;
		struct imx_pin_reg *pin_reg;

		if (info->flags & SHARE_MUX_CONF_REG)
			conf_reg = mux_reg;
		else
			conf_reg = be32_to_cpu(*list++);

		pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
		pin_reg = &info->pin_regs[pin_id];
		grp->pins[i] = pin_id;
		pin_reg->mux_reg = mux_reg;
		pin_reg->conf_reg = conf_reg;
		grp->input_reg[i] = be32_to_cpu(*list++);
		grp->mux_mode[i] = be32_to_cpu(*list++);
		grp->input_val[i] = be32_to_cpu(*list++);

		/* SION bit is in mux register */
		config = be32_to_cpu(*list++);
		if (config & IMX_PAD_SION)
			grp->mux_mode[i] |= IOMUXC_CONFIG_SION;
		grp->configs[i] = config & ~IMX_PAD_SION;
	}

#ifdef DEBUG
	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
#endif

	return 0;
}

static int imx_pinctrl_parse_functions(struct device_node *np,
				       struct imx_pinctrl_soc_info *info,
				       u32 index)
{
	struct device_node *child;
	struct imx_pmx_func *func;
	struct imx_pin_group *grp;
	static u32 grp_index;
	u32 i = 0;

	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);

	func = &info->functions[index];

	/* Initialise function */
	func->name = np->name;
	func->num_groups = of_get_child_count(np);
	if (func->num_groups <= 0) {
		dev_err(info->dev, "no groups defined in %s\n", np->full_name);
		return -EINVAL;
	}
	func->groups = devm_kzalloc(info->dev,
			func->num_groups * sizeof(char *), GFP_KERNEL);

	for_each_child_of_node(np, child) {
		func->groups[i] = child->name;
		grp = &info->groups[grp_index++];
		imx_pinctrl_parse_groups(child, grp, info, i++);
	}

	return 0;
}

static int imx_pinctrl_probe_dt(struct platform_device *pdev,
				struct imx_pinctrl_soc_info *info)
{
	struct device_node *np = pdev->dev.of_node;
	struct device_node *child;
	u32 nfuncs = 0;
	u32 i = 0;

	if (!np)
		return -ENODEV;

	nfuncs = of_get_child_count(np);
	if (nfuncs <= 0) {
		dev_err(&pdev->dev, "no functions defined\n");
		return -EINVAL;
	}

	info->nfunctions = nfuncs;
	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
					GFP_KERNEL);
	if (!info->functions)
		return -ENOMEM;

	info->ngroups = 0;
	for_each_child_of_node(np, child)
		info->ngroups += of_get_child_count(child);
	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
					GFP_KERNEL);
	if (!info->groups)
		return -ENOMEM;

	for_each_child_of_node(np, child)
		imx_pinctrl_parse_functions(child, info, i++);

	return 0;
}

int imx_pinctrl_probe(struct platform_device *pdev,
		      struct imx_pinctrl_soc_info *info)
{
	struct imx_pinctrl *ipctl;
	struct resource *res;
	int ret;

	if (!info || !info->pins || !info->npins) {
		dev_err(&pdev->dev, "wrong pinctrl info\n");
		return -EINVAL;
	}
	info->dev = &pdev->dev;

	/* Create state holders etc for this driver */
	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	if (!ipctl)
		return -ENOMEM;

	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
				      info->npins, GFP_KERNEL);
	if (!info->pin_regs)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ipctl->base))
		return PTR_ERR(ipctl->base);

	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	imx_pinctrl_desc.pins = info->pins;
	imx_pinctrl_desc.npins = info->npins;

	ret = imx_pinctrl_probe_dt(pdev, info);
	if (ret) {
		dev_err(&pdev->dev, "fail to probe dt properties\n");
		return ret;
	}

	ipctl->info = info;
	ipctl->dev = info->dev;
	platform_set_drvdata(pdev, ipctl);
	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	if (!ipctl->pctl) {
		dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
		return -EINVAL;
	}

	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");

	return 0;
}

int imx_pinctrl_remove(struct platform_device *pdev)
{
	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);

	pinctrl_unregister(ipctl->pctl);

	return 0;
}
Commit	Line	Data
ae75ff81 DA	1	/*
	2	* Core driver for the imx pin controller
	3	*
	4	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	5	* Copyright (C) 2012 Linaro Ltd.
	6	*
	7	* Author: Dong Aisheng <dong.aisheng@linaro.org>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*/
	14
	15	#include <linux/err.h>
	16	#include <linux/init.h>
	17	#include <linux/io.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/pinctrl/machine.h>
	22	#include <linux/pinctrl/pinconf.h>
	23	#include <linux/pinctrl/pinctrl.h>
	24	#include <linux/pinctrl/pinmux.h>
	25	#include <linux/slab.h>
	26
	27	#include "core.h"
	28	#include "pinctrl-imx.h"
	29
3a86a5f8 DN	30	#define IMX_PMX_DUMP(info, p, m, c, n) \
	31	{ \
	32	int i, j; \
	33	printk(KERN_DEBUG "Format: Pin Mux Config\n"); \
	34	for (i = 0; i < n; i++) { \
	35	j = p[i]; \
	36	printk(KERN_DEBUG "%s %d 0x%lx\n", \
	37	info->pins[j].name, \
	38	m[i], c[i]); \
	39	} \
ae75ff81 DA	40	}
	41
	42	/* The bits in CONFIG cell defined in binding doc*/
	43	#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
	44	#define IMX_PAD_SION 0x40000000 /* set SION */
	45
	46	/**
	47	* @dev: a pointer back to containing device
	48	* @base: the offset to the controller in virtual memory
	49	*/
	50	struct imx_pinctrl {
	51	struct device *dev;
	52	struct pinctrl_dev *pctl;
	53	void __iomem *base;
	54	const struct imx_pinctrl_soc_info *info;
	55	};
	56
ae75ff81 DA	57	static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
	58	const struct imx_pinctrl_soc_info *info,
	59	const char *name)
	60	{
	61	const struct imx_pin_group *grp = NULL;
	62	int i;
	63
	64	for (i = 0; i < info->ngroups; i++) {
	65	if (!strcmp(info->groups[i].name, name)) {
	66	grp = &info->groups[i];
	67	break;
	68	}
	69	}
	70
	71	return grp;
	72	}
	73
	74	static int imx_get_groups_count(struct pinctrl_dev *pctldev)
	75	{
	76	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	77	const struct imx_pinctrl_soc_info *info = ipctl->info;
	78
	79	return info->ngroups;
	80	}
	81
	82	static const char imx_get_group_name(struct pinctrl_dev pctldev,
	83	unsigned selector)
	84	{
	85	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	86	const struct imx_pinctrl_soc_info *info = ipctl->info;
	87
	88	return info->groups[selector].name;
	89	}
	90
	91	static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
	92	const unsigned **pins,
	93	unsigned *npins)
	94	{
	95	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	96	const struct imx_pinctrl_soc_info *info = ipctl->info;
	97
	98	if (selector >= info->ngroups)
	99	return -EINVAL;
	100
	101	*pins = info->groups[selector].pins;
	102	*npins = info->groups[selector].npins;
	103
	104	return 0;
	105	}
	106
	107	static void imx_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	108	unsigned offset)
	109	{
	110	seq_printf(s, "%s", dev_name(pctldev->dev));
	111	}
	112
	113	static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
	114	struct device_node *np,
	115	struct pinctrl_map *map, unsigned num_maps)
	116	{
	117	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	118	const struct imx_pinctrl_soc_info *info = ipctl->info;
	119	const struct imx_pin_group *grp;
	120	struct pinctrl_map *new_map;
121	struct device_node *parent;
122	int map_num = 1;
18071610	123	int i, j;
ae75ff81 DA	124
	125	/*
	126	* first find the group of this node and check if we need create
	127	* config maps for pins
	128	*/
	129	grp = imx_pinctrl_find_group_by_name(info, np->name);
	130	if (!grp) {
	131	dev_err(info->dev, "unable to find group for node %s\n",
	132	np->name);
	133	return -EINVAL;
	134	}
	135
	136	for (i = 0; i < grp->npins; i++) {
	137	if (!(grp->configs[i] & IMX_NO_PAD_CTL))
	138	map_num++;
	139	}
	140
	141	new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
	142	if (!new_map)
	143	return -ENOMEM;
	144
	145	*map = new_map;
	146	*num_maps = map_num;
	147
	148	/* create mux map */
	149	parent = of_get_parent(np);
c71157c5 DN	150	if (!parent) {
c71157c5 DN	151	kfree(new_map);
ae75ff81	152	return -EINVAL;
c71157c5	153	}
ae75ff81 DA	154	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
	155	new_map[0].data.mux.function = parent->name;
	156	new_map[0].data.mux.group = np->name;
	157	of_node_put(parent);
	158
	159	/* create config map */
	160	new_map++;
18071610	161	for (i = j = 0; i < grp->npins; i++) {
ae75ff81	162	if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
18071610 HW	163	new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
18071610 HW	164	new_map[j].data.configs.group_or_pin =
ae75ff81	165	pin_get_name(pctldev, grp->pins[i]);
18071610 HW	166	new_map[j].data.configs.configs = &grp->configs[i];
	167	new_map[j].data.configs.num_configs = 1;
	168	j++;
ae75ff81 DA	169	}
	170	}
	171
	172	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
67695f2e	173	(map)->data.mux.function, (map)->data.mux.group, map_num);
ae75ff81 DA	174
	175	return 0;
	176	}
	177
	178	static void imx_dt_free_map(struct pinctrl_dev *pctldev,
	179	struct pinctrl_map *map, unsigned num_maps)
	180	{
3a86a5f8	181	kfree(map);
ae75ff81 DA	182	}
ae75ff81 DA	183
022ab148	184	static const struct pinctrl_ops imx_pctrl_ops = {
ae75ff81 DA	185	.get_groups_count = imx_get_groups_count,
	186	.get_group_name = imx_get_group_name,
	187	.get_group_pins = imx_get_group_pins,
	188	.pin_dbg_show = imx_pin_dbg_show,
	189	.dt_node_to_map = imx_dt_node_to_map,
	190	.dt_free_map = imx_dt_free_map,
	191
	192	};
	193
	194	static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
	195	unsigned group)
	196	{
	197	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	198	const struct imx_pinctrl_soc_info *info = ipctl->info;
	199	const struct imx_pin_reg *pin_reg;
e1641531 SG	200	const unsigned pins, mux, *input_val;
e1641531 SG	201	u16 *input_reg;
ae75ff81 DA	202	unsigned int npins, pin_id;
	203	int i;
	204
	205	/*
	206	* Configure the mux mode for each pin in the group for a specific
	207	* function.
	208	*/
	209	pins = info->groups[group].pins;
	210	npins = info->groups[group].npins;
	211	mux = info->groups[group].mux_mode;
e1641531 SG	212	input_val = info->groups[group].input_val;
e1641531 SG	213	input_reg = info->groups[group].input_reg;
ae75ff81	214
e1641531	215	WARN_ON(!pins \|\| !npins \|\| !mux \|\| !input_val \|\| !input_reg);
ae75ff81 DA	216
	217	dev_dbg(ipctl->dev, "enable function %s group %s\n",
	218	info->functions[selector].name, info->groups[group].name);
	219
	220	for (i = 0; i < npins; i++) {
	221	pin_id = pins[i];
e1641531	222	pin_reg = &info->pin_regs[pin_id];
ae75ff81	223
bf5a5309	224	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
ae75ff81 DA	225	dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
	226	info->pins[pin_id].name);
	227	return -EINVAL;
	228	}
	229
bf5a5309 JL	230	if (info->flags & SHARE_MUX_CONF_REG) {
	231	u32 reg;
	232	reg = readl(ipctl->base + pin_reg->mux_reg);
	233	reg &= ~(0x7 << 20);
	234	reg \|= (mux[i] << 20);
	235	writel(reg, ipctl->base + pin_reg->mux_reg);
	236	} else {
	237	writel(mux[i], ipctl->base + pin_reg->mux_reg);
	238	}
ae75ff81 DA	239	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
	240	pin_reg->mux_reg, mux[i]);
	241
94176faf SG	242	/*
	243	* If the select input value begins with 0xff, it's a quirky
	244	* select input and the value should be interpreted as below.
	245	* 31 23 15 7 0
	246	* \| 0xff \| shift \| width \| select \|
	247	* It's used to work around the problem that the select
	248	* input for some pin is not implemented in the select
	249	* input register but in some general purpose register.
	250	* We encode the select input value, width and shift of
	251	* the bit field into input_val cell of pin function ID
	252	* in device tree, and then decode them here for setting
	253	* up the select input bits in general purpose register.
	254	*/
	255	if (input_val[i] >> 24 == 0xff) {
	256	u32 val = input_val[i];
	257	u8 select = val & 0xff;
	258	u8 width = (val >> 8) & 0xff;
	259	u8 shift = (val >> 16) & 0xff;
	260	u32 mask = ((1 << width) - 1) << shift;
	261	/*
	262	* The input_reg[i] here is actually some IOMUXC general
	263	* purpose register, not regular select input register.
	264	*/
	265	val = readl(ipctl->base + input_reg[i]);
	266	val &= ~mask;
	267	val \|= select << shift;
	268	writel(val, ipctl->base + input_reg[i]);
	269	} else if (input_reg[i]) {
	270	/*
	271	* Regular select input register can never be at offset
	272	* 0, and we only print register value for regular case.
	273	*/
e1641531	274	writel(input_val[i], ipctl->base + input_reg[i]);
ae75ff81 DA	275	dev_dbg(ipctl->dev,
ae75ff81 DA	276	"==>select_input: offset 0x%x val 0x%x\n",
e1641531	277	input_reg[i], input_val[i]);
ae75ff81 DA	278	}
	279	}
	280
	281	return 0;
	282	}
	283
ae75ff81 DA	284	static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
	285	{
	286	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	287	const struct imx_pinctrl_soc_info *info = ipctl->info;
	288
	289	return info->nfunctions;
	290	}
	291
	292	static const char imx_pmx_get_func_name(struct pinctrl_dev pctldev,
	293	unsigned selector)
	294	{
	295	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	296	const struct imx_pinctrl_soc_info *info = ipctl->info;
	297
	298	return info->functions[selector].name;
	299	}
	300
	301	static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
	302	const char * const **groups,
	303	unsigned * const num_groups)
	304	{
	305	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	306	const struct imx_pinctrl_soc_info *info = ipctl->info;
	307
	308	*groups = info->functions[selector].groups;
	309	*num_groups = info->functions[selector].num_groups;
	310
	311	return 0;
	312	}
	313
022ab148	314	static const struct pinmux_ops imx_pmx_ops = {
ae75ff81 DA	315	.get_functions_count = imx_pmx_get_funcs_count,
	316	.get_function_name = imx_pmx_get_func_name,
	317	.get_function_groups = imx_pmx_get_groups,
	318	.enable = imx_pmx_enable,
ae75ff81 DA	319	};
	320
	321	static int imx_pinconf_get(struct pinctrl_dev *pctldev,
	322	unsigned pin_id, unsigned long *config)
	323	{
	324	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	325	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	326	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81	327
bf5a5309	328	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	329	dev_err(info->dev, "Pin(%s) does not support config function\n",
	330	info->pins[pin_id].name);
	331	return -EINVAL;
	332	}
	333
	334	*config = readl(ipctl->base + pin_reg->conf_reg);
	335
bf5a5309 JL	336	if (info->flags & SHARE_MUX_CONF_REG)
	337	*config &= 0xffff;
	338
ae75ff81 DA	339	return 0;
	340	}
	341
	342	static int imx_pinconf_set(struct pinctrl_dev *pctldev,
	343	unsigned pin_id, unsigned long config)
	344	{
	345	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	346	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	347	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81	348
bf5a5309	349	if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
ae75ff81 DA	350	dev_err(info->dev, "Pin(%s) does not support config function\n",
	351	info->pins[pin_id].name);
	352	return -EINVAL;
	353	}
	354
	355	dev_dbg(ipctl->dev, "pinconf set pin %s\n",
	356	info->pins[pin_id].name);
	357
bf5a5309 JL	358	if (info->flags & SHARE_MUX_CONF_REG) {
	359	u32 reg;
	360	reg = readl(ipctl->base + pin_reg->conf_reg);
	361	reg &= ~0xffff;
	362	reg \|= config;
	363	writel(reg, ipctl->base + pin_reg->conf_reg);
	364	} else {
	365	writel(config, ipctl->base + pin_reg->conf_reg);
	366	}
ae75ff81 DA	367	dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
	368	pin_reg->conf_reg, config);
	369
	370	return 0;
	371	}
	372
	373	static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
	374	struct seq_file *s, unsigned pin_id)
	375	{
	376	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	377	const struct imx_pinctrl_soc_info *info = ipctl->info;
e1641531	378	const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
ae75ff81 DA	379	unsigned long config;
ae75ff81 DA	380
ae75ff81 DA	381	if (!pin_reg \|\| !pin_reg->conf_reg) {
	382	seq_printf(s, "N/A");
	383	return;
	384	}
	385
	386	config = readl(ipctl->base + pin_reg->conf_reg);
	387	seq_printf(s, "0x%lx", config);
	388	}
	389
	390	static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
	391	struct seq_file *s, unsigned group)
	392	{
	393	struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
	394	const struct imx_pinctrl_soc_info *info = ipctl->info;
	395	struct imx_pin_group *grp;
	396	unsigned long config;
	397	const char *name;
	398	int i, ret;
	399
	400	if (group > info->ngroups)
	401	return;
	402
	403	seq_printf(s, "\n");
	404	grp = &info->groups[group];
	405	for (i = 0; i < grp->npins; i++) {
	406	name = pin_get_name(pctldev, grp->pins[i]);
	407	ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
	408	if (ret)
	409	return;
	410	seq_printf(s, "%s: 0x%lx", name, config);
	411	}
	412	}
	413
022ab148	414	static const struct pinconf_ops imx_pinconf_ops = {
ae75ff81 DA	415	.pin_config_get = imx_pinconf_get,
	416	.pin_config_set = imx_pinconf_set,
	417	.pin_config_dbg_show = imx_pinconf_dbg_show,
	418	.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
	419	};
	420
	421	static struct pinctrl_desc imx_pinctrl_desc = {
	422	.pctlops = &imx_pctrl_ops,
	423	.pmxops = &imx_pmx_ops,
	424	.confops = &imx_pinconf_ops,
	425	.owner = THIS_MODULE,
	426	};
	427
e1641531 SG	428	/*
	429	* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
	430	* 1 u32 CONFIG, so 24 types in total for each pin.
	431	*/
	432	#define FSL_PIN_SIZE 24
bf5a5309	433	#define SHARE_FSL_PIN_SIZE 20
ae75ff81	434
150632b0 GKH	435	static int imx_pinctrl_parse_groups(struct device_node *np,
	436	struct imx_pin_group *grp,
	437	struct imx_pinctrl_soc_info *info,
	438	u32 index)
ae75ff81	439	{
bf5a5309	440	int size, pin_size;
a695145b	441	const __be32 *list;
e1641531	442	int i;
ae75ff81 DA	443	u32 config;
	444
	445	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
	446
bf5a5309 JL	447	if (info->flags & SHARE_MUX_CONF_REG)
	448	pin_size = SHARE_FSL_PIN_SIZE;
	449	else
	450	pin_size = FSL_PIN_SIZE;
ae75ff81 DA	451	/* Initialise group */
	452	grp->name = np->name;
	453
	454	/*
	455	* the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
	456	* do sanity check and calculate pins number
	457	*/
	458	list = of_get_property(np, "fsl,pins", &size);
1bf1fea9 SH	459	if (!list) {
	460	dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
	461	return -EINVAL;
	462	}
	463
ae75ff81	464	/* we do not check return since it's safe node passed down */
bf5a5309	465	if (!size \|\| size % pin_size) {
01312513	466	dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
ae75ff81 DA	467	return -EINVAL;
	468	}
	469
bf5a5309	470	grp->npins = size / pin_size;
ae75ff81 DA	471	grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	472	GFP_KERNEL);
	473	grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	474	GFP_KERNEL);
e1641531 SG	475	grp->input_reg = devm_kzalloc(info->dev, grp->npins * sizeof(u16),
	476	GFP_KERNEL);
	477	grp->input_val = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
	478	GFP_KERNEL);
ae75ff81 DA	479	grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
ae75ff81 DA	480	GFP_KERNEL);
e1641531 SG	481	for (i = 0; i < grp->npins; i++) {
e1641531 SG	482	u32 mux_reg = be32_to_cpu(*list++);
bf5a5309 JL	483	u32 conf_reg;
	484	unsigned int pin_id;
	485	struct imx_pin_reg *pin_reg;
e1641531	486
bf5a5309 JL	487	if (info->flags & SHARE_MUX_CONF_REG)
	488	conf_reg = mux_reg;
	489	else
	490	conf_reg = be32_to_cpu(*list++);
	491
	492	pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
	493	pin_reg = &info->pin_regs[pin_id];
e1641531 SG	494	grp->pins[i] = pin_id;
	495	pin_reg->mux_reg = mux_reg;
	496	pin_reg->conf_reg = conf_reg;
	497	grp->input_reg[i] = be32_to_cpu(*list++);
	498	grp->mux_mode[i] = be32_to_cpu(*list++);
	499	grp->input_val[i] = be32_to_cpu(*list++);
	500
ae75ff81 DA	501	/* SION bit is in mux register */
	502	config = be32_to_cpu(*list++);
	503	if (config & IMX_PAD_SION)
e1641531 SG	504	grp->mux_mode[i] \|= IOMUXC_CONFIG_SION;
e1641531 SG	505	grp->configs[i] = config & ~IMX_PAD_SION;
ae75ff81 DA	506	}
ae75ff81 DA	507
a6e7360b	508	#ifdef DEBUG
ae75ff81	509	IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
a6e7360b	510	#endif
3a86a5f8	511
ae75ff81 DA	512	return 0;
	513	}
	514
150632b0 GKH	515	static int imx_pinctrl_parse_functions(struct device_node *np,
	516	struct imx_pinctrl_soc_info *info,
	517	u32 index)
ae75ff81 DA	518	{
	519	struct device_node *child;
	520	struct imx_pmx_func *func;
	521	struct imx_pin_group *grp;
ae75ff81 DA	522	static u32 grp_index;
	523	u32 i = 0;
	524
	525	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
	526
	527	func = &info->functions[index];
	528
	529	/* Initialise function */
	530	func->name = np->name;
	531	func->num_groups = of_get_child_count(np);
	532	if (func->num_groups <= 0) {
01312513	533	dev_err(info->dev, "no groups defined in %s\n", np->full_name);
ae75ff81 DA	534	return -EINVAL;
	535	}
	536	func->groups = devm_kzalloc(info->dev,
	537	func->num_groups * sizeof(char *), GFP_KERNEL);
	538
	539	for_each_child_of_node(np, child) {
	540	func->groups[i] = child->name;
	541	grp = &info->groups[grp_index++];
5e13762c	542	imx_pinctrl_parse_groups(child, grp, info, i++);
ae75ff81 DA	543	}
	544
	545	return 0;
	546	}
	547
150632b0	548	static int imx_pinctrl_probe_dt(struct platform_device *pdev,
ae75ff81 DA	549	struct imx_pinctrl_soc_info *info)
	550	{
	551	struct device_node *np = pdev->dev.of_node;
	552	struct device_node *child;
ae75ff81 DA	553	u32 nfuncs = 0;
	554	u32 i = 0;
	555
	556	if (!np)
	557	return -ENODEV;
	558
	559	nfuncs = of_get_child_count(np);
	560	if (nfuncs <= 0) {
	561	dev_err(&pdev->dev, "no functions defined\n");
	562	return -EINVAL;
	563	}
	564
	565	info->nfunctions = nfuncs;
	566	info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
	567	GFP_KERNEL);
	568	if (!info->functions)
	569	return -ENOMEM;
	570
	571	info->ngroups = 0;
	572	for_each_child_of_node(np, child)
	573	info->ngroups += of_get_child_count(child);
	574	info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
	575	GFP_KERNEL);
	576	if (!info->groups)
	577	return -ENOMEM;
	578
7ea46e0f SH	579	for_each_child_of_node(np, child)
7ea46e0f SH	580	imx_pinctrl_parse_functions(child, info, i++);
ae75ff81 DA	581
	582	return 0;
	583	}
	584
150632b0 GKH	585	int imx_pinctrl_probe(struct platform_device *pdev,
150632b0 GKH	586	struct imx_pinctrl_soc_info *info)
ae75ff81 DA	587	{
	588	struct imx_pinctrl *ipctl;
	589	struct resource *res;
	590	int ret;
	591
e1641531	592	if (!info \|\| !info->pins \|\| !info->npins) {
ae75ff81 DA	593	dev_err(&pdev->dev, "wrong pinctrl info\n");
	594	return -EINVAL;
	595	}
	596	info->dev = &pdev->dev;
	597
	598	/* Create state holders etc for this driver */
	599	ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
	600	if (!ipctl)
	601	return -ENOMEM;
	602
e1641531 SG	603	info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(info->pin_regs)
	604	info->npins, GFP_KERNEL);
	605	if (!info->pin_regs)
	606	return -ENOMEM;
	607
ae75ff81	608	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9e0c1fb2 TR	609	ipctl->base = devm_ioremap_resource(&pdev->dev, res);
	610	if (IS_ERR(ipctl->base))
	611	return PTR_ERR(ipctl->base);
ae75ff81 DA	612
	613	imx_pinctrl_desc.name = dev_name(&pdev->dev);
	614	imx_pinctrl_desc.pins = info->pins;
	615	imx_pinctrl_desc.npins = info->npins;
	616
	617	ret = imx_pinctrl_probe_dt(pdev, info);
	618	if (ret) {
	619	dev_err(&pdev->dev, "fail to probe dt properties\n");
	620	return ret;
	621	}
	622
	623	ipctl->info = info;
	624	ipctl->dev = info->dev;
	625	platform_set_drvdata(pdev, ipctl);
	626	ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
	627	if (!ipctl->pctl) {
	628	dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
	629	return -EINVAL;
	630	}
	631
	632	dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
	633
	634	return 0;
	635	}
	636
f90f54b3	637	int imx_pinctrl_remove(struct platform_device *pdev)
ae75ff81 DA	638	{
	639	struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
	640
	641	pinctrl_unregister(ipctl->pctl);
	642
	643	return 0;
	644	}