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ae75ff81 DA |
1 | /* |
2 | * IMX pinmux core definitions | |
3 | * | |
4 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
5 | * Copyright (C) 2012 Linaro Ltd. | |
6 | * | |
7 | * Author: Dong Aisheng <dong.aisheng@linaro.org> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #ifndef __DRIVERS_PINCTRL_IMX_H | |
16 | #define __DRIVERS_PINCTRL_IMX_H | |
17 | ||
18 | struct platform_device; | |
19 | ||
8f903f8a SH |
20 | /** |
21 | * struct imx_pin_group - describes a single i.MX pin | |
22 | * @pin: the pin_id of this pin | |
23 | * @mux_mode: the mux mode for this pin. | |
24 | * @input_reg: the select input register offset for this pin if any | |
25 | * 0 if no select input setting needed. | |
26 | * @input_val: the select input value for this pin. | |
27 | * @configs: the config for this pin. | |
28 | */ | |
29 | struct imx_pin { | |
30 | unsigned int pin; | |
31 | unsigned int mux_mode; | |
32 | u16 input_reg; | |
33 | unsigned int input_val; | |
34 | unsigned long config; | |
35 | }; | |
36 | ||
ae75ff81 DA |
37 | /** |
38 | * struct imx_pin_group - describes an IMX pin group | |
39 | * @name: the name of this specific pin group | |
ae75ff81 DA |
40 | * @npins: the number of pins in this group array, i.e. the number of |
41 | * elements in .pins so we can iterate over that array | |
8f903f8a SH |
42 | * @pin_ids: array of pin_ids. pinctrl forces us to maintain such an array |
43 | * @pins: array of pins | |
ae75ff81 DA |
44 | */ |
45 | struct imx_pin_group { | |
46 | const char *name; | |
ae75ff81 | 47 | unsigned npins; |
8f903f8a SH |
48 | unsigned int *pin_ids; |
49 | struct imx_pin *pins; | |
ae75ff81 DA |
50 | }; |
51 | ||
52 | /** | |
53 | * struct imx_pmx_func - describes IMX pinmux functions | |
54 | * @name: the name of this specific function | |
55 | * @groups: corresponding pin groups | |
56 | * @num_groups: the number of groups | |
57 | */ | |
58 | struct imx_pmx_func { | |
59 | const char *name; | |
60 | const char **groups; | |
61 | unsigned num_groups; | |
62 | }; | |
63 | ||
64 | /** | |
65 | * struct imx_pin_reg - describe a pin reg map | |
ae75ff81 DA |
66 | * @mux_reg: mux register offset |
67 | * @conf_reg: config register offset | |
ae75ff81 DA |
68 | */ |
69 | struct imx_pin_reg { | |
ae75ff81 DA |
70 | u16 mux_reg; |
71 | u16 conf_reg; | |
ae75ff81 DA |
72 | }; |
73 | ||
74 | struct imx_pinctrl_soc_info { | |
75 | struct device *dev; | |
76 | const struct pinctrl_pin_desc *pins; | |
77 | unsigned int npins; | |
e1641531 | 78 | struct imx_pin_reg *pin_regs; |
ae75ff81 DA |
79 | struct imx_pin_group *groups; |
80 | unsigned int ngroups; | |
81 | struct imx_pmx_func *functions; | |
82 | unsigned int nfunctions; | |
bf5a5309 | 83 | unsigned int flags; |
ae75ff81 DA |
84 | }; |
85 | ||
bf5a5309 JL |
86 | #define ZERO_OFFSET_VALID 0x1 |
87 | #define SHARE_MUX_CONF_REG 0x2 | |
88 | ||
ae75ff81 DA |
89 | #define NO_MUX 0x0 |
90 | #define NO_PAD 0x0 | |
91 | ||
ae75ff81 DA |
92 | #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) |
93 | ||
94 | #define PAD_CTL_MASK(len) ((1 << len) - 1) | |
95 | #define IMX_MUX_MASK 0x7 | |
96 | #define IOMUXC_CONFIG_SION (0x1 << 4) | |
97 | ||
98 | int imx_pinctrl_probe(struct platform_device *pdev, | |
99 | struct imx_pinctrl_soc_info *info); | |
100 | int imx_pinctrl_remove(struct platform_device *pdev); | |
101 | #endif /* __DRIVERS_PINCTRL_IMX_H */ |