Commit | Line | Data |
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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
f4b3f523 | 7 | * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> |
2ec1d359 AR |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
3e3c62ca | 17 | #include <linux/platform_device.h> |
2ec1d359 | 18 | #include <linux/io.h> |
af7dc228 RV |
19 | #include <linux/clk.h> |
20 | #include <linux/err.h> | |
2ec1d359 AR |
21 | #include <linux/gpio.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
855f80cd | 25 | #include <linux/of_device.h> |
32e67eee | 26 | #include <linux/of_address.h> |
e32af889 | 27 | #include <linux/pinctrl/machine.h> |
e98ea774 | 28 | #include <linux/pinctrl/pinctrl.h> |
dbfe8ca2 | 29 | #include <linux/pinctrl/pinmux.h> |
d41af627 | 30 | #include <linux/pinctrl/pinconf.h> |
dbfe8ca2 LW |
31 | /* Since we request GPIOs from ourself */ |
32 | #include <linux/pinctrl/consumer.h> | |
e98ea774 | 33 | #include "pinctrl-nomadik.h" |
8d99b32d | 34 | #include "core.h" |
e98ea774 | 35 | |
2ec1d359 AR |
36 | /* |
37 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
38 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 39 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
40 | * |
41 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
42 | */ | |
43 | ||
8d993397 LW |
44 | /* |
45 | * pin configurations are represented by 32-bit integers: | |
46 | * | |
47 | * bit 0.. 8 - Pin Number (512 Pins Maximum) | |
48 | * bit 9..10 - Alternate Function Selection | |
49 | * bit 11..12 - Pull up/down state | |
50 | * bit 13 - Sleep mode behaviour | |
51 | * bit 14 - Direction | |
52 | * bit 15 - Value (if output) | |
53 | * bit 16..18 - SLPM pull up/down state | |
54 | * bit 19..20 - SLPM direction | |
55 | * bit 21..22 - SLPM Value (if output) | |
56 | * bit 23..25 - PDIS value (if input) | |
57 | * bit 26 - Gpio mode | |
58 | * bit 27 - Sleep mode | |
59 | * | |
60 | * to facilitate the definition, the following macros are provided | |
61 | * | |
62 | * PIN_CFG_DEFAULT - default config (0): | |
63 | * pull up/down = disabled | |
64 | * sleep mode = input/wakeup | |
65 | * direction = input | |
66 | * value = low | |
67 | * SLPM direction = same as normal | |
68 | * SLPM pull = same as normal | |
69 | * SLPM value = same as normal | |
70 | * | |
71 | * PIN_CFG - default config with alternate function | |
72 | */ | |
73 | ||
74 | typedef unsigned long pin_cfg_t; | |
75 | ||
76 | #define PIN_NUM_MASK 0x1ff | |
77 | #define PIN_NUM(x) ((x) & PIN_NUM_MASK) | |
78 | ||
79 | #define PIN_ALT_SHIFT 9 | |
80 | #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) | |
81 | #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) | |
82 | #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT) | |
83 | #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT) | |
84 | #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT) | |
85 | #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT) | |
86 | ||
87 | #define PIN_PULL_SHIFT 11 | |
88 | #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) | |
89 | #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) | |
90 | #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT) | |
91 | #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT) | |
92 | #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT) | |
93 | ||
94 | #define PIN_SLPM_SHIFT 13 | |
95 | #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) | |
96 | #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) | |
97 | #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) | |
98 | #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) | |
99 | /* These two replace the above in DB8500v2+ */ | |
100 | #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) | |
101 | #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) | |
102 | #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE | |
103 | ||
104 | #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */ | |
105 | #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */ | |
106 | ||
107 | #define PIN_DIR_SHIFT 14 | |
108 | #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) | |
109 | #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) | |
110 | #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) | |
111 | #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) | |
112 | ||
113 | #define PIN_VAL_SHIFT 15 | |
114 | #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) | |
115 | #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) | |
116 | #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) | |
117 | #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) | |
118 | ||
119 | #define PIN_SLPM_PULL_SHIFT 16 | |
120 | #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) | |
121 | #define PIN_SLPM_PULL(x) \ | |
122 | (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) | |
123 | #define PIN_SLPM_PULL_NONE \ | |
124 | ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) | |
125 | #define PIN_SLPM_PULL_UP \ | |
126 | ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) | |
127 | #define PIN_SLPM_PULL_DOWN \ | |
128 | ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) | |
129 | ||
130 | #define PIN_SLPM_DIR_SHIFT 19 | |
131 | #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) | |
132 | #define PIN_SLPM_DIR(x) \ | |
133 | (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) | |
134 | #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) | |
135 | #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) | |
136 | ||
137 | #define PIN_SLPM_VAL_SHIFT 21 | |
138 | #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) | |
139 | #define PIN_SLPM_VAL(x) \ | |
140 | (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) | |
141 | #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) | |
142 | #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) | |
143 | ||
144 | #define PIN_SLPM_PDIS_SHIFT 23 | |
145 | #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT) | |
146 | #define PIN_SLPM_PDIS(x) \ | |
147 | (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT) | |
148 | #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT) | |
149 | #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT) | |
150 | #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT) | |
151 | ||
152 | #define PIN_LOWEMI_SHIFT 25 | |
153 | #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT) | |
154 | #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT) | |
155 | #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT) | |
156 | #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT) | |
157 | ||
158 | #define PIN_GPIOMODE_SHIFT 26 | |
159 | #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT) | |
160 | #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT) | |
161 | #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT) | |
162 | #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT) | |
163 | ||
164 | #define PIN_SLEEPMODE_SHIFT 27 | |
165 | #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT) | |
166 | #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT) | |
167 | #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT) | |
168 | #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT) | |
169 | ||
170 | ||
171 | /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ | |
172 | #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) | |
173 | #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) | |
174 | #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) | |
175 | #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) | |
176 | #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) | |
177 | ||
178 | #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) | |
179 | #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) | |
180 | #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) | |
181 | #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) | |
182 | #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) | |
183 | ||
184 | #define PIN_CFG_DEFAULT (0) | |
185 | ||
186 | #define PIN_CFG(num, alt) \ | |
187 | (PIN_CFG_DEFAULT |\ | |
188 | (PIN_NUM(num) | PIN_##alt)) | |
189 | ||
190 | #define PIN_CFG_INPUT(num, alt, pull) \ | |
191 | (PIN_CFG_DEFAULT |\ | |
192 | (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) | |
193 | ||
194 | #define PIN_CFG_OUTPUT(num, alt, val) \ | |
195 | (PIN_CFG_DEFAULT |\ | |
196 | (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) | |
197 | ||
198 | /* | |
199 | * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving | |
200 | * the "gpio" namespace for generic and cross-machine functions | |
201 | */ | |
202 | ||
203 | #define GPIO_BLOCK_SHIFT 5 | |
204 | #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) | |
205 | ||
206 | /* Register in the logic block */ | |
207 | #define NMK_GPIO_DAT 0x00 | |
208 | #define NMK_GPIO_DATS 0x04 | |
209 | #define NMK_GPIO_DATC 0x08 | |
210 | #define NMK_GPIO_PDIS 0x0c | |
211 | #define NMK_GPIO_DIR 0x10 | |
212 | #define NMK_GPIO_DIRS 0x14 | |
213 | #define NMK_GPIO_DIRC 0x18 | |
214 | #define NMK_GPIO_SLPC 0x1c | |
215 | #define NMK_GPIO_AFSLA 0x20 | |
216 | #define NMK_GPIO_AFSLB 0x24 | |
217 | #define NMK_GPIO_LOWEMI 0x28 | |
218 | ||
219 | #define NMK_GPIO_RIMSC 0x40 | |
220 | #define NMK_GPIO_FIMSC 0x44 | |
221 | #define NMK_GPIO_IS 0x48 | |
222 | #define NMK_GPIO_IC 0x4c | |
223 | #define NMK_GPIO_RWIMSC 0x50 | |
224 | #define NMK_GPIO_FWIMSC 0x54 | |
225 | #define NMK_GPIO_WKS 0x58 | |
226 | /* These appear in DB8540 and later ASICs */ | |
227 | #define NMK_GPIO_EDGELEVEL 0x5C | |
228 | #define NMK_GPIO_LEVEL 0x60 | |
229 | ||
230 | ||
231 | /* Pull up/down values */ | |
232 | enum nmk_gpio_pull { | |
233 | NMK_GPIO_PULL_NONE, | |
234 | NMK_GPIO_PULL_UP, | |
235 | NMK_GPIO_PULL_DOWN, | |
236 | }; | |
237 | ||
238 | /* Sleep mode */ | |
239 | enum nmk_gpio_slpm { | |
240 | NMK_GPIO_SLPM_INPUT, | |
241 | NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT, | |
242 | NMK_GPIO_SLPM_NOCHANGE, | |
243 | NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE, | |
244 | }; | |
245 | ||
2ec1d359 AR |
246 | struct nmk_gpio_chip { |
247 | struct gpio_chip chip; | |
248 | void __iomem *addr; | |
af7dc228 | 249 | struct clk *clk; |
33b744b3 | 250 | unsigned int bank; |
2ec1d359 | 251 | unsigned int parent_irq; |
194e15ba LW |
252 | int latent_parent_irq; |
253 | u32 (*get_latent_status)(unsigned int bank); | |
01727e61 | 254 | void (*set_ioforce)(bool enable); |
c0fcb8db | 255 | spinlock_t lock; |
33d78647 | 256 | bool sleepmode; |
2ec1d359 AR |
257 | /* Keep track of configured edges */ |
258 | u32 edge_rising; | |
259 | u32 edge_falling; | |
b9df468d RV |
260 | u32 real_wake; |
261 | u32 rwimsc; | |
262 | u32 fwimsc; | |
6c12fe88 RV |
263 | u32 rimsc; |
264 | u32 fimsc; | |
bc6f5cf6 | 265 | u32 pull_up; |
ebc6178d | 266 | u32 lowemi; |
2ec1d359 AR |
267 | }; |
268 | ||
f1671bf5 JA |
269 | /** |
270 | * struct nmk_pinctrl - state container for the Nomadik pin controller | |
271 | * @dev: containing device pointer | |
272 | * @pctl: corresponding pin controller device | |
273 | * @soc: SoC data for this specific chip | |
274 | * @prcm_base: PRCM register range virtual base | |
275 | */ | |
e98ea774 LW |
276 | struct nmk_pinctrl { |
277 | struct device *dev; | |
278 | struct pinctrl_dev *pctl; | |
279 | const struct nmk_pinctrl_soc_data *soc; | |
f1671bf5 | 280 | void __iomem *prcm_base; |
e98ea774 LW |
281 | }; |
282 | ||
01727e61 RV |
283 | static struct nmk_gpio_chip * |
284 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
285 | ||
286 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
287 | ||
288 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
289 | ||
6f9a974c RV |
290 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
291 | unsigned offset, int gpio_mode) | |
292 | { | |
293 | u32 bit = 1 << offset; | |
294 | u32 afunc, bfunc; | |
295 | ||
296 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
297 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
298 | if (gpio_mode & NMK_GPIO_ALT_A) | |
299 | afunc |= bit; | |
300 | if (gpio_mode & NMK_GPIO_ALT_B) | |
301 | bfunc |= bit; | |
302 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
303 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
304 | } | |
305 | ||
81a3c298 RV |
306 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
307 | unsigned offset, enum nmk_gpio_slpm mode) | |
308 | { | |
309 | u32 bit = 1 << offset; | |
310 | u32 slpm; | |
311 | ||
312 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
313 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
314 | slpm |= bit; | |
315 | else | |
316 | slpm &= ~bit; | |
317 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
318 | } | |
319 | ||
5b327edf RV |
320 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
321 | unsigned offset, enum nmk_gpio_pull pull) | |
322 | { | |
323 | u32 bit = 1 << offset; | |
324 | u32 pdis; | |
325 | ||
326 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
bc6f5cf6 | 327 | if (pull == NMK_GPIO_PULL_NONE) { |
5b327edf | 328 | pdis |= bit; |
bc6f5cf6 RA |
329 | nmk_chip->pull_up &= ~bit; |
330 | } else { | |
5b327edf | 331 | pdis &= ~bit; |
bc6f5cf6 RA |
332 | } |
333 | ||
5b327edf RV |
334 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); |
335 | ||
bc6f5cf6 RA |
336 | if (pull == NMK_GPIO_PULL_UP) { |
337 | nmk_chip->pull_up |= bit; | |
5b327edf | 338 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
bc6f5cf6 RA |
339 | } else if (pull == NMK_GPIO_PULL_DOWN) { |
340 | nmk_chip->pull_up &= ~bit; | |
5b327edf | 341 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
bc6f5cf6 | 342 | } |
5b327edf RV |
343 | } |
344 | ||
ebc6178d RV |
345 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, |
346 | unsigned offset, bool lowemi) | |
347 | { | |
348 | u32 bit = BIT(offset); | |
349 | bool enabled = nmk_chip->lowemi & bit; | |
350 | ||
351 | if (lowemi == enabled) | |
352 | return; | |
353 | ||
354 | if (lowemi) | |
355 | nmk_chip->lowemi |= bit; | |
356 | else | |
357 | nmk_chip->lowemi &= ~bit; | |
358 | ||
359 | writel_relaxed(nmk_chip->lowemi, | |
360 | nmk_chip->addr + NMK_GPIO_LOWEMI); | |
361 | } | |
362 | ||
378be066 RV |
363 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
364 | unsigned offset) | |
365 | { | |
366 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
367 | } | |
368 | ||
6720db7c RV |
369 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
370 | unsigned offset, int val) | |
371 | { | |
372 | if (val) | |
373 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
374 | else | |
375 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
376 | } | |
377 | ||
378 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
379 | unsigned offset, int val) | |
380 | { | |
381 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
382 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
383 | } | |
384 | ||
01727e61 RV |
385 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
386 | unsigned offset, int gpio_mode, | |
387 | bool glitch) | |
388 | { | |
6c12fe88 RV |
389 | u32 rwimsc = nmk_chip->rwimsc; |
390 | u32 fwimsc = nmk_chip->fwimsc; | |
01727e61 RV |
391 | |
392 | if (glitch && nmk_chip->set_ioforce) { | |
393 | u32 bit = BIT(offset); | |
394 | ||
01727e61 RV |
395 | /* Prevent spurious wakeups */ |
396 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
397 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
398 | ||
399 | nmk_chip->set_ioforce(true); | |
400 | } | |
401 | ||
402 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
403 | ||
404 | if (glitch && nmk_chip->set_ioforce) { | |
405 | nmk_chip->set_ioforce(false); | |
406 | ||
407 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
408 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
409 | } | |
410 | } | |
411 | ||
6c42ad1c RV |
412 | static void |
413 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | |
414 | { | |
415 | u32 falling = nmk_chip->fimsc & BIT(offset); | |
416 | u32 rising = nmk_chip->rimsc & BIT(offset); | |
417 | int gpio = nmk_chip->chip.base + offset; | |
e0bc34a3 | 418 | int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); |
6c42ad1c RV |
419 | struct irq_data *d = irq_get_irq_data(irq); |
420 | ||
421 | if (!rising && !falling) | |
422 | return; | |
423 | ||
424 | if (!d || !irqd_irq_disabled(d)) | |
425 | return; | |
426 | ||
427 | if (rising) { | |
428 | nmk_chip->rimsc &= ~BIT(offset); | |
429 | writel_relaxed(nmk_chip->rimsc, | |
430 | nmk_chip->addr + NMK_GPIO_RIMSC); | |
431 | } | |
432 | ||
433 | if (falling) { | |
434 | nmk_chip->fimsc &= ~BIT(offset); | |
435 | writel_relaxed(nmk_chip->fimsc, | |
436 | nmk_chip->addr + NMK_GPIO_FIMSC); | |
437 | } | |
438 | ||
439 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | |
440 | } | |
441 | ||
f1671bf5 JA |
442 | static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value) |
443 | { | |
444 | u32 val; | |
445 | ||
446 | val = readl(reg); | |
447 | val = ((val & ~mask) | (value & mask)); | |
448 | writel(val, reg); | |
449 | } | |
450 | ||
c22df08c JNG |
451 | static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct, |
452 | unsigned offset, unsigned alt_num) | |
453 | { | |
454 | int i; | |
455 | u16 reg; | |
456 | u8 bit; | |
457 | u8 alt_index; | |
458 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
459 | const u16 *gpiocr_regs; | |
460 | ||
4ca075de FB |
461 | if (!npct->prcm_base) |
462 | return; | |
463 | ||
c22df08c JNG |
464 | if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) { |
465 | dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n", | |
466 | alt_num); | |
467 | return; | |
468 | } | |
469 | ||
470 | for (i = 0 ; i < npct->soc->npins_altcx ; i++) { | |
471 | if (npct->soc->altcx_pins[i].pin == offset) | |
472 | break; | |
473 | } | |
474 | if (i == npct->soc->npins_altcx) { | |
475 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n", | |
476 | offset); | |
477 | return; | |
478 | } | |
479 | ||
480 | pin_desc = npct->soc->altcx_pins + i; | |
481 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
482 | ||
483 | /* | |
484 | * If alt_num is NULL, just clear current ALTCx selection | |
485 | * to make sure we come back to a pure ALTC selection | |
486 | */ | |
487 | if (!alt_num) { | |
488 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
489 | if (pin_desc->altcx[i].used == true) { | |
490 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
491 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
492 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
493 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
494 | dev_dbg(npct->dev, |
495 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
496 | offset, i+1); | |
497 | } | |
498 | } | |
499 | } | |
500 | return; | |
501 | } | |
502 | ||
503 | alt_index = alt_num - 1; | |
504 | if (pin_desc->altcx[alt_index].used == false) { | |
505 | dev_warn(npct->dev, | |
506 | "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n", | |
507 | offset, alt_num); | |
508 | return; | |
509 | } | |
510 | ||
511 | /* | |
512 | * Check if any other ALTCx functions are activated on this pin | |
513 | * and disable it first. | |
514 | */ | |
515 | for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) { | |
516 | if (i == alt_index) | |
517 | continue; | |
518 | if (pin_desc->altcx[i].used == true) { | |
519 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
520 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 JA |
521 | if (readl(npct->prcm_base + reg) & BIT(bit)) { |
522 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0); | |
c22df08c JNG |
523 | dev_dbg(npct->dev, |
524 | "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n", | |
525 | offset, i+1); | |
526 | } | |
527 | } | |
528 | } | |
529 | ||
530 | reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index]; | |
531 | bit = pin_desc->altcx[alt_index].control_bit; | |
532 | dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n", | |
533 | offset, alt_index+1); | |
f1671bf5 | 534 | nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit)); |
c22df08c JNG |
535 | } |
536 | ||
01727e61 RV |
537 | /* |
538 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
539 | * - Save SLPM registers | |
540 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
541 | * - Configure the GPIO registers for the IOs that are being switched | |
542 | * - Set IOFORCE=1 | |
543 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
544 | * - Set IOFORCE=0 | |
545 | * - Restore SLPM registers | |
546 | * - Any spurious wake up event during switch sequence to be ignored and | |
547 | * cleared | |
548 | */ | |
549 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
550 | { | |
551 | int i; | |
552 | ||
553 | for (i = 0; i < NUM_BANKS; i++) { | |
554 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
555 | unsigned int temp = slpm[i]; | |
556 | ||
557 | if (!chip) | |
558 | break; | |
559 | ||
3c0227d2 RV |
560 | clk_enable(chip->clk); |
561 | ||
01727e61 RV |
562 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); |
563 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
564 | } | |
565 | } | |
566 | ||
567 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
568 | { | |
569 | int i; | |
570 | ||
571 | for (i = 0; i < NUM_BANKS; i++) { | |
572 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
573 | ||
574 | if (!chip) | |
575 | break; | |
576 | ||
577 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
3c0227d2 RV |
578 | |
579 | clk_disable(chip->clk); | |
01727e61 RV |
580 | } |
581 | } | |
582 | ||
0fafd50e | 583 | static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio) |
2249b19f JNG |
584 | { |
585 | int i; | |
586 | u16 reg; | |
587 | u8 bit; | |
588 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
589 | const struct prcm_gpiocr_altcx_pin_desc *pin_desc; | |
590 | const u16 *gpiocr_regs; | |
591 | ||
4ca075de FB |
592 | if (!npct->prcm_base) |
593 | return NMK_GPIO_ALT_C; | |
594 | ||
2249b19f JNG |
595 | for (i = 0; i < npct->soc->npins_altcx; i++) { |
596 | if (npct->soc->altcx_pins[i].pin == gpio) | |
597 | break; | |
598 | } | |
599 | if (i == npct->soc->npins_altcx) | |
600 | return NMK_GPIO_ALT_C; | |
601 | ||
602 | pin_desc = npct->soc->altcx_pins + i; | |
603 | gpiocr_regs = npct->soc->prcm_gpiocr_registers; | |
604 | for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) { | |
605 | if (pin_desc->altcx[i].used == true) { | |
606 | reg = gpiocr_regs[pin_desc->altcx[i].reg_index]; | |
607 | bit = pin_desc->altcx[i].control_bit; | |
f1671bf5 | 608 | if (readl(npct->prcm_base + reg) & BIT(bit)) |
2249b19f JNG |
609 | return NMK_GPIO_ALT_C+i+1; |
610 | } | |
611 | } | |
612 | return NMK_GPIO_ALT_C; | |
613 | } | |
614 | ||
2ec1d359 AR |
615 | int nmk_gpio_get_mode(int gpio) |
616 | { | |
617 | struct nmk_gpio_chip *nmk_chip; | |
618 | u32 afunc, bfunc, bit; | |
619 | ||
a60b57ed | 620 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
2ec1d359 AR |
621 | if (!nmk_chip) |
622 | return -EINVAL; | |
623 | ||
a60b57ed | 624 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 | 625 | |
3c0227d2 RV |
626 | clk_enable(nmk_chip->clk); |
627 | ||
2ec1d359 AR |
628 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; |
629 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
630 | ||
3c0227d2 RV |
631 | clk_disable(nmk_chip->clk); |
632 | ||
2ec1d359 AR |
633 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); |
634 | } | |
635 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
636 | ||
637 | ||
638 | /* IRQ functions */ | |
639 | static inline int nmk_gpio_get_bitmask(int gpio) | |
640 | { | |
a60b57ed | 641 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
2ec1d359 AR |
642 | } |
643 | ||
f272c00e | 644 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 | 645 | { |
e0bc34a3 LW |
646 | struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
647 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
3c0227d2 RV |
648 | |
649 | clk_enable(nmk_chip->clk); | |
a60b57ed | 650 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
3c0227d2 | 651 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
652 | } |
653 | ||
4d4e20f7 RV |
654 | enum nmk_gpio_irq_type { |
655 | NORMAL, | |
656 | WAKE, | |
657 | }; | |
658 | ||
040e5ecd | 659 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
660 | int gpio, enum nmk_gpio_irq_type which, |
661 | bool enable) | |
2ec1d359 | 662 | { |
040e5ecd | 663 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
6c12fe88 RV |
664 | u32 *rimscval; |
665 | u32 *fimscval; | |
666 | u32 rimscreg; | |
667 | u32 fimscreg; | |
668 | ||
669 | if (which == NORMAL) { | |
670 | rimscreg = NMK_GPIO_RIMSC; | |
671 | fimscreg = NMK_GPIO_FIMSC; | |
672 | rimscval = &nmk_chip->rimsc; | |
673 | fimscval = &nmk_chip->fimsc; | |
674 | } else { | |
675 | rimscreg = NMK_GPIO_RWIMSC; | |
676 | fimscreg = NMK_GPIO_FWIMSC; | |
677 | rimscval = &nmk_chip->rwimsc; | |
678 | fimscval = &nmk_chip->fwimsc; | |
679 | } | |
2ec1d359 | 680 | |
040e5ecd | 681 | /* we must individually set/clear the two edges */ |
2ec1d359 | 682 | if (nmk_chip->edge_rising & bitmask) { |
040e5ecd | 683 | if (enable) |
6c12fe88 | 684 | *rimscval |= bitmask; |
040e5ecd | 685 | else |
6c12fe88 RV |
686 | *rimscval &= ~bitmask; |
687 | writel(*rimscval, nmk_chip->addr + rimscreg); | |
2ec1d359 AR |
688 | } |
689 | if (nmk_chip->edge_falling & bitmask) { | |
040e5ecd | 690 | if (enable) |
6c12fe88 | 691 | *fimscval |= bitmask; |
040e5ecd | 692 | else |
6c12fe88 RV |
693 | *fimscval &= ~bitmask; |
694 | writel(*fimscval, nmk_chip->addr + fimscreg); | |
2ec1d359 | 695 | } |
040e5ecd | 696 | } |
2ec1d359 | 697 | |
b9df468d RV |
698 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
699 | int gpio, bool on) | |
700 | { | |
b982ff0e RV |
701 | /* |
702 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is | |
703 | * disabled, since setting SLPM to 1 increases power consumption, and | |
704 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. | |
705 | */ | |
706 | if (nmk_chip->sleepmode && on) { | |
e85bbc19 | 707 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, |
b982ff0e | 708 | NMK_GPIO_SLPM_WAKEUP_ENABLE); |
33d78647 LW |
709 | } |
710 | ||
b9df468d RV |
711 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
712 | } | |
713 | ||
714 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 | 715 | { |
2ec1d359 AR |
716 | struct nmk_gpio_chip *nmk_chip; |
717 | unsigned long flags; | |
040e5ecd | 718 | u32 bitmask; |
2ec1d359 | 719 | |
f272c00e | 720 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 721 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 | 722 | if (!nmk_chip) |
4d4e20f7 | 723 | return -EINVAL; |
2ec1d359 | 724 | |
3c0227d2 | 725 | clk_enable(nmk_chip->clk); |
b9df468d RV |
726 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
727 | spin_lock(&nmk_chip->lock); | |
728 | ||
a60b57ed | 729 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
b9df468d RV |
730 | |
731 | if (!(nmk_chip->real_wake & bitmask)) | |
a60b57ed | 732 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
b9df468d RV |
733 | |
734 | spin_unlock(&nmk_chip->lock); | |
735 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 736 | clk_disable(nmk_chip->clk); |
4d4e20f7 RV |
737 | |
738 | return 0; | |
2ec1d359 AR |
739 | } |
740 | ||
f272c00e | 741 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 742 | { |
b9df468d | 743 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 744 | } |
040e5ecd | 745 | |
f272c00e | 746 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 747 | { |
b9df468d | 748 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
749 | } |
750 | ||
f272c00e | 751 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 752 | { |
7e3f7e59 RV |
753 | struct nmk_gpio_chip *nmk_chip; |
754 | unsigned long flags; | |
b9df468d | 755 | u32 bitmask; |
7e3f7e59 | 756 | |
f272c00e | 757 | nmk_chip = irq_data_get_irq_chip_data(d); |
7e3f7e59 RV |
758 | if (!nmk_chip) |
759 | return -EINVAL; | |
a60b57ed | 760 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
7e3f7e59 | 761 | |
3c0227d2 | 762 | clk_enable(nmk_chip->clk); |
01727e61 RV |
763 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
764 | spin_lock(&nmk_chip->lock); | |
765 | ||
479a0c7e | 766 | if (irqd_irq_disabled(d)) |
a60b57ed | 767 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
b9df468d RV |
768 | |
769 | if (on) | |
770 | nmk_chip->real_wake |= bitmask; | |
771 | else | |
772 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
773 | |
774 | spin_unlock(&nmk_chip->lock); | |
775 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
3c0227d2 | 776 | clk_disable(nmk_chip->clk); |
7e3f7e59 RV |
777 | |
778 | return 0; | |
040e5ecd RV |
779 | } |
780 | ||
f272c00e | 781 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 782 | { |
479a0c7e | 783 | bool enabled = !irqd_irq_disabled(d); |
3c0227d2 | 784 | bool wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
785 | struct nmk_gpio_chip *nmk_chip; |
786 | unsigned long flags; | |
787 | u32 bitmask; | |
788 | ||
f272c00e | 789 | nmk_chip = irq_data_get_irq_chip_data(d); |
a60b57ed | 790 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
2ec1d359 AR |
791 | if (!nmk_chip) |
792 | return -EINVAL; | |
2ec1d359 AR |
793 | if (type & IRQ_TYPE_LEVEL_HIGH) |
794 | return -EINVAL; | |
795 | if (type & IRQ_TYPE_LEVEL_LOW) | |
796 | return -EINVAL; | |
797 | ||
3c0227d2 | 798 | clk_enable(nmk_chip->clk); |
2ec1d359 AR |
799 | spin_lock_irqsave(&nmk_chip->lock, flags); |
800 | ||
7a852d80 | 801 | if (enabled) |
a60b57ed | 802 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
4d4e20f7 | 803 | |
b9df468d | 804 | if (enabled || wake) |
a60b57ed | 805 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
7a852d80 | 806 | |
2ec1d359 AR |
807 | nmk_chip->edge_rising &= ~bitmask; |
808 | if (type & IRQ_TYPE_EDGE_RISING) | |
809 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
810 | |
811 | nmk_chip->edge_falling &= ~bitmask; | |
812 | if (type & IRQ_TYPE_EDGE_FALLING) | |
813 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 814 | |
7a852d80 | 815 | if (enabled) |
a60b57ed | 816 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
4d4e20f7 | 817 | |
b9df468d | 818 | if (enabled || wake) |
a60b57ed | 819 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
2ec1d359 | 820 | |
7a852d80 | 821 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
3c0227d2 | 822 | clk_disable(nmk_chip->clk); |
2ec1d359 AR |
823 | |
824 | return 0; | |
825 | } | |
826 | ||
3c0227d2 RV |
827 | static unsigned int nmk_gpio_irq_startup(struct irq_data *d) |
828 | { | |
829 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 | 830 | |
3c0227d2 RV |
831 | clk_enable(nmk_chip->clk); |
832 | nmk_gpio_irq_unmask(d); | |
2ec1d359 AR |
833 | return 0; |
834 | } | |
835 | ||
3c0227d2 RV |
836 | static void nmk_gpio_irq_shutdown(struct irq_data *d) |
837 | { | |
838 | struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); | |
839 | ||
840 | nmk_gpio_irq_mask(d); | |
841 | clk_disable(nmk_chip->clk); | |
842 | } | |
843 | ||
2ec1d359 AR |
844 | static struct irq_chip nmk_gpio_irq_chip = { |
845 | .name = "Nomadik-GPIO", | |
f272c00e LB |
846 | .irq_ack = nmk_gpio_irq_ack, |
847 | .irq_mask = nmk_gpio_irq_mask, | |
848 | .irq_unmask = nmk_gpio_irq_unmask, | |
849 | .irq_set_type = nmk_gpio_irq_set_type, | |
850 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
3c0227d2 RV |
851 | .irq_startup = nmk_gpio_irq_startup, |
852 | .irq_shutdown = nmk_gpio_irq_shutdown, | |
4921e745 | 853 | .flags = IRQCHIP_MASK_ON_SUSPEND, |
2ec1d359 AR |
854 | }; |
855 | ||
33b744b3 RV |
856 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
857 | u32 status) | |
2ec1d359 | 858 | { |
6845664a | 859 | struct irq_chip *host_chip = irq_get_chip(irq); |
e0bc34a3 | 860 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
2ec1d359 | 861 | |
adfed159 | 862 | chained_irq_enter(host_chip, desc); |
aaedaa2b | 863 | |
33b744b3 RV |
864 | while (status) { |
865 | int bit = __ffs(status); | |
866 | ||
e0bc34a3 | 867 | generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); |
33b744b3 | 868 | status &= ~BIT(bit); |
2ec1d359 | 869 | } |
aaedaa2b | 870 | |
adfed159 | 871 | chained_irq_exit(host_chip, desc); |
2ec1d359 AR |
872 | } |
873 | ||
33b744b3 RV |
874 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
875 | { | |
e0bc34a3 LW |
876 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
877 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
3c0227d2 RV |
878 | u32 status; |
879 | ||
e0bc34a3 | 880 | pr_err("PLONK IRQ %d\n", irq); |
3c0227d2 RV |
881 | clk_enable(nmk_chip->clk); |
882 | status = readl(nmk_chip->addr + NMK_GPIO_IS); | |
883 | clk_disable(nmk_chip->clk); | |
33b744b3 RV |
884 | |
885 | __nmk_gpio_irq_handler(irq, desc, status); | |
886 | } | |
887 | ||
194e15ba | 888 | static void nmk_gpio_latent_irq_handler(unsigned int irq, |
33b744b3 RV |
889 | struct irq_desc *desc) |
890 | { | |
e0bc34a3 LW |
891 | struct gpio_chip *chip = irq_desc_get_handler_data(desc); |
892 | struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
194e15ba | 893 | u32 status = nmk_chip->get_latent_status(nmk_chip->bank); |
33b744b3 RV |
894 | |
895 | __nmk_gpio_irq_handler(irq, desc, status); | |
896 | } | |
897 | ||
2ec1d359 | 898 | /* I/O Functions */ |
dbfe8ca2 LW |
899 | |
900 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | |
901 | { | |
902 | /* | |
903 | * Map back to global GPIO space and request muxing, the direction | |
904 | * parameter does not matter for this controller. | |
905 | */ | |
906 | int gpio = chip->base + offset; | |
907 | ||
908 | return pinctrl_request_gpio(gpio); | |
909 | } | |
910 | ||
911 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | |
912 | { | |
913 | int gpio = chip->base + offset; | |
914 | ||
915 | pinctrl_free_gpio(gpio); | |
916 | } | |
917 | ||
2ec1d359 AR |
918 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
919 | { | |
920 | struct nmk_gpio_chip *nmk_chip = | |
921 | container_of(chip, struct nmk_gpio_chip, chip); | |
922 | ||
3c0227d2 RV |
923 | clk_enable(nmk_chip->clk); |
924 | ||
2ec1d359 | 925 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); |
3c0227d2 RV |
926 | |
927 | clk_disable(nmk_chip->clk); | |
928 | ||
2ec1d359 AR |
929 | return 0; |
930 | } | |
931 | ||
2ec1d359 AR |
932 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
933 | { | |
934 | struct nmk_gpio_chip *nmk_chip = | |
935 | container_of(chip, struct nmk_gpio_chip, chip); | |
936 | u32 bit = 1 << offset; | |
3c0227d2 RV |
937 | int value; |
938 | ||
939 | clk_enable(nmk_chip->clk); | |
2ec1d359 | 940 | |
3c0227d2 | 941 | value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; |
2ec1d359 | 942 | |
3c0227d2 RV |
943 | clk_disable(nmk_chip->clk); |
944 | ||
945 | return value; | |
2ec1d359 AR |
946 | } |
947 | ||
948 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
949 | int val) | |
950 | { | |
951 | struct nmk_gpio_chip *nmk_chip = | |
952 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 953 | |
3c0227d2 RV |
954 | clk_enable(nmk_chip->clk); |
955 | ||
6720db7c | 956 | __nmk_gpio_set_output(nmk_chip, offset, val); |
3c0227d2 RV |
957 | |
958 | clk_disable(nmk_chip->clk); | |
2ec1d359 AR |
959 | } |
960 | ||
6647c6c0 RV |
961 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
962 | int val) | |
963 | { | |
964 | struct nmk_gpio_chip *nmk_chip = | |
965 | container_of(chip, struct nmk_gpio_chip, chip); | |
966 | ||
3c0227d2 RV |
967 | clk_enable(nmk_chip->clk); |
968 | ||
6720db7c | 969 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 | 970 | |
3c0227d2 RV |
971 | clk_disable(nmk_chip->clk); |
972 | ||
6647c6c0 RV |
973 | return 0; |
974 | } | |
975 | ||
d0b543c7 RV |
976 | #ifdef CONFIG_DEBUG_FS |
977 | ||
978 | #include <linux/seq_file.h> | |
979 | ||
2249b19f JNG |
980 | static void nmk_gpio_dbg_show_one(struct seq_file *s, |
981 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
982 | unsigned offset, unsigned gpio) | |
d0b543c7 | 983 | { |
6f4350a6 | 984 | const char *label = gpiochip_is_requested(chip, offset); |
d0b543c7 RV |
985 | struct nmk_gpio_chip *nmk_chip = |
986 | container_of(chip, struct nmk_gpio_chip, chip); | |
6f4350a6 LW |
987 | int mode; |
988 | bool is_out; | |
989 | bool pull; | |
990 | u32 bit = 1 << offset; | |
d0b543c7 RV |
991 | const char *modes[] = { |
992 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
993 | [NMK_GPIO_ALT_A] = "altA", | |
994 | [NMK_GPIO_ALT_B] = "altB", | |
995 | [NMK_GPIO_ALT_C] = "altC", | |
2249b19f JNG |
996 | [NMK_GPIO_ALT_C+1] = "altC1", |
997 | [NMK_GPIO_ALT_C+2] = "altC2", | |
998 | [NMK_GPIO_ALT_C+3] = "altC3", | |
999 | [NMK_GPIO_ALT_C+4] = "altC4", | |
d0b543c7 RV |
1000 | }; |
1001 | ||
3c0227d2 | 1002 | clk_enable(nmk_chip->clk); |
6f4350a6 LW |
1003 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); |
1004 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
1005 | mode = nmk_gpio_get_mode(gpio); | |
2249b19f JNG |
1006 | if ((mode == NMK_GPIO_ALT_C) && pctldev) |
1007 | mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); | |
6f4350a6 LW |
1008 | |
1009 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
1010 | gpio, label ?: "(none)", | |
1011 | is_out ? "out" : "in ", | |
1012 | chip->get | |
1013 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
1014 | : "? ", | |
1015 | (mode < 0) ? "unknown" : modes[mode], | |
1016 | pull ? "pull" : "none"); | |
1017 | ||
4705845b LW |
1018 | if (!is_out) { |
1019 | int irq = gpio_to_irq(gpio); | |
6f4350a6 LW |
1020 | struct irq_desc *desc = irq_to_desc(irq); |
1021 | ||
1022 | /* This races with request_irq(), set_irq_type(), | |
1023 | * and set_irq_wake() ... but those are "rare". | |
1024 | */ | |
4705845b | 1025 | if (irq > 0 && desc && desc->action) { |
6f4350a6 LW |
1026 | char *trigger; |
1027 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | |
1028 | ||
1029 | if (nmk_chip->edge_rising & bitmask) | |
1030 | trigger = "edge-rising"; | |
1031 | else if (nmk_chip->edge_falling & bitmask) | |
1032 | trigger = "edge-falling"; | |
1033 | else | |
1034 | trigger = "edge-undefined"; | |
1035 | ||
1036 | seq_printf(s, " irq-%d %s%s", | |
1037 | irq, trigger, | |
1038 | irqd_is_wakeup_set(&desc->irq_data) | |
1039 | ? " wakeup" : ""); | |
8ea72a30 | 1040 | } |
6f4350a6 LW |
1041 | } |
1042 | clk_disable(nmk_chip->clk); | |
1043 | } | |
1044 | ||
1045 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
1046 | { | |
1047 | unsigned i; | |
1048 | unsigned gpio = chip->base; | |
8ea72a30 | 1049 | |
6f4350a6 | 1050 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
2249b19f | 1051 | nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
d0b543c7 RV |
1052 | seq_printf(s, "\n"); |
1053 | } | |
1054 | } | |
1055 | ||
1056 | #else | |
6f4350a6 | 1057 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, |
2249b19f | 1058 | struct pinctrl_dev *pctldev, |
6f4350a6 LW |
1059 | struct gpio_chip *chip, |
1060 | unsigned offset, unsigned gpio) | |
1061 | { | |
1062 | } | |
d0b543c7 RV |
1063 | #define nmk_gpio_dbg_show NULL |
1064 | #endif | |
1065 | ||
2ec1d359 AR |
1066 | /* This structure is replicated for each GPIO block allocated at probe time */ |
1067 | static struct gpio_chip nmk_gpio_template = { | |
dbfe8ca2 LW |
1068 | .request = nmk_gpio_request, |
1069 | .free = nmk_gpio_free, | |
2ec1d359 AR |
1070 | .direction_input = nmk_gpio_make_input, |
1071 | .get = nmk_gpio_get_input, | |
1072 | .direction_output = nmk_gpio_make_output, | |
1073 | .set = nmk_gpio_set_output, | |
d0b543c7 | 1074 | .dbg_show = nmk_gpio_dbg_show, |
9fb1f39e | 1075 | .can_sleep = false, |
2ec1d359 AR |
1076 | }; |
1077 | ||
3c0227d2 RV |
1078 | void nmk_gpio_clocks_enable(void) |
1079 | { | |
1080 | int i; | |
1081 | ||
1082 | for (i = 0; i < NUM_BANKS; i++) { | |
1083 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1084 | ||
1085 | if (!chip) | |
1086 | continue; | |
1087 | ||
1088 | clk_enable(chip->clk); | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | void nmk_gpio_clocks_disable(void) | |
1093 | { | |
1094 | int i; | |
1095 | ||
1096 | for (i = 0; i < NUM_BANKS; i++) { | |
1097 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1098 | ||
1099 | if (!chip) | |
1100 | continue; | |
1101 | ||
1102 | clk_disable(chip->clk); | |
1103 | } | |
1104 | } | |
1105 | ||
b9df468d RV |
1106 | /* |
1107 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
1108 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
1109 | * and not the rest of the interrupts which we needed to have as wakeups for | |
1110 | * cpuidle. | |
1111 | * | |
1112 | * PM ops are not used since this needs to be done at the end, after all the | |
1113 | * other drivers are done with their suspend callbacks. | |
1114 | */ | |
1115 | void nmk_gpio_wakeups_suspend(void) | |
1116 | { | |
1117 | int i; | |
1118 | ||
1119 | for (i = 0; i < NUM_BANKS; i++) { | |
1120 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1121 | ||
1122 | if (!chip) | |
1123 | break; | |
1124 | ||
3c0227d2 RV |
1125 | clk_enable(chip->clk); |
1126 | ||
b9df468d RV |
1127 | writel(chip->rwimsc & chip->real_wake, |
1128 | chip->addr + NMK_GPIO_RWIMSC); | |
1129 | writel(chip->fwimsc & chip->real_wake, | |
1130 | chip->addr + NMK_GPIO_FWIMSC); | |
1131 | ||
3c0227d2 | 1132 | clk_disable(chip->clk); |
b9df468d RV |
1133 | } |
1134 | } | |
1135 | ||
1136 | void nmk_gpio_wakeups_resume(void) | |
1137 | { | |
1138 | int i; | |
1139 | ||
1140 | for (i = 0; i < NUM_BANKS; i++) { | |
1141 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
1142 | ||
1143 | if (!chip) | |
1144 | break; | |
1145 | ||
3c0227d2 RV |
1146 | clk_enable(chip->clk); |
1147 | ||
b9df468d RV |
1148 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1149 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
1150 | ||
3c0227d2 | 1151 | clk_disable(chip->clk); |
b9df468d RV |
1152 | } |
1153 | } | |
1154 | ||
bc6f5cf6 RA |
1155 | /* |
1156 | * Read the pull up/pull down status. | |
1157 | * A bit set in 'pull_up' means that pull up | |
1158 | * is selected if pull is enabled in PDIS register. | |
1159 | * Note: only pull up/down set via this driver can | |
1160 | * be detected due to HW limitations. | |
1161 | */ | |
1162 | void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |
1163 | { | |
1164 | if (gpio_bank < NUM_BANKS) { | |
1165 | struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; | |
1166 | ||
1167 | if (!chip) | |
1168 | return; | |
1169 | ||
1170 | *pull_up = chip->pull_up; | |
1171 | } | |
1172 | } | |
1173 | ||
150632b0 | 1174 | static int nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 1175 | { |
513c27f8 | 1176 | struct device_node *np = dev->dev.of_node; |
2ec1d359 AR |
1177 | struct nmk_gpio_chip *nmk_chip; |
1178 | struct gpio_chip *chip; | |
3e3c62ca | 1179 | struct resource *res; |
af7dc228 | 1180 | struct clk *clk; |
194e15ba | 1181 | int latent_irq; |
8f18bcfc | 1182 | bool supports_sleepmode; |
8d91771c | 1183 | void __iomem *base; |
3e3c62ca | 1184 | int irq; |
2ec1d359 AR |
1185 | int ret; |
1186 | ||
f4b3f523 | 1187 | if (of_get_property(np, "st,supports-sleepmode", NULL)) |
8f18bcfc LW |
1188 | supports_sleepmode = true; |
1189 | else | |
1190 | supports_sleepmode = false; | |
513c27f8 | 1191 | |
f4b3f523 LW |
1192 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { |
1193 | dev_err(&dev->dev, "gpio-bank property not found\n"); | |
1194 | return -EINVAL; | |
513c27f8 | 1195 | } |
3e3c62ca | 1196 | |
3e3c62ca | 1197 | irq = platform_get_irq(dev, 0); |
50f690d8 LW |
1198 | if (irq < 0) |
1199 | return irq; | |
3e3c62ca | 1200 | |
8f18bcfc | 1201 | /* It's OK for this IRQ not to be present */ |
194e15ba | 1202 | latent_irq = platform_get_irq(dev, 1); |
33b744b3 | 1203 | |
690ebabb | 1204 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
9e0c1fb2 | 1205 | base = devm_ioremap_resource(&dev->dev, res); |
06991c28 LT |
1206 | if (IS_ERR(base)) |
1207 | return PTR_ERR(base); | |
8d91771c | 1208 | |
5e754f33 | 1209 | clk = devm_clk_get(&dev->dev, NULL); |
50f690d8 LW |
1210 | if (IS_ERR(clk)) |
1211 | return PTR_ERR(clk); | |
efec381c | 1212 | clk_prepare(clk); |
af7dc228 | 1213 | |
5e754f33 | 1214 | nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); |
50f690d8 LW |
1215 | if (!nmk_chip) |
1216 | return -ENOMEM; | |
513c27f8 | 1217 | |
2ec1d359 AR |
1218 | /* |
1219 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
1220 | * so we can simply convert the resource address, without remapping | |
1221 | */ | |
33b744b3 | 1222 | nmk_chip->bank = dev->id; |
af7dc228 | 1223 | nmk_chip->clk = clk; |
8d91771c | 1224 | nmk_chip->addr = base; |
2ec1d359 | 1225 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 1226 | nmk_chip->parent_irq = irq; |
194e15ba | 1227 | nmk_chip->latent_parent_irq = latent_irq; |
8f18bcfc | 1228 | nmk_chip->sleepmode = supports_sleepmode; |
c0fcb8db | 1229 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
1230 | |
1231 | chip = &nmk_chip->chip; | |
8f18bcfc LW |
1232 | chip->base = dev->id * NMK_GPIO_PER_CHIP; |
1233 | chip->ngpio = NMK_GPIO_PER_CHIP; | |
1234 | chip->label = dev_name(&dev->dev); | |
2ec1d359 AR |
1235 | chip->dev = &dev->dev; |
1236 | chip->owner = THIS_MODULE; | |
1237 | ||
ebc6178d RV |
1238 | clk_enable(nmk_chip->clk); |
1239 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | |
1240 | clk_disable(nmk_chip->clk); | |
513c27f8 LJ |
1241 | chip->of_node = np; |
1242 | ||
2ec1d359 AR |
1243 | ret = gpiochip_add(&nmk_chip->chip); |
1244 | if (ret) | |
50f690d8 | 1245 | return ret; |
2ec1d359 | 1246 | |
01727e61 RV |
1247 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1248 | ||
1249 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
513c27f8 | 1250 | |
3e3c62ca | 1251 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 | 1252 | |
e0bc34a3 LW |
1253 | /* |
1254 | * Let the generic code handle this edge IRQ, the the chained | |
1255 | * handler will perform the actual work of handling the parent | |
1256 | * interrupt. | |
1257 | */ | |
1258 | ret = gpiochip_irqchip_add(&nmk_chip->chip, | |
1259 | &nmk_gpio_irq_chip, | |
1260 | 0, | |
1261 | handle_edge_irq, | |
1262 | IRQ_TYPE_EDGE_FALLING); | |
1263 | if (ret) { | |
1264 | dev_err(&dev->dev, "could not add irqchip\n"); | |
50f690d8 | 1265 | ret = gpiochip_remove(&nmk_chip->chip); |
e0bc34a3 | 1266 | return -ENODEV; |
a60b57ed | 1267 | } |
e0bc34a3 LW |
1268 | /* Then register the chain on the parent IRQ */ |
1269 | gpiochip_set_chained_irqchip(&nmk_chip->chip, | |
1270 | &nmk_gpio_irq_chip, | |
1271 | nmk_chip->parent_irq, | |
1272 | nmk_gpio_irq_handler); | |
1273 | if (nmk_chip->latent_parent_irq > 0) | |
1274 | gpiochip_set_chained_irqchip(&nmk_chip->chip, | |
1275 | &nmk_gpio_irq_chip, | |
1276 | nmk_chip->latent_parent_irq, | |
1277 | nmk_gpio_latent_irq_handler); | |
2ec1d359 | 1278 | |
513c27f8 LJ |
1279 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1280 | ||
2ec1d359 | 1281 | return 0; |
2ec1d359 AR |
1282 | } |
1283 | ||
e98ea774 LW |
1284 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) |
1285 | { | |
1286 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1287 | ||
1288 | return npct->soc->ngroups; | |
1289 | } | |
1290 | ||
1291 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | |
1292 | unsigned selector) | |
1293 | { | |
1294 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1295 | ||
1296 | return npct->soc->groups[selector].name; | |
1297 | } | |
1298 | ||
1299 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
1300 | const unsigned **pins, | |
1301 | unsigned *num_pins) | |
1302 | { | |
1303 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1304 | ||
1305 | *pins = npct->soc->groups[selector].pins; | |
1306 | *num_pins = npct->soc->groups[selector].npins; | |
1307 | return 0; | |
1308 | } | |
1309 | ||
24cbdd75 LW |
1310 | static struct pinctrl_gpio_range * |
1311 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | |
1312 | { | |
1313 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1314 | int i; | |
1315 | ||
1316 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1317 | struct pinctrl_gpio_range *range; | |
1318 | ||
1319 | range = &npct->soc->gpio_ranges[i]; | |
1320 | if (offset >= range->pin_base && | |
1321 | offset <= (range->pin_base + range->npins - 1)) | |
1322 | return range; | |
1323 | } | |
1324 | return NULL; | |
1325 | } | |
1326 | ||
e98ea774 LW |
1327 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
1328 | unsigned offset) | |
1329 | { | |
24cbdd75 LW |
1330 | struct pinctrl_gpio_range *range; |
1331 | struct gpio_chip *chip; | |
1332 | ||
1333 | range = nmk_match_gpio_range(pctldev, offset); | |
1334 | if (!range || !range->gc) { | |
1335 | seq_printf(s, "invalid pin offset"); | |
1336 | return; | |
1337 | } | |
1338 | chip = range->gc; | |
2249b19f | 1339 | nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); |
e98ea774 LW |
1340 | } |
1341 | ||
e32af889 GF |
1342 | static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, |
1343 | struct pinctrl_map *map, unsigned num_maps) | |
1344 | { | |
1345 | int i; | |
1346 | ||
1347 | for (i = 0; i < num_maps; i++) | |
1348 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
1349 | kfree(map[i].data.configs.configs); | |
1350 | kfree(map); | |
1351 | } | |
1352 | ||
1353 | static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | |
1354 | unsigned *num_maps, unsigned reserve) | |
1355 | { | |
1356 | unsigned old_num = *reserved_maps; | |
1357 | unsigned new_num = *num_maps + reserve; | |
1358 | struct pinctrl_map *new_map; | |
1359 | ||
1360 | if (old_num >= new_num) | |
1361 | return 0; | |
1362 | ||
1363 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
1364 | if (!new_map) | |
1365 | return -ENOMEM; | |
1366 | ||
1367 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
1368 | ||
1369 | *map = new_map; | |
1370 | *reserved_maps = new_num; | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |
1376 | unsigned *num_maps, const char *group, | |
1377 | const char *function) | |
1378 | { | |
1379 | if (*num_maps == *reserved_maps) | |
1380 | return -ENOSPC; | |
1381 | ||
1382 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
1383 | (*map)[*num_maps].data.mux.group = group; | |
1384 | (*map)[*num_maps].data.mux.function = function; | |
1385 | (*num_maps)++; | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static int nmk_dt_add_map_configs(struct pinctrl_map **map, | |
1391 | unsigned *reserved_maps, | |
1392 | unsigned *num_maps, const char *group, | |
1393 | unsigned long *configs, unsigned num_configs) | |
1394 | { | |
1395 | unsigned long *dup_configs; | |
1396 | ||
1397 | if (*num_maps == *reserved_maps) | |
1398 | return -ENOSPC; | |
1399 | ||
1400 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
1401 | GFP_KERNEL); | |
1402 | if (!dup_configs) | |
1403 | return -ENOMEM; | |
1404 | ||
1405 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
1406 | ||
1407 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
1408 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
1409 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
1410 | (*num_maps)++; | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
87ff934a SK |
1415 | #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, } |
1416 | #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \ | |
e32af889 GF |
1417 | .size = ARRAY_SIZE(y), } |
1418 | ||
1419 | static const unsigned long nmk_pin_input_modes[] = { | |
1420 | PIN_INPUT_NOPULL, | |
1421 | PIN_INPUT_PULLUP, | |
1422 | PIN_INPUT_PULLDOWN, | |
1423 | }; | |
1424 | ||
1425 | static const unsigned long nmk_pin_output_modes[] = { | |
1426 | PIN_OUTPUT_LOW, | |
1427 | PIN_OUTPUT_HIGH, | |
1428 | PIN_DIR_OUTPUT, | |
1429 | }; | |
1430 | ||
1431 | static const unsigned long nmk_pin_sleep_modes[] = { | |
1432 | PIN_SLEEPMODE_DISABLED, | |
1433 | PIN_SLEEPMODE_ENABLED, | |
1434 | }; | |
1435 | ||
1436 | static const unsigned long nmk_pin_sleep_input_modes[] = { | |
1437 | PIN_SLPM_INPUT_NOPULL, | |
1438 | PIN_SLPM_INPUT_PULLUP, | |
1439 | PIN_SLPM_INPUT_PULLDOWN, | |
1440 | PIN_SLPM_DIR_INPUT, | |
1441 | }; | |
1442 | ||
1443 | static const unsigned long nmk_pin_sleep_output_modes[] = { | |
1444 | PIN_SLPM_OUTPUT_LOW, | |
1445 | PIN_SLPM_OUTPUT_HIGH, | |
1446 | PIN_SLPM_DIR_OUTPUT, | |
1447 | }; | |
1448 | ||
1449 | static const unsigned long nmk_pin_sleep_wakeup_modes[] = { | |
1450 | PIN_SLPM_WAKEUP_DISABLE, | |
1451 | PIN_SLPM_WAKEUP_ENABLE, | |
1452 | }; | |
1453 | ||
1454 | static const unsigned long nmk_pin_gpio_modes[] = { | |
1455 | PIN_GPIOMODE_DISABLED, | |
1456 | PIN_GPIOMODE_ENABLED, | |
1457 | }; | |
1458 | ||
1459 | static const unsigned long nmk_pin_sleep_pdis_modes[] = { | |
1460 | PIN_SLPM_PDIS_DISABLED, | |
1461 | PIN_SLPM_PDIS_ENABLED, | |
1462 | }; | |
1463 | ||
1464 | struct nmk_cfg_param { | |
1465 | const char *property; | |
1466 | unsigned long config; | |
1467 | const unsigned long *choice; | |
1468 | int size; | |
1469 | }; | |
1470 | ||
1471 | static const struct nmk_cfg_param nmk_cfg_params[] = { | |
1472 | NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes), | |
1473 | NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes), | |
1474 | NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes), | |
1475 | NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes), | |
1476 | NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes), | |
1477 | NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes), | |
1478 | NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes), | |
1479 | NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes), | |
1480 | }; | |
1481 | ||
1482 | static int nmk_dt_pin_config(int index, int val, unsigned long *config) | |
1483 | { | |
1484 | int ret = 0; | |
1485 | ||
1486 | if (nmk_cfg_params[index].choice == NULL) | |
1487 | *config = nmk_cfg_params[index].config; | |
1488 | else { | |
1489 | /* test if out of range */ | |
1490 | if (val < nmk_cfg_params[index].size) { | |
1491 | *config = nmk_cfg_params[index].config | | |
1492 | nmk_cfg_params[index].choice[val]; | |
1493 | } | |
1494 | } | |
1495 | return ret; | |
1496 | } | |
1497 | ||
1498 | static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) | |
1499 | { | |
1500 | int i, pin_number; | |
1501 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1502 | ||
1503 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
1504 | for (i = 0; i < npct->soc->npins; i++) | |
1505 | if (npct->soc->pins[i].number == pin_number) | |
1506 | return npct->soc->pins[i].name; | |
1507 | return NULL; | |
1508 | } | |
1509 | ||
1510 | static bool nmk_pinctrl_dt_get_config(struct device_node *np, | |
1511 | unsigned long *configs) | |
1512 | { | |
1513 | bool has_config = 0; | |
1514 | unsigned long cfg = 0; | |
1515 | int i, val, ret; | |
1516 | ||
1517 | for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) { | |
1518 | ret = of_property_read_u32(np, | |
1519 | nmk_cfg_params[i].property, &val); | |
1520 | if (ret != -EINVAL) { | |
1521 | if (nmk_dt_pin_config(i, val, &cfg) == 0) { | |
1522 | *configs |= cfg; | |
1523 | has_config = 1; | |
1524 | } | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | return has_config; | |
1529 | } | |
1530 | ||
2230a36e | 1531 | static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1532 | struct device_node *np, |
1533 | struct pinctrl_map **map, | |
1534 | unsigned *reserved_maps, | |
1535 | unsigned *num_maps) | |
1536 | { | |
1537 | int ret; | |
1538 | const char *function = NULL; | |
1539 | unsigned long configs = 0; | |
1540 | bool has_config = 0; | |
1541 | unsigned reserve = 0; | |
1542 | struct property *prop; | |
1543 | const char *group, *gpio_name; | |
1544 | struct device_node *np_config; | |
1545 | ||
1546 | ret = of_property_read_string(np, "ste,function", &function); | |
1547 | if (ret >= 0) | |
1548 | reserve = 1; | |
1549 | ||
1550 | has_config = nmk_pinctrl_dt_get_config(np, &configs); | |
1551 | ||
1552 | np_config = of_parse_phandle(np, "ste,config", 0); | |
1553 | if (np_config) | |
1554 | has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); | |
1555 | ||
1556 | ret = of_property_count_strings(np, "ste,pins"); | |
1557 | if (ret < 0) | |
1558 | goto exit; | |
1559 | ||
1560 | if (has_config) | |
1561 | reserve++; | |
1562 | ||
1563 | reserve *= ret; | |
1564 | ||
1565 | ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve); | |
1566 | if (ret < 0) | |
1567 | goto exit; | |
1568 | ||
1569 | of_property_for_each_string(np, "ste,pins", prop, group) { | |
1570 | if (function) { | |
1571 | ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, | |
1572 | group, function); | |
1573 | if (ret < 0) | |
1574 | goto exit; | |
1575 | } | |
1576 | if (has_config) { | |
1577 | gpio_name = nmk_find_pin_name(pctldev, group); | |
1578 | ||
1579 | ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, | |
1580 | gpio_name, &configs, 1); | |
1581 | if (ret < 0) | |
1582 | goto exit; | |
1583 | } | |
1584 | ||
1585 | } | |
1586 | exit: | |
1587 | return ret; | |
1588 | } | |
1589 | ||
2230a36e | 1590 | static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, |
e32af889 GF |
1591 | struct device_node *np_config, |
1592 | struct pinctrl_map **map, unsigned *num_maps) | |
1593 | { | |
1594 | unsigned reserved_maps; | |
1595 | struct device_node *np; | |
1596 | int ret; | |
1597 | ||
1598 | reserved_maps = 0; | |
1599 | *map = NULL; | |
1600 | *num_maps = 0; | |
1601 | ||
1602 | for_each_child_of_node(np_config, np) { | |
1603 | ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, | |
1604 | &reserved_maps, num_maps); | |
1605 | if (ret < 0) { | |
1606 | nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); | |
1607 | return ret; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | return 0; | |
1612 | } | |
1613 | ||
022ab148 | 1614 | static const struct pinctrl_ops nmk_pinctrl_ops = { |
e98ea774 LW |
1615 | .get_groups_count = nmk_get_groups_cnt, |
1616 | .get_group_name = nmk_get_group_name, | |
1617 | .get_group_pins = nmk_get_group_pins, | |
1618 | .pin_dbg_show = nmk_pin_dbg_show, | |
e32af889 GF |
1619 | .dt_node_to_map = nmk_pinctrl_dt_node_to_map, |
1620 | .dt_free_map = nmk_pinctrl_dt_free_map, | |
e98ea774 LW |
1621 | }; |
1622 | ||
dbfe8ca2 LW |
1623 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
1624 | { | |
1625 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1626 | ||
1627 | return npct->soc->nfunctions; | |
1628 | } | |
1629 | ||
1630 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
1631 | unsigned function) | |
1632 | { | |
1633 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1634 | ||
1635 | return npct->soc->functions[function].name; | |
1636 | } | |
1637 | ||
1638 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
1639 | unsigned function, | |
1640 | const char * const **groups, | |
1641 | unsigned * const num_groups) | |
1642 | { | |
1643 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1644 | ||
1645 | *groups = npct->soc->functions[function].groups; | |
1646 | *num_groups = npct->soc->functions[function].ngroups; | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
1652 | unsigned group) | |
1653 | { | |
1654 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1655 | const struct nmk_pingroup *g; | |
1656 | static unsigned int slpm[NUM_BANKS]; | |
f84b4171 | 1657 | unsigned long flags = 0; |
dbfe8ca2 LW |
1658 | bool glitch; |
1659 | int ret = -EINVAL; | |
1660 | int i; | |
1661 | ||
1662 | g = &npct->soc->groups[group]; | |
1663 | ||
1664 | if (g->altsetting < 0) | |
1665 | return -EINVAL; | |
1666 | ||
1667 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
1668 | ||
daf73174 LW |
1669 | /* |
1670 | * If we're setting altfunc C by setting both AFSLA and AFSLB to 1, | |
1671 | * we may pass through an undesired state. In this case we take | |
1672 | * some extra care. | |
1673 | * | |
1674 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
1675 | * - Save SLPM registers (since we have a shadow register in the | |
1676 | * nmk_chip we're using that as backup) | |
1677 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
1678 | * - Configure the GPIO registers for the IOs that are being switched | |
1679 | * - Set IOFORCE=1 | |
1680 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
1681 | * - Set IOFORCE=0 | |
1682 | * - Restore SLPM registers | |
1683 | * - Any spurious wake up event during switch sequence to be ignored | |
1684 | * and cleared | |
1685 | * | |
1686 | * We REALLY need to save ALL slpm registers, because the external | |
1687 | * IOFORCE will switch *all* ports to their sleepmode setting to as | |
1688 | * to avoid glitches. (Not just one port!) | |
1689 | */ | |
c22df08c | 1690 | glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); |
dbfe8ca2 LW |
1691 | |
1692 | if (glitch) { | |
1693 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
1694 | ||
1695 | /* Initially don't put any pins to sleep when switching */ | |
1696 | memset(slpm, 0xff, sizeof(slpm)); | |
1697 | ||
1698 | /* | |
1699 | * Then mask the pins that need to be sleeping now when we're | |
1700 | * switching to the ALT C function. | |
1701 | */ | |
1702 | for (i = 0; i < g->npins; i++) | |
1703 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | |
1704 | nmk_gpio_glitch_slpm_init(slpm); | |
1705 | } | |
1706 | ||
1707 | for (i = 0; i < g->npins; i++) { | |
1708 | struct pinctrl_gpio_range *range; | |
1709 | struct nmk_gpio_chip *nmk_chip; | |
1710 | struct gpio_chip *chip; | |
1711 | unsigned bit; | |
1712 | ||
1713 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | |
1714 | if (!range) { | |
1715 | dev_err(npct->dev, | |
1716 | "invalid pin offset %d in group %s at index %d\n", | |
1717 | g->pins[i], g->name, i); | |
1718 | goto out_glitch; | |
1719 | } | |
1720 | if (!range->gc) { | |
1721 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | |
1722 | g->pins[i], g->name, i); | |
1723 | goto out_glitch; | |
1724 | } | |
1725 | chip = range->gc; | |
1726 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1727 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | |
1728 | ||
1729 | clk_enable(nmk_chip->clk); | |
1730 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | |
1731 | /* | |
1732 | * If the pin is switching to altfunc, and there was an | |
1733 | * interrupt installed on it which has been lazy disabled, | |
1734 | * actually mask the interrupt to prevent spurious interrupts | |
1735 | * that would occur while the pin is under control of the | |
1736 | * peripheral. Only SKE does this. | |
1737 | */ | |
1738 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | |
1739 | ||
c22df08c JNG |
1740 | __nmk_gpio_set_mode_safe(nmk_chip, bit, |
1741 | (g->altsetting & NMK_GPIO_ALT_C), glitch); | |
dbfe8ca2 | 1742 | clk_disable(nmk_chip->clk); |
c22df08c JNG |
1743 | |
1744 | /* | |
1745 | * Call PRCM GPIOCR config function in case ALTC | |
1746 | * has been selected: | |
1747 | * - If selection is a ALTCx, some bits in PRCM GPIOCR registers | |
1748 | * must be set. | |
1749 | * - If selection is pure ALTC and previous selection was ALTCx, | |
1750 | * then some bits in PRCM GPIOCR registers must be cleared. | |
1751 | */ | |
1752 | if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C) | |
1753 | nmk_prcm_altcx_set_mode(npct, g->pins[i], | |
1754 | g->altsetting >> NMK_GPIO_ALT_CX_SHIFT); | |
dbfe8ca2 LW |
1755 | } |
1756 | ||
1757 | /* When all pins are successfully reconfigured we get here */ | |
1758 | ret = 0; | |
1759 | ||
1760 | out_glitch: | |
1761 | if (glitch) { | |
1762 | nmk_gpio_glitch_slpm_restore(slpm); | |
1763 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
1764 | } | |
1765 | ||
1766 | return ret; | |
1767 | } | |
1768 | ||
1769 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | |
1770 | unsigned function, unsigned group) | |
1771 | { | |
1772 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1773 | const struct nmk_pingroup *g; | |
1774 | ||
1775 | g = &npct->soc->groups[group]; | |
1776 | ||
1777 | if (g->altsetting < 0) | |
1778 | return; | |
1779 | ||
1780 | /* Poke out the mux, set the pin to some default state? */ | |
1781 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
1782 | } | |
1783 | ||
5212d096 AL |
1784 | static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, |
1785 | struct pinctrl_gpio_range *range, | |
1786 | unsigned offset) | |
dbfe8ca2 LW |
1787 | { |
1788 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1789 | struct nmk_gpio_chip *nmk_chip; | |
1790 | struct gpio_chip *chip; | |
1791 | unsigned bit; | |
1792 | ||
1793 | if (!range) { | |
1794 | dev_err(npct->dev, "invalid range\n"); | |
1795 | return -EINVAL; | |
1796 | } | |
1797 | if (!range->gc) { | |
1798 | dev_err(npct->dev, "missing GPIO chip in range\n"); | |
1799 | return -EINVAL; | |
1800 | } | |
1801 | chip = range->gc; | |
1802 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1803 | ||
1804 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | |
1805 | ||
1806 | clk_enable(nmk_chip->clk); | |
1807 | bit = offset % NMK_GPIO_PER_CHIP; | |
1808 | /* There is no glitch when converting any pin to GPIO */ | |
1809 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1810 | clk_disable(nmk_chip->clk); | |
1811 | ||
1812 | return 0; | |
1813 | } | |
1814 | ||
5212d096 AL |
1815 | static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, |
1816 | struct pinctrl_gpio_range *range, | |
1817 | unsigned offset) | |
dbfe8ca2 LW |
1818 | { |
1819 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1820 | ||
1821 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | |
1822 | /* Set the pin to some default state, GPIO is usually default */ | |
1823 | } | |
1824 | ||
022ab148 | 1825 | static const struct pinmux_ops nmk_pinmux_ops = { |
dbfe8ca2 LW |
1826 | .get_functions_count = nmk_pmx_get_funcs_cnt, |
1827 | .get_function_name = nmk_pmx_get_func_name, | |
1828 | .get_function_groups = nmk_pmx_get_func_groups, | |
1829 | .enable = nmk_pmx_enable, | |
1830 | .disable = nmk_pmx_disable, | |
1831 | .gpio_request_enable = nmk_gpio_request_enable, | |
1832 | .gpio_disable_free = nmk_gpio_disable_free, | |
1833 | }; | |
1834 | ||
5212d096 AL |
1835 | static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, |
1836 | unsigned long *config) | |
d41af627 LW |
1837 | { |
1838 | /* Not implemented */ | |
1839 | return -EINVAL; | |
1840 | } | |
1841 | ||
5212d096 | 1842 | static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
03b054e9 | 1843 | unsigned long *configs, unsigned num_configs) |
d41af627 LW |
1844 | { |
1845 | static const char *pullnames[] = { | |
1846 | [NMK_GPIO_PULL_NONE] = "none", | |
1847 | [NMK_GPIO_PULL_UP] = "up", | |
1848 | [NMK_GPIO_PULL_DOWN] = "down", | |
1849 | [3] /* illegal */ = "??" | |
1850 | }; | |
1851 | static const char *slpmnames[] = { | |
1852 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | |
1853 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
1854 | }; | |
1855 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
1856 | struct nmk_gpio_chip *nmk_chip; | |
1857 | struct pinctrl_gpio_range *range; | |
1858 | struct gpio_chip *chip; | |
1859 | unsigned bit; | |
03b054e9 SY |
1860 | pin_cfg_t cfg; |
1861 | int pull, slpm, output, val, i; | |
1862 | bool lowemi, gpiomode, sleep; | |
d41af627 LW |
1863 | |
1864 | range = nmk_match_gpio_range(pctldev, pin); | |
1865 | if (!range) { | |
1866 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | |
1867 | return -EINVAL; | |
1868 | } | |
1869 | if (!range->gc) { | |
1870 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | |
1871 | pin); | |
1872 | return -EINVAL; | |
1873 | } | |
1874 | chip = range->gc; | |
1875 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | |
1876 | ||
03b054e9 | 1877 | for (i = 0; i < num_configs; i++) { |
d41af627 | 1878 | /* |
03b054e9 SY |
1879 | * The pin config contains pin number and altfunction fields, |
1880 | * here we just ignore that part. It's being handled by the | |
1881 | * framework and pinmux callback respectively. | |
d41af627 | 1882 | */ |
03b054e9 SY |
1883 | cfg = (pin_cfg_t) configs[i]; |
1884 | pull = PIN_PULL(cfg); | |
1885 | slpm = PIN_SLPM(cfg); | |
1886 | output = PIN_DIR(cfg); | |
1887 | val = PIN_VAL(cfg); | |
1888 | lowemi = PIN_LOWEMI(cfg); | |
1889 | gpiomode = PIN_GPIOMODE(cfg); | |
1890 | sleep = PIN_SLEEPMODE(cfg); | |
1891 | ||
1892 | if (sleep) { | |
1893 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
1894 | int slpm_output = PIN_SLPM_DIR(cfg); | |
1895 | int slpm_val = PIN_SLPM_VAL(cfg); | |
1896 | ||
1897 | /* All pins go into GPIO mode at sleep */ | |
1898 | gpiomode = true; | |
1899 | ||
1900 | /* | |
1901 | * The SLPM_* values are normal values + 1 to allow zero | |
1902 | * to mean "same as normal". | |
1903 | */ | |
1904 | if (slpm_pull) | |
1905 | pull = slpm_pull - 1; | |
1906 | if (slpm_output) | |
1907 | output = slpm_output - 1; | |
1908 | if (slpm_val) | |
1909 | val = slpm_val - 1; | |
1910 | ||
1911 | dev_dbg(nmk_chip->chip.dev, | |
1912 | "pin %d: sleep pull %s, dir %s, val %s\n", | |
1913 | pin, | |
1914 | slpm_pull ? pullnames[pull] : "same", | |
1915 | slpm_output ? (output ? "output" : "input") | |
1916 | : "same", | |
1917 | slpm_val ? (val ? "high" : "low") : "same"); | |
1918 | } | |
d41af627 | 1919 | |
03b054e9 SY |
1920 | dev_dbg(nmk_chip->chip.dev, |
1921 | "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | |
1922 | pin, cfg, pullnames[pull], slpmnames[slpm], | |
1923 | output ? "output " : "input", | |
1924 | output ? (val ? "high" : "low") : "", | |
1925 | lowemi ? "on" : "off"); | |
d41af627 | 1926 | |
03b054e9 SY |
1927 | clk_enable(nmk_chip->clk); |
1928 | bit = pin % NMK_GPIO_PER_CHIP; | |
1929 | if (gpiomode) | |
1930 | /* No glitch when going to GPIO mode */ | |
1931 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | |
1932 | if (output) | |
1933 | __nmk_gpio_make_output(nmk_chip, bit, val); | |
1934 | else { | |
1935 | __nmk_gpio_make_input(nmk_chip, bit); | |
1936 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | |
1937 | } | |
1938 | /* TODO: isn't this only applicable on output pins? */ | |
1939 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | |
1940 | ||
1941 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | |
1942 | clk_disable(nmk_chip->clk); | |
1943 | } /* for each config */ | |
d41af627 | 1944 | |
d41af627 LW |
1945 | return 0; |
1946 | } | |
1947 | ||
022ab148 | 1948 | static const struct pinconf_ops nmk_pinconf_ops = { |
d41af627 LW |
1949 | .pin_config_get = nmk_pin_config_get, |
1950 | .pin_config_set = nmk_pin_config_set, | |
1951 | }; | |
1952 | ||
e98ea774 LW |
1953 | static struct pinctrl_desc nmk_pinctrl_desc = { |
1954 | .name = "pinctrl-nomadik", | |
1955 | .pctlops = &nmk_pinctrl_ops, | |
dbfe8ca2 | 1956 | .pmxops = &nmk_pinmux_ops, |
d41af627 | 1957 | .confops = &nmk_pinconf_ops, |
e98ea774 LW |
1958 | .owner = THIS_MODULE, |
1959 | }; | |
1960 | ||
855f80cd | 1961 | static const struct of_device_id nmk_pinctrl_match[] = { |
6010d403 | 1962 | { |
3fd765a9 | 1963 | .compatible = "stericsson,stn8815-pinctrl", |
6010d403 LW |
1964 | .data = (void *)PINCTRL_NMK_STN8815, |
1965 | }, | |
855f80cd | 1966 | { |
6b09a834 | 1967 | .compatible = "stericsson,db8500-pinctrl", |
855f80cd LJ |
1968 | .data = (void *)PINCTRL_NMK_DB8500, |
1969 | }, | |
356d3e45 | 1970 | { |
6b09a834 | 1971 | .compatible = "stericsson,db8540-pinctrl", |
356d3e45 GF |
1972 | .data = (void *)PINCTRL_NMK_DB8540, |
1973 | }, | |
855f80cd LJ |
1974 | {}, |
1975 | }; | |
1976 | ||
131d85bc | 1977 | #ifdef CONFIG_PM_SLEEP |
c003eed7 | 1978 | static int nmk_pinctrl_suspend(struct device *dev) |
8d99b32d JD |
1979 | { |
1980 | struct nmk_pinctrl *npct; | |
1981 | ||
c003eed7 | 1982 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1983 | if (!npct) |
1984 | return -EINVAL; | |
1985 | ||
1986 | return pinctrl_force_sleep(npct->pctl); | |
1987 | } | |
1988 | ||
c003eed7 | 1989 | static int nmk_pinctrl_resume(struct device *dev) |
8d99b32d JD |
1990 | { |
1991 | struct nmk_pinctrl *npct; | |
1992 | ||
c003eed7 | 1993 | npct = dev_get_drvdata(dev); |
8d99b32d JD |
1994 | if (!npct) |
1995 | return -EINVAL; | |
1996 | ||
1997 | return pinctrl_force_default(npct->pctl); | |
1998 | } | |
131d85bc | 1999 | #endif |
8d99b32d | 2000 | |
150632b0 | 2001 | static int nmk_pinctrl_probe(struct platform_device *pdev) |
e98ea774 | 2002 | { |
f4b3f523 | 2003 | const struct of_device_id *match; |
855f80cd | 2004 | struct device_node *np = pdev->dev.of_node; |
32e67eee | 2005 | struct device_node *prcm_np; |
e98ea774 | 2006 | struct nmk_pinctrl *npct; |
855f80cd | 2007 | unsigned int version = 0; |
e98ea774 LW |
2008 | int i; |
2009 | ||
2010 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | |
2011 | if (!npct) | |
2012 | return -ENOMEM; | |
2013 | ||
f4b3f523 LW |
2014 | match = of_match_device(nmk_pinctrl_match, &pdev->dev); |
2015 | if (!match) | |
2016 | return -ENODEV; | |
2017 | version = (unsigned int) match->data; | |
855f80cd | 2018 | |
e98ea774 | 2019 | /* Poke in other ASIC variants here */ |
f79c5ed9 LW |
2020 | if (version == PINCTRL_NMK_STN8815) |
2021 | nmk_pinctrl_stn8815_init(&npct->soc); | |
855f80cd | 2022 | if (version == PINCTRL_NMK_DB8500) |
e98ea774 | 2023 | nmk_pinctrl_db8500_init(&npct->soc); |
45a1b531 PC |
2024 | if (version == PINCTRL_NMK_DB8540) |
2025 | nmk_pinctrl_db8540_init(&npct->soc); | |
e98ea774 | 2026 | |
f4b3f523 LW |
2027 | prcm_np = of_parse_phandle(np, "prcm", 0); |
2028 | if (prcm_np) | |
2029 | npct->prcm_base = of_iomap(prcm_np, 0); | |
32e67eee LJ |
2030 | if (!npct->prcm_base) { |
2031 | if (version == PINCTRL_NMK_STN8815) { | |
2032 | dev_info(&pdev->dev, | |
2033 | "No PRCM base, " | |
2034 | "assuming no ALT-Cx control is available\n"); | |
2035 | } else { | |
2036 | dev_err(&pdev->dev, "missing PRCM base address\n"); | |
2037 | return -EINVAL; | |
f1671bf5 | 2038 | } |
f1671bf5 JA |
2039 | } |
2040 | ||
e98ea774 LW |
2041 | /* |
2042 | * We need all the GPIO drivers to probe FIRST, or we will not be able | |
2043 | * to obtain references to the struct gpio_chip * for them, and we | |
2044 | * need this to proceed. | |
2045 | */ | |
2046 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | |
1d853ca5 | 2047 | if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) { |
e98ea774 | 2048 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); |
e98ea774 LW |
2049 | return -EPROBE_DEFER; |
2050 | } | |
1d853ca5 | 2051 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip; |
e98ea774 LW |
2052 | } |
2053 | ||
2054 | nmk_pinctrl_desc.pins = npct->soc->pins; | |
2055 | nmk_pinctrl_desc.npins = npct->soc->npins; | |
2056 | npct->dev = &pdev->dev; | |
f1671bf5 | 2057 | |
e98ea774 LW |
2058 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); |
2059 | if (!npct->pctl) { | |
2060 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | |
2061 | return -EINVAL; | |
2062 | } | |
2063 | ||
2064 | /* We will handle a range of GPIO pins */ | |
2065 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | |
2066 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | |
2067 | ||
2068 | platform_set_drvdata(pdev, npct); | |
2069 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | |
2070 | ||
2071 | return 0; | |
2072 | } | |
2073 | ||
513c27f8 LJ |
2074 | static const struct of_device_id nmk_gpio_match[] = { |
2075 | { .compatible = "st,nomadik-gpio", }, | |
2076 | {} | |
2077 | }; | |
2078 | ||
3e3c62ca RV |
2079 | static struct platform_driver nmk_gpio_driver = { |
2080 | .driver = { | |
2ec1d359 AR |
2081 | .owner = THIS_MODULE, |
2082 | .name = "gpio", | |
513c27f8 | 2083 | .of_match_table = nmk_gpio_match, |
5317e4d1 | 2084 | }, |
2ec1d359 | 2085 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
2086 | }; |
2087 | ||
c003eed7 UH |
2088 | static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops, |
2089 | nmk_pinctrl_suspend, | |
2090 | nmk_pinctrl_resume); | |
2091 | ||
e98ea774 LW |
2092 | static struct platform_driver nmk_pinctrl_driver = { |
2093 | .driver = { | |
2094 | .owner = THIS_MODULE, | |
2095 | .name = "pinctrl-nomadik", | |
855f80cd | 2096 | .of_match_table = nmk_pinctrl_match, |
c003eed7 | 2097 | .pm = &nmk_pinctrl_pm_ops, |
e98ea774 LW |
2098 | }, |
2099 | .probe = nmk_pinctrl_probe, | |
e98ea774 LW |
2100 | }; |
2101 | ||
2ec1d359 AR |
2102 | static int __init nmk_gpio_init(void) |
2103 | { | |
e98ea774 LW |
2104 | int ret; |
2105 | ||
2106 | ret = platform_driver_register(&nmk_gpio_driver); | |
2107 | if (ret) | |
2108 | return ret; | |
2109 | return platform_driver_register(&nmk_pinctrl_driver); | |
2ec1d359 AR |
2110 | } |
2111 | ||
33f45ea9 | 2112 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
2113 | |
2114 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
2115 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
2116 | MODULE_LICENSE("GPL"); |