projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
[deliverable/linux.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d
HS		 61enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
66d750e1 65 RK3288,
daecdc66 66 RK3368,
a282926d
HS		 67};
68
fc72c923
HS		 69/**
70 * Encode variants of iomux registers into a type variable
71 */
72#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 73#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 74#define IOMUX_SOURCE_PMU BIT(2)
62f49226 75#define IOMUX_UNROUTED BIT(3)
fc72c923
HS		 76
77/**
78 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 79 * @offset: if initialized to -1 it will be autocalculated, by specifying
80 * an initial offset value the relevant source offset can be reset
81 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 82 */
83struct rockchip_iomux {
84 int type;
6bc0d121 85 int offset;
65fca613
HS		 86};
87
d3e51161
HS		 88/**
89 * @reg_base: register base of the gpio bank
6ca5274d 90 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 91 * @clk: clock of the gpio bank
92 * @irq: interrupt of the gpio bank
5ae0c7ad 93 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 94 * @pin_base: first pin number
95 * @nr_pins: number of pins in this bank
96 * @name: name of the bank
97 * @bank_num: number of the bank, to account for holes
fc72c923 98 * @iomux: array describing the 4 iomux sources of the bank
d3e51161
HS		 99 * @valid: are all necessary informations present
100 * @of_node: dt node of this bank
101 * @drvdata: common pinctrl basedata
102 * @domain: irqdomain of the gpio bank
103 * @gpio_chip: gpiolib chip
104 * @grange: gpio range
105 * @slock: spinlock for the gpio bank
106 */
107struct rockchip_pin_bank {
108 void __iomem *reg_base;
751a99ab 109 struct regmap *regmap_pull;
d3e51161
HS		 110 struct clk *clk;
111 int irq;
5ae0c7ad 112 u32 saved_masks;
d3e51161
HS		 113 u32 pin_base;
114 u8 nr_pins;
115 char *name;
116 u8 bank_num;
fc72c923 117 struct rockchip_iomux iomux[4];
d3e51161
HS		 118 bool valid;
119 struct device_node *of_node;
120 struct rockchip_pinctrl *drvdata;
121 struct irq_domain *domain;
122 struct gpio_chip gpio_chip;
123 struct pinctrl_gpio_range grange;
124 spinlock_t slock;
5a927501 125 u32 toggle_edge_mode;
d3e51161
HS		 126};
127
128#define PIN_BANK(id, pins, label) \
129 { \
130 .bank_num = id, \
131 .nr_pins = pins, \
132 .name = label, \
6bc0d121
HS		 133 .iomux = { \
134 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
137 { .offset = -1 }, \
138 }, \
d3e51161
HS		 139 }
140
fc72c923
HS		 141#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
142 { \
143 .bank_num = id, \
144 .nr_pins = pins, \
145 .name = label, \
146 .iomux = { \
6bc0d121
HS		 147 { .type = iom0, .offset = -1 }, \
148 { .type = iom1, .offset = -1 }, \
149 { .type = iom2, .offset = -1 }, \
150 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 151 }, \
152 }
153
d3e51161 154/**
d3e51161
HS		 155 */
156struct rockchip_pin_ctrl {
157 struct rockchip_pin_bank *pin_banks;
158 u32 nr_banks;
159 u32 nr_pins;
160 char *label;
a282926d 161 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 162 int grf_mux_offset;
163 int pmu_mux_offset;
751a99ab
HS		 164 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
165 int pin_num, struct regmap **regmap,
166 int *reg, u8 *bit);
ef17f69f
HS		 167 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
168 int pin_num, struct regmap **regmap,
169 int *reg, u8 *bit);
d3e51161
HS		 170};
171
172struct rockchip_pin_config {
173 unsigned int func;
174 unsigned long *configs;
175 unsigned int nconfigs;
176};
177
178/**
179 * struct rockchip_pin_group: represent group of pins of a pinmux function.
180 * @name: name of the pin group, used to lookup the group.
181 * @pins: the pins included in this group.
182 * @npins: number of pins included in this group.
183 * @func: the mux function number to be programmed when selected.
184 * @configs: the config values to be set for each pin
185 * @nconfigs: number of configs for each pin
186 */
187struct rockchip_pin_group {
188 const char *name;
189 unsigned int npins;
190 unsigned int *pins;
191 struct rockchip_pin_config *data;
192};
193
194/**
195 * struct rockchip_pmx_func: represent a pin function.
196 * @name: name of the pin function, used to lookup the function.
197 * @groups: one or more names of pin groups that provide this function.
198 * @num_groups: number of groups included in @groups.
199 */
200struct rockchip_pmx_func {
201 const char *name;
202 const char **groups;
203 u8 ngroups;
204};
205
206struct rockchip_pinctrl {
751a99ab 207 struct regmap *regmap_base;
bfc7a42a 208 int reg_size;
751a99ab 209 struct regmap *regmap_pull;
14dee867 210 struct regmap *regmap_pmu;
d3e51161
HS		 211 struct device *dev;
212 struct rockchip_pin_ctrl *ctrl;
213 struct pinctrl_desc pctl;
214 struct pinctrl_dev *pctl_dev;
215 struct rockchip_pin_group *groups;
216 unsigned int ngroups;
217 struct rockchip_pmx_func *functions;
218 unsigned int nfunctions;
219};
220
751a99ab
HS		 221static struct regmap_config rockchip_regmap_config = {
222 .reg_bits = 32,
223 .val_bits = 32,
224 .reg_stride = 4,
225};
226
d3e51161
HS		 227static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
228{
229 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
230}
231
232static const inline struct rockchip_pin_group *pinctrl_name_to_group(
233 const struct rockchip_pinctrl *info,
234 const char *name)
235{
d3e51161
HS		 236 int i;
237
238 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 239 if (!strcmp(info->groups[i].name, name))
240 return &info->groups[i];
d3e51161
HS		 241 }
242
1cb95395 243 return NULL;
d3e51161
HS		 244}
245
246/*
247 * given a pin number that is local to a pin controller, find out the pin bank
248 * and the register base of the pin bank.
249 */
250static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
251 unsigned pin)
252{
253 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
254
51578b9b 255 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 256 b++;
257
258 return b;
259}
260
261static struct rockchip_pin_bank *bank_num_to_bank(
262 struct rockchip_pinctrl *info,
263 unsigned num)
264{
265 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
266 int i;
267
1cb95395 268 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 269 if (b->bank_num == num)
1cb95395 270 return b;
d3e51161
HS		 271 }
272
1cb95395 273 return ERR_PTR(-EINVAL);
d3e51161
HS		 274}
275
276/*
277 * Pinctrl_ops handling
278 */
279
280static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
281{
282 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
283
284 return info->ngroups;
285}
286
287static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
288 unsigned selector)
289{
290 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
291
292 return info->groups[selector].name;
293}
294
295static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
296 unsigned selector, const unsigned **pins,
297 unsigned *npins)
298{
299 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
300
301 if (selector >= info->ngroups)
302 return -EINVAL;
303
304 *pins = info->groups[selector].pins;
305 *npins = info->groups[selector].npins;
306
307 return 0;
308}
309
310static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
311 struct device_node *np,
312 struct pinctrl_map **map, unsigned *num_maps)
313{
314 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
315 const struct rockchip_pin_group *grp;
316 struct pinctrl_map *new_map;
317 struct device_node *parent;
318 int map_num = 1;
319 int i;
320
321 /*
322 * first find the group of this node and check if we need to create
323 * config maps for pins
324 */
325 grp = pinctrl_name_to_group(info, np->name);
326 if (!grp) {
327 dev_err(info->dev, "unable to find group for node %s\n",
328 np->name);
329 return -EINVAL;
330 }
331
332 map_num += grp->npins;
333 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
334 GFP_KERNEL);
335 if (!new_map)
336 return -ENOMEM;
337
338 *map = new_map;
339 *num_maps = map_num;
340
341 /* create mux map */
342 parent = of_get_parent(np);
343 if (!parent) {
344 devm_kfree(pctldev->dev, new_map);
345 return -EINVAL;
346 }
347 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
348 new_map[0].data.mux.function = parent->name;
349 new_map[0].data.mux.group = np->name;
350 of_node_put(parent);
351
352 /* create config map */
353 new_map++;
354 for (i = 0; i < grp->npins; i++) {
355 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
356 new_map[i].data.configs.group_or_pin =
357 pin_get_name(pctldev, grp->pins[i]);
358 new_map[i].data.configs.configs = grp->data[i].configs;
359 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
360 }
361
362 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
363 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
364
365 return 0;
366}
367
368static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
369 struct pinctrl_map *map, unsigned num_maps)
370{
371}
372
373static const struct pinctrl_ops rockchip_pctrl_ops = {
374 .get_groups_count = rockchip_get_groups_count,
375 .get_group_name = rockchip_get_group_name,
376 .get_group_pins = rockchip_get_group_pins,
377 .dt_node_to_map = rockchip_dt_node_to_map,
378 .dt_free_map = rockchip_dt_free_map,
379};
380
381/*
382 * Hardware access
383 */
384
a076e2ed
HS		 385static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
386{
387 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 388 int iomux_num = (pin / 8);
95ec8ae4 389 struct regmap *regmap;
751a99ab 390 unsigned int val;
03716e1d 391 int reg, ret, mask;
a076e2ed
HS		 392 u8 bit;
393
fc72c923
HS		 394 if (iomux_num > 3)
395 return -EINVAL;
396
62f49226
HS		 397 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
398 dev_err(info->dev, "pin %d is unrouted\n", pin);
399 return -EINVAL;
400 }
401
fc72c923 402 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 403 return RK_FUNC_GPIO;
404
95ec8ae4
HS		 405 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
406 ? info->regmap_pmu : info->regmap_base;
407
a076e2ed 408 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 409 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 410 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 411 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
412 if ((pin % 8) >= 4)
413 reg += 0x4;
414 bit = (pin % 4) * 4;
415 } else {
416 bit = (pin % 8) * 2;
417 }
a076e2ed 418
95ec8ae4 419 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 420 if (ret)
421 return ret;
422
03716e1d 423 return ((val >> bit) & mask);
a076e2ed
HS		 424}
425
d3e51161
HS		 426/*
427 * Set a new mux function for a pin.
428 *
429 * The register is divided into the upper and lower 16 bit. When changing
430 * a value, the previous register value is not read and changed. Instead
431 * it seems the changed bits are marked in the upper 16 bit, while the
432 * changed value gets set in the same offset in the lower 16 bit.
433 * All pin settings seem to be 2 bit wide in both the upper and lower
434 * parts.
435 * @bank: pin bank to change
436 * @pin: pin to change
437 * @mux: new mux function to set
438 */
14797189 439static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 440{
441 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 442 int iomux_num = (pin / 8);
95ec8ae4 443 struct regmap *regmap;
03716e1d 444 int reg, ret, mask;
d3e51161
HS		 445 unsigned long flags;
446 u8 bit;
99e872d9 447 u32 data, rmask;
d3e51161 448
fc72c923
HS		 449 if (iomux_num > 3)
450 return -EINVAL;
451
62f49226
HS		 452 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
453 dev_err(info->dev, "pin %d is unrouted\n", pin);
454 return -EINVAL;
455 }
456
fc72c923 457 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
c4a532de
HS		 458 if (mux != RK_FUNC_GPIO) {
459 dev_err(info->dev,
460 "pin %d only supports a gpio mux\n", pin);
461 return -ENOTSUPP;
462 } else {
463 return 0;
464 }
465 }
466
d3e51161
HS		 467 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
468 bank->bank_num, pin, mux);
469
95ec8ae4
HS		 470 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
471 ? info->regmap_pmu : info->regmap_base;
472
d3e51161 473 /* get basic quadrupel of mux registers and the correct reg inside */
03716e1d 474 mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3;
6bc0d121 475 reg = bank->iomux[iomux_num].offset;
03716e1d
HS		 476 if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) {
477 if ((pin % 8) >= 4)
478 reg += 0x4;
479 bit = (pin % 4) * 4;
480 } else {
481 bit = (pin % 8) * 2;
482 }
d3e51161
HS		 483
484 spin_lock_irqsave(&bank->slock, flags);
485
03716e1d 486 data = (mask << (bit + 16));
99e872d9 487 rmask = data | (data >> 16);
03716e1d 488 data |= (mux & mask) << bit;
99e872d9 489 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161
HS		 490
491 spin_unlock_irqrestore(&bank->slock, flags);
14797189 492
751a99ab 493 return ret;
d3e51161
HS		 494}
495
a282926d
HS		 496#define RK2928_PULL_OFFSET 0x118
497#define RK2928_PULL_PINS_PER_REG 16
498#define RK2928_PULL_BANK_STRIDE 8
499
500static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 501 int pin_num, struct regmap **regmap,
502 int *reg, u8 *bit)
a282926d
HS		 503{
504 struct rockchip_pinctrl *info = bank->drvdata;
505
751a99ab
HS		 506 *regmap = info->regmap_base;
507 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 508 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
509 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
510
511 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
512};
513
bfc7a42a 514#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 515#define RK3188_PULL_BITS_PER_PIN 2
516#define RK3188_PULL_PINS_PER_REG 8
517#define RK3188_PULL_BANK_STRIDE 16
14dee867 518#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 519
520static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 521 int pin_num, struct regmap **regmap,
522 int *reg, u8 *bit)
6ca5274d
HS		 523{
524 struct rockchip_pinctrl *info = bank->drvdata;
525
526 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 527 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 528 *regmap = info->regmap_pmu ? info->regmap_pmu
529 : bank->regmap_pull;
530 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 531 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 532 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
533 *bit *= RK3188_PULL_BITS_PER_PIN;
534 } else {
751a99ab
HS		 535 *regmap = info->regmap_pull ? info->regmap_pull
536 : info->regmap_base;
537 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
538
bfc7a42a
HS		 539 /* correct the offset, as it is the 2nd pull register */
540 *reg -= 4;
6ca5274d
HS		 541 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
542 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
543
544 /*
545 * The bits in these registers have an inverse ordering
546 * with the lowest pin being in bits 15:14 and the highest
547 * pin in bits 1:0
548 */
549 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
550 *bit *= RK3188_PULL_BITS_PER_PIN;
551 }
552}
553
304f077d
HS		 554#define RK3288_PULL_OFFSET 0x140
555static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
556 int pin_num, struct regmap **regmap,
557 int *reg, u8 *bit)
558{
559 struct rockchip_pinctrl *info = bank->drvdata;
560
561 /* The first 24 pins of the first bank are located in PMU */
562 if (bank->bank_num == 0) {
563 *regmap = info->regmap_pmu;
564 *reg = RK3188_PULL_PMU_OFFSET;
565
566 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
567 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
568 *bit *= RK3188_PULL_BITS_PER_PIN;
569 } else {
570 *regmap = info->regmap_base;
571 *reg = RK3288_PULL_OFFSET;
572
573 /* correct the offset, as we're starting with the 2nd bank */
574 *reg -= 0x10;
575 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
576 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
577
578 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
579 *bit *= RK3188_PULL_BITS_PER_PIN;
580 }
581}
582
b547c800
HS		 583#define RK3288_DRV_PMU_OFFSET 0x70
584#define RK3288_DRV_GRF_OFFSET 0x1c0
585#define RK3288_DRV_BITS_PER_PIN 2
586#define RK3288_DRV_PINS_PER_REG 8
587#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 588
589static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
590 int pin_num, struct regmap **regmap,
591 int *reg, u8 *bit)
592{
593 struct rockchip_pinctrl *info = bank->drvdata;
594
595 /* The first 24 pins of the first bank are located in PMU */
596 if (bank->bank_num == 0) {
597 *regmap = info->regmap_pmu;
598 *reg = RK3288_DRV_PMU_OFFSET;
599
600 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
601 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
602 *bit *= RK3288_DRV_BITS_PER_PIN;
603 } else {
604 *regmap = info->regmap_base;
605 *reg = RK3288_DRV_GRF_OFFSET;
606
607 /* correct the offset, as we're starting with the 2nd bank */
608 *reg -= 0x10;
609 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
610 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
611
612 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
613 *bit *= RK3288_DRV_BITS_PER_PIN;
614 }
615}
616
fea0fe60
JC		 617#define RK3228_PULL_OFFSET 0x100
618
619static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
620 int pin_num, struct regmap **regmap,
621 int *reg, u8 *bit)
622{
623 struct rockchip_pinctrl *info = bank->drvdata;
624
625 *regmap = info->regmap_base;
626 *reg = RK3228_PULL_OFFSET;
627 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
628 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
629
630 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
631 *bit *= RK3188_PULL_BITS_PER_PIN;
632}
633
634#define RK3228_DRV_GRF_OFFSET 0x200
635
636static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
637 int pin_num, struct regmap **regmap,
638 int *reg, u8 *bit)
639{
640 struct rockchip_pinctrl *info = bank->drvdata;
641
642 *regmap = info->regmap_base;
643 *reg = RK3228_DRV_GRF_OFFSET;
644 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
645 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
646
647 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
648 *bit *= RK3288_DRV_BITS_PER_PIN;
649}
650
daecdc66
HS		 651#define RK3368_PULL_GRF_OFFSET 0x100
652#define RK3368_PULL_PMU_OFFSET 0x10
653
654static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
655 int pin_num, struct regmap **regmap,
656 int *reg, u8 *bit)
657{
658 struct rockchip_pinctrl *info = bank->drvdata;
659
660 /* The first 32 pins of the first bank are located in PMU */
661 if (bank->bank_num == 0) {
662 *regmap = info->regmap_pmu;
663 *reg = RK3368_PULL_PMU_OFFSET;
664
665 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
666 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
667 *bit *= RK3188_PULL_BITS_PER_PIN;
668 } else {
669 *regmap = info->regmap_base;
670 *reg = RK3368_PULL_GRF_OFFSET;
671
672 /* correct the offset, as we're starting with the 2nd bank */
673 *reg -= 0x10;
674 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
675 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
676
677 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
678 *bit *= RK3188_PULL_BITS_PER_PIN;
679 }
680}
681
682#define RK3368_DRV_PMU_OFFSET 0x20
683#define RK3368_DRV_GRF_OFFSET 0x200
684
685static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
686 int pin_num, struct regmap **regmap,
687 int *reg, u8 *bit)
688{
689 struct rockchip_pinctrl *info = bank->drvdata;
690
691 /* The first 32 pins of the first bank are located in PMU */
692 if (bank->bank_num == 0) {
693 *regmap = info->regmap_pmu;
694 *reg = RK3368_DRV_PMU_OFFSET;
695
696 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
697 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
698 *bit *= RK3288_DRV_BITS_PER_PIN;
699 } else {
700 *regmap = info->regmap_base;
701 *reg = RK3368_DRV_GRF_OFFSET;
702
703 /* correct the offset, as we're starting with the 2nd bank */
704 *reg -= 0x10;
705 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
706 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
707
708 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
709 *bit *= RK3288_DRV_BITS_PER_PIN;
710 }
711}
712
ef17f69f
HS		 713static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
714
715static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
716 int pin_num)
b547c800 717{
ef17f69f
HS		 718 struct rockchip_pinctrl *info = bank->drvdata;
719 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 720 struct regmap *regmap;
721 int reg, ret;
722 u32 data;
723 u8 bit;
724
ef17f69f 725 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 726
727 ret = regmap_read(regmap, reg, &data);
728 if (ret)
729 return ret;
730
731 data >>= bit;
732 data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
733
ef17f69f 734 return rockchip_perpin_drv_list[data];
b547c800
HS		 735}
736
ef17f69f
HS		 737static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
738 int pin_num, int strength)
b547c800
HS		 739{
740 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 741 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 742 struct regmap *regmap;
743 unsigned long flags;
744 int reg, ret, i;
99e872d9 745 u32 data, rmask;
b547c800
HS		 746 u8 bit;
747
ef17f69f 748 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 749
750 ret = -EINVAL;
ef17f69f
HS		 751 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
752 if (rockchip_perpin_drv_list[i] == strength) {
b547c800
HS		 753 ret = i;
754 break;
755 }
756 }
757
758 if (ret < 0) {
759 dev_err(info->dev, "unsupported driver strength %d\n",
760 strength);
761 return ret;
762 }
763
764 spin_lock_irqsave(&bank->slock, flags);
765
766 /* enable the write to the equivalent lower bits */
767 data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 768 rmask = data | (data >> 16);
b547c800
HS		 769 data |= (ret << bit);
770
99e872d9 771 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 772 spin_unlock_irqrestore(&bank->slock, flags);
773
774 return ret;
775}
776
d3e51161
HS		 777static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
778{
779 struct rockchip_pinctrl *info = bank->drvdata;
780 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 781 struct regmap *regmap;
782 int reg, ret;
d3e51161 783 u8 bit;
6ca5274d 784 u32 data;
d3e51161
HS		 785
786 /* rk3066b does support any pulls */
a282926d 787 if (ctrl->type == RK3066B)
d3e51161
HS		 788 return PIN_CONFIG_BIAS_DISABLE;
789
751a99ab
HS		 790 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
791
792 ret = regmap_read(regmap, reg, &data);
793 if (ret)
794 return ret;
6ca5274d 795
a282926d
HS		 796 switch (ctrl->type) {
797 case RK2928:
751a99ab 798 return !(data & BIT(bit))
d3e51161
HS		 799 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
800 : PIN_CONFIG_BIAS_DISABLE;
a282926d 801 case RK3188:
66d750e1 802 case RK3288:
daecdc66 803 case RK3368:
751a99ab 804 data >>= bit;
6ca5274d
HS		 805 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
806
807 switch (data) {
808 case 0:
809 return PIN_CONFIG_BIAS_DISABLE;
810 case 1:
811 return PIN_CONFIG_BIAS_PULL_UP;
812 case 2:
813 return PIN_CONFIG_BIAS_PULL_DOWN;
814 case 3:
815 return PIN_CONFIG_BIAS_BUS_HOLD;
816 }
817
818 dev_err(info->dev, "unknown pull setting\n");
d3e51161 819 return -EIO;
a282926d
HS		 820 default:
821 dev_err(info->dev, "unsupported pinctrl type\n");
822 return -EINVAL;
823 };
d3e51161
HS		 824}
825
826static int rockchip_set_pull(struct rockchip_pin_bank *bank,
827 int pin_num, int pull)
828{
829 struct rockchip_pinctrl *info = bank->drvdata;
830 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab
HS		 831 struct regmap *regmap;
832 int reg, ret;
d3e51161
HS		 833 unsigned long flags;
834 u8 bit;
99e872d9 835 u32 data, rmask;
d3e51161
HS		 836
837 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
838 bank->bank_num, pin_num, pull);
839
840 /* rk3066b does support any pulls */
a282926d 841 if (ctrl->type == RK3066B)
d3e51161
HS		 842 return pull ? -EINVAL : 0;
843
751a99ab 844 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 845
a282926d
HS		 846 switch (ctrl->type) {
847 case RK2928:
d3e51161
HS		 848 spin_lock_irqsave(&bank->slock, flags);
849
850 data = BIT(bit + 16);
851 if (pull == PIN_CONFIG_BIAS_DISABLE)
852 data |= BIT(bit);
751a99ab 853 ret = regmap_write(regmap, reg, data);
d3e51161
HS		 854
855 spin_unlock_irqrestore(&bank->slock, flags);
a282926d
HS		 856 break;
857 case RK3188:
66d750e1 858 case RK3288:
daecdc66 859 case RK3368:
6ca5274d
HS		 860 spin_lock_irqsave(&bank->slock, flags);
861
862 /* enable the write to the equivalent lower bits */
863 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 864 rmask = data | (data >> 16);
6ca5274d
HS		 865
866 switch (pull) {
867 case PIN_CONFIG_BIAS_DISABLE:
868 break;
869 case PIN_CONFIG_BIAS_PULL_UP:
870 data |= (1 << bit);
871 break;
872 case PIN_CONFIG_BIAS_PULL_DOWN:
873 data |= (2 << bit);
874 break;
875 case PIN_CONFIG_BIAS_BUS_HOLD:
876 data |= (3 << bit);
877 break;
878 default:
d32c3e26 879 spin_unlock_irqrestore(&bank->slock, flags);
6ca5274d
HS		 880 dev_err(info->dev, "unsupported pull setting %d\n",
881 pull);
882 return -EINVAL;
883 }
884
99e872d9 885 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d
HS		 886
887 spin_unlock_irqrestore(&bank->slock, flags);
888 break;
a282926d
HS		 889 default:
890 dev_err(info->dev, "unsupported pinctrl type\n");
891 return -EINVAL;
d3e51161
HS		 892 }
893
751a99ab 894 return ret;
d3e51161
HS		 895}
896
897/*
898 * Pinmux_ops handling
899 */
900
901static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
902{
903 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
904
905 return info->nfunctions;
906}
907
908static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
909 unsigned selector)
910{
911 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
912
913 return info->functions[selector].name;
914}
915
916static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
917 unsigned selector, const char * const **groups,
918 unsigned * const num_groups)
919{
920 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
921
922 *groups = info->functions[selector].groups;
923 *num_groups = info->functions[selector].ngroups;
924
925 return 0;
926}
927
03e9f0ca
LW		 928static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
929 unsigned group)
d3e51161
HS		 930{
931 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
932 const unsigned int *pins = info->groups[group].pins;
933 const struct rockchip_pin_config *data = info->groups[group].data;
934 struct rockchip_pin_bank *bank;
14797189 935 int cnt, ret = 0;
d3e51161
HS		 936
937 dev_dbg(info->dev, "enable function %s group %s\n",
938 info->functions[selector].name, info->groups[group].name);
939
940 /*
941 * for each pin in the pin group selected, program the correspoding pin
942 * pin function number in the config register.
943 */
944 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
945 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 946 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
947 data[cnt].func);
948 if (ret)
949 break;
950 }
951
952 if (ret) {
953 /* revert the already done pin settings */
954 for (cnt--; cnt >= 0; cnt--)
955 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
956
957 return ret;
d3e51161
HS		 958 }
959
960 return 0;
961}
962
d3e51161
HS		 963/*
964 * The calls to gpio_direction_output() and gpio_direction_input()
965 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
966 * function called from the gpiolib interface).
967 */
e5c2c9db
DA		 968static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
969 int pin, bool input)
d3e51161 970{
d3e51161 971 struct rockchip_pin_bank *bank;
e5c2c9db 972 int ret;
fab262f5 973 unsigned long flags;
d3e51161
HS		 974 u32 data;
975
d3e51161 976 bank = gc_to_pin_bank(chip);
d3e51161 977
14797189
HS		 978 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
979 if (ret < 0)
980 return ret;
d3e51161 981
07a06ae9 982 clk_enable(bank->clk);
fab262f5
DA		 983 spin_lock_irqsave(&bank->slock, flags);
984
d3e51161
HS		 985 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
986 /* set bit to 1 for output, 0 for input */
987 if (!input)
988 data |= BIT(pin);
989 else
990 data &= ~BIT(pin);
991 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
992
fab262f5 993 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 994 clk_disable(bank->clk);
fab262f5 995
d3e51161
HS		 996 return 0;
997}
998
e5c2c9db
DA		 999static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1000 struct pinctrl_gpio_range *range,
1001 unsigned offset, bool input)
1002{
1003 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1004 struct gpio_chip *chip;
1005 int pin;
1006
1007 chip = range->gc;
1008 pin = offset - chip->base;
1009 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1010 offset, range->name, pin, input ? "input" : "output");
1011
1012 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1013 input);
1014}
1015
d3e51161
HS		 1016static const struct pinmux_ops rockchip_pmx_ops = {
1017 .get_functions_count = rockchip_pmx_get_funcs_count,
1018 .get_function_name = rockchip_pmx_get_func_name,
1019 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 1020 .set_mux = rockchip_pmx_set,
d3e51161
HS		 1021 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1022};
1023
1024/*
1025 * Pinconf_ops handling
1026 */
1027
44b6d930
HS		 1028static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1029 enum pin_config_param pull)
1030{
a282926d
HS		 1031 switch (ctrl->type) {
1032 case RK2928:
1033 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1034 pull == PIN_CONFIG_BIAS_DISABLE);
1035 case RK3066B:
44b6d930 1036 return pull ? false : true;
a282926d 1037 case RK3188:
66d750e1 1038 case RK3288:
daecdc66 1039 case RK3368:
a282926d 1040 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 1041 }
1042
a282926d 1043 return false;
44b6d930
HS		 1044}
1045
e5c2c9db 1046static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 1047static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1048
d3e51161
HS		 1049/* set the pin config settings for a specified pin */
1050static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 1051 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 1052{
1053 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1054 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9
SY		 1055 enum pin_config_param param;
1056 u16 arg;
1057 int i;
1058 int rc;
1059
1060 for (i = 0; i < num_configs; i++) {
1061 param = pinconf_to_config_param(configs[i]);
1062 arg = pinconf_to_config_argument(configs[i]);
1063
1064 switch (param) {
1065 case PIN_CONFIG_BIAS_DISABLE:
1066 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1067 param);
1068 if (rc)
1069 return rc;
1070 break;
1071 case PIN_CONFIG_BIAS_PULL_UP:
1072 case PIN_CONFIG_BIAS_PULL_DOWN:
1073 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1074 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 1075 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1076 return -ENOTSUPP;
1077
1078 if (!arg)
1079 return -EINVAL;
1080
1081 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1082 param);
1083 if (rc)
1084 return rc;
1085 break;
a076e2ed 1086 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 1087 rockchip_gpio_set(&bank->gpio_chip,
1088 pin - bank->pin_base, arg);
1089 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1090 pin - bank->pin_base, false);
a076e2ed
HS		 1091 if (rc)
1092 return rc;
1093 break;
b547c800
HS		 1094 case PIN_CONFIG_DRIVE_STRENGTH:
1095 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1096 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1097 return -ENOTSUPP;
1098
ef17f69f
HS		 1099 rc = rockchip_set_drive_perpin(bank,
1100 pin - bank->pin_base, arg);
b547c800
HS		 1101 if (rc < 0)
1102 return rc;
1103 break;
03b054e9 1104 default:
44b6d930 1105 return -ENOTSUPP;
03b054e9
SY		 1106 break;
1107 }
1108 } /* for each config */
d3e51161
HS		 1109
1110 return 0;
1111}
1112
1113/* get the pin config settings for a specified pin */
1114static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1115 unsigned long *config)
1116{
1117 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1118 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1119 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 1120 u16 arg;
a076e2ed 1121 int rc;
d3e51161
HS		 1122
1123 switch (param) {
1124 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 1125 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1126 return -EINVAL;
1127
dab3eba7 1128 arg = 0;
44b6d930 1129 break;
d3e51161
HS		 1130 case PIN_CONFIG_BIAS_PULL_UP:
1131 case PIN_CONFIG_BIAS_PULL_DOWN:
1132 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 1133 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 1134 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1135 return -ENOTSUPP;
d3e51161 1136
44b6d930 1137 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 1138 return -EINVAL;
1139
dab3eba7 1140 arg = 1;
d3e51161 1141 break;
a076e2ed
HS		 1142 case PIN_CONFIG_OUTPUT:
1143 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1144 if (rc != RK_FUNC_GPIO)
1145 return -EINVAL;
1146
1147 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1148 if (rc < 0)
1149 return rc;
1150
1151 arg = rc ? 1 : 0;
1152 break;
b547c800
HS		 1153 case PIN_CONFIG_DRIVE_STRENGTH:
1154 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 1155 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 1156 return -ENOTSUPP;
1157
ef17f69f 1158 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 1159 if (rc < 0)
1160 return rc;
1161
1162 arg = rc;
1163 break;
d3e51161
HS		 1164 default:
1165 return -ENOTSUPP;
1166 break;
1167 }
1168
dab3eba7
HS		 1169 *config = pinconf_to_config_packed(param, arg);
1170
d3e51161
HS		 1171 return 0;
1172}
1173
1174static const struct pinconf_ops rockchip_pinconf_ops = {
1175 .pin_config_get = rockchip_pinconf_get,
1176 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 1177 .is_generic = true,
d3e51161
HS		 1178};
1179
65fca613
HS		 1180static const struct of_device_id rockchip_bank_match[] = {
1181 { .compatible = "rockchip,gpio-bank" },
6ca5274d 1182 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 1183 {},
1184};
d3e51161
HS		 1185
1186static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1187 struct device_node *np)
1188{
1189 struct device_node *child;
1190
1191 for_each_child_of_node(np, child) {
65fca613 1192 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 1193 continue;
1194
1195 info->nfunctions++;
1196 info->ngroups += of_get_child_count(child);
1197 }
1198}
1199
1200static int rockchip_pinctrl_parse_groups(struct device_node *np,
1201 struct rockchip_pin_group *grp,
1202 struct rockchip_pinctrl *info,
1203 u32 index)
1204{
1205 struct rockchip_pin_bank *bank;
1206 int size;
1207 const __be32 *list;
1208 int num;
1209 int i, j;
1210 int ret;
1211
1212 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1213
1214 /* Initialise group */
1215 grp->name = np->name;
1216
1217 /*
1218 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1219 * do sanity check and calculate pins number
1220 */
1221 list = of_get_property(np, "rockchip,pins", &size);
1222 /* we do not check return since it's safe node passed down */
1223 size /= sizeof(*list);
1224 if (!size || size % 4) {
1225 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1226 return -EINVAL;
1227 }
1228
1229 grp->npins = size / 4;
1230
1231 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1232 GFP_KERNEL);
1233 grp->data = devm_kzalloc(info->dev, grp->npins *
1234 sizeof(struct rockchip_pin_config),
1235 GFP_KERNEL);
1236 if (!grp->pins || !grp->data)
1237 return -ENOMEM;
1238
1239 for (i = 0, j = 0; i < size; i += 4, j++) {
1240 const __be32 *phandle;
1241 struct device_node *np_config;
1242
1243 num = be32_to_cpu(*list++);
1244 bank = bank_num_to_bank(info, num);
1245 if (IS_ERR(bank))
1246 return PTR_ERR(bank);
1247
1248 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1249 grp->data[j].func = be32_to_cpu(*list++);
1250
1251 phandle = list++;
1252 if (!phandle)
1253 return -EINVAL;
1254
1255 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 1256 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 1257 &grp->data[j].configs, &grp->data[j].nconfigs);
1258 if (ret)
1259 return ret;
1260 }
1261
1262 return 0;
1263}
1264
1265static int rockchip_pinctrl_parse_functions(struct device_node *np,
1266 struct rockchip_pinctrl *info,
1267 u32 index)
1268{
1269 struct device_node *child;
1270 struct rockchip_pmx_func *func;
1271 struct rockchip_pin_group *grp;
1272 int ret;
1273 static u32 grp_index;
1274 u32 i = 0;
1275
1276 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1277
1278 func = &info->functions[index];
1279
1280 /* Initialise function */
1281 func->name = np->name;
1282 func->ngroups = of_get_child_count(np);
1283 if (func->ngroups <= 0)
1284 return 0;
1285
1286 func->groups = devm_kzalloc(info->dev,
1287 func->ngroups * sizeof(char *), GFP_KERNEL);
1288 if (!func->groups)
1289 return -ENOMEM;
1290
1291 for_each_child_of_node(np, child) {
1292 func->groups[i] = child->name;
1293 grp = &info->groups[grp_index++];
1294 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 1295 if (ret) {
1296 of_node_put(child);
d3e51161 1297 return ret;
f7a81b7f 1298 }
d3e51161
HS		 1299 }
1300
1301 return 0;
1302}
1303
1304static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1305 struct rockchip_pinctrl *info)
1306{
1307 struct device *dev = &pdev->dev;
1308 struct device_node *np = dev->of_node;
1309 struct device_node *child;
1310 int ret;
1311 int i;
1312
1313 rockchip_pinctrl_child_count(info, np);
1314
1315 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1316 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1317
1318 info->functions = devm_kzalloc(dev, info->nfunctions *
1319 sizeof(struct rockchip_pmx_func),
1320 GFP_KERNEL);
1321 if (!info->functions) {
1322 dev_err(dev, "failed to allocate memory for function list\n");
1323 return -EINVAL;
1324 }
1325
1326 info->groups = devm_kzalloc(dev, info->ngroups *
1327 sizeof(struct rockchip_pin_group),
1328 GFP_KERNEL);
1329 if (!info->groups) {
1330 dev_err(dev, "failed allocate memory for ping group list\n");
1331 return -EINVAL;
1332 }
1333
1334 i = 0;
1335
1336 for_each_child_of_node(np, child) {
65fca613 1337 if (of_match_node(rockchip_bank_match, child))
d3e51161 1338 continue;
65fca613 1339
d3e51161
HS		 1340 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1341 if (ret) {
1342 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 1343 of_node_put(child);
d3e51161
HS		 1344 return ret;
1345 }
1346 }
1347
1348 return 0;
1349}
1350
1351static int rockchip_pinctrl_register(struct platform_device *pdev,
1352 struct rockchip_pinctrl *info)
1353{
1354 struct pinctrl_desc *ctrldesc = &info->pctl;
1355 struct pinctrl_pin_desc *pindesc, *pdesc;
1356 struct rockchip_pin_bank *pin_bank;
1357 int pin, bank, ret;
1358 int k;
1359
1360 ctrldesc->name = "rockchip-pinctrl";
1361 ctrldesc->owner = THIS_MODULE;
1362 ctrldesc->pctlops = &rockchip_pctrl_ops;
1363 ctrldesc->pmxops = &rockchip_pmx_ops;
1364 ctrldesc->confops = &rockchip_pinconf_ops;
1365
1366 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1367 info->ctrl->nr_pins, GFP_KERNEL);
1368 if (!pindesc) {
1369 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1370 return -ENOMEM;
1371 }
1372 ctrldesc->pins = pindesc;
1373 ctrldesc->npins = info->ctrl->nr_pins;
1374
1375 pdesc = pindesc;
1376 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1377 pin_bank = &info->ctrl->pin_banks[bank];
1378 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1379 pdesc->number = k;
1380 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1381 pin_bank->name, pin);
1382 pdesc++;
1383 }
1384 }
1385
0fb7dcb1
DA		 1386 ret = rockchip_pinctrl_parse_dt(pdev, info);
1387 if (ret)
1388 return ret;
1389
d3e51161 1390 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
323de9ef 1391 if (IS_ERR(info->pctl_dev)) {
d3e51161 1392 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 1393 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 1394 }
1395
1396 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1397 pin_bank = &info->ctrl->pin_banks[bank];
1398 pin_bank->grange.name = pin_bank->name;
1399 pin_bank->grange.id = bank;
1400 pin_bank->grange.pin_base = pin_bank->pin_base;
1401 pin_bank->grange.base = pin_bank->gpio_chip.base;
1402 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1403 pin_bank->grange.gc = &pin_bank->gpio_chip;
1404 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1405 }
1406
d3e51161
HS		 1407 return 0;
1408}
1409
1410/*
1411 * GPIO handling
1412 */
1413
1414static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1415{
1416 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1417 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1418 unsigned long flags;
1419 u32 data;
1420
07a06ae9 1421 clk_enable(bank->clk);
d3e51161
HS		 1422 spin_lock_irqsave(&bank->slock, flags);
1423
1424 data = readl(reg);
1425 data &= ~BIT(offset);
1426 if (value)
1427 data |= BIT(offset);
1428 writel(data, reg);
1429
1430 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1431 clk_disable(bank->clk);
d3e51161
HS		 1432}
1433
1434/*
1435 * Returns the level of the pin for input direction and setting of the DR
1436 * register for output gpios.
1437 */
1438static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1439{
1440 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1441 u32 data;
1442
07a06ae9 1443 clk_enable(bank->clk);
d3e51161 1444 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 1445 clk_disable(bank->clk);
d3e51161
HS		 1446 data >>= offset;
1447 data &= 1;
1448 return data;
1449}
1450
1451/*
1452 * gpiolib gpio_direction_input callback function. The setting of the pin
1453 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1454 * interface.
1455 */
1456static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1457{
1458 return pinctrl_gpio_direction_input(gc->base + offset);
1459}
1460
1461/*
1462 * gpiolib gpio_direction_output callback function. The setting of the pin
1463 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1464 * interface.
1465 */
1466static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1467 unsigned offset, int value)
1468{
1469 rockchip_gpio_set(gc, offset, value);
1470 return pinctrl_gpio_direction_output(gc->base + offset);
1471}
1472
1473/*
1474 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1475 * and a virtual IRQ, if not already present.
1476 */
1477static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1478{
1479 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1480 unsigned int virq;
1481
1482 if (!bank->domain)
1483 return -ENXIO;
1484
1485 virq = irq_create_mapping(bank->domain, offset);
1486
1487 return (virq) ? : -ENXIO;
1488}
1489
1490static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 1491 .request = gpiochip_generic_request,
1492 .free = gpiochip_generic_free,
d3e51161
HS		 1493 .set = rockchip_gpio_set,
1494 .get = rockchip_gpio_get,
1495 .direction_input = rockchip_gpio_direction_input,
1496 .direction_output = rockchip_gpio_direction_output,
1497 .to_irq = rockchip_gpio_to_irq,
1498 .owner = THIS_MODULE,
1499};
1500
1501/*
1502 * Interrupt handling
1503 */
1504
bd0b9ac4 1505static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 1506{
5663bb27
JL		 1507 struct irq_chip *chip = irq_desc_get_chip(desc);
1508 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 1509 u32 pend;
1510
1511 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1512
1513 chained_irq_enter(chip, desc);
1514
1515 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1516
1517 while (pend) {
415f748c 1518 unsigned int irq, virq;
d3e51161
HS		 1519
1520 irq = __ffs(pend);
1521 pend &= ~BIT(irq);
1522 virq = irq_linear_revmap(bank->domain, irq);
1523
1524 if (!virq) {
1525 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1526 continue;
1527 }
1528
1529 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1530
5a927501
HS		 1531 /*
1532 * Triggering IRQ on both rising and falling edge
1533 * needs manual intervention.
1534 */
1535 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 1536 u32 data, data_old, polarity;
1537 unsigned long flags;
1538
1539 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1540 do {
1541 spin_lock_irqsave(&bank->slock, flags);
1542
1543 polarity = readl_relaxed(bank->reg_base +
1544 GPIO_INT_POLARITY);
1545 if (data & BIT(irq))
1546 polarity &= ~BIT(irq);
1547 else
1548 polarity |= BIT(irq);
1549 writel(polarity,
1550 bank->reg_base + GPIO_INT_POLARITY);
1551
1552 spin_unlock_irqrestore(&bank->slock, flags);
1553
1554 data_old = data;
1555 data = readl_relaxed(bank->reg_base +
1556 GPIO_EXT_PORT);
1557 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 1558 }
1559
d3e51161
HS		 1560 generic_handle_irq(virq);
1561 }
1562
1563 chained_irq_exit(chip, desc);
1564}
1565
1566static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1567{
1568 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1569 struct rockchip_pin_bank *bank = gc->private;
1570 u32 mask = BIT(d->hwirq);
1571 u32 polarity;
1572 u32 level;
1573 u32 data;
fab262f5 1574 unsigned long flags;
14797189 1575 int ret;
d3e51161 1576
5a927501 1577 /* make sure the pin is configured as gpio input */
14797189
HS		 1578 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1579 if (ret < 0)
1580 return ret;
1581
07a06ae9 1582 clk_enable(bank->clk);
fab262f5
DA		 1583 spin_lock_irqsave(&bank->slock, flags);
1584
5a927501
HS		 1585 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1586 data &= ~mask;
1587 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1588
fab262f5
DA		 1589 spin_unlock_irqrestore(&bank->slock, flags);
1590
d3e51161 1591 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 1592 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 1593 else
2dbf1bc5 1594 irq_set_handler_locked(d, handle_level_irq);
d3e51161 1595
fab262f5 1596 spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 1597 irq_gc_lock(gc);
1598
1599 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1600 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1601
1602 switch (type) {
5a927501
HS		 1603 case IRQ_TYPE_EDGE_BOTH:
1604 bank->toggle_edge_mode |= mask;
1605 level |= mask;
1606
1607 /*
1608 * Determine gpio state. If 1 next interrupt should be falling
1609 * otherwise rising.
1610 */
1611 data = readl(bank->reg_base + GPIO_EXT_PORT);
1612 if (data & mask)
1613 polarity &= ~mask;
1614 else
1615 polarity |= mask;
1616 break;
d3e51161 1617 case IRQ_TYPE_EDGE_RISING:
5a927501 1618 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1619 level |= mask;
1620 polarity |= mask;
1621 break;
1622 case IRQ_TYPE_EDGE_FALLING:
5a927501 1623 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1624 level |= mask;
1625 polarity &= ~mask;
1626 break;
1627 case IRQ_TYPE_LEVEL_HIGH:
5a927501 1628 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1629 level &= ~mask;
1630 polarity |= mask;
1631 break;
1632 case IRQ_TYPE_LEVEL_LOW:
5a927501 1633 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 1634 level &= ~mask;
1635 polarity &= ~mask;
1636 break;
1637 default:
7cc5f970 1638 irq_gc_unlock(gc);
fab262f5 1639 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1640 clk_disable(bank->clk);
d3e51161
HS		 1641 return -EINVAL;
1642 }
1643
1644 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1645 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1646
1647 irq_gc_unlock(gc);
fab262f5 1648 spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1649 clk_disable(bank->clk);
d3e51161 1650
d3e51161
HS		 1651 return 0;
1652}
1653
68bda47c
DA		 1654static void rockchip_irq_suspend(struct irq_data *d)
1655{
1656 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1657 struct rockchip_pin_bank *bank = gc->private;
1658
07a06ae9 1659 clk_enable(bank->clk);
5ae0c7ad
DA		 1660 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1661 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 1662 clk_disable(bank->clk);
68bda47c
DA		 1663}
1664
1665static void rockchip_irq_resume(struct irq_data *d)
1666{
1667 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1668 struct rockchip_pin_bank *bank = gc->private;
1669
07a06ae9 1670 clk_enable(bank->clk);
5ae0c7ad 1671 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 1672 clk_disable(bank->clk);
1673}
1674
1675static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1676{
1677 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1678 struct rockchip_pin_bank *bank = gc->private;
1679
1680 clk_enable(bank->clk);
1681 irq_gc_mask_clr_bit(d);
1682}
1683
1684void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1685{
1686 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1687 struct rockchip_pin_bank *bank = gc->private;
1688
1689 irq_gc_mask_set_bit(d);
1690 clk_disable(bank->clk);
f2dd028c
DA		 1691}
1692
d3e51161
HS		 1693static int rockchip_interrupts_register(struct platform_device *pdev,
1694 struct rockchip_pinctrl *info)
1695{
1696 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1697 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1698 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1699 struct irq_chip_generic *gc;
1700 int ret;
07a06ae9 1701 int i, j;
d3e51161
HS		 1702
1703 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1704 if (!bank->valid) {
1705 dev_warn(&pdev->dev, "bank %s is not valid\n",
1706 bank->name);
1707 continue;
1708 }
1709
07a06ae9
LH		 1710 ret = clk_enable(bank->clk);
1711 if (ret) {
1712 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1713 bank->name);
1714 continue;
1715 }
1716
d3e51161
HS		 1717 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1718 &irq_generic_chip_ops, NULL);
1719 if (!bank->domain) {
1720 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1721 bank->name);
07a06ae9 1722 clk_disable(bank->clk);
d3e51161
HS		 1723 continue;
1724 }
1725
1726 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1727 "rockchip_gpio_irq", handle_level_irq,
1728 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1729 if (ret) {
1730 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1731 bank->name);
1732 irq_domain_remove(bank->domain);
07a06ae9 1733 clk_disable(bank->clk);
d3e51161
HS		 1734 continue;
1735 }
1736
5ae0c7ad
DA		 1737 /*
1738 * Linux assumes that all interrupts start out disabled/masked.
1739 * Our driver only uses the concept of masked and always keeps
1740 * things enabled, so for us that's all masked and all enabled.
1741 */
1742 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1743 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1744
d3e51161
HS		 1745 gc = irq_get_domain_generic_chip(bank->domain, 0);
1746 gc->reg_base = bank->reg_base;
1747 gc->private = bank;
f2dd028c 1748 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 1749 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1750 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
07a06ae9
LH		 1751 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
1752 gc->chip_types[0].chip.irq_unmask =
1753 rockchip_irq_gc_mask_clr_bit;
d3e51161 1754 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 1755 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1756 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 1757 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 1758 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 1759
03051bc2
TG		 1760 irq_set_chained_handler_and_data(bank->irq,
1761 rockchip_irq_demux, bank);
07a06ae9
LH		 1762
1763 /* map the gpio irqs here, when the clock is still running */
1764 for (j = 0 ; j < 32 ; j++)
1765 irq_create_mapping(bank->domain, j);
1766
1767 clk_disable(bank->clk);
d3e51161
HS		 1768 }
1769
1770 return 0;
1771}
1772
1773static int rockchip_gpiolib_register(struct platform_device *pdev,
1774 struct rockchip_pinctrl *info)
1775{
1776 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1777 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1778 struct gpio_chip *gc;
1779 int ret;
1780 int i;
1781
1782 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1783 if (!bank->valid) {
1784 dev_warn(&pdev->dev, "bank %s is not valid\n",
1785 bank->name);
1786 continue;
1787 }
1788
1789 bank->gpio_chip = rockchip_gpiolib_chip;
1790
1791 gc = &bank->gpio_chip;
1792 gc->base = bank->pin_base;
1793 gc->ngpio = bank->nr_pins;
1794 gc->dev = &pdev->dev;
1795 gc->of_node = bank->of_node;
1796 gc->label = bank->name;
1797
1798 ret = gpiochip_add(gc);
1799 if (ret) {
1800 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1801 gc->label, ret);
1802 goto fail;
1803 }
1804 }
1805
1806 rockchip_interrupts_register(pdev, info);
1807
1808 return 0;
1809
1810fail:
1811 for (--i, --bank; i >= 0; --i, --bank) {
1812 if (!bank->valid)
1813 continue;
b4e7c55d 1814 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 1815 }
1816 return ret;
1817}
1818
1819static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1820 struct rockchip_pinctrl *info)
1821{
1822 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1823 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 1824 int i;
1825
b4e7c55d 1826 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 1827 if (!bank->valid)
1828 continue;
b4e7c55d 1829 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 1830 }
1831
b4e7c55d 1832 return 0;
d3e51161
HS		 1833}
1834
1835static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 1836 struct rockchip_pinctrl *info)
d3e51161
HS		 1837{
1838 struct resource res;
751a99ab 1839 void __iomem *base;
d3e51161
HS		 1840
1841 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 1842 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 1843 return -ENOENT;
1844 }
1845
622f3237 1846 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 1847 if (IS_ERR(bank->reg_base))
1848 return PTR_ERR(bank->reg_base);
1849
6ca5274d
HS		 1850 /*
1851 * special case, where parts of the pull setting-registers are
1852 * part of the PMU register space
1853 */
1854 if (of_device_is_compatible(bank->of_node,
1855 "rockchip,rk3188-gpio-bank0")) {
a658efaa 1856 struct device_node *node;
bfc7a42a 1857
a658efaa
HS		 1858 node = of_parse_phandle(bank->of_node->parent,
1859 "rockchip,pmu", 0);
1860 if (!node) {
1861 if (of_address_to_resource(bank->of_node, 1, &res)) {
1862 dev_err(info->dev, "cannot find IO resource for bank\n");
1863 return -ENOENT;
1864 }
1865
1866 base = devm_ioremap_resource(info->dev, &res);
1867 if (IS_ERR(base))
1868 return PTR_ERR(base);
1869 rockchip_regmap_config.max_register =
1870 resource_size(&res) - 4;
1871 rockchip_regmap_config.name =
1872 "rockchip,rk3188-gpio-bank0-pull";
1873 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1874 base,
1875 &rockchip_regmap_config);
6ca5274d 1876 }
6ca5274d 1877 }
65fca613 1878
d3e51161
HS		 1879 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1880
1881 bank->clk = of_clk_get(bank->of_node, 0);
1882 if (IS_ERR(bank->clk))
1883 return PTR_ERR(bank->clk);
1884
07a06ae9 1885 return clk_prepare(bank->clk);
d3e51161
HS		 1886}
1887
1888static const struct of_device_id rockchip_pinctrl_dt_match[];
1889
1890/* retrieve the soc specific data */
1891static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1892 struct rockchip_pinctrl *d,
1893 struct platform_device *pdev)
1894{
1895 const struct of_device_id *match;
1896 struct device_node *node = pdev->dev.of_node;
1897 struct device_node *np;
1898 struct rockchip_pin_ctrl *ctrl;
1899 struct rockchip_pin_bank *bank;
95ec8ae4 1900 int grf_offs, pmu_offs, i, j;
d3e51161
HS		 1901
1902 match = of_match_node(rockchip_pinctrl_dt_match, node);
1903 ctrl = (struct rockchip_pin_ctrl *)match->data;
1904
1905 for_each_child_of_node(node, np) {
1906 if (!of_find_property(np, "gpio-controller", NULL))
1907 continue;
1908
1909 bank = ctrl->pin_banks;
1910 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1911 if (!strcmp(bank->name, np->name)) {
1912 bank->of_node = np;
1913
622f3237 1914 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 1915 bank->valid = true;
1916
1917 break;
1918 }
1919 }
1920 }
1921
95ec8ae4
HS		 1922 grf_offs = ctrl->grf_mux_offset;
1923 pmu_offs = ctrl->pmu_mux_offset;
d3e51161
HS		 1924 bank = ctrl->pin_banks;
1925 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 1926 int bank_pins = 0;
1927
d3e51161
HS		 1928 spin_lock_init(&bank->slock);
1929 bank->drvdata = d;
1930 bank->pin_base = ctrl->nr_pins;
1931 ctrl->nr_pins += bank->nr_pins;
6bc0d121
HS		 1932
1933 /* calculate iomux offsets */
1934 for (j = 0; j < 4; j++) {
1935 struct rockchip_iomux *iom = &bank->iomux[j];
03716e1d 1936 int inc;
6bc0d121
HS		 1937
1938 if (bank_pins >= bank->nr_pins)
1939 break;
1940
1941 /* preset offset value, set new start value */
1942 if (iom->offset >= 0) {
95ec8ae4
HS		 1943 if (iom->type & IOMUX_SOURCE_PMU)
1944 pmu_offs = iom->offset;
1945 else
1946 grf_offs = iom->offset;
6bc0d121 1947 } else { /* set current offset */
95ec8ae4
HS		 1948 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
1949 pmu_offs : grf_offs;
6bc0d121
HS		 1950 }
1951
1952 dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n",
1953 i, j, iom->offset);
1954
1955 /*
1956 * Increase offset according to iomux width.
03716e1d 1957 * 4bit iomux'es are spread over two registers.
6bc0d121 1958 */
03716e1d 1959 inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4;
95ec8ae4
HS		 1960 if (iom->type & IOMUX_SOURCE_PMU)
1961 pmu_offs += inc;
1962 else
1963 grf_offs += inc;
6bc0d121
HS		 1964
1965 bank_pins += 8;
1966 }
d3e51161
HS		 1967 }
1968
1969 return ctrl;
1970}
1971
8dca9331
CZ		 1972#define RK3288_GRF_GPIO6C_IOMUX 0x64
1973#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
1974
1975static u32 rk3288_grf_gpio6c_iomux;
1976
9198f509
CZ		 1977static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
1978{
1979 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 1980 int ret = pinctrl_force_sleep(info->pctl_dev);
1981
1982 if (ret)
1983 return ret;
1984
1985 /*
1986 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
1987 * the setting here, and restore it at resume.
1988 */
1989 if (info->ctrl->type == RK3288) {
1990 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
1991 &rk3288_grf_gpio6c_iomux);
1992 if (ret) {
1993 pinctrl_force_default(info->pctl_dev);
1994 return ret;
1995 }
1996 }
9198f509 1997
8dca9331 1998 return 0;
9198f509
CZ		 1999}
2000
2001static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2002{
2003 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2004 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2005 rk3288_grf_gpio6c_iomux |
2006 GPIO6C6_SEL_WRITE_ENABLE);
2007
2008 if (ret)
2009 return ret;
9198f509
CZ		 2010
2011 return pinctrl_force_default(info->pctl_dev);
2012}
2013
2014static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2015 rockchip_pinctrl_resume);
2016
d3e51161
HS		 2017static int rockchip_pinctrl_probe(struct platform_device *pdev)
2018{
2019 struct rockchip_pinctrl *info;
2020 struct device *dev = &pdev->dev;
2021 struct rockchip_pin_ctrl *ctrl;
14dee867 2022 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 2023 struct resource *res;
751a99ab 2024 void __iomem *base;
d3e51161
HS		 2025 int ret;
2026
2027 if (!dev->of_node) {
2028 dev_err(dev, "device tree node not found\n");
2029 return -ENODEV;
2030 }
2031
2032 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2033 if (!info)
2034 return -ENOMEM;
2035
622f3237
HS		 2036 info->dev = dev;
2037
d3e51161
HS		 2038 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2039 if (!ctrl) {
2040 dev_err(dev, "driver data not available\n");
2041 return -EINVAL;
2042 }
2043 info->ctrl = ctrl;
d3e51161 2044
1e747e59
HS		 2045 node = of_parse_phandle(np, "rockchip,grf", 0);
2046 if (node) {
2047 info->regmap_base = syscon_node_to_regmap(node);
2048 if (IS_ERR(info->regmap_base))
2049 return PTR_ERR(info->regmap_base);
2050 } else {
2051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 2052 base = devm_ioremap_resource(&pdev->dev, res);
2053 if (IS_ERR(base))
2054 return PTR_ERR(base);
2055
2056 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 2057 rockchip_regmap_config.name = "rockchip,pinctrl";
2058 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2059 &rockchip_regmap_config);
2060
2061 /* to check for the old dt-bindings */
2062 info->reg_size = resource_size(res);
2063
2064 /* Honor the old binding, with pull registers as 2nd resource */
2065 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2066 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2067 base = devm_ioremap_resource(&pdev->dev, res);
2068 if (IS_ERR(base))
2069 return PTR_ERR(base);
2070
2071 rockchip_regmap_config.max_register =
2072 resource_size(res) - 4;
2073 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2074 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2075 base,
2076 &rockchip_regmap_config);
2077 }
6ca5274d
HS		 2078 }
2079
14dee867
HS		 2080 /* try to find the optional reference to the pmu syscon */
2081 node = of_parse_phandle(np, "rockchip,pmu", 0);
2082 if (node) {
2083 info->regmap_pmu = syscon_node_to_regmap(node);
2084 if (IS_ERR(info->regmap_pmu))
2085 return PTR_ERR(info->regmap_pmu);
2086 }
2087
d3e51161
HS		 2088 ret = rockchip_gpiolib_register(pdev, info);
2089 if (ret)
2090 return ret;
2091
2092 ret = rockchip_pinctrl_register(pdev, info);
2093 if (ret) {
2094 rockchip_gpiolib_unregister(pdev, info);
2095 return ret;
2096 }
2097
2098 platform_set_drvdata(pdev, info);
2099
2100 return 0;
2101}
2102
2103static struct rockchip_pin_bank rk2928_pin_banks[] = {
2104 PIN_BANK(0, 32, "gpio0"),
2105 PIN_BANK(1, 32, "gpio1"),
2106 PIN_BANK(2, 32, "gpio2"),
2107 PIN_BANK(3, 32, "gpio3"),
2108};
2109
2110static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2111 .pin_banks = rk2928_pin_banks,
2112 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2113 .label = "RK2928-GPIO",
a282926d 2114 .type = RK2928,
95ec8ae4 2115 .grf_mux_offset = 0xa8,
a282926d 2116 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2117};
2118
c5ce7670
XZ		 2119static struct rockchip_pin_bank rk3036_pin_banks[] = {
2120 PIN_BANK(0, 32, "gpio0"),
2121 PIN_BANK(1, 32, "gpio1"),
2122 PIN_BANK(2, 32, "gpio2"),
2123};
2124
2125static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2126 .pin_banks = rk3036_pin_banks,
2127 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2128 .label = "RK3036-GPIO",
2129 .type = RK2928,
2130 .grf_mux_offset = 0xa8,
2131 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2132};
2133
d3e51161
HS		 2134static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2135 PIN_BANK(0, 32, "gpio0"),
2136 PIN_BANK(1, 32, "gpio1"),
2137 PIN_BANK(2, 32, "gpio2"),
2138 PIN_BANK(3, 32, "gpio3"),
2139 PIN_BANK(4, 32, "gpio4"),
2140 PIN_BANK(6, 16, "gpio6"),
2141};
2142
2143static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2144 .pin_banks = rk3066a_pin_banks,
2145 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2146 .label = "RK3066a-GPIO",
a282926d 2147 .type = RK2928,
95ec8ae4 2148 .grf_mux_offset = 0xa8,
a282926d 2149 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 2150};
2151
2152static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2153 PIN_BANK(0, 32, "gpio0"),
2154 PIN_BANK(1, 32, "gpio1"),
2155 PIN_BANK(2, 32, "gpio2"),
2156 PIN_BANK(3, 32, "gpio3"),
2157};
2158
2159static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2160 .pin_banks = rk3066b_pin_banks,
2161 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2162 .label = "RK3066b-GPIO",
a282926d 2163 .type = RK3066B,
95ec8ae4 2164 .grf_mux_offset = 0x60,
d3e51161
HS		 2165};
2166
2167static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 2168 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 2169 PIN_BANK(1, 32, "gpio1"),
2170 PIN_BANK(2, 32, "gpio2"),
2171 PIN_BANK(3, 32, "gpio3"),
2172};
2173
2174static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2175 .pin_banks = rk3188_pin_banks,
2176 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2177 .label = "RK3188-GPIO",
a282926d 2178 .type = RK3188,
95ec8ae4 2179 .grf_mux_offset = 0x60,
6ca5274d 2180 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 2181};
2182
fea0fe60
JC		 2183static struct rockchip_pin_bank rk3228_pin_banks[] = {
2184 PIN_BANK(0, 32, "gpio0"),
2185 PIN_BANK(1, 32, "gpio1"),
2186 PIN_BANK(2, 32, "gpio2"),
2187 PIN_BANK(3, 32, "gpio3"),
2188};
2189
2190static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2191 .pin_banks = rk3228_pin_banks,
2192 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2193 .label = "RK3228-GPIO",
2194 .type = RK3288,
2195 .grf_mux_offset = 0x0,
2196 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2197 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2198};
2199
304f077d
HS		 2200static struct rockchip_pin_bank rk3288_pin_banks[] = {
2201 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2202 IOMUX_SOURCE_PMU,
2203 IOMUX_SOURCE_PMU,
2204 IOMUX_UNROUTED
2205 ),
2206 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2207 IOMUX_UNROUTED,
2208 IOMUX_UNROUTED,
2209 0
2210 ),
2211 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2212 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2213 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2214 IOMUX_WIDTH_4BIT,
2215 0,
2216 0
2217 ),
2218 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2219 0,
2220 0,
2221 IOMUX_UNROUTED
2222 ),
2223 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2224 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2225 0,
2226 IOMUX_WIDTH_4BIT,
2227 IOMUX_UNROUTED
2228 ),
2229 PIN_BANK(8, 16, "gpio8"),
2230};
2231
2232static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2233 .pin_banks = rk3288_pin_banks,
2234 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2235 .label = "RK3288-GPIO",
66d750e1 2236 .type = RK3288,
304f077d
HS		 2237 .grf_mux_offset = 0x0,
2238 .pmu_mux_offset = 0x84,
2239 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 2240 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 2241};
2242
daecdc66
HS		 2243static struct rockchip_pin_bank rk3368_pin_banks[] = {
2244 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2245 IOMUX_SOURCE_PMU,
2246 IOMUX_SOURCE_PMU,
2247 IOMUX_SOURCE_PMU
2248 ),
2249 PIN_BANK(1, 32, "gpio1"),
2250 PIN_BANK(2, 32, "gpio2"),
2251 PIN_BANK(3, 32, "gpio3"),
2252};
2253
2254static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2255 .pin_banks = rk3368_pin_banks,
2256 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2257 .label = "RK3368-GPIO",
2258 .type = RK3368,
2259 .grf_mux_offset = 0x0,
2260 .pmu_mux_offset = 0x0,
2261 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2262 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2263};
2264
2265
d3e51161
HS		 2266static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2267 { .compatible = "rockchip,rk2928-pinctrl",
2268 .data = (void *)&rk2928_pin_ctrl },
c5ce7670
XZ		 2269 { .compatible = "rockchip,rk3036-pinctrl",
2270 .data = (void *)&rk3036_pin_ctrl },
d3e51161
HS		 2271 { .compatible = "rockchip,rk3066a-pinctrl",
2272 .data = (void *)&rk3066a_pin_ctrl },
2273 { .compatible = "rockchip,rk3066b-pinctrl",
2274 .data = (void *)&rk3066b_pin_ctrl },
2275 { .compatible = "rockchip,rk3188-pinctrl",
2276 .data = (void *)&rk3188_pin_ctrl },
fea0fe60
JC		 2277 { .compatible = "rockchip,rk3228-pinctrl",
2278 .data = (void *)&rk3228_pin_ctrl },
304f077d
HS		 2279 { .compatible = "rockchip,rk3288-pinctrl",
2280 .data = (void *)&rk3288_pin_ctrl },
daecdc66
HS		 2281 { .compatible = "rockchip,rk3368-pinctrl",
2282 .data = (void *)&rk3368_pin_ctrl },
d3e51161
HS		 2283 {},
2284};
2285MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
2286
2287static struct platform_driver rockchip_pinctrl_driver = {
2288 .probe = rockchip_pinctrl_probe,
2289 .driver = {
2290 .name = "rockchip-pinctrl",
9198f509 2291 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 2292 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 2293 },
2294};
2295
2296static int __init rockchip_pinctrl_drv_register(void)
2297{
2298 return platform_driver_register(&rockchip_pinctrl_driver);
2299}
2300postcore_initcall(rockchip_pinctrl_drv_register);
2301
2302MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
2303MODULE_DESCRIPTION("Rockchip pinctrl driver");
2304MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.229888 seconds and 5 git commands to generate.