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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
39 | #include <linux/clk-provider.h> | |
40 | #include <dt-bindings/pinctrl/rockchip.h> | |
41 | ||
42 | #include "core.h" | |
43 | #include "pinconf.h" | |
44 | ||
45 | /* GPIO control registers */ | |
46 | #define GPIO_SWPORT_DR 0x00 | |
47 | #define GPIO_SWPORT_DDR 0x04 | |
48 | #define GPIO_INTEN 0x30 | |
49 | #define GPIO_INTMASK 0x34 | |
50 | #define GPIO_INTTYPE_LEVEL 0x38 | |
51 | #define GPIO_INT_POLARITY 0x3c | |
52 | #define GPIO_INT_STATUS 0x40 | |
53 | #define GPIO_INT_RAWSTATUS 0x44 | |
54 | #define GPIO_DEBOUNCE 0x48 | |
55 | #define GPIO_PORTS_EOI 0x4c | |
56 | #define GPIO_EXT_PORT 0x50 | |
57 | #define GPIO_LS_SYNC 0x60 | |
58 | ||
59 | /** | |
60 | * @reg_base: register base of the gpio bank | |
61 | * @clk: clock of the gpio bank | |
62 | * @irq: interrupt of the gpio bank | |
63 | * @pin_base: first pin number | |
64 | * @nr_pins: number of pins in this bank | |
65 | * @name: name of the bank | |
66 | * @bank_num: number of the bank, to account for holes | |
67 | * @valid: are all necessary informations present | |
68 | * @of_node: dt node of this bank | |
69 | * @drvdata: common pinctrl basedata | |
70 | * @domain: irqdomain of the gpio bank | |
71 | * @gpio_chip: gpiolib chip | |
72 | * @grange: gpio range | |
73 | * @slock: spinlock for the gpio bank | |
74 | */ | |
75 | struct rockchip_pin_bank { | |
76 | void __iomem *reg_base; | |
77 | struct clk *clk; | |
78 | int irq; | |
79 | u32 pin_base; | |
80 | u8 nr_pins; | |
81 | char *name; | |
82 | u8 bank_num; | |
83 | bool valid; | |
84 | struct device_node *of_node; | |
85 | struct rockchip_pinctrl *drvdata; | |
86 | struct irq_domain *domain; | |
87 | struct gpio_chip gpio_chip; | |
88 | struct pinctrl_gpio_range grange; | |
89 | spinlock_t slock; | |
90 | ||
91 | }; | |
92 | ||
93 | #define PIN_BANK(id, pins, label) \ | |
94 | { \ | |
95 | .bank_num = id, \ | |
96 | .nr_pins = pins, \ | |
97 | .name = label, \ | |
98 | } | |
99 | ||
100 | /** | |
101 | * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but | |
102 | * instead decide this automatically based on the pad-type. | |
103 | */ | |
104 | struct rockchip_pin_ctrl { | |
105 | struct rockchip_pin_bank *pin_banks; | |
106 | u32 nr_banks; | |
107 | u32 nr_pins; | |
108 | char *label; | |
109 | int mux_offset; | |
110 | int pull_offset; | |
111 | bool pull_auto; | |
112 | int pull_bank_stride; | |
113 | }; | |
114 | ||
115 | struct rockchip_pin_config { | |
116 | unsigned int func; | |
117 | unsigned long *configs; | |
118 | unsigned int nconfigs; | |
119 | }; | |
120 | ||
121 | /** | |
122 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
123 | * @name: name of the pin group, used to lookup the group. | |
124 | * @pins: the pins included in this group. | |
125 | * @npins: number of pins included in this group. | |
126 | * @func: the mux function number to be programmed when selected. | |
127 | * @configs: the config values to be set for each pin | |
128 | * @nconfigs: number of configs for each pin | |
129 | */ | |
130 | struct rockchip_pin_group { | |
131 | const char *name; | |
132 | unsigned int npins; | |
133 | unsigned int *pins; | |
134 | struct rockchip_pin_config *data; | |
135 | }; | |
136 | ||
137 | /** | |
138 | * struct rockchip_pmx_func: represent a pin function. | |
139 | * @name: name of the pin function, used to lookup the function. | |
140 | * @groups: one or more names of pin groups that provide this function. | |
141 | * @num_groups: number of groups included in @groups. | |
142 | */ | |
143 | struct rockchip_pmx_func { | |
144 | const char *name; | |
145 | const char **groups; | |
146 | u8 ngroups; | |
147 | }; | |
148 | ||
149 | struct rockchip_pinctrl { | |
150 | void __iomem *reg_base; | |
151 | struct device *dev; | |
152 | struct rockchip_pin_ctrl *ctrl; | |
153 | struct pinctrl_desc pctl; | |
154 | struct pinctrl_dev *pctl_dev; | |
155 | struct rockchip_pin_group *groups; | |
156 | unsigned int ngroups; | |
157 | struct rockchip_pmx_func *functions; | |
158 | unsigned int nfunctions; | |
159 | }; | |
160 | ||
161 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) | |
162 | { | |
163 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
164 | } | |
165 | ||
166 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
167 | const struct rockchip_pinctrl *info, | |
168 | const char *name) | |
169 | { | |
170 | const struct rockchip_pin_group *grp = NULL; | |
171 | int i; | |
172 | ||
173 | for (i = 0; i < info->ngroups; i++) { | |
174 | if (strcmp(info->groups[i].name, name)) | |
175 | continue; | |
176 | ||
177 | grp = &info->groups[i]; | |
178 | break; | |
179 | } | |
180 | ||
181 | return grp; | |
182 | } | |
183 | ||
184 | /* | |
185 | * given a pin number that is local to a pin controller, find out the pin bank | |
186 | * and the register base of the pin bank. | |
187 | */ | |
188 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
189 | unsigned pin) | |
190 | { | |
191 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
192 | ||
193 | while ((pin >= b->pin_base) && | |
194 | ((b->pin_base + b->nr_pins - 1) < pin)) | |
195 | b++; | |
196 | ||
197 | return b; | |
198 | } | |
199 | ||
200 | static struct rockchip_pin_bank *bank_num_to_bank( | |
201 | struct rockchip_pinctrl *info, | |
202 | unsigned num) | |
203 | { | |
204 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
205 | int i; | |
206 | ||
207 | for (i = 0; i < info->ctrl->nr_banks; i++) { | |
208 | if (b->bank_num == num) | |
209 | break; | |
210 | ||
211 | b++; | |
212 | } | |
213 | ||
214 | if (b->bank_num != num) | |
215 | return ERR_PTR(-EINVAL); | |
216 | ||
217 | return b; | |
218 | } | |
219 | ||
220 | /* | |
221 | * Pinctrl_ops handling | |
222 | */ | |
223 | ||
224 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
225 | { | |
226 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
227 | ||
228 | return info->ngroups; | |
229 | } | |
230 | ||
231 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
232 | unsigned selector) | |
233 | { | |
234 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
235 | ||
236 | return info->groups[selector].name; | |
237 | } | |
238 | ||
239 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
240 | unsigned selector, const unsigned **pins, | |
241 | unsigned *npins) | |
242 | { | |
243 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
244 | ||
245 | if (selector >= info->ngroups) | |
246 | return -EINVAL; | |
247 | ||
248 | *pins = info->groups[selector].pins; | |
249 | *npins = info->groups[selector].npins; | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
255 | struct device_node *np, | |
256 | struct pinctrl_map **map, unsigned *num_maps) | |
257 | { | |
258 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
259 | const struct rockchip_pin_group *grp; | |
260 | struct pinctrl_map *new_map; | |
261 | struct device_node *parent; | |
262 | int map_num = 1; | |
263 | int i; | |
264 | ||
265 | /* | |
266 | * first find the group of this node and check if we need to create | |
267 | * config maps for pins | |
268 | */ | |
269 | grp = pinctrl_name_to_group(info, np->name); | |
270 | if (!grp) { | |
271 | dev_err(info->dev, "unable to find group for node %s\n", | |
272 | np->name); | |
273 | return -EINVAL; | |
274 | } | |
275 | ||
276 | map_num += grp->npins; | |
277 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
278 | GFP_KERNEL); | |
279 | if (!new_map) | |
280 | return -ENOMEM; | |
281 | ||
282 | *map = new_map; | |
283 | *num_maps = map_num; | |
284 | ||
285 | /* create mux map */ | |
286 | parent = of_get_parent(np); | |
287 | if (!parent) { | |
288 | devm_kfree(pctldev->dev, new_map); | |
289 | return -EINVAL; | |
290 | } | |
291 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
292 | new_map[0].data.mux.function = parent->name; | |
293 | new_map[0].data.mux.group = np->name; | |
294 | of_node_put(parent); | |
295 | ||
296 | /* create config map */ | |
297 | new_map++; | |
298 | for (i = 0; i < grp->npins; i++) { | |
299 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
300 | new_map[i].data.configs.group_or_pin = | |
301 | pin_get_name(pctldev, grp->pins[i]); | |
302 | new_map[i].data.configs.configs = grp->data[i].configs; | |
303 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
304 | } | |
305 | ||
306 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
307 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
313 | struct pinctrl_map *map, unsigned num_maps) | |
314 | { | |
315 | } | |
316 | ||
317 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
318 | .get_groups_count = rockchip_get_groups_count, | |
319 | .get_group_name = rockchip_get_group_name, | |
320 | .get_group_pins = rockchip_get_group_pins, | |
321 | .dt_node_to_map = rockchip_dt_node_to_map, | |
322 | .dt_free_map = rockchip_dt_free_map, | |
323 | }; | |
324 | ||
325 | /* | |
326 | * Hardware access | |
327 | */ | |
328 | ||
329 | /* | |
330 | * Set a new mux function for a pin. | |
331 | * | |
332 | * The register is divided into the upper and lower 16 bit. When changing | |
333 | * a value, the previous register value is not read and changed. Instead | |
334 | * it seems the changed bits are marked in the upper 16 bit, while the | |
335 | * changed value gets set in the same offset in the lower 16 bit. | |
336 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
337 | * parts. | |
338 | * @bank: pin bank to change | |
339 | * @pin: pin to change | |
340 | * @mux: new mux function to set | |
341 | */ | |
342 | static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) | |
343 | { | |
344 | struct rockchip_pinctrl *info = bank->drvdata; | |
345 | void __iomem *reg = info->reg_base + info->ctrl->mux_offset; | |
346 | unsigned long flags; | |
347 | u8 bit; | |
348 | u32 data; | |
349 | ||
350 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", | |
351 | bank->bank_num, pin, mux); | |
352 | ||
353 | /* get basic quadrupel of mux registers and the correct reg inside */ | |
354 | reg += bank->bank_num * 0x10; | |
355 | reg += (pin / 8) * 4; | |
356 | bit = (pin % 8) * 2; | |
357 | ||
358 | spin_lock_irqsave(&bank->slock, flags); | |
359 | ||
360 | data = (3 << (bit + 16)); | |
361 | data |= (mux & 3) << bit; | |
362 | writel(data, reg); | |
363 | ||
364 | spin_unlock_irqrestore(&bank->slock, flags); | |
365 | } | |
366 | ||
367 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) | |
368 | { | |
369 | struct rockchip_pinctrl *info = bank->drvdata; | |
370 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
371 | void __iomem *reg; | |
372 | u8 bit; | |
373 | ||
374 | /* rk3066b does support any pulls */ | |
375 | if (!ctrl->pull_offset) | |
376 | return PIN_CONFIG_BIAS_DISABLE; | |
377 | ||
378 | reg = info->reg_base + ctrl->pull_offset; | |
379 | ||
380 | if (ctrl->pull_auto) { | |
381 | reg += bank->bank_num * ctrl->pull_bank_stride; | |
382 | reg += (pin_num / 16) * 4; | |
383 | bit = pin_num % 16; | |
384 | ||
385 | return !(readl_relaxed(reg) & BIT(bit)) | |
386 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT | |
387 | : PIN_CONFIG_BIAS_DISABLE; | |
388 | } else { | |
389 | dev_err(info->dev, "pull support for rk31xx not implemented\n"); | |
390 | return -EIO; | |
391 | } | |
392 | } | |
393 | ||
394 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
395 | int pin_num, int pull) | |
396 | { | |
397 | struct rockchip_pinctrl *info = bank->drvdata; | |
398 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
399 | void __iomem *reg; | |
400 | unsigned long flags; | |
401 | u8 bit; | |
402 | u32 data; | |
403 | ||
404 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
405 | bank->bank_num, pin_num, pull); | |
406 | ||
407 | /* rk3066b does support any pulls */ | |
408 | if (!ctrl->pull_offset) | |
409 | return pull ? -EINVAL : 0; | |
410 | ||
411 | reg = info->reg_base + ctrl->pull_offset; | |
412 | ||
413 | if (ctrl->pull_auto) { | |
414 | if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT && | |
415 | pull != PIN_CONFIG_BIAS_DISABLE) { | |
416 | dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n"); | |
417 | return -EINVAL; | |
418 | } | |
419 | ||
420 | reg += bank->bank_num * ctrl->pull_bank_stride; | |
421 | reg += (pin_num / 16) * 4; | |
422 | bit = pin_num % 16; | |
423 | ||
424 | spin_lock_irqsave(&bank->slock, flags); | |
425 | ||
426 | data = BIT(bit + 16); | |
427 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
428 | data |= BIT(bit); | |
429 | writel(data, reg); | |
430 | ||
431 | spin_unlock_irqrestore(&bank->slock, flags); | |
432 | } else { | |
433 | if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) { | |
434 | dev_err(info->dev, "pull direction (up/down) needs to be specified\n"); | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | dev_err(info->dev, "pull support for rk31xx not implemented\n"); | |
439 | return -EIO; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | /* | |
446 | * Pinmux_ops handling | |
447 | */ | |
448 | ||
449 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
450 | { | |
451 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
452 | ||
453 | return info->nfunctions; | |
454 | } | |
455 | ||
456 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
457 | unsigned selector) | |
458 | { | |
459 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
460 | ||
461 | return info->functions[selector].name; | |
462 | } | |
463 | ||
464 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
465 | unsigned selector, const char * const **groups, | |
466 | unsigned * const num_groups) | |
467 | { | |
468 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
469 | ||
470 | *groups = info->functions[selector].groups; | |
471 | *num_groups = info->functions[selector].ngroups; | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
477 | unsigned group) | |
478 | { | |
479 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
480 | const unsigned int *pins = info->groups[group].pins; | |
481 | const struct rockchip_pin_config *data = info->groups[group].data; | |
482 | struct rockchip_pin_bank *bank; | |
483 | int cnt; | |
484 | ||
485 | dev_dbg(info->dev, "enable function %s group %s\n", | |
486 | info->functions[selector].name, info->groups[group].name); | |
487 | ||
488 | /* | |
489 | * for each pin in the pin group selected, program the correspoding pin | |
490 | * pin function number in the config register. | |
491 | */ | |
492 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
493 | bank = pin_to_bank(info, pins[cnt]); | |
494 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, | |
495 | data[cnt].func); | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | static void rockchip_pmx_disable(struct pinctrl_dev *pctldev, | |
502 | unsigned selector, unsigned group) | |
503 | { | |
504 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
505 | const unsigned int *pins = info->groups[group].pins; | |
506 | struct rockchip_pin_bank *bank; | |
507 | int cnt; | |
508 | ||
509 | dev_dbg(info->dev, "disable function %s group %s\n", | |
510 | info->functions[selector].name, info->groups[group].name); | |
511 | ||
512 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
513 | bank = pin_to_bank(info, pins[cnt]); | |
514 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
515 | } | |
516 | } | |
517 | ||
518 | /* | |
519 | * The calls to gpio_direction_output() and gpio_direction_input() | |
520 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
521 | * function called from the gpiolib interface). | |
522 | */ | |
523 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
524 | struct pinctrl_gpio_range *range, | |
525 | unsigned offset, bool input) | |
526 | { | |
527 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
528 | struct rockchip_pin_bank *bank; | |
529 | struct gpio_chip *chip; | |
530 | int pin; | |
531 | u32 data; | |
532 | ||
533 | chip = range->gc; | |
534 | bank = gc_to_pin_bank(chip); | |
535 | pin = offset - chip->base; | |
536 | ||
537 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
538 | offset, range->name, pin, input ? "input" : "output"); | |
539 | ||
540 | rockchip_set_mux(bank, pin, RK_FUNC_GPIO); | |
541 | ||
542 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
543 | /* set bit to 1 for output, 0 for input */ | |
544 | if (!input) | |
545 | data |= BIT(pin); | |
546 | else | |
547 | data &= ~BIT(pin); | |
548 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
553 | static const struct pinmux_ops rockchip_pmx_ops = { | |
554 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
555 | .get_function_name = rockchip_pmx_get_func_name, | |
556 | .get_function_groups = rockchip_pmx_get_groups, | |
557 | .enable = rockchip_pmx_enable, | |
558 | .disable = rockchip_pmx_disable, | |
559 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, | |
560 | }; | |
561 | ||
562 | /* | |
563 | * Pinconf_ops handling | |
564 | */ | |
565 | ||
566 | /* set the pin config settings for a specified pin */ | |
567 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
568 | unsigned long config) | |
569 | { | |
570 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
571 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
572 | enum pin_config_param param = pinconf_to_config_param(config); | |
573 | ||
574 | switch (param) { | |
575 | case PIN_CONFIG_BIAS_DISABLE: | |
576 | case PIN_CONFIG_BIAS_PULL_UP: | |
577 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
578 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
579 | return rockchip_set_pull(bank, pin - bank->pin_base, param); | |
580 | break; | |
581 | default: | |
582 | return -ENOTSUPP; | |
583 | break; | |
584 | } | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | /* get the pin config settings for a specified pin */ | |
590 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
591 | unsigned long *config) | |
592 | { | |
593 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
594 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
595 | enum pin_config_param param = pinconf_to_config_param(*config); | |
596 | unsigned int pull; | |
597 | ||
598 | switch (param) { | |
599 | case PIN_CONFIG_BIAS_DISABLE: | |
600 | case PIN_CONFIG_BIAS_PULL_UP: | |
601 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
602 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
603 | pull = rockchip_get_pull(bank, pin - bank->pin_base); | |
604 | ||
605 | if (pull != param) | |
606 | return -EINVAL; | |
607 | ||
608 | *config = 0; | |
609 | break; | |
610 | default: | |
611 | return -ENOTSUPP; | |
612 | break; | |
613 | } | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
619 | .pin_config_get = rockchip_pinconf_get, | |
620 | .pin_config_set = rockchip_pinconf_set, | |
621 | }; | |
622 | ||
623 | static const char *gpio_compat = "rockchip,gpio-bank"; | |
624 | ||
625 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
626 | struct device_node *np) | |
627 | { | |
628 | struct device_node *child; | |
629 | ||
630 | for_each_child_of_node(np, child) { | |
631 | if (of_device_is_compatible(child, gpio_compat)) | |
632 | continue; | |
633 | ||
634 | info->nfunctions++; | |
635 | info->ngroups += of_get_child_count(child); | |
636 | } | |
637 | } | |
638 | ||
639 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
640 | struct rockchip_pin_group *grp, | |
641 | struct rockchip_pinctrl *info, | |
642 | u32 index) | |
643 | { | |
644 | struct rockchip_pin_bank *bank; | |
645 | int size; | |
646 | const __be32 *list; | |
647 | int num; | |
648 | int i, j; | |
649 | int ret; | |
650 | ||
651 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
652 | ||
653 | /* Initialise group */ | |
654 | grp->name = np->name; | |
655 | ||
656 | /* | |
657 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
658 | * do sanity check and calculate pins number | |
659 | */ | |
660 | list = of_get_property(np, "rockchip,pins", &size); | |
661 | /* we do not check return since it's safe node passed down */ | |
662 | size /= sizeof(*list); | |
663 | if (!size || size % 4) { | |
664 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
665 | return -EINVAL; | |
666 | } | |
667 | ||
668 | grp->npins = size / 4; | |
669 | ||
670 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
671 | GFP_KERNEL); | |
672 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
673 | sizeof(struct rockchip_pin_config), | |
674 | GFP_KERNEL); | |
675 | if (!grp->pins || !grp->data) | |
676 | return -ENOMEM; | |
677 | ||
678 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
679 | const __be32 *phandle; | |
680 | struct device_node *np_config; | |
681 | ||
682 | num = be32_to_cpu(*list++); | |
683 | bank = bank_num_to_bank(info, num); | |
684 | if (IS_ERR(bank)) | |
685 | return PTR_ERR(bank); | |
686 | ||
687 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
688 | grp->data[j].func = be32_to_cpu(*list++); | |
689 | ||
690 | phandle = list++; | |
691 | if (!phandle) | |
692 | return -EINVAL; | |
693 | ||
694 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
695 | ret = pinconf_generic_parse_dt_config(np_config, | |
696 | &grp->data[j].configs, &grp->data[j].nconfigs); | |
697 | if (ret) | |
698 | return ret; | |
699 | } | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
704 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
705 | struct rockchip_pinctrl *info, | |
706 | u32 index) | |
707 | { | |
708 | struct device_node *child; | |
709 | struct rockchip_pmx_func *func; | |
710 | struct rockchip_pin_group *grp; | |
711 | int ret; | |
712 | static u32 grp_index; | |
713 | u32 i = 0; | |
714 | ||
715 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
716 | ||
717 | func = &info->functions[index]; | |
718 | ||
719 | /* Initialise function */ | |
720 | func->name = np->name; | |
721 | func->ngroups = of_get_child_count(np); | |
722 | if (func->ngroups <= 0) | |
723 | return 0; | |
724 | ||
725 | func->groups = devm_kzalloc(info->dev, | |
726 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
727 | if (!func->groups) | |
728 | return -ENOMEM; | |
729 | ||
730 | for_each_child_of_node(np, child) { | |
731 | func->groups[i] = child->name; | |
732 | grp = &info->groups[grp_index++]; | |
733 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
734 | if (ret) | |
735 | return ret; | |
736 | } | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
741 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
742 | struct rockchip_pinctrl *info) | |
743 | { | |
744 | struct device *dev = &pdev->dev; | |
745 | struct device_node *np = dev->of_node; | |
746 | struct device_node *child; | |
747 | int ret; | |
748 | int i; | |
749 | ||
750 | rockchip_pinctrl_child_count(info, np); | |
751 | ||
752 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
753 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
754 | ||
755 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
756 | sizeof(struct rockchip_pmx_func), | |
757 | GFP_KERNEL); | |
758 | if (!info->functions) { | |
759 | dev_err(dev, "failed to allocate memory for function list\n"); | |
760 | return -EINVAL; | |
761 | } | |
762 | ||
763 | info->groups = devm_kzalloc(dev, info->ngroups * | |
764 | sizeof(struct rockchip_pin_group), | |
765 | GFP_KERNEL); | |
766 | if (!info->groups) { | |
767 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
768 | return -EINVAL; | |
769 | } | |
770 | ||
771 | i = 0; | |
772 | ||
773 | for_each_child_of_node(np, child) { | |
774 | if (of_device_is_compatible(child, gpio_compat)) | |
775 | continue; | |
776 | ret = rockchip_pinctrl_parse_functions(child, info, i++); | |
777 | if (ret) { | |
778 | dev_err(&pdev->dev, "failed to parse function\n"); | |
779 | return ret; | |
780 | } | |
781 | } | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
786 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
787 | struct rockchip_pinctrl *info) | |
788 | { | |
789 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
790 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
791 | struct rockchip_pin_bank *pin_bank; | |
792 | int pin, bank, ret; | |
793 | int k; | |
794 | ||
795 | ctrldesc->name = "rockchip-pinctrl"; | |
796 | ctrldesc->owner = THIS_MODULE; | |
797 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
798 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
799 | ctrldesc->confops = &rockchip_pinconf_ops; | |
800 | ||
801 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
802 | info->ctrl->nr_pins, GFP_KERNEL); | |
803 | if (!pindesc) { | |
804 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
805 | return -ENOMEM; | |
806 | } | |
807 | ctrldesc->pins = pindesc; | |
808 | ctrldesc->npins = info->ctrl->nr_pins; | |
809 | ||
810 | pdesc = pindesc; | |
811 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
812 | pin_bank = &info->ctrl->pin_banks[bank]; | |
813 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
814 | pdesc->number = k; | |
815 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
816 | pin_bank->name, pin); | |
817 | pdesc++; | |
818 | } | |
819 | } | |
820 | ||
821 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); | |
822 | if (!info->pctl_dev) { | |
823 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); | |
824 | return -EINVAL; | |
825 | } | |
826 | ||
827 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
828 | pin_bank = &info->ctrl->pin_banks[bank]; | |
829 | pin_bank->grange.name = pin_bank->name; | |
830 | pin_bank->grange.id = bank; | |
831 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
832 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
833 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
834 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
835 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
836 | } | |
837 | ||
838 | ret = rockchip_pinctrl_parse_dt(pdev, info); | |
839 | if (ret) { | |
840 | pinctrl_unregister(info->pctl_dev); | |
841 | return ret; | |
842 | } | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | /* | |
848 | * GPIO handling | |
849 | */ | |
850 | ||
851 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) | |
852 | { | |
853 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
854 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
855 | unsigned long flags; | |
856 | u32 data; | |
857 | ||
858 | spin_lock_irqsave(&bank->slock, flags); | |
859 | ||
860 | data = readl(reg); | |
861 | data &= ~BIT(offset); | |
862 | if (value) | |
863 | data |= BIT(offset); | |
864 | writel(data, reg); | |
865 | ||
866 | spin_unlock_irqrestore(&bank->slock, flags); | |
867 | } | |
868 | ||
869 | /* | |
870 | * Returns the level of the pin for input direction and setting of the DR | |
871 | * register for output gpios. | |
872 | */ | |
873 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
874 | { | |
875 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
876 | u32 data; | |
877 | ||
878 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
879 | data >>= offset; | |
880 | data &= 1; | |
881 | return data; | |
882 | } | |
883 | ||
884 | /* | |
885 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
886 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
887 | * interface. | |
888 | */ | |
889 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
890 | { | |
891 | return pinctrl_gpio_direction_input(gc->base + offset); | |
892 | } | |
893 | ||
894 | /* | |
895 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
896 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
897 | * interface. | |
898 | */ | |
899 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
900 | unsigned offset, int value) | |
901 | { | |
902 | rockchip_gpio_set(gc, offset, value); | |
903 | return pinctrl_gpio_direction_output(gc->base + offset); | |
904 | } | |
905 | ||
906 | /* | |
907 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
908 | * and a virtual IRQ, if not already present. | |
909 | */ | |
910 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
911 | { | |
912 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
913 | unsigned int virq; | |
914 | ||
915 | if (!bank->domain) | |
916 | return -ENXIO; | |
917 | ||
918 | virq = irq_create_mapping(bank->domain, offset); | |
919 | ||
920 | return (virq) ? : -ENXIO; | |
921 | } | |
922 | ||
923 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
924 | .set = rockchip_gpio_set, | |
925 | .get = rockchip_gpio_get, | |
926 | .direction_input = rockchip_gpio_direction_input, | |
927 | .direction_output = rockchip_gpio_direction_output, | |
928 | .to_irq = rockchip_gpio_to_irq, | |
929 | .owner = THIS_MODULE, | |
930 | }; | |
931 | ||
932 | /* | |
933 | * Interrupt handling | |
934 | */ | |
935 | ||
936 | static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) | |
937 | { | |
938 | struct irq_chip *chip = irq_get_chip(irq); | |
939 | struct rockchip_pin_bank *bank = irq_get_handler_data(irq); | |
940 | u32 pend; | |
941 | ||
942 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
943 | ||
944 | chained_irq_enter(chip, desc); | |
945 | ||
946 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
947 | ||
948 | while (pend) { | |
949 | unsigned int virq; | |
950 | ||
951 | irq = __ffs(pend); | |
952 | pend &= ~BIT(irq); | |
953 | virq = irq_linear_revmap(bank->domain, irq); | |
954 | ||
955 | if (!virq) { | |
956 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
957 | continue; | |
958 | } | |
959 | ||
960 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
961 | ||
962 | generic_handle_irq(virq); | |
963 | } | |
964 | ||
965 | chained_irq_exit(chip, desc); | |
966 | } | |
967 | ||
968 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
969 | { | |
970 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
971 | struct rockchip_pin_bank *bank = gc->private; | |
972 | u32 mask = BIT(d->hwirq); | |
973 | u32 polarity; | |
974 | u32 level; | |
975 | u32 data; | |
976 | ||
977 | if (type & IRQ_TYPE_EDGE_BOTH) | |
978 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
979 | else | |
980 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
981 | ||
982 | irq_gc_lock(gc); | |
983 | ||
984 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
985 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
986 | ||
987 | switch (type) { | |
988 | case IRQ_TYPE_EDGE_RISING: | |
989 | level |= mask; | |
990 | polarity |= mask; | |
991 | break; | |
992 | case IRQ_TYPE_EDGE_FALLING: | |
993 | level |= mask; | |
994 | polarity &= ~mask; | |
995 | break; | |
996 | case IRQ_TYPE_LEVEL_HIGH: | |
997 | level &= ~mask; | |
998 | polarity |= mask; | |
999 | break; | |
1000 | case IRQ_TYPE_LEVEL_LOW: | |
1001 | level &= ~mask; | |
1002 | polarity &= ~mask; | |
1003 | break; | |
1004 | default: | |
1005 | return -EINVAL; | |
1006 | } | |
1007 | ||
1008 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1009 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1010 | ||
1011 | irq_gc_unlock(gc); | |
1012 | ||
1013 | /* make sure the pin is configured as gpio input */ | |
1014 | rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); | |
1015 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
1016 | data &= ~mask; | |
1017 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static int rockchip_interrupts_register(struct platform_device *pdev, | |
1023 | struct rockchip_pinctrl *info) | |
1024 | { | |
1025 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1026 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1027 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1028 | struct irq_chip_generic *gc; | |
1029 | int ret; | |
1030 | int i; | |
1031 | ||
1032 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1033 | if (!bank->valid) { | |
1034 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1035 | bank->name); | |
1036 | continue; | |
1037 | } | |
1038 | ||
1039 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
1040 | &irq_generic_chip_ops, NULL); | |
1041 | if (!bank->domain) { | |
1042 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1043 | bank->name); | |
1044 | continue; | |
1045 | } | |
1046 | ||
1047 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1048 | "rockchip_gpio_irq", handle_level_irq, | |
1049 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1050 | if (ret) { | |
1051 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1052 | bank->name); | |
1053 | irq_domain_remove(bank->domain); | |
1054 | continue; | |
1055 | } | |
1056 | ||
1057 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
1058 | gc->reg_base = bank->reg_base; | |
1059 | gc->private = bank; | |
1060 | gc->chip_types[0].regs.mask = GPIO_INTEN; | |
1061 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; | |
1062 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
1063 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
1064 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
1065 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
1066 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
1067 | ||
1068 | irq_set_handler_data(bank->irq, bank); | |
1069 | irq_set_chained_handler(bank->irq, rockchip_irq_demux); | |
1070 | } | |
1071 | ||
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1076 | struct rockchip_pinctrl *info) | |
1077 | { | |
1078 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1079 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1080 | struct gpio_chip *gc; | |
1081 | int ret; | |
1082 | int i; | |
1083 | ||
1084 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1085 | if (!bank->valid) { | |
1086 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1087 | bank->name); | |
1088 | continue; | |
1089 | } | |
1090 | ||
1091 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1092 | ||
1093 | gc = &bank->gpio_chip; | |
1094 | gc->base = bank->pin_base; | |
1095 | gc->ngpio = bank->nr_pins; | |
1096 | gc->dev = &pdev->dev; | |
1097 | gc->of_node = bank->of_node; | |
1098 | gc->label = bank->name; | |
1099 | ||
1100 | ret = gpiochip_add(gc); | |
1101 | if (ret) { | |
1102 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1103 | gc->label, ret); | |
1104 | goto fail; | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | rockchip_interrupts_register(pdev, info); | |
1109 | ||
1110 | return 0; | |
1111 | ||
1112 | fail: | |
1113 | for (--i, --bank; i >= 0; --i, --bank) { | |
1114 | if (!bank->valid) | |
1115 | continue; | |
1116 | ||
1117 | if (gpiochip_remove(&bank->gpio_chip)) | |
1118 | dev_err(&pdev->dev, "gpio chip %s remove failed\n", | |
1119 | bank->gpio_chip.label); | |
1120 | } | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1125 | struct rockchip_pinctrl *info) | |
1126 | { | |
1127 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1128 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1129 | int ret = 0; | |
1130 | int i; | |
1131 | ||
1132 | for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { | |
1133 | if (!bank->valid) | |
1134 | continue; | |
1135 | ||
1136 | ret = gpiochip_remove(&bank->gpio_chip); | |
1137 | } | |
1138 | ||
1139 | if (ret) | |
1140 | dev_err(&pdev->dev, "gpio chip remove failed\n"); | |
1141 | ||
1142 | return ret; | |
1143 | } | |
1144 | ||
1145 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
1146 | struct device *dev) | |
1147 | { | |
1148 | struct resource res; | |
1149 | ||
1150 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
1151 | dev_err(dev, "cannot find IO resource for bank\n"); | |
1152 | return -ENOENT; | |
1153 | } | |
1154 | ||
1155 | bank->reg_base = devm_ioremap_resource(dev, &res); | |
1156 | if (IS_ERR(bank->reg_base)) | |
1157 | return PTR_ERR(bank->reg_base); | |
1158 | ||
1159 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); | |
1160 | ||
1161 | bank->clk = of_clk_get(bank->of_node, 0); | |
1162 | if (IS_ERR(bank->clk)) | |
1163 | return PTR_ERR(bank->clk); | |
1164 | ||
1165 | return clk_prepare_enable(bank->clk); | |
1166 | } | |
1167 | ||
1168 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1169 | ||
1170 | /* retrieve the soc specific data */ | |
1171 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1172 | struct rockchip_pinctrl *d, | |
1173 | struct platform_device *pdev) | |
1174 | { | |
1175 | const struct of_device_id *match; | |
1176 | struct device_node *node = pdev->dev.of_node; | |
1177 | struct device_node *np; | |
1178 | struct rockchip_pin_ctrl *ctrl; | |
1179 | struct rockchip_pin_bank *bank; | |
1180 | int i; | |
1181 | ||
1182 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1183 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1184 | ||
1185 | for_each_child_of_node(node, np) { | |
1186 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1187 | continue; | |
1188 | ||
1189 | bank = ctrl->pin_banks; | |
1190 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1191 | if (!strcmp(bank->name, np->name)) { | |
1192 | bank->of_node = np; | |
1193 | ||
1194 | if (!rockchip_get_bank_data(bank, &pdev->dev)) | |
1195 | bank->valid = true; | |
1196 | ||
1197 | break; | |
1198 | } | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | bank = ctrl->pin_banks; | |
1203 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1204 | spin_lock_init(&bank->slock); | |
1205 | bank->drvdata = d; | |
1206 | bank->pin_base = ctrl->nr_pins; | |
1207 | ctrl->nr_pins += bank->nr_pins; | |
1208 | } | |
1209 | ||
1210 | return ctrl; | |
1211 | } | |
1212 | ||
1213 | static int rockchip_pinctrl_probe(struct platform_device *pdev) | |
1214 | { | |
1215 | struct rockchip_pinctrl *info; | |
1216 | struct device *dev = &pdev->dev; | |
1217 | struct rockchip_pin_ctrl *ctrl; | |
1218 | struct resource *res; | |
1219 | int ret; | |
1220 | ||
1221 | if (!dev->of_node) { | |
1222 | dev_err(dev, "device tree node not found\n"); | |
1223 | return -ENODEV; | |
1224 | } | |
1225 | ||
1226 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1227 | if (!info) | |
1228 | return -ENOMEM; | |
1229 | ||
1230 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); | |
1231 | if (!ctrl) { | |
1232 | dev_err(dev, "driver data not available\n"); | |
1233 | return -EINVAL; | |
1234 | } | |
1235 | info->ctrl = ctrl; | |
1236 | info->dev = dev; | |
1237 | ||
1238 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1239 | if (!res) { | |
1240 | dev_err(dev, "cannot find IO resource\n"); | |
1241 | return -ENOENT; | |
1242 | } | |
1243 | ||
1244 | info->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
1245 | if (IS_ERR(info->reg_base)) | |
1246 | return PTR_ERR(info->reg_base); | |
1247 | ||
1248 | ret = rockchip_gpiolib_register(pdev, info); | |
1249 | if (ret) | |
1250 | return ret; | |
1251 | ||
1252 | ret = rockchip_pinctrl_register(pdev, info); | |
1253 | if (ret) { | |
1254 | rockchip_gpiolib_unregister(pdev, info); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | platform_set_drvdata(pdev, info); | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
1264 | PIN_BANK(0, 32, "gpio0"), | |
1265 | PIN_BANK(1, 32, "gpio1"), | |
1266 | PIN_BANK(2, 32, "gpio2"), | |
1267 | PIN_BANK(3, 32, "gpio3"), | |
1268 | }; | |
1269 | ||
1270 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
1271 | .pin_banks = rk2928_pin_banks, | |
1272 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
1273 | .label = "RK2928-GPIO", | |
1274 | .mux_offset = 0xa8, | |
1275 | .pull_offset = 0x118, | |
1276 | .pull_auto = 1, | |
1277 | .pull_bank_stride = 8, | |
1278 | }; | |
1279 | ||
1280 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { | |
1281 | PIN_BANK(0, 32, "gpio0"), | |
1282 | PIN_BANK(1, 32, "gpio1"), | |
1283 | PIN_BANK(2, 32, "gpio2"), | |
1284 | PIN_BANK(3, 32, "gpio3"), | |
1285 | PIN_BANK(4, 32, "gpio4"), | |
1286 | PIN_BANK(6, 16, "gpio6"), | |
1287 | }; | |
1288 | ||
1289 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
1290 | .pin_banks = rk3066a_pin_banks, | |
1291 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
1292 | .label = "RK3066a-GPIO", | |
1293 | .mux_offset = 0xa8, | |
1294 | .pull_offset = 0x118, | |
1295 | .pull_auto = 1, | |
1296 | .pull_bank_stride = 8, | |
1297 | }; | |
1298 | ||
1299 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
1300 | PIN_BANK(0, 32, "gpio0"), | |
1301 | PIN_BANK(1, 32, "gpio1"), | |
1302 | PIN_BANK(2, 32, "gpio2"), | |
1303 | PIN_BANK(3, 32, "gpio3"), | |
1304 | }; | |
1305 | ||
1306 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
1307 | .pin_banks = rk3066b_pin_banks, | |
1308 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
1309 | .label = "RK3066b-GPIO", | |
1310 | .mux_offset = 0x60, | |
1311 | .pull_offset = -EINVAL, | |
1312 | }; | |
1313 | ||
1314 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
1315 | PIN_BANK(0, 32, "gpio0"), | |
1316 | PIN_BANK(1, 32, "gpio1"), | |
1317 | PIN_BANK(2, 32, "gpio2"), | |
1318 | PIN_BANK(3, 32, "gpio3"), | |
1319 | }; | |
1320 | ||
1321 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
1322 | .pin_banks = rk3188_pin_banks, | |
1323 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
1324 | .label = "RK3188-GPIO", | |
1325 | .mux_offset = 0x68, | |
1326 | .pull_offset = 0x164, | |
1327 | .pull_bank_stride = 16, | |
1328 | }; | |
1329 | ||
1330 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { | |
1331 | { .compatible = "rockchip,rk2928-pinctrl", | |
1332 | .data = (void *)&rk2928_pin_ctrl }, | |
1333 | { .compatible = "rockchip,rk3066a-pinctrl", | |
1334 | .data = (void *)&rk3066a_pin_ctrl }, | |
1335 | { .compatible = "rockchip,rk3066b-pinctrl", | |
1336 | .data = (void *)&rk3066b_pin_ctrl }, | |
1337 | { .compatible = "rockchip,rk3188-pinctrl", | |
1338 | .data = (void *)&rk3188_pin_ctrl }, | |
1339 | {}, | |
1340 | }; | |
1341 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
1342 | ||
1343 | static struct platform_driver rockchip_pinctrl_driver = { | |
1344 | .probe = rockchip_pinctrl_probe, | |
1345 | .driver = { | |
1346 | .name = "rockchip-pinctrl", | |
1347 | .owner = THIS_MODULE, | |
1348 | .of_match_table = of_match_ptr(rockchip_pinctrl_dt_match), | |
1349 | }, | |
1350 | }; | |
1351 | ||
1352 | static int __init rockchip_pinctrl_drv_register(void) | |
1353 | { | |
1354 | return platform_driver_register(&rockchip_pinctrl_driver); | |
1355 | } | |
1356 | postcore_initcall(rockchip_pinctrl_drv_register); | |
1357 | ||
1358 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
1359 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
1360 | MODULE_LICENSE("GPL v2"); |