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Merge remote-tracking branch 'pinctrl/for-next'
[deliverable/linux.git] / drivers / pinctrl / pinctrl-st.c
CommitLineData
701016c0
SK		 1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Authors:
4 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/of.h>
727b0f71 17#include <linux/of_irq.h>
701016c0
SK		 18#include <linux/of_gpio.h>
19#include <linux/of_address.h>
20#include <linux/regmap.h>
21#include <linux/mfd/syscon.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/platform_device.h>
26#include "core.h"
27
28/* PIO Block registers */
29/* PIO output */
30#define REG_PIO_POUT 0x00
31/* Set bits of POUT */
32#define REG_PIO_SET_POUT 0x04
33/* Clear bits of POUT */
34#define REG_PIO_CLR_POUT 0x08
35/* PIO input */
36#define REG_PIO_PIN 0x10
37/* PIO configuration */
38#define REG_PIO_PC(n) (0x20 + (n) * 0x10)
39/* Set bits of PC[2:0] */
40#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
41/* Clear bits of PC[2:0] */
42#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
43/* PIO input comparison */
44#define REG_PIO_PCOMP 0x50
45/* Set bits of PCOMP */
46#define REG_PIO_SET_PCOMP 0x54
47/* Clear bits of PCOMP */
48#define REG_PIO_CLR_PCOMP 0x58
49/* PIO input comparison mask */
50#define REG_PIO_PMASK 0x60
51/* Set bits of PMASK */
52#define REG_PIO_SET_PMASK 0x64
53/* Clear bits of PMASK */
54#define REG_PIO_CLR_PMASK 0x68
55
56#define ST_GPIO_DIRECTION_BIDIR 0x1
57#define ST_GPIO_DIRECTION_OUT 0x2
58#define ST_GPIO_DIRECTION_IN 0x4
59
60/**
61 * Packed style retime configuration.
62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
64 */
65#define RT_P_CFGS_PER_BANK 2
66#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
67#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
68#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
69#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
70#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
71#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
72#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
73
74/**
75 * Dedicated style retime Configuration register
76 * each register is dedicated per pin.
77 */
78#define RT_D_CFGS_PER_BANK 8
79#define RT_D_CFG_CLK_SHIFT 0
80#define RT_D_CFG_CLK_MASK (0x3 << 0)
81#define RT_D_CFG_CLKNOTDATA_SHIFT 2
82#define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
83#define RT_D_CFG_DELAY_SHIFT 3
84#define RT_D_CFG_DELAY_MASK (0xf << 3)
85#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
86#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
87#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
88#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
89#define RT_D_CFG_INVERTCLK_SHIFT 9
90#define RT_D_CFG_INVERTCLK_MASK BIT(9)
91#define RT_D_CFG_RETIME_SHIFT 10
92#define RT_D_CFG_RETIME_MASK BIT(10)
93
94/*
95 * Pinconf is represented in an opaque unsigned long variable.
96 * Below is the bit allocation details for each possible configuration.
97 * All the bit fields can be encapsulated into four variables
98 * (direction, retime-type, retime-clk, retime-delay)
99 *
100 * +----------------+
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
103 *[27] | oe | |
104 * +----------------+ v
105 *[26] | pu | [Direction ]
106 * +----------------+ ^
107 *[25] | od | |
108 * +----------------+-------------
109 *[24] | reserved-2 |
110 * +----------------+-------------
111 *[23] | retime | |
112 * +----------------+ |
113 *[22] | retime-invclk | |
114 * +----------------+ v
115 *[21] |retime-clknotdat| [Retime-type ]
116 * +----------------+ ^
117 *[20] | retime-de | |
118 * +----------------+-------------
119 *[19:18]| retime-clk |------>[Retime-Clk ]
120 * +----------------+
121 *[17:16]| reserved-1 |
122 * +----------------+
123 *[15..0]| retime-delay |------>[Retime Delay]
124 * +----------------+
125 */
126
127#define ST_PINCONF_UNPACK(conf, param)\
128 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
129 & ST_PINCONF_ ##param ##_MASK)
130
131#define ST_PINCONF_PACK(conf, val, param) (conf |=\
132 ((val & ST_PINCONF_ ##param ##_MASK) << \
133 ST_PINCONF_ ##param ##_SHIFT))
134
135/* Output enable */
136#define ST_PINCONF_OE_MASK 0x1
137#define ST_PINCONF_OE_SHIFT 27
138#define ST_PINCONF_OE BIT(27)
139#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
140#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
141
142/* Pull Up */
143#define ST_PINCONF_PU_MASK 0x1
144#define ST_PINCONF_PU_SHIFT 26
145#define ST_PINCONF_PU BIT(26)
146#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
147#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
148
149/* Open Drain */
150#define ST_PINCONF_OD_MASK 0x1
151#define ST_PINCONF_OD_SHIFT 25
152#define ST_PINCONF_OD BIT(25)
153#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
154#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
155
156#define ST_PINCONF_RT_MASK 0x1
157#define ST_PINCONF_RT_SHIFT 23
158#define ST_PINCONF_RT BIT(23)
159#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
160#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
161
162#define ST_PINCONF_RT_INVERTCLK_MASK 0x1
163#define ST_PINCONF_RT_INVERTCLK_SHIFT 22
164#define ST_PINCONF_RT_INVERTCLK BIT(22)
165#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
166 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
167#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
168 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
169
170#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
171#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
172#define ST_PINCONF_RT_CLKNOTDATA BIT(21)
173#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
174 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
175#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
176 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
177
178#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
179#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
180#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
181#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
182 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
183#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
184 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
185
186#define ST_PINCONF_RT_CLK_MASK 0x3
187#define ST_PINCONF_RT_CLK_SHIFT 18
188#define ST_PINCONF_RT_CLK BIT(18)
189#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
190#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
191
192/* RETIME_DELAY in Pico Secs */
193#define ST_PINCONF_RT_DELAY_MASK 0xffff
194#define ST_PINCONF_RT_DELAY_SHIFT 0
195#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
196#define ST_PINCONF_PACK_RT_DELAY(conf, val) \
197 ST_PINCONF_PACK(conf, val, RT_DELAY)
198
199#define ST_GPIO_PINS_PER_BANK (8)
200#define OF_GPIO_ARGS_MIN (4)
201#define OF_RT_ARGS_MIN (2)
202
203#define gpio_range_to_bank(chip) \
204 container_of(chip, struct st_gpio_bank, range)
205
e2ed0e88
LJ		 206#define pc_to_bank(pc) \
207 container_of(pc, struct st_gpio_bank, pc)
208
701016c0
SK		 209enum st_retime_style {
210 st_retime_style_none,
211 st_retime_style_packed,
212 st_retime_style_dedicated,
213};
214
215struct st_retime_dedicated {
216 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
217};
218
219struct st_retime_packed {
220 struct regmap_field *clk1notclk0;
221 struct regmap_field *delay_0;
222 struct regmap_field *delay_1;
223 struct regmap_field *invertclk;
224 struct regmap_field *retime;
225 struct regmap_field *clknotdata;
226 struct regmap_field *double_edge;
227};
228
229struct st_pio_control {
230 u32 rt_pin_mask;
231 struct regmap_field *alt, *oe, *pu, *od;
232 /* retiming */
233 union {
234 struct st_retime_packed rt_p;
235 struct st_retime_dedicated rt_d;
236 } rt;
237};
238
239struct st_pctl_data {
a4bc1f57
MC		 240 const enum st_retime_style rt_style;
241 const unsigned int *input_delays;
242 const int ninput_delays;
243 const unsigned int *output_delays;
244 const int noutput_delays;
701016c0 245 /* register offset information */
a4bc1f57 246 const int alt, oe, pu, od, rt;
701016c0
SK		 247};
248
249struct st_pinconf {
250 int pin;
251 const char *name;
252 unsigned long config;
253 int altfunc;
254};
255
256struct st_pmx_func {
257 const char *name;
258 const char **groups;
259 unsigned ngroups;
260};
261
262struct st_pctl_group {
263 const char *name;
264 unsigned int *pins;
265 unsigned npins;
266 struct st_pinconf *pin_conf;
267};
268
155795b9
SK		 269/*
270 * Edge triggers are not supported at hardware level, it is supported by
271 * software by exploiting the level trigger support in hardware.
272 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
273 * of each gpio pin in a GPIO bank.
274 *
275 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
276 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
277 *
278 * bit allocation per pin is:
279 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
280 * --------------------------------------------------------
281 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
282 * --------------------------------------------------------
283 *
284 * A pin can have one of following the values in its edge configuration field.
285 *
286 * ------- ----------------------------
287 * [0-3] - Description
288 * ------- ----------------------------
289 * 0000 - No edge IRQ.
290 * 0001 - Falling edge IRQ.
291 * 0010 - Rising edge IRQ.
292 * 0011 - Rising and Falling edge IRQ.
293 * ------- ----------------------------
294 */
295
296#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
297#define ST_IRQ_EDGE_MASK 0xf
298#define ST_IRQ_EDGE_FALLING BIT(0)
299#define ST_IRQ_EDGE_RISING BIT(1)
300#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
301
302#define ST_IRQ_RISING_EDGE_CONF(pin) \
303 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
304
305#define ST_IRQ_FALLING_EDGE_CONF(pin) \
306 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
307
308#define ST_IRQ_BOTH_EDGE_CONF(pin) \
309 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
310
311#define ST_IRQ_EDGE_CONF(conf, pin) \
312 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
313
701016c0
SK		 314struct st_gpio_bank {
315 struct gpio_chip gpio_chip;
316 struct pinctrl_gpio_range range;
317 void __iomem *base;
318 struct st_pio_control pc;
155795b9
SK		 319 unsigned long irq_edge_conf;
320 spinlock_t lock;
701016c0
SK		 321};
322
323struct st_pinctrl {
324 struct device *dev;
325 struct pinctrl_dev *pctl;
326 struct st_gpio_bank *banks;
327 int nbanks;
328 struct st_pmx_func *functions;
329 int nfunctions;
330 struct st_pctl_group *groups;
331 int ngroups;
332 struct regmap *regmap;
333 const struct st_pctl_data *data;
727b0f71 334 void __iomem *irqmux_base;
701016c0
SK		 335};
336
337/* SOC specific data */
338/* STiH415 data */
a4bc1f57
MC		 339static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500};
340static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000};
701016c0
SK		 341
342#define STIH415_PCTRL_COMMON_DATA \
343 .rt_style = st_retime_style_packed, \
344 .input_delays = stih415_input_delays, \
3b02dad2 345 .ninput_delays = ARRAY_SIZE(stih415_input_delays), \
701016c0 346 .output_delays = stih415_output_delays, \
3b02dad2 347 .noutput_delays = ARRAY_SIZE(stih415_output_delays)
701016c0
SK		 348
349static const struct st_pctl_data stih415_sbc_data = {
350 STIH415_PCTRL_COMMON_DATA,
351 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16,
352};
353
354static const struct st_pctl_data stih415_front_data = {
355 STIH415_PCTRL_COMMON_DATA,
356 .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16,
357};
358
359static const struct st_pctl_data stih415_rear_data = {
360 STIH415_PCTRL_COMMON_DATA,
361 .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38,
362};
363
364static const struct st_pctl_data stih415_left_data = {
365 STIH415_PCTRL_COMMON_DATA,
366 .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6,
367};
368
369static const struct st_pctl_data stih415_right_data = {
370 STIH415_PCTRL_COMMON_DATA,
371 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11,
372};
373
374/* STiH416 data */
a4bc1f57
MC		 375static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250,
376 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
701016c0
SK		 377
378static const struct st_pctl_data stih416_data = {
379 .rt_style = st_retime_style_dedicated,
380 .input_delays = stih416_delays,
88430acf 381 .ninput_delays = ARRAY_SIZE(stih416_delays),
701016c0 382 .output_delays = stih416_delays,
88430acf 383 .noutput_delays = ARRAY_SIZE(stih416_delays),
701016c0
SK		 384 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
385};
386
7ce717db
GC		 387static const struct st_pctl_data stih407_flashdata = {
388 .rt_style = st_retime_style_none,
389 .input_delays = stih416_delays,
390 .ninput_delays = ARRAY_SIZE(stih416_delays),
391 .output_delays = stih416_delays,
392 .noutput_delays = ARRAY_SIZE(stih416_delays),
393 .alt = 0,
394 .oe = -1, /* Not Available */
395 .pu = -1, /* Not Available */
396 .od = 60,
397 .rt = 100,
398};
399
f89e68fc
LJ		 400static struct st_pio_control *st_get_pio_control(
401 struct pinctrl_dev *pctldev, int pin)
402{
403 struct pinctrl_gpio_range *range =
404 pinctrl_find_gpio_range_from_pin(pctldev, pin);
405 struct st_gpio_bank *bank = gpio_range_to_bank(range);
406
407 return &bank->pc;
408}
409
701016c0
SK		 410/* Low level functions.. */
411static inline int st_gpio_bank(int gpio)
412{
413 return gpio/ST_GPIO_PINS_PER_BANK;
414}
415
416static inline int st_gpio_pin(int gpio)
417{
418 return gpio%ST_GPIO_PINS_PER_BANK;
419}
420
421static void st_pinconf_set_config(struct st_pio_control *pc,
422 int pin, unsigned long config)
423{
424 struct regmap_field *output_enable = pc->oe;
425 struct regmap_field *pull_up = pc->pu;
426 struct regmap_field *open_drain = pc->od;
427 unsigned int oe_value, pu_value, od_value;
428 unsigned long mask = BIT(pin);
429
4e6a609f
GC		 430 if (output_enable) {
431 regmap_field_read(output_enable, &oe_value);
432 oe_value &= ~mask;
433 if (config & ST_PINCONF_OE)
434 oe_value |= mask;
435 regmap_field_write(output_enable, oe_value);
436 }
437
438 if (pull_up) {
439 regmap_field_read(pull_up, &pu_value);
440 pu_value &= ~mask;
441 if (config & ST_PINCONF_PU)
442 pu_value |= mask;
443 regmap_field_write(pull_up, pu_value);
444 }
445
446 if (open_drain) {
447 regmap_field_read(open_drain, &od_value);
448 od_value &= ~mask;
449 if (config & ST_PINCONF_OD)
450 od_value |= mask;
451 regmap_field_write(open_drain, od_value);
452 }
701016c0
SK		 453}
454
455static void st_pctl_set_function(struct st_pio_control *pc,
456 int pin_id, int function)
457{
458 struct regmap_field *alt = pc->alt;
459 unsigned int val;
460 int pin = st_gpio_pin(pin_id);
461 int offset = pin * 4;
462
4e6a609f
GC		 463 if (!alt)
464 return;
465
701016c0
SK		 466 regmap_field_read(alt, &val);
467 val &= ~(0xf << offset);
468 val |= function << offset;
469 regmap_field_write(alt, val);
470}
471
c2a4bf47
LJ		 472static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
473{
474 struct regmap_field *alt = pc->alt;
475 unsigned int val;
476 int offset = pin * 4;
477
478 if (!alt)
479 return 0;
480
481 regmap_field_read(alt, &val);
482
483 return (val >> offset) & 0xf;
484}
485
701016c0
SK		 486static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
487 const struct st_pctl_data *data, unsigned long config)
488{
a4bc1f57 489 const unsigned int *delay_times;
701016c0
SK		 490 int num_delay_times, i, closest_index = -1;
491 unsigned int closest_divergence = UINT_MAX;
492
493 if (ST_PINCONF_UNPACK_OE(config)) {
494 delay_times = data->output_delays;
495 num_delay_times = data->noutput_delays;
496 } else {
497 delay_times = data->input_delays;
498 num_delay_times = data->ninput_delays;
499 }
500
501 for (i = 0; i < num_delay_times; i++) {
502 unsigned int divergence = abs(delay - delay_times[i]);
503
504 if (divergence == 0)
505 return i;
506
507 if (divergence < closest_divergence) {
508 closest_divergence = divergence;
509 closest_index = i;
510 }
511 }
512
513 pr_warn("Attempt to set delay %d, closest available %d\n",
514 delay, delay_times[closest_index]);
515
516 return closest_index;
517}
518
519static unsigned long st_pinconf_bit_to_delay(unsigned int index,
520 const struct st_pctl_data *data, unsigned long output)
521{
a4bc1f57 522 const unsigned int *delay_times;
701016c0
SK		 523 int num_delay_times;
524
525 if (output) {
526 delay_times = data->output_delays;
527 num_delay_times = data->noutput_delays;
528 } else {
529 delay_times = data->input_delays;
530 num_delay_times = data->ninput_delays;
531 }
532
533 if (index < num_delay_times) {
534 return delay_times[index];
535 } else {
536 pr_warn("Delay not found in/out delay list\n");
537 return 0;
538 }
539}
540
541static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
542 int enable, int pin)
543{
544 unsigned int val = 0;
545
546 regmap_field_read(field, &val);
547 if (enable)
548 val |= BIT(pin);
549 else
550 val &= ~BIT(pin);
551 regmap_field_write(field, val);
552}
553
554static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
555 struct st_pio_control *pc, unsigned long config, int pin)
556{
557 const struct st_pctl_data *data = info->data;
558 struct st_retime_packed *rt_p = &pc->rt.rt_p;
559 unsigned int delay;
560
561 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
562 ST_PINCONF_UNPACK_RT_CLK(config), pin);
563
564 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
565 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
566
567 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
568 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
569
570 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
571 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
572
573 st_regmap_field_bit_set_clear_pin(rt_p->retime,
574 ST_PINCONF_UNPACK_RT(config), pin);
575
576 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
577 data, config);
578 /* 2 bit delay, lsb */
579 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
580 /* 2 bit delay, msb */
581 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
582
583}
584
585static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
586 struct st_pio_control *pc, unsigned long config, int pin)
587{
588 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
589 int clk = ST_PINCONF_UNPACK_RT_CLK(config);
590 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
591 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
592 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
593 int retime = ST_PINCONF_UNPACK_RT(config);
594
595 unsigned long delay = st_pinconf_delay_to_bit(
596 ST_PINCONF_UNPACK_RT_DELAY(config),
597 info->data, config);
598 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
599
600 unsigned long retime_config =
601 ((clk) << RT_D_CFG_CLK_SHIFT) |
602 ((delay) << RT_D_CFG_DELAY_SHIFT) |
603 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
604 ((retime) << RT_D_CFG_RETIME_SHIFT) |
605 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
606 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
607 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
608
609 regmap_field_write(rt_d->rt[pin], retime_config);
610}
611
612static void st_pinconf_get_direction(struct st_pio_control *pc,
613 int pin, unsigned long *config)
614{
615 unsigned int oe_value, pu_value, od_value;
616
4e6a609f
GC		 617 if (pc->oe) {
618 regmap_field_read(pc->oe, &oe_value);
619 if (oe_value & BIT(pin))
620 ST_PINCONF_PACK_OE(*config);
621 }
701016c0 622
4e6a609f
GC		 623 if (pc->pu) {
624 regmap_field_read(pc->pu, &pu_value);
625 if (pu_value & BIT(pin))
626 ST_PINCONF_PACK_PU(*config);
627 }
701016c0 628
4e6a609f
GC		 629 if (pc->od) {
630 regmap_field_read(pc->od, &od_value);
631 if (od_value & BIT(pin))
632 ST_PINCONF_PACK_OD(*config);
633 }
701016c0
SK		 634}
635
636static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
637 struct st_pio_control *pc, int pin, unsigned long *config)
638{
639 const struct st_pctl_data *data = info->data;
640 struct st_retime_packed *rt_p = &pc->rt.rt_p;
641 unsigned int delay_bits, delay, delay0, delay1, val;
642 int output = ST_PINCONF_UNPACK_OE(*config);
643
644 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
645 ST_PINCONF_PACK_RT(*config);
646
647 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
648 ST_PINCONF_PACK_RT_CLK(*config, 1);
649
650 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
651 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
652
653 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
654 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
655
656 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
657 ST_PINCONF_PACK_RT_INVERTCLK(*config);
658
659 regmap_field_read(rt_p->delay_0, &delay0);
660 regmap_field_read(rt_p->delay_1, &delay1);
661 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
662 (((delay0 & BIT(pin)) ? 1 : 0));
663 delay = st_pinconf_bit_to_delay(delay_bits, data, output);
664 ST_PINCONF_PACK_RT_DELAY(*config, delay);
665
666 return 0;
667}
668
669static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
670 struct st_pio_control *pc, int pin, unsigned long *config)
671{
672 unsigned int value;
673 unsigned long delay_bits, delay, rt_clk;
674 int output = ST_PINCONF_UNPACK_OE(*config);
675 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
676
677 regmap_field_read(rt_d->rt[pin], &value);
678
679 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
680 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
681
682 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
683 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
684 ST_PINCONF_PACK_RT_DELAY(*config, delay);
685
686 if (value & RT_D_CFG_CLKNOTDATA_MASK)
687 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
688
689 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
690 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
691
692 if (value & RT_D_CFG_INVERTCLK_MASK)
693 ST_PINCONF_PACK_RT_INVERTCLK(*config);
694
695 if (value & RT_D_CFG_RETIME_MASK)
696 ST_PINCONF_PACK_RT(*config);
697
698 return 0;
699}
700
701/* GPIO related functions */
702
703static inline void __st_gpio_set(struct st_gpio_bank *bank,
704 unsigned offset, int value)
705{
706 if (value)
707 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
708 else
709 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
710}
711
712static void st_gpio_direction(struct st_gpio_bank *bank,
713 unsigned int gpio, unsigned int direction)
714{
715 int offset = st_gpio_pin(gpio);
716 int i = 0;
717 /**
718 * There are three configuration registers (PIOn_PC0, PIOn_PC1
719 * and PIOn_PC2) for each port. These are used to configure the
720 * PIO port pins. Each pin can be configured as an input, output,
721 * bidirectional, or alternative function pin. Three bits, one bit
722 * from each of the three registers, configure the corresponding bit of
723 * the port. Valid bit settings is:
724 *
725 * PC2 PC1 PC0 Direction.
726 * 0 0 0 [Input Weak pull-up]
727 * 0 0 or 1 1 [Bidirection]
728 * 0 1 0 [Output]
729 * 1 0 0 [Input]
730 *
731 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
732 * individually.
733 */
734 for (i = 0; i <= 2; i++) {
735 if (direction & BIT(i))
736 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
737 else
738 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
739 }
740}
741
701016c0
SK		 742static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
743{
2e862a7b 744 struct st_gpio_bank *bank = gpiochip_get_data(chip);
701016c0
SK		 745
746 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
747}
748
749static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
750{
2e862a7b 751 struct st_gpio_bank *bank = gpiochip_get_data(chip);
701016c0
SK		 752 __st_gpio_set(bank, offset, value);
753}
754
755static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
756{
757 pinctrl_gpio_direction_input(chip->base + offset);
758
759 return 0;
760}
761
762static int st_gpio_direction_output(struct gpio_chip *chip,
763 unsigned offset, int value)
764{
2e862a7b 765 struct st_gpio_bank *bank = gpiochip_get_data(chip);
701016c0
SK		 766
767 __st_gpio_set(bank, offset, value);
768 pinctrl_gpio_direction_output(chip->base + offset);
769
770 return 0;
771}
772
1e702ec2
LJ		 773static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
774{
2e862a7b 775 struct st_gpio_bank *bank = gpiochip_get_data(chip);
1e702ec2
LJ		 776 struct st_pio_control pc = bank->pc;
777 unsigned long config;
778 unsigned int direction = 0;
779 unsigned int function;
780 unsigned int value;
781 int i = 0;
782
783 /* Alternate function direction is handled by Pinctrl */
784 function = st_pctl_get_pin_function(&pc, offset);
785 if (function) {
786 st_pinconf_get_direction(&pc, offset, &config);
787 return !ST_PINCONF_UNPACK_OE(config);
788 }
789
790 /*
791 * GPIO direction is handled differently
792 * - See st_gpio_direction() above for an explanation
793 */
794 for (i = 0; i <= 2; i++) {
795 value = readl(bank->base + REG_PIO_PC(i));
796 direction |= ((value >> offset) & 0x1) << i;
797 }
798
799 return (direction == ST_GPIO_DIRECTION_IN);
800}
801
701016c0
SK		 802/* Pinctrl Groups */
803static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
804{
805 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
806
807 return info->ngroups;
808}
809
810static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
811 unsigned selector)
812{
813 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
814
815 return info->groups[selector].name;
816}
817
818static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
819 unsigned selector, const unsigned **pins, unsigned *npins)
820{
821 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
822
823 if (selector >= info->ngroups)
824 return -EINVAL;
825
826 *pins = info->groups[selector].pins;
827 *npins = info->groups[selector].npins;
828
829 return 0;
830}
831
56411f3c 832static inline const struct st_pctl_group *st_pctl_find_group_by_name(
701016c0
SK		 833 const struct st_pinctrl *info, const char *name)
834{
835 int i;
836
837 for (i = 0; i < info->ngroups; i++) {
838 if (!strcmp(info->groups[i].name, name))
839 return &info->groups[i];
840 }
841
842 return NULL;
843}
844
845static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
846 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
847{
848 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
849 const struct st_pctl_group *grp;
850 struct pinctrl_map *new_map;
851 struct device_node *parent;
852 int map_num, i;
853
854 grp = st_pctl_find_group_by_name(info, np->name);
855 if (!grp) {
856 dev_err(info->dev, "unable to find group for node %s\n",
857 np->name);
858 return -EINVAL;
859 }
860
861 map_num = grp->npins + 1;
862 new_map = devm_kzalloc(pctldev->dev,
863 sizeof(*new_map) * map_num, GFP_KERNEL);
864 if (!new_map)
865 return -ENOMEM;
866
867 parent = of_get_parent(np);
868 if (!parent) {
869 devm_kfree(pctldev->dev, new_map);
870 return -EINVAL;
871 }
872
873 *map = new_map;
874 *num_maps = map_num;
875 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
876 new_map[0].data.mux.function = parent->name;
877 new_map[0].data.mux.group = np->name;
878 of_node_put(parent);
879
880 /* create config map per pin */
881 new_map++;
882 for (i = 0; i < grp->npins; i++) {
883 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
884 new_map[i].data.configs.group_or_pin =
885 pin_get_name(pctldev, grp->pins[i]);
886 new_map[i].data.configs.configs = &grp->pin_conf[i].config;
887 new_map[i].data.configs.num_configs = 1;
888 }
889 dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
890 (*map)->data.mux.function, grp->name, map_num);
891
892 return 0;
893}
894
895static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
896 struct pinctrl_map *map, unsigned num_maps)
897{
898}
899
900static struct pinctrl_ops st_pctlops = {
901 .get_groups_count = st_pctl_get_groups_count,
902 .get_group_pins = st_pctl_get_group_pins,
903 .get_group_name = st_pctl_get_group_name,
904 .dt_node_to_map = st_pctl_dt_node_to_map,
905 .dt_free_map = st_pctl_dt_free_map,
906};
907
908/* Pinmux */
909static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
910{
911 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
912
913 return info->nfunctions;
914}
915
ef75bfd5 916static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
701016c0
SK		 917 unsigned selector)
918{
919 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
920
921 return info->functions[selector].name;
922}
923
924static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
925 unsigned selector, const char * const **grps, unsigned * const ngrps)
926{
927 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
928 *grps = info->functions[selector].groups;
929 *ngrps = info->functions[selector].ngroups;
930
931 return 0;
932}
933
03e9f0ca
LW		 934static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
935 unsigned group)
701016c0
SK		 936{
937 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
938 struct st_pinconf *conf = info->groups[group].pin_conf;
939 struct st_pio_control *pc;
940 int i;
941
942 for (i = 0; i < info->groups[group].npins; i++) {
943 pc = st_get_pio_control(pctldev, conf[i].pin);
944 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
945 }
946
947 return 0;
948}
949
701016c0
SK		 950static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
951 struct pinctrl_gpio_range *range, unsigned gpio,
952 bool input)
953{
954 struct st_gpio_bank *bank = gpio_range_to_bank(range);
955 /*
956 * When a PIO bank is used in its primary function mode (altfunc = 0)
957 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
958 * for the primary PIO functions are driven by the related PIO block
959 */
960 st_pctl_set_function(&bank->pc, gpio, 0);
961 st_gpio_direction(bank, gpio, input ?
962 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
963
964 return 0;
965}
966
967static struct pinmux_ops st_pmxops = {
968 .get_functions_count = st_pmx_get_funcs_count,
969 .get_function_name = st_pmx_get_fname,
970 .get_function_groups = st_pmx_get_groups,
03e9f0ca 971 .set_mux = st_pmx_set_mux,
701016c0 972 .gpio_set_direction = st_pmx_set_gpio_direction,
8ba5905c 973 .strict = true,
701016c0
SK		 974};
975
976/* Pinconf */
977static void st_pinconf_get_retime(struct st_pinctrl *info,
978 struct st_pio_control *pc, int pin, unsigned long *config)
979{
980 if (info->data->rt_style == st_retime_style_packed)
981 st_pinconf_get_retime_packed(info, pc, pin, config);
982 else if (info->data->rt_style == st_retime_style_dedicated)
983 if ((BIT(pin) & pc->rt_pin_mask))
984 st_pinconf_get_retime_dedicated(info, pc,
985 pin, config);
986}
987
988static void st_pinconf_set_retime(struct st_pinctrl *info,
989 struct st_pio_control *pc, int pin, unsigned long config)
990{
991 if (info->data->rt_style == st_retime_style_packed)
992 st_pinconf_set_retime_packed(info, pc, config, pin);
993 else if (info->data->rt_style == st_retime_style_dedicated)
994 if ((BIT(pin) & pc->rt_pin_mask))
995 st_pinconf_set_retime_dedicated(info, pc,
996 config, pin);
997}
998
03b054e9
SY		 999static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
1000 unsigned long *configs, unsigned num_configs)
701016c0
SK		 1001{
1002 int pin = st_gpio_pin(pin_id);
1003 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1004 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
03b054e9 1005 int i;
701016c0 1006
03b054e9
SY		 1007 for (i = 0; i < num_configs; i++) {
1008 st_pinconf_set_config(pc, pin, configs[i]);
1009 st_pinconf_set_retime(info, pc, pin, configs[i]);
1010 } /* for each config */
701016c0
SK		 1011
1012 return 0;
1013}
1014
1015static int st_pinconf_get(struct pinctrl_dev *pctldev,
1016 unsigned pin_id, unsigned long *config)
1017{
1018 int pin = st_gpio_pin(pin_id);
1019 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1020 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
1021
1022 *config = 0;
1023 st_pinconf_get_direction(pc, pin, config);
1024 st_pinconf_get_retime(info, pc, pin, config);
1025
1026 return 0;
1027}
1028
1029static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1030 struct seq_file *s, unsigned pin_id)
1031{
e2ed0e88 1032 struct st_pio_control *pc;
701016c0 1033 unsigned long config;
a8381fac 1034 unsigned int function;
e2ed0e88 1035 int offset = st_gpio_pin(pin_id);
a8381fac 1036 char f[16];
701016c0 1037
96d16c30 1038 mutex_unlock(&pctldev->mutex);
e2ed0e88 1039 pc = st_get_pio_control(pctldev, pin_id);
96d16c30
FV		 1040 st_pinconf_get(pctldev, pin_id, &config);
1041 mutex_lock(&pctldev->mutex);
a8381fac
LJ		 1042
1043 function = st_pctl_get_pin_function(pc, offset);
1044 if (function)
1045 snprintf(f, 10, "Alt Fn %d", function);
1046 else
1047 snprintf(f, 5, "GPIO");
1048
1049 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
701016c0
SK		 1050 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1051 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
e2ed0e88 1052 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset),
701016c0
SK		 1053 ST_PINCONF_UNPACK_PU(config),
1054 ST_PINCONF_UNPACK_OD(config),
a8381fac 1055 f,
701016c0
SK		 1056 ST_PINCONF_UNPACK_RT(config),
1057 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1058 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1059 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1060 ST_PINCONF_UNPACK_RT_CLK(config),
1061 ST_PINCONF_UNPACK_RT_DELAY(config));
1062}
1063
1064static struct pinconf_ops st_confops = {
1065 .pin_config_get = st_pinconf_get,
1066 .pin_config_set = st_pinconf_set,
1067 .pin_config_dbg_show = st_pinconf_dbg_show,
1068};
1069
1070static void st_pctl_dt_child_count(struct st_pinctrl *info,
1071 struct device_node *np)
1072{
1073 struct device_node *child;
1074 for_each_child_of_node(np, child) {
1075 if (of_property_read_bool(child, "gpio-controller")) {
1076 info->nbanks++;
1077 } else {
1078 info->nfunctions++;
1079 info->ngroups += of_get_child_count(child);
1080 }
1081 }
1082}
1083
1084static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1085 int bank, struct st_pio_control *pc)
1086{
1087 struct device *dev = info->dev;
1088 struct regmap *rm = info->regmap;
1089 const struct st_pctl_data *data = info->data;
1090 /* 2 registers per bank */
1091 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1092 struct st_retime_packed *rt_p = &pc->rt.rt_p;
1093 /* cfg0 */
1094 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1095 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1096 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1097 /* cfg1 */
1098 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1099 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1100 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1101 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1102
1103 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1104 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
1105 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1106 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1107 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1108 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1109 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1110
1111 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1112 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1113 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1114 IS_ERR(rt_p->double_edge))
1115 return -EINVAL;
1116
1117 return 0;
1118}
1119
1120static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1121 int bank, struct st_pio_control *pc)
1122{
1123 struct device *dev = info->dev;
1124 struct regmap *rm = info->regmap;
1125 const struct st_pctl_data *data = info->data;
1126 /* 8 registers per bank */
1127 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1128 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1129 unsigned int j;
1130 u32 pin_mask = pc->rt_pin_mask;
1131
1132 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1133 if (BIT(j) & pin_mask) {
1134 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1135 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1136 if (IS_ERR(rt_d->rt[j]))
1137 return -EINVAL;
1138 reg_offset += 4;
1139 }
1140 }
1141 return 0;
1142}
1143
1144static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1145 int bank, struct st_pio_control *pc)
1146{
1147 const struct st_pctl_data *data = info->data;
1148 if (data->rt_style == st_retime_style_packed)
1149 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1150 else if (data->rt_style == st_retime_style_dedicated)
1151 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1152
1153 return -EINVAL;
1154}
1155
4e6a609f
GC		 1156
1157static struct regmap_field *st_pc_get_value(struct device *dev,
1158 struct regmap *regmap, int bank,
1159 int data, int lsb, int msb)
1160{
1161 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1162
1163 if (data < 0)
1164 return NULL;
1165
1166 return devm_regmap_field_alloc(dev, regmap, reg);
1167}
1168
1169static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1170 struct device_node *np)
701016c0
SK		 1171{
1172 const struct st_pctl_data *data = info->data;
1173 /**
1174 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1175 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1176 * So each register is shared across 4 banks.
1177 */
1178 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1179 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
701016c0
SK		 1180 struct st_pio_control *pc = &info->banks[bank].pc;
1181 struct device *dev = info->dev;
1182 struct regmap *regmap = info->regmap;
1183
4e6a609f
GC		 1184 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1185 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1186 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1187 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
701016c0
SK		 1188
1189 /* retime avaiable for all pins by default */
1190 pc->rt_pin_mask = 0xff;
1191 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1192 st_pctl_dt_setup_retime(info, bank, pc);
1193
4e6a609f 1194 return;
701016c0
SK		 1195}
1196
1197/*
1198 * Each pin is represented in of the below forms.
1199 * <bank offset mux direction rt_type rt_delay rt_clk>
1200 */
1201static int st_pctl_dt_parse_groups(struct device_node *np,
1202 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1203{
1204 /* bank pad direction val altfunction */
1205 const __be32 *list;
1206 struct property *pp;
1207 struct st_pinconf *conf;
701016c0 1208 struct device_node *pins;
701016c0
SK		 1209 int i = 0, npins = 0, nr_props;
1210
1211 pins = of_get_child_by_name(np, "st,pins");
1212 if (!pins)
1213 return -ENODATA;
1214
1215 for_each_property_of_node(pins, pp) {
1216 /* Skip those we do not want to proceed */
1217 if (!strcmp(pp->name, "name"))
1218 continue;
1219
1220 if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
1221 npins++;
1222 } else {
1223 pr_warn("Invalid st,pins in %s node\n", np->name);
1224 return -EINVAL;
1225 }
1226 }
1227
1228 grp->npins = npins;
1229 grp->name = np->name;
1230 grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
1231 grp->pin_conf = devm_kzalloc(info->dev,
1232 npins * sizeof(*conf), GFP_KERNEL);
1233
1234 if (!grp->pins || !grp->pin_conf)
1235 return -ENOMEM;
1236
1237 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1238 for_each_property_of_node(pins, pp) {
1239 if (!strcmp(pp->name, "name"))
1240 continue;
1241 nr_props = pp->length/sizeof(u32);
1242 list = pp->value;
1243 conf = &grp->pin_conf[i];
1244
1245 /* bank & offset */
1f978217
RS		 1246 be32_to_cpup(list++);
1247 be32_to_cpup(list++);
701016c0
SK		 1248 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1249 conf->name = pp->name;
1250 grp->pins[i] = conf->pin;
1251 /* mux */
1252 conf->altfunc = be32_to_cpup(list++);
1253 conf->config = 0;
1254 /* direction */
1255 conf->config |= be32_to_cpup(list++);
1256 /* rt_type rt_delay rt_clk */
1257 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1258 /* rt_type */
1259 conf->config |= be32_to_cpup(list++);
1260 /* rt_delay */
1261 conf->config |= be32_to_cpup(list++);
1262 /* rt_clk */
1263 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1264 conf->config |= be32_to_cpup(list++);
1265 }
1266 i++;
1267 }
1268 of_node_put(pins);
1269
1270 return 0;
1271}
1272
1273static int st_pctl_parse_functions(struct device_node *np,
1274 struct st_pinctrl *info, u32 index, int *grp_index)
1275{
1276 struct device_node *child;
1277 struct st_pmx_func *func;
1278 struct st_pctl_group *grp;
1279 int ret, i;
1280
1281 func = &info->functions[index];
1282 func->name = np->name;
1283 func->ngroups = of_get_child_count(np);
8b0c107c 1284 if (func->ngroups == 0) {
701016c0
SK		 1285 dev_err(info->dev, "No groups defined\n");
1286 return -EINVAL;
1287 }
1288 func->groups = devm_kzalloc(info->dev,
1289 func->ngroups * sizeof(char *), GFP_KERNEL);
1290 if (!func->groups)
1291 return -ENOMEM;
1292
1293 i = 0;
1294 for_each_child_of_node(np, child) {
1295 func->groups[i] = child->name;
1296 grp = &info->groups[*grp_index];
1297 *grp_index += 1;
1298 ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1299 if (ret)
1300 return ret;
1301 }
1302 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
1303 index, func->name, func->ngroups);
1304
1305 return 0;
1306}
1307
727b0f71
SK		 1308static void st_gpio_irq_mask(struct irq_data *d)
1309{
130cbe30 1310 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2e862a7b 1311 struct st_gpio_bank *bank = gpiochip_get_data(gc);
727b0f71
SK		 1312
1313 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1314}
1315
1316static void st_gpio_irq_unmask(struct irq_data *d)
1317{
130cbe30 1318 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2e862a7b 1319 struct st_gpio_bank *bank = gpiochip_get_data(gc);
727b0f71
SK		 1320
1321 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1322}
1323
727b0f71
SK		 1324static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1325{
130cbe30 1326 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2e862a7b 1327 struct st_gpio_bank *bank = gpiochip_get_data(gc);
727b0f71
SK		 1328 unsigned long flags;
1329 int comp, pin = d->hwirq;
1330 u32 val;
155795b9 1331 u32 pin_edge_conf = 0;
727b0f71
SK		 1332
1333 switch (type) {
1334 case IRQ_TYPE_LEVEL_HIGH:
1335 comp = 0;
1336 break;
155795b9
SK		 1337 case IRQ_TYPE_EDGE_FALLING:
1338 comp = 0;
1339 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1340 break;
727b0f71
SK		 1341 case IRQ_TYPE_LEVEL_LOW:
1342 comp = 1;
1343 break;
155795b9
SK		 1344 case IRQ_TYPE_EDGE_RISING:
1345 comp = 1;
1346 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1347 break;
1348 case IRQ_TYPE_EDGE_BOTH:
1349 comp = st_gpio_get(&bank->gpio_chip, pin);
1350 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1351 break;
727b0f71
SK		 1352 default:
1353 return -EINVAL;
1354 }
1355
155795b9
SK		 1356 spin_lock_irqsave(&bank->lock, flags);
1357 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1358 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1359 bank->irq_edge_conf |= pin_edge_conf;
1360 spin_unlock_irqrestore(&bank->lock, flags);
1361
727b0f71
SK		 1362 val = readl(bank->base + REG_PIO_PCOMP);
1363 val &= ~BIT(pin);
1364 val |= (comp << pin);
1365 writel(val, bank->base + REG_PIO_PCOMP);
1366
1367 return 0;
1368}
1369
155795b9
SK		 1370/*
1371 * As edge triggers are not supported at hardware level, it is supported by
1372 * software by exploiting the level trigger support in hardware.
1373 *
1374 * Steps for detection raising edge interrupt in software.
1375 *
1376 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1377 *
1378 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1379 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1380 * IGNORE calling the actual interrupt handler for the pin at this stage.
1381 *
1382 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1383 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1384 * DISPATCH the interrupt to the interrupt handler of the pin.
1385 *
1386 * step-1 ________ __________
1387 * | | step - 3
1388 * | |
1389 * step -2 |_____|
1390 *
1391 * falling edge is also detected int the same way.
1392 *
1393 */
727b0f71
SK		 1394static void __gpio_irq_handler(struct st_gpio_bank *bank)
1395{
1396 unsigned long port_in, port_mask, port_comp, active_irqs;
155795b9
SK		 1397 unsigned long bank_edge_mask, flags;
1398 int n, val, ecfg;
1399
1400 spin_lock_irqsave(&bank->lock, flags);
1401 bank_edge_mask = bank->irq_edge_conf;
1402 spin_unlock_irqrestore(&bank->lock, flags);
727b0f71
SK		 1403
1404 for (;;) {
1405 port_in = readl(bank->base + REG_PIO_PIN);
1406 port_comp = readl(bank->base + REG_PIO_PCOMP);
1407 port_mask = readl(bank->base + REG_PIO_PMASK);
1408
1409 active_irqs = (port_in ^ port_comp) & port_mask;
1410
1411 if (active_irqs == 0)
1412 break;
1413
1414 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
155795b9
SK		 1415 /* check if we are detecting fake edges ... */
1416 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1417
1418 if (ecfg) {
1419 /* edge detection. */
1420 val = st_gpio_get(&bank->gpio_chip, n);
1421
1422 writel(BIT(n),
1423 val ? bank->base + REG_PIO_SET_PCOMP :
1424 bank->base + REG_PIO_CLR_PCOMP);
1425
1426 if (ecfg != ST_IRQ_EDGE_BOTH &&
1427 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1428 continue;
1429 }
1430
130cbe30 1431 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
727b0f71
SK		 1432 }
1433 }
1434}
1435
bd0b9ac4 1436static void st_gpio_irq_handler(struct irq_desc *desc)
727b0f71
SK		 1437{
1438 /* interrupt dedicated per bank */
5663bb27 1439 struct irq_chip *chip = irq_desc_get_chip(desc);
130cbe30 1440 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2e862a7b 1441 struct st_gpio_bank *bank = gpiochip_get_data(gc);
727b0f71
SK		 1442
1443 chained_irq_enter(chip, desc);
1444 __gpio_irq_handler(bank);
1445 chained_irq_exit(chip, desc);
1446}
1447
bd0b9ac4 1448static void st_gpio_irqmux_handler(struct irq_desc *desc)
727b0f71 1449{
5663bb27
JL		 1450 struct irq_chip *chip = irq_desc_get_chip(desc);
1451 struct st_pinctrl *info = irq_desc_get_handler_data(desc);
727b0f71
SK		 1452 unsigned long status;
1453 int n;
1454
1455 chained_irq_enter(chip, desc);
1456
1457 status = readl(info->irqmux_base);
1458
7a2deccf 1459 for_each_set_bit(n, &status, info->nbanks)
727b0f71
SK		 1460 __gpio_irq_handler(&info->banks[n]);
1461
1462 chained_irq_exit(chip, desc);
1463}
1464
701016c0 1465static struct gpio_chip st_gpio_template = {
98c85d58
JG		 1466 .request = gpiochip_generic_request,
1467 .free = gpiochip_generic_free,
701016c0
SK		 1468 .get = st_gpio_get,
1469 .set = st_gpio_set,
1470 .direction_input = st_gpio_direction_input,
1471 .direction_output = st_gpio_direction_output,
1e702ec2 1472 .get_direction = st_gpio_get_direction,
701016c0 1473 .ngpio = ST_GPIO_PINS_PER_BANK,
727b0f71
SK		 1474};
1475
1476static struct irq_chip st_gpio_irqchip = {
1477 .name = "GPIO",
fce7fcc7 1478 .irq_disable = st_gpio_irq_mask,
727b0f71
SK		 1479 .irq_mask = st_gpio_irq_mask,
1480 .irq_unmask = st_gpio_irq_unmask,
1481 .irq_set_type = st_gpio_irq_set_type,
8708ebca 1482 .flags = IRQCHIP_SKIP_SET_WAKE,
701016c0
SK		 1483};
1484
1485static int st_gpiolib_register_bank(struct st_pinctrl *info,
1486 int bank_nr, struct device_node *np)
1487{
1488 struct st_gpio_bank *bank = &info->banks[bank_nr];
1489 struct pinctrl_gpio_range *range = &bank->range;
1490 struct device *dev = info->dev;
1491 int bank_num = of_alias_get_id(np, "gpio");
727b0f71 1492 struct resource res, irq_res;
130cbe30 1493 int gpio_irq = 0, err;
701016c0
SK		 1494
1495 if (of_address_to_resource(np, 0, &res))
1496 return -ENODEV;
1497
656445f3
SK		 1498 bank->base = devm_ioremap_resource(dev, &res);
1499 if (IS_ERR(bank->base))
1500 return PTR_ERR(bank->base);
701016c0
SK		 1501
1502 bank->gpio_chip = st_gpio_template;
1503 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1504 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1505 bank->gpio_chip.of_node = np;
58383c78 1506 bank->gpio_chip.parent = dev;
155795b9 1507 spin_lock_init(&bank->lock);
701016c0
SK		 1508
1509 of_property_read_string(np, "st,bank-name", &range->name);
1510 bank->gpio_chip.label = range->name;
1511
1512 range->id = bank_num;
1513 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1514 range->npins = bank->gpio_chip.ngpio;
1515 range->gc = &bank->gpio_chip;
2e862a7b 1516 err = gpiochip_add_data(&bank->gpio_chip, bank);
701016c0
SK		 1517 if (err) {
1518 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
1519 return err;
1520 }
1521 dev_info(dev, "%s bank added.\n", range->name);
1522
727b0f71
SK		 1523 /**
1524 * GPIO bank can have one of the two possible types of
1525 * interrupt-wirings.
1526 *
1527 * First type is via irqmux, single interrupt is used by multiple
1528 * gpio banks. This reduces number of overall interrupts numbers
1529 * required. All these banks belong to a single pincontroller.
1530 * _________
1531 * | |----> [gpio-bank (n) ]
1532 * | |----> [gpio-bank (n + 1)]
1533 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1534 * | |----> [gpio-bank (... )]
1535 * |_________|----> [gpio-bank (n + 7)]
1536 *
1537 * Second type has a dedicated interrupt per each gpio bank.
1538 *
1539 * [irqN]----> [gpio-bank (n)]
1540 */
1541
bcca9220 1542 if (of_irq_to_resource(np, 0, &irq_res)) {
727b0f71 1543 gpio_irq = irq_res.start;
130cbe30
LW		 1544 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
1545 gpio_irq, st_gpio_irq_handler);
727b0f71
SK		 1546 }
1547
2e537276 1548 if (info->irqmux_base || gpio_irq > 0) {
130cbe30
LW		 1549 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
1550 0, handle_simple_irq,
1551 IRQ_TYPE_LEVEL_LOW);
1552 if (err) {
7471725f 1553 gpiochip_remove(&bank->gpio_chip);
130cbe30
LW		 1554 dev_info(dev, "could not add irqchip\n");
1555 return err;
727b0f71 1556 }
727b0f71
SK		 1557 } else {
1558 dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
1559 }
1560
701016c0
SK		 1561 return 0;
1562}
1563
baa9946e 1564static const struct of_device_id st_pctl_of_match[] = {
701016c0
SK		 1565 { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data },
1566 { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data },
1567 { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data },
1568 { .compatible = "st,stih415-right-pinctrl",
1569 .data = &stih415_right_data },
1570 { .compatible = "st,stih415-front-pinctrl",
1571 .data = &stih415_front_data },
1572 { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data},
1573 { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data},
1574 { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
1575 { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
1576 { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
7ce717db
GC		 1577 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data},
1578 { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data},
1579 { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data},
1580 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
701016c0
SK		 1581 { /* sentinel */ }
1582};
1583
1584static int st_pctl_probe_dt(struct platform_device *pdev,
1585 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1586{
1587 int ret = 0;
1588 int i = 0, j = 0, k = 0, bank;
1589 struct pinctrl_pin_desc *pdesc;
1590 struct device_node *np = pdev->dev.of_node;
1591 struct device_node *child;
1592 int grp_index = 0;
727b0f71
SK		 1593 int irq = 0;
1594 struct resource *res;
701016c0
SK		 1595
1596 st_pctl_dt_child_count(info, np);
1597 if (!info->nbanks) {
1598 dev_err(&pdev->dev, "you need atleast one gpio bank\n");
1599 return -EINVAL;
1600 }
1601
1602 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
1603 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1604 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
1605
1606 info->functions = devm_kzalloc(&pdev->dev,
1607 info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
1608
1609 info->groups = devm_kzalloc(&pdev->dev,
1610 info->ngroups * sizeof(*info->groups) , GFP_KERNEL);
1611
1612 info->banks = devm_kzalloc(&pdev->dev,
1613 info->nbanks * sizeof(*info->banks), GFP_KERNEL);
1614
1615 if (!info->functions || !info->groups || !info->banks)
1616 return -ENOMEM;
1617
1618 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
5c75acdc 1619 if (IS_ERR(info->regmap)) {
701016c0 1620 dev_err(info->dev, "No syscfg phandle specified\n");
5c75acdc 1621 return PTR_ERR(info->regmap);
701016c0
SK		 1622 }
1623 info->data = of_match_node(st_pctl_of_match, np)->data;
1624
727b0f71
SK		 1625 irq = platform_get_irq(pdev, 0);
1626
1627 if (irq > 0) {
1628 res = platform_get_resource_byname(pdev,
1629 IORESOURCE_MEM, "irqmux");
1630 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
1631
1632 if (IS_ERR(info->irqmux_base))
1633 return PTR_ERR(info->irqmux_base);
1634
1b11b0cb
TG		 1635 irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1636 info);
727b0f71
SK		 1637
1638 }
1639
701016c0
SK		 1640 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1641 pdesc = devm_kzalloc(&pdev->dev,
1642 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
1643 if (!pdesc)
1644 return -ENOMEM;
1645
1646 pctl_desc->pins = pdesc;
1647
1648 bank = 0;
1649 for_each_child_of_node(np, child) {
1650 if (of_property_read_bool(child, "gpio-controller")) {
1651 const char *bank_name = NULL;
1652 ret = st_gpiolib_register_bank(info, bank, child);
1653 if (ret)
1654 return ret;
1655
1656 k = info->banks[bank].range.pin_base;
1657 bank_name = info->banks[bank].range.name;
1658 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1659 pdesc->number = k;
1660 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
1661 bank_name, j);
1662 pdesc++;
1663 }
1664 st_parse_syscfgs(info, bank, child);
1665 bank++;
1666 } else {
1667 ret = st_pctl_parse_functions(child, info,
1668 i++, &grp_index);
1669 if (ret) {
1670 dev_err(&pdev->dev, "No functions found.\n");
1671 return ret;
1672 }
1673 }
1674 }
1675
1676 return 0;
1677}
1678
1679static int st_pctl_probe(struct platform_device *pdev)
1680{
1681 struct st_pinctrl *info;
1682 struct pinctrl_desc *pctl_desc;
1683 int ret, i;
1684
1685 if (!pdev->dev.of_node) {
1686 dev_err(&pdev->dev, "device node not found.\n");
1687 return -EINVAL;
1688 }
1689
1690 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1691 if (!pctl_desc)
1692 return -ENOMEM;
1693
1694 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1695 if (!info)
1696 return -ENOMEM;
1697
1698 info->dev = &pdev->dev;
1699 platform_set_drvdata(pdev, info);
1700 ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1701 if (ret)
1702 return ret;
1703
c9dd66b7
SK		 1704 pctl_desc->owner = THIS_MODULE;
1705 pctl_desc->pctlops = &st_pctlops;
1706 pctl_desc->pmxops = &st_pmxops;
1707 pctl_desc->confops = &st_confops;
701016c0
SK		 1708 pctl_desc->name = dev_name(&pdev->dev);
1709
e8e2cb23 1710 info->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, info);
323de9ef 1711 if (IS_ERR(info->pctl)) {
701016c0 1712 dev_err(&pdev->dev, "Failed pinctrl registration\n");
323de9ef 1713 return PTR_ERR(info->pctl);
701016c0
SK		 1714 }
1715
1716 for (i = 0; i < info->nbanks; i++)
1717 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1718
1719 return 0;
1720}
1721
1722static struct platform_driver st_pctl_driver = {
1723 .driver = {
1724 .name = "st-pinctrl",
539fde59 1725 .of_match_table = st_pctl_of_match,
701016c0
SK		 1726 },
1727 .probe = st_pctl_probe,
1728};
1729
1730static int __init st_pctl_init(void)
1731{
1732 return platform_driver_register(&st_pctl_driver);
1733}
1734arch_initcall(st_pctl_init);
Linux kernel - Deliverables
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