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dc0a3938 TR |
1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/phy/phy.h> | |
19 | #include <linux/pinctrl/pinctrl.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/reset.h> | |
c61c2d70 | 23 | #include <linux/slab.h> |
dc0a3938 TR |
24 | |
25 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> | |
26 | ||
27 | #include "core.h" | |
28 | #include "pinctrl-utils.h" | |
29 | ||
30 | #define XUSB_PADCTL_ELPG_PROGRAM 0x01c | |
31 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) | |
32 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) | |
33 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) | |
34 | ||
35 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 | |
36 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) | |
37 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) | |
38 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) | |
39 | ||
40 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 | |
41 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) | |
42 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) | |
43 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) | |
44 | ||
45 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 | |
46 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) | |
47 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) | |
48 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) | |
49 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) | |
50 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) | |
51 | ||
52 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 | |
53 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) | |
54 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) | |
55 | ||
56 | struct tegra_xusb_padctl_function { | |
57 | const char *name; | |
58 | const char * const *groups; | |
59 | unsigned int num_groups; | |
60 | }; | |
61 | ||
62 | struct tegra_xusb_padctl_group { | |
63 | const unsigned int *funcs; | |
64 | unsigned int num_funcs; | |
65 | }; | |
66 | ||
67 | struct tegra_xusb_padctl_soc { | |
68 | const struct pinctrl_pin_desc *pins; | |
69 | unsigned int num_pins; | |
70 | ||
71 | const struct tegra_xusb_padctl_function *functions; | |
72 | unsigned int num_functions; | |
73 | ||
74 | const struct tegra_xusb_padctl_lane *lanes; | |
75 | unsigned int num_lanes; | |
76 | }; | |
77 | ||
78 | struct tegra_xusb_padctl_lane { | |
79 | const char *name; | |
80 | ||
81 | unsigned int offset; | |
82 | unsigned int shift; | |
83 | unsigned int mask; | |
84 | unsigned int iddq; | |
85 | ||
86 | const unsigned int *funcs; | |
87 | unsigned int num_funcs; | |
88 | }; | |
89 | ||
90 | struct tegra_xusb_padctl { | |
91 | struct device *dev; | |
92 | void __iomem *regs; | |
93 | struct mutex lock; | |
94 | struct reset_control *rst; | |
95 | ||
96 | const struct tegra_xusb_padctl_soc *soc; | |
97 | struct pinctrl_dev *pinctrl; | |
98 | struct pinctrl_desc desc; | |
99 | ||
100 | struct phy_provider *provider; | |
101 | struct phy *phys[2]; | |
102 | ||
103 | unsigned int enable; | |
104 | }; | |
105 | ||
106 | static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, | |
107 | unsigned long offset) | |
108 | { | |
109 | writel(value, padctl->regs + offset); | |
110 | } | |
111 | ||
112 | static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, | |
113 | unsigned long offset) | |
114 | { | |
115 | return readl(padctl->regs + offset); | |
116 | } | |
117 | ||
118 | static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl) | |
119 | { | |
120 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
121 | ||
122 | return padctl->soc->num_pins; | |
123 | } | |
124 | ||
125 | static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl, | |
126 | unsigned int group) | |
127 | { | |
128 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
129 | ||
130 | return padctl->soc->pins[group].name; | |
131 | } | |
132 | ||
133 | enum tegra_xusb_padctl_param { | |
134 | TEGRA_XUSB_PADCTL_IDDQ, | |
135 | }; | |
136 | ||
137 | static const struct tegra_xusb_padctl_property { | |
138 | const char *name; | |
139 | enum tegra_xusb_padctl_param param; | |
140 | } properties[] = { | |
141 | { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ }, | |
142 | }; | |
143 | ||
144 | #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value)) | |
145 | #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16) | |
146 | #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff) | |
147 | ||
148 | static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl, | |
149 | struct device_node *np, | |
150 | struct pinctrl_map **maps, | |
151 | unsigned int *reserved_maps, | |
152 | unsigned int *num_maps) | |
153 | { | |
154 | unsigned int i, reserve = 0, num_configs = 0; | |
155 | unsigned long config, *configs = NULL; | |
156 | const char *function, *group; | |
157 | struct property *prop; | |
158 | int err = 0; | |
159 | u32 value; | |
160 | ||
161 | err = of_property_read_string(np, "nvidia,function", &function); | |
162 | if (err < 0) { | |
163 | if (err != -EINVAL) | |
164 | return err; | |
165 | ||
166 | function = NULL; | |
167 | } | |
168 | ||
169 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
170 | err = of_property_read_u32(np, properties[i].name, &value); | |
171 | if (err < 0) { | |
172 | if (err == -EINVAL) | |
173 | continue; | |
174 | ||
c61c2d70 | 175 | goto out; |
dc0a3938 TR |
176 | } |
177 | ||
178 | config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value); | |
179 | ||
180 | err = pinctrl_utils_add_config(padctl->pinctrl, &configs, | |
181 | &num_configs, config); | |
182 | if (err < 0) | |
c61c2d70 | 183 | goto out; |
dc0a3938 TR |
184 | } |
185 | ||
186 | if (function) | |
187 | reserve++; | |
188 | ||
189 | if (num_configs) | |
190 | reserve++; | |
191 | ||
192 | err = of_property_count_strings(np, "nvidia,lanes"); | |
193 | if (err < 0) | |
c61c2d70 | 194 | goto out; |
dc0a3938 TR |
195 | |
196 | reserve *= err; | |
197 | ||
198 | err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps, | |
199 | num_maps, reserve); | |
200 | if (err < 0) | |
c61c2d70 | 201 | goto out; |
dc0a3938 TR |
202 | |
203 | of_property_for_each_string(np, "nvidia,lanes", prop, group) { | |
204 | if (function) { | |
205 | err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps, | |
206 | reserved_maps, num_maps, group, | |
207 | function); | |
208 | if (err < 0) | |
c61c2d70 | 209 | goto out; |
dc0a3938 TR |
210 | } |
211 | ||
212 | if (num_configs) { | |
213 | err = pinctrl_utils_add_map_configs(padctl->pinctrl, | |
214 | maps, reserved_maps, num_maps, group, | |
215 | configs, num_configs, | |
216 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
217 | if (err < 0) | |
c61c2d70 | 218 | goto out; |
dc0a3938 TR |
219 | } |
220 | } | |
221 | ||
c61c2d70 TR |
222 | err = 0; |
223 | ||
224 | out: | |
225 | kfree(configs); | |
226 | return err; | |
dc0a3938 TR |
227 | } |
228 | ||
229 | static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, | |
230 | struct device_node *parent, | |
231 | struct pinctrl_map **maps, | |
232 | unsigned int *num_maps) | |
233 | { | |
234 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
235 | unsigned int reserved_maps = 0; | |
236 | struct device_node *np; | |
237 | int err; | |
238 | ||
239 | *num_maps = 0; | |
240 | *maps = NULL; | |
241 | ||
242 | for_each_child_of_node(parent, np) { | |
243 | err = tegra_xusb_padctl_parse_subnode(padctl, np, maps, | |
244 | &reserved_maps, | |
245 | num_maps); | |
246 | if (err < 0) | |
247 | return err; | |
248 | } | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
253 | static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { | |
254 | .get_groups_count = tegra_xusb_padctl_get_groups_count, | |
255 | .get_group_name = tegra_xusb_padctl_get_group_name, | |
256 | .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map, | |
257 | .dt_free_map = pinctrl_utils_dt_free_map, | |
258 | }; | |
259 | ||
260 | static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl) | |
261 | { | |
262 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
263 | ||
264 | return padctl->soc->num_functions; | |
265 | } | |
266 | ||
267 | static const char * | |
268 | tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl, | |
269 | unsigned int function) | |
270 | { | |
271 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
272 | ||
273 | return padctl->soc->functions[function].name; | |
274 | } | |
275 | ||
276 | static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl, | |
277 | unsigned int function, | |
278 | const char * const **groups, | |
279 | unsigned * const num_groups) | |
280 | { | |
281 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
282 | ||
283 | *num_groups = padctl->soc->functions[function].num_groups; | |
284 | *groups = padctl->soc->functions[function].groups; | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
03e9f0ca LW |
289 | static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl, |
290 | unsigned int function, | |
291 | unsigned int group) | |
dc0a3938 TR |
292 | { |
293 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
294 | const struct tegra_xusb_padctl_lane *lane; | |
295 | unsigned int i; | |
296 | u32 value; | |
297 | ||
298 | lane = &padctl->soc->lanes[group]; | |
299 | ||
300 | for (i = 0; i < lane->num_funcs; i++) | |
301 | if (lane->funcs[i] == function) | |
302 | break; | |
303 | ||
304 | if (i >= lane->num_funcs) | |
305 | return -EINVAL; | |
306 | ||
307 | value = padctl_readl(padctl, lane->offset); | |
308 | value &= ~(lane->mask << lane->shift); | |
309 | value |= i << lane->shift; | |
310 | padctl_writel(padctl, value, lane->offset); | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = { | |
316 | .get_functions_count = tegra_xusb_padctl_get_functions_count, | |
317 | .get_function_name = tegra_xusb_padctl_get_function_name, | |
318 | .get_function_groups = tegra_xusb_padctl_get_function_groups, | |
03e9f0ca | 319 | .set_mux = tegra_xusb_padctl_pinmux_set, |
dc0a3938 TR |
320 | }; |
321 | ||
322 | static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, | |
323 | unsigned int group, | |
324 | unsigned long *config) | |
325 | { | |
326 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
327 | const struct tegra_xusb_padctl_lane *lane; | |
328 | enum tegra_xusb_padctl_param param; | |
329 | u32 value; | |
330 | ||
331 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config); | |
332 | lane = &padctl->soc->lanes[group]; | |
333 | ||
334 | switch (param) { | |
335 | case TEGRA_XUSB_PADCTL_IDDQ: | |
336 | /* lanes with iddq == 0 don't support this parameter */ | |
337 | if (lane->iddq == 0) | |
338 | return -EINVAL; | |
339 | ||
340 | value = padctl_readl(padctl, lane->offset); | |
341 | ||
342 | if (value & BIT(lane->iddq)) | |
343 | value = 0; | |
344 | else | |
345 | value = 1; | |
346 | ||
347 | *config = TEGRA_XUSB_PADCTL_PACK(param, value); | |
348 | break; | |
349 | ||
350 | default: | |
351 | dev_err(padctl->dev, "invalid configuration parameter: %04x\n", | |
352 | param); | |
353 | return -ENOTSUPP; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl, | |
360 | unsigned int group, | |
361 | unsigned long *configs, | |
362 | unsigned int num_configs) | |
363 | { | |
364 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
365 | const struct tegra_xusb_padctl_lane *lane; | |
366 | enum tegra_xusb_padctl_param param; | |
367 | unsigned long value; | |
368 | unsigned int i; | |
369 | u32 regval; | |
370 | ||
371 | lane = &padctl->soc->lanes[group]; | |
372 | ||
373 | for (i = 0; i < num_configs; i++) { | |
374 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]); | |
375 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]); | |
376 | ||
377 | switch (param) { | |
378 | case TEGRA_XUSB_PADCTL_IDDQ: | |
379 | /* lanes with iddq == 0 don't support this parameter */ | |
380 | if (lane->iddq == 0) | |
381 | return -EINVAL; | |
382 | ||
383 | regval = padctl_readl(padctl, lane->offset); | |
384 | ||
385 | if (value) | |
386 | regval &= ~BIT(lane->iddq); | |
387 | else | |
388 | regval |= BIT(lane->iddq); | |
389 | ||
390 | padctl_writel(padctl, regval, lane->offset); | |
391 | break; | |
392 | ||
393 | default: | |
394 | dev_err(padctl->dev, | |
395 | "invalid configuration parameter: %04x\n", | |
396 | param); | |
397 | return -ENOTSUPP; | |
398 | } | |
399 | } | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | #ifdef CONFIG_DEBUG_FS | |
405 | static const char *strip_prefix(const char *s) | |
406 | { | |
407 | const char *comma = strchr(s, ','); | |
408 | if (!comma) | |
409 | return s; | |
410 | ||
411 | return comma + 1; | |
412 | } | |
413 | ||
414 | static void | |
415 | tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl, | |
416 | struct seq_file *s, | |
417 | unsigned int group) | |
418 | { | |
419 | unsigned int i; | |
420 | ||
421 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
422 | unsigned long config, value; | |
423 | int err; | |
424 | ||
425 | config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0); | |
426 | ||
427 | err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group, | |
428 | &config); | |
429 | if (err < 0) | |
430 | continue; | |
431 | ||
432 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); | |
433 | ||
434 | seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name), | |
435 | value); | |
436 | } | |
437 | } | |
438 | ||
439 | static void | |
440 | tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl, | |
441 | struct seq_file *s, | |
442 | unsigned long config) | |
443 | { | |
444 | enum tegra_xusb_padctl_param param; | |
445 | const char *name = "unknown"; | |
446 | unsigned long value; | |
447 | unsigned int i; | |
448 | ||
449 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config); | |
450 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); | |
451 | ||
452 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
453 | if (properties[i].param == param) { | |
454 | name = properties[i].name; | |
455 | break; | |
456 | } | |
457 | } | |
458 | ||
459 | seq_printf(s, "%s=%lu", strip_prefix(name), value); | |
460 | } | |
461 | #endif | |
462 | ||
463 | static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = { | |
464 | .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get, | |
465 | .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set, | |
466 | #ifdef CONFIG_DEBUG_FS | |
467 | .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show, | |
468 | .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show, | |
469 | #endif | |
470 | }; | |
471 | ||
472 | static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) | |
473 | { | |
474 | u32 value; | |
475 | ||
476 | mutex_lock(&padctl->lock); | |
477 | ||
478 | if (padctl->enable++ > 0) | |
479 | goto out; | |
480 | ||
481 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
482 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; | |
483 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
484 | ||
485 | usleep_range(100, 200); | |
486 | ||
487 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
488 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; | |
489 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
490 | ||
491 | usleep_range(100, 200); | |
492 | ||
493 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
494 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; | |
495 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
496 | ||
497 | out: | |
498 | mutex_unlock(&padctl->lock); | |
499 | return 0; | |
500 | } | |
501 | ||
502 | static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) | |
503 | { | |
504 | u32 value; | |
505 | ||
506 | mutex_lock(&padctl->lock); | |
507 | ||
508 | if (WARN_ON(padctl->enable == 0)) | |
509 | goto out; | |
510 | ||
511 | if (--padctl->enable > 0) | |
512 | goto out; | |
513 | ||
514 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
515 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; | |
516 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
517 | ||
518 | usleep_range(100, 200); | |
519 | ||
520 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
521 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; | |
522 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
523 | ||
524 | usleep_range(100, 200); | |
525 | ||
526 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
527 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; | |
528 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
529 | ||
530 | out: | |
531 | mutex_unlock(&padctl->lock); | |
532 | return 0; | |
533 | } | |
534 | ||
535 | static int tegra_xusb_phy_init(struct phy *phy) | |
536 | { | |
537 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
538 | ||
539 | return tegra_xusb_padctl_enable(padctl); | |
540 | } | |
541 | ||
542 | static int tegra_xusb_phy_exit(struct phy *phy) | |
543 | { | |
544 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
545 | ||
546 | return tegra_xusb_padctl_disable(padctl); | |
547 | } | |
548 | ||
549 | static int pcie_phy_power_on(struct phy *phy) | |
550 | { | |
551 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
552 | unsigned long timeout; | |
553 | int err = -ETIMEDOUT; | |
554 | u32 value; | |
555 | ||
556 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
557 | value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; | |
558 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
559 | ||
560 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); | |
561 | value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | | |
562 | XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | | |
563 | XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; | |
564 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); | |
565 | ||
566 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
567 | value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; | |
568 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
569 | ||
570 | timeout = jiffies + msecs_to_jiffies(50); | |
571 | ||
572 | while (time_before(jiffies, timeout)) { | |
573 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
574 | if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { | |
575 | err = 0; | |
576 | break; | |
577 | } | |
578 | ||
579 | usleep_range(100, 200); | |
580 | } | |
581 | ||
582 | return err; | |
583 | } | |
584 | ||
585 | static int pcie_phy_power_off(struct phy *phy) | |
586 | { | |
587 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
588 | u32 value; | |
589 | ||
590 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
591 | value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; | |
592 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static const struct phy_ops pcie_phy_ops = { | |
598 | .init = tegra_xusb_phy_init, | |
599 | .exit = tegra_xusb_phy_exit, | |
600 | .power_on = pcie_phy_power_on, | |
601 | .power_off = pcie_phy_power_off, | |
602 | .owner = THIS_MODULE, | |
603 | }; | |
604 | ||
605 | static int sata_phy_power_on(struct phy *phy) | |
606 | { | |
607 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
608 | unsigned long timeout; | |
609 | int err = -ETIMEDOUT; | |
610 | u32 value; | |
611 | ||
612 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
613 | value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; | |
614 | value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; | |
615 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
616 | ||
617 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
618 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; | |
619 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; | |
620 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
621 | ||
622 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
623 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; | |
624 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
625 | ||
626 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
627 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; | |
628 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
629 | ||
630 | timeout = jiffies + msecs_to_jiffies(50); | |
631 | ||
632 | while (time_before(jiffies, timeout)) { | |
633 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
634 | if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { | |
635 | err = 0; | |
636 | break; | |
637 | } | |
638 | ||
639 | usleep_range(100, 200); | |
640 | } | |
641 | ||
642 | return err; | |
643 | } | |
644 | ||
645 | static int sata_phy_power_off(struct phy *phy) | |
646 | { | |
647 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
648 | u32 value; | |
649 | ||
650 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
651 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; | |
652 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
653 | ||
654 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
655 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; | |
656 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
657 | ||
658 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
659 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; | |
660 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; | |
661 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
662 | ||
663 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
664 | value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; | |
665 | value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; | |
666 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static const struct phy_ops sata_phy_ops = { | |
672 | .init = tegra_xusb_phy_init, | |
673 | .exit = tegra_xusb_phy_exit, | |
674 | .power_on = sata_phy_power_on, | |
675 | .power_off = sata_phy_power_off, | |
676 | .owner = THIS_MODULE, | |
677 | }; | |
678 | ||
679 | static struct phy *tegra_xusb_padctl_xlate(struct device *dev, | |
680 | struct of_phandle_args *args) | |
681 | { | |
682 | struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev); | |
683 | unsigned int index = args->args[0]; | |
684 | ||
685 | if (args->args_count <= 0) | |
686 | return ERR_PTR(-EINVAL); | |
687 | ||
8e1594db | 688 | if (index >= ARRAY_SIZE(padctl->phys)) |
dc0a3938 TR |
689 | return ERR_PTR(-EINVAL); |
690 | ||
691 | return padctl->phys[index]; | |
692 | } | |
693 | ||
694 | #define PIN_OTG_0 0 | |
695 | #define PIN_OTG_1 1 | |
696 | #define PIN_OTG_2 2 | |
697 | #define PIN_ULPI_0 3 | |
698 | #define PIN_HSIC_0 4 | |
699 | #define PIN_HSIC_1 5 | |
700 | #define PIN_PCIE_0 6 | |
701 | #define PIN_PCIE_1 7 | |
702 | #define PIN_PCIE_2 8 | |
703 | #define PIN_PCIE_3 9 | |
704 | #define PIN_PCIE_4 10 | |
705 | #define PIN_SATA_0 11 | |
706 | ||
707 | static const struct pinctrl_pin_desc tegra124_pins[] = { | |
708 | PINCTRL_PIN(PIN_OTG_0, "otg-0"), | |
709 | PINCTRL_PIN(PIN_OTG_1, "otg-1"), | |
710 | PINCTRL_PIN(PIN_OTG_2, "otg-2"), | |
711 | PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"), | |
712 | PINCTRL_PIN(PIN_HSIC_0, "hsic-0"), | |
713 | PINCTRL_PIN(PIN_HSIC_1, "hsic-1"), | |
714 | PINCTRL_PIN(PIN_PCIE_0, "pcie-0"), | |
715 | PINCTRL_PIN(PIN_PCIE_1, "pcie-1"), | |
716 | PINCTRL_PIN(PIN_PCIE_2, "pcie-2"), | |
717 | PINCTRL_PIN(PIN_PCIE_3, "pcie-3"), | |
718 | PINCTRL_PIN(PIN_PCIE_4, "pcie-4"), | |
719 | PINCTRL_PIN(PIN_SATA_0, "sata-0"), | |
720 | }; | |
721 | ||
722 | static const char * const tegra124_snps_groups[] = { | |
723 | "otg-0", | |
724 | "otg-1", | |
725 | "otg-2", | |
726 | "ulpi-0", | |
727 | "hsic-0", | |
728 | "hsic-1", | |
729 | }; | |
730 | ||
731 | static const char * const tegra124_xusb_groups[] = { | |
732 | "otg-0", | |
733 | "otg-1", | |
734 | "otg-2", | |
735 | "ulpi-0", | |
736 | "hsic-0", | |
737 | "hsic-1", | |
738 | }; | |
739 | ||
740 | static const char * const tegra124_uart_groups[] = { | |
741 | "otg-0", | |
742 | "otg-1", | |
743 | "otg-2", | |
744 | }; | |
745 | ||
746 | static const char * const tegra124_pcie_groups[] = { | |
747 | "pcie-0", | |
748 | "pcie-1", | |
749 | "pcie-2", | |
750 | "pcie-3", | |
751 | "pcie-4", | |
752 | "sata-0", | |
753 | }; | |
754 | ||
755 | static const char * const tegra124_usb3_groups[] = { | |
756 | "pcie-0", | |
757 | "pcie-1", | |
758 | "pcie-2", | |
759 | "pcie-3", | |
760 | "pcie-4", | |
761 | "sata-0", | |
762 | }; | |
763 | ||
764 | static const char * const tegra124_sata_groups[] = { | |
765 | "pcie-0", | |
766 | "pcie-1", | |
767 | "pcie-2", | |
768 | "pcie-3", | |
769 | "pcie-4", | |
770 | "sata-0", | |
771 | }; | |
772 | ||
773 | static const char * const tegra124_rsvd_groups[] = { | |
774 | "otg-0", | |
775 | "otg-1", | |
776 | "otg-2", | |
777 | "pcie-0", | |
778 | "pcie-1", | |
779 | "pcie-2", | |
780 | "pcie-3", | |
781 | "pcie-4", | |
782 | "sata-0", | |
783 | }; | |
784 | ||
785 | #define TEGRA124_FUNCTION(_name) \ | |
786 | { \ | |
787 | .name = #_name, \ | |
788 | .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \ | |
789 | .groups = tegra124_##_name##_groups, \ | |
790 | } | |
791 | ||
792 | static struct tegra_xusb_padctl_function tegra124_functions[] = { | |
793 | TEGRA124_FUNCTION(snps), | |
794 | TEGRA124_FUNCTION(xusb), | |
795 | TEGRA124_FUNCTION(uart), | |
796 | TEGRA124_FUNCTION(pcie), | |
797 | TEGRA124_FUNCTION(usb3), | |
798 | TEGRA124_FUNCTION(sata), | |
799 | TEGRA124_FUNCTION(rsvd), | |
800 | }; | |
801 | ||
802 | enum tegra124_function { | |
803 | TEGRA124_FUNC_SNPS, | |
804 | TEGRA124_FUNC_XUSB, | |
805 | TEGRA124_FUNC_UART, | |
806 | TEGRA124_FUNC_PCIE, | |
807 | TEGRA124_FUNC_USB3, | |
808 | TEGRA124_FUNC_SATA, | |
809 | TEGRA124_FUNC_RSVD, | |
810 | }; | |
811 | ||
812 | static const unsigned int tegra124_otg_functions[] = { | |
813 | TEGRA124_FUNC_SNPS, | |
814 | TEGRA124_FUNC_XUSB, | |
815 | TEGRA124_FUNC_UART, | |
816 | TEGRA124_FUNC_RSVD, | |
817 | }; | |
818 | ||
819 | static const unsigned int tegra124_usb_functions[] = { | |
820 | TEGRA124_FUNC_SNPS, | |
821 | TEGRA124_FUNC_XUSB, | |
822 | }; | |
823 | ||
824 | static const unsigned int tegra124_pci_functions[] = { | |
825 | TEGRA124_FUNC_PCIE, | |
826 | TEGRA124_FUNC_USB3, | |
827 | TEGRA124_FUNC_SATA, | |
828 | TEGRA124_FUNC_RSVD, | |
829 | }; | |
830 | ||
831 | #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ | |
832 | { \ | |
833 | .name = _name, \ | |
834 | .offset = _offset, \ | |
835 | .shift = _shift, \ | |
836 | .mask = _mask, \ | |
837 | .iddq = _iddq, \ | |
838 | .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ | |
839 | .funcs = tegra124_##_funcs##_functions, \ | |
840 | } | |
841 | ||
842 | static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { | |
843 | TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), | |
844 | TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), | |
845 | TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), | |
846 | TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), | |
847 | TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), | |
848 | TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), | |
849 | TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), | |
850 | TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), | |
851 | TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), | |
852 | TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), | |
853 | TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), | |
854 | TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), | |
855 | }; | |
856 | ||
857 | static const struct tegra_xusb_padctl_soc tegra124_soc = { | |
858 | .num_pins = ARRAY_SIZE(tegra124_pins), | |
859 | .pins = tegra124_pins, | |
860 | .num_functions = ARRAY_SIZE(tegra124_functions), | |
861 | .functions = tegra124_functions, | |
862 | .num_lanes = ARRAY_SIZE(tegra124_lanes), | |
863 | .lanes = tegra124_lanes, | |
864 | }; | |
865 | ||
866 | static const struct of_device_id tegra_xusb_padctl_of_match[] = { | |
867 | { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc }, | |
868 | { } | |
869 | }; | |
870 | MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match); | |
871 | ||
872 | static int tegra_xusb_padctl_probe(struct platform_device *pdev) | |
873 | { | |
874 | struct tegra_xusb_padctl *padctl; | |
875 | const struct of_device_id *match; | |
876 | struct resource *res; | |
877 | struct phy *phy; | |
878 | int err; | |
879 | ||
880 | padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL); | |
881 | if (!padctl) | |
882 | return -ENOMEM; | |
883 | ||
884 | platform_set_drvdata(pdev, padctl); | |
885 | mutex_init(&padctl->lock); | |
886 | padctl->dev = &pdev->dev; | |
887 | ||
888 | match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); | |
889 | padctl->soc = match->data; | |
890 | ||
891 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
892 | padctl->regs = devm_ioremap_resource(&pdev->dev, res); | |
893 | if (IS_ERR(padctl->regs)) | |
894 | return PTR_ERR(padctl->regs); | |
895 | ||
896 | padctl->rst = devm_reset_control_get(&pdev->dev, NULL); | |
897 | if (IS_ERR(padctl->rst)) | |
898 | return PTR_ERR(padctl->rst); | |
899 | ||
900 | err = reset_control_deassert(padctl->rst); | |
901 | if (err < 0) | |
902 | return err; | |
903 | ||
904 | memset(&padctl->desc, 0, sizeof(padctl->desc)); | |
905 | padctl->desc.name = dev_name(padctl->dev); | |
906 | padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; | |
907 | padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; | |
908 | padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; | |
909 | padctl->desc.owner = THIS_MODULE; | |
910 | ||
911 | padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl); | |
912 | if (!padctl->pinctrl) { | |
913 | dev_err(&pdev->dev, "failed to register pincontrol\n"); | |
914 | err = -ENODEV; | |
915 | goto reset; | |
916 | } | |
917 | ||
dbc98635 | 918 | phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops); |
dc0a3938 TR |
919 | if (IS_ERR(phy)) { |
920 | err = PTR_ERR(phy); | |
921 | goto unregister; | |
922 | } | |
923 | ||
924 | padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; | |
925 | phy_set_drvdata(phy, padctl); | |
926 | ||
dbc98635 | 927 | phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops); |
dc0a3938 TR |
928 | if (IS_ERR(phy)) { |
929 | err = PTR_ERR(phy); | |
930 | goto unregister; | |
931 | } | |
932 | ||
933 | padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy; | |
934 | phy_set_drvdata(phy, padctl); | |
935 | ||
936 | padctl->provider = devm_of_phy_provider_register(&pdev->dev, | |
937 | tegra_xusb_padctl_xlate); | |
8a3cfb7c DC |
938 | if (IS_ERR(padctl->provider)) { |
939 | err = PTR_ERR(padctl->provider); | |
dc0a3938 TR |
940 | dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); |
941 | goto unregister; | |
942 | } | |
943 | ||
944 | return 0; | |
945 | ||
946 | unregister: | |
947 | pinctrl_unregister(padctl->pinctrl); | |
948 | reset: | |
949 | reset_control_assert(padctl->rst); | |
950 | return err; | |
951 | } | |
952 | ||
953 | static int tegra_xusb_padctl_remove(struct platform_device *pdev) | |
954 | { | |
955 | struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev); | |
956 | int err; | |
957 | ||
958 | pinctrl_unregister(padctl->pinctrl); | |
959 | ||
960 | err = reset_control_assert(padctl->rst); | |
961 | if (err < 0) | |
962 | dev_err(&pdev->dev, "failed to assert reset: %d\n", err); | |
963 | ||
964 | return err; | |
965 | } | |
966 | ||
967 | static struct platform_driver tegra_xusb_padctl_driver = { | |
968 | .driver = { | |
969 | .name = "tegra-xusb-padctl", | |
970 | .of_match_table = tegra_xusb_padctl_of_match, | |
971 | }, | |
972 | .probe = tegra_xusb_padctl_probe, | |
973 | .remove = tegra_xusb_padctl_remove, | |
974 | }; | |
975 | module_platform_driver(tegra_xusb_padctl_driver); | |
976 | ||
977 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
978 | MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver"); | |
979 | MODULE_LICENSE("GPL v2"); |