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dc0a3938 TR |
1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of.h> | |
18 | #include <linux/phy/phy.h> | |
19 | #include <linux/pinctrl/pinctrl.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/reset.h> | |
c61c2d70 | 23 | #include <linux/slab.h> |
dc0a3938 TR |
24 | |
25 | #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> | |
26 | ||
27 | #include "core.h" | |
28 | #include "pinctrl-utils.h" | |
29 | ||
30 | #define XUSB_PADCTL_ELPG_PROGRAM 0x01c | |
31 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26) | |
32 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25) | |
33 | #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24) | |
34 | ||
35 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040 | |
36 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19) | |
37 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12) | |
38 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1) | |
39 | ||
40 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044 | |
41 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6) | |
42 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5) | |
43 | #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4) | |
44 | ||
45 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138 | |
46 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27) | |
47 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24) | |
48 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3) | |
49 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1) | |
50 | #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0) | |
51 | ||
52 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148 | |
53 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1) | |
54 | #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0) | |
55 | ||
56 | struct tegra_xusb_padctl_function { | |
57 | const char *name; | |
58 | const char * const *groups; | |
59 | unsigned int num_groups; | |
60 | }; | |
61 | ||
dc0a3938 TR |
62 | struct tegra_xusb_padctl_soc { |
63 | const struct pinctrl_pin_desc *pins; | |
64 | unsigned int num_pins; | |
65 | ||
66 | const struct tegra_xusb_padctl_function *functions; | |
67 | unsigned int num_functions; | |
68 | ||
69 | const struct tegra_xusb_padctl_lane *lanes; | |
70 | unsigned int num_lanes; | |
71 | }; | |
72 | ||
73 | struct tegra_xusb_padctl_lane { | |
74 | const char *name; | |
75 | ||
76 | unsigned int offset; | |
77 | unsigned int shift; | |
78 | unsigned int mask; | |
79 | unsigned int iddq; | |
80 | ||
81 | const unsigned int *funcs; | |
82 | unsigned int num_funcs; | |
83 | }; | |
84 | ||
85 | struct tegra_xusb_padctl { | |
86 | struct device *dev; | |
87 | void __iomem *regs; | |
88 | struct mutex lock; | |
89 | struct reset_control *rst; | |
90 | ||
91 | const struct tegra_xusb_padctl_soc *soc; | |
92 | struct pinctrl_dev *pinctrl; | |
93 | struct pinctrl_desc desc; | |
94 | ||
95 | struct phy_provider *provider; | |
96 | struct phy *phys[2]; | |
97 | ||
98 | unsigned int enable; | |
99 | }; | |
100 | ||
101 | static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, | |
102 | unsigned long offset) | |
103 | { | |
104 | writel(value, padctl->regs + offset); | |
105 | } | |
106 | ||
107 | static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl, | |
108 | unsigned long offset) | |
109 | { | |
110 | return readl(padctl->regs + offset); | |
111 | } | |
112 | ||
113 | static int tegra_xusb_padctl_get_groups_count(struct pinctrl_dev *pinctrl) | |
114 | { | |
115 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
116 | ||
117 | return padctl->soc->num_pins; | |
118 | } | |
119 | ||
120 | static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl, | |
121 | unsigned int group) | |
122 | { | |
123 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
124 | ||
125 | return padctl->soc->pins[group].name; | |
126 | } | |
127 | ||
8480c2e7 JH |
128 | static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, |
129 | unsigned group, | |
130 | const unsigned **pins, | |
131 | unsigned *num_pins) | |
132 | { | |
133 | /* | |
134 | * For the tegra-xusb pad controller groups are synonomous | |
135 | * with lanes/pins and there is always one lane/pin per group. | |
136 | */ | |
137 | *pins = &pinctrl->desc->pins[group].number; | |
138 | *num_pins = 1; | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
dc0a3938 TR |
143 | enum tegra_xusb_padctl_param { |
144 | TEGRA_XUSB_PADCTL_IDDQ, | |
145 | }; | |
146 | ||
147 | static const struct tegra_xusb_padctl_property { | |
148 | const char *name; | |
149 | enum tegra_xusb_padctl_param param; | |
150 | } properties[] = { | |
151 | { "nvidia,iddq", TEGRA_XUSB_PADCTL_IDDQ }, | |
152 | }; | |
153 | ||
154 | #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value)) | |
155 | #define TEGRA_XUSB_PADCTL_UNPACK_PARAM(config) ((config) >> 16) | |
156 | #define TEGRA_XUSB_PADCTL_UNPACK_VALUE(config) ((config) & 0xffff) | |
157 | ||
158 | static int tegra_xusb_padctl_parse_subnode(struct tegra_xusb_padctl *padctl, | |
159 | struct device_node *np, | |
160 | struct pinctrl_map **maps, | |
161 | unsigned int *reserved_maps, | |
162 | unsigned int *num_maps) | |
163 | { | |
164 | unsigned int i, reserve = 0, num_configs = 0; | |
165 | unsigned long config, *configs = NULL; | |
166 | const char *function, *group; | |
167 | struct property *prop; | |
168 | int err = 0; | |
169 | u32 value; | |
170 | ||
171 | err = of_property_read_string(np, "nvidia,function", &function); | |
172 | if (err < 0) { | |
173 | if (err != -EINVAL) | |
174 | return err; | |
175 | ||
176 | function = NULL; | |
177 | } | |
178 | ||
179 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
180 | err = of_property_read_u32(np, properties[i].name, &value); | |
181 | if (err < 0) { | |
182 | if (err == -EINVAL) | |
183 | continue; | |
184 | ||
c61c2d70 | 185 | goto out; |
dc0a3938 TR |
186 | } |
187 | ||
188 | config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value); | |
189 | ||
190 | err = pinctrl_utils_add_config(padctl->pinctrl, &configs, | |
191 | &num_configs, config); | |
192 | if (err < 0) | |
c61c2d70 | 193 | goto out; |
dc0a3938 TR |
194 | } |
195 | ||
196 | if (function) | |
197 | reserve++; | |
198 | ||
199 | if (num_configs) | |
200 | reserve++; | |
201 | ||
202 | err = of_property_count_strings(np, "nvidia,lanes"); | |
203 | if (err < 0) | |
c61c2d70 | 204 | goto out; |
dc0a3938 TR |
205 | |
206 | reserve *= err; | |
207 | ||
208 | err = pinctrl_utils_reserve_map(padctl->pinctrl, maps, reserved_maps, | |
209 | num_maps, reserve); | |
210 | if (err < 0) | |
c61c2d70 | 211 | goto out; |
dc0a3938 TR |
212 | |
213 | of_property_for_each_string(np, "nvidia,lanes", prop, group) { | |
214 | if (function) { | |
215 | err = pinctrl_utils_add_map_mux(padctl->pinctrl, maps, | |
216 | reserved_maps, num_maps, group, | |
217 | function); | |
218 | if (err < 0) | |
c61c2d70 | 219 | goto out; |
dc0a3938 TR |
220 | } |
221 | ||
222 | if (num_configs) { | |
223 | err = pinctrl_utils_add_map_configs(padctl->pinctrl, | |
224 | maps, reserved_maps, num_maps, group, | |
225 | configs, num_configs, | |
226 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
227 | if (err < 0) | |
c61c2d70 | 228 | goto out; |
dc0a3938 TR |
229 | } |
230 | } | |
231 | ||
c61c2d70 TR |
232 | err = 0; |
233 | ||
234 | out: | |
235 | kfree(configs); | |
236 | return err; | |
dc0a3938 TR |
237 | } |
238 | ||
239 | static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl, | |
240 | struct device_node *parent, | |
241 | struct pinctrl_map **maps, | |
242 | unsigned int *num_maps) | |
243 | { | |
244 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
245 | unsigned int reserved_maps = 0; | |
246 | struct device_node *np; | |
247 | int err; | |
248 | ||
249 | *num_maps = 0; | |
250 | *maps = NULL; | |
251 | ||
252 | for_each_child_of_node(parent, np) { | |
253 | err = tegra_xusb_padctl_parse_subnode(padctl, np, maps, | |
254 | &reserved_maps, | |
255 | num_maps); | |
21a8fe88 JL |
256 | if (err < 0) { |
257 | of_node_put(np); | |
dc0a3938 | 258 | return err; |
21a8fe88 | 259 | } |
dc0a3938 TR |
260 | } |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = { | |
266 | .get_groups_count = tegra_xusb_padctl_get_groups_count, | |
267 | .get_group_name = tegra_xusb_padctl_get_group_name, | |
8480c2e7 | 268 | .get_group_pins = tegra_xusb_padctl_get_group_pins, |
dc0a3938 TR |
269 | .dt_node_to_map = tegra_xusb_padctl_dt_node_to_map, |
270 | .dt_free_map = pinctrl_utils_dt_free_map, | |
271 | }; | |
272 | ||
273 | static int tegra_xusb_padctl_get_functions_count(struct pinctrl_dev *pinctrl) | |
274 | { | |
275 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
276 | ||
277 | return padctl->soc->num_functions; | |
278 | } | |
279 | ||
280 | static const char * | |
281 | tegra_xusb_padctl_get_function_name(struct pinctrl_dev *pinctrl, | |
282 | unsigned int function) | |
283 | { | |
284 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
285 | ||
286 | return padctl->soc->functions[function].name; | |
287 | } | |
288 | ||
289 | static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl, | |
290 | unsigned int function, | |
291 | const char * const **groups, | |
292 | unsigned * const num_groups) | |
293 | { | |
294 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
295 | ||
296 | *num_groups = padctl->soc->functions[function].num_groups; | |
297 | *groups = padctl->soc->functions[function].groups; | |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
03e9f0ca LW |
302 | static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl, |
303 | unsigned int function, | |
304 | unsigned int group) | |
dc0a3938 TR |
305 | { |
306 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
307 | const struct tegra_xusb_padctl_lane *lane; | |
308 | unsigned int i; | |
309 | u32 value; | |
310 | ||
311 | lane = &padctl->soc->lanes[group]; | |
312 | ||
313 | for (i = 0; i < lane->num_funcs; i++) | |
314 | if (lane->funcs[i] == function) | |
315 | break; | |
316 | ||
317 | if (i >= lane->num_funcs) | |
318 | return -EINVAL; | |
319 | ||
320 | value = padctl_readl(padctl, lane->offset); | |
321 | value &= ~(lane->mask << lane->shift); | |
322 | value |= i << lane->shift; | |
323 | padctl_writel(padctl, value, lane->offset); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = { | |
329 | .get_functions_count = tegra_xusb_padctl_get_functions_count, | |
330 | .get_function_name = tegra_xusb_padctl_get_function_name, | |
331 | .get_function_groups = tegra_xusb_padctl_get_function_groups, | |
03e9f0ca | 332 | .set_mux = tegra_xusb_padctl_pinmux_set, |
dc0a3938 TR |
333 | }; |
334 | ||
335 | static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, | |
336 | unsigned int group, | |
337 | unsigned long *config) | |
338 | { | |
339 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
340 | const struct tegra_xusb_padctl_lane *lane; | |
341 | enum tegra_xusb_padctl_param param; | |
342 | u32 value; | |
343 | ||
344 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(*config); | |
345 | lane = &padctl->soc->lanes[group]; | |
346 | ||
347 | switch (param) { | |
348 | case TEGRA_XUSB_PADCTL_IDDQ: | |
349 | /* lanes with iddq == 0 don't support this parameter */ | |
350 | if (lane->iddq == 0) | |
351 | return -EINVAL; | |
352 | ||
353 | value = padctl_readl(padctl, lane->offset); | |
354 | ||
355 | if (value & BIT(lane->iddq)) | |
356 | value = 0; | |
357 | else | |
358 | value = 1; | |
359 | ||
360 | *config = TEGRA_XUSB_PADCTL_PACK(param, value); | |
361 | break; | |
362 | ||
363 | default: | |
364 | dev_err(padctl->dev, "invalid configuration parameter: %04x\n", | |
365 | param); | |
366 | return -ENOTSUPP; | |
367 | } | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | static int tegra_xusb_padctl_pinconf_group_set(struct pinctrl_dev *pinctrl, | |
373 | unsigned int group, | |
374 | unsigned long *configs, | |
375 | unsigned int num_configs) | |
376 | { | |
377 | struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); | |
378 | const struct tegra_xusb_padctl_lane *lane; | |
379 | enum tegra_xusb_padctl_param param; | |
380 | unsigned long value; | |
381 | unsigned int i; | |
382 | u32 regval; | |
383 | ||
384 | lane = &padctl->soc->lanes[group]; | |
385 | ||
386 | for (i = 0; i < num_configs; i++) { | |
387 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(configs[i]); | |
388 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(configs[i]); | |
389 | ||
390 | switch (param) { | |
391 | case TEGRA_XUSB_PADCTL_IDDQ: | |
392 | /* lanes with iddq == 0 don't support this parameter */ | |
393 | if (lane->iddq == 0) | |
394 | return -EINVAL; | |
395 | ||
396 | regval = padctl_readl(padctl, lane->offset); | |
397 | ||
398 | if (value) | |
399 | regval &= ~BIT(lane->iddq); | |
400 | else | |
401 | regval |= BIT(lane->iddq); | |
402 | ||
403 | padctl_writel(padctl, regval, lane->offset); | |
404 | break; | |
405 | ||
406 | default: | |
407 | dev_err(padctl->dev, | |
408 | "invalid configuration parameter: %04x\n", | |
409 | param); | |
410 | return -ENOTSUPP; | |
411 | } | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | #ifdef CONFIG_DEBUG_FS | |
418 | static const char *strip_prefix(const char *s) | |
419 | { | |
420 | const char *comma = strchr(s, ','); | |
421 | if (!comma) | |
422 | return s; | |
423 | ||
424 | return comma + 1; | |
425 | } | |
426 | ||
427 | static void | |
428 | tegra_xusb_padctl_pinconf_group_dbg_show(struct pinctrl_dev *pinctrl, | |
429 | struct seq_file *s, | |
430 | unsigned int group) | |
431 | { | |
432 | unsigned int i; | |
433 | ||
434 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
435 | unsigned long config, value; | |
436 | int err; | |
437 | ||
438 | config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, 0); | |
439 | ||
440 | err = tegra_xusb_padctl_pinconf_group_get(pinctrl, group, | |
441 | &config); | |
442 | if (err < 0) | |
443 | continue; | |
444 | ||
445 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); | |
446 | ||
447 | seq_printf(s, "\n\t%s=%lu\n", strip_prefix(properties[i].name), | |
448 | value); | |
449 | } | |
450 | } | |
451 | ||
452 | static void | |
453 | tegra_xusb_padctl_pinconf_config_dbg_show(struct pinctrl_dev *pinctrl, | |
454 | struct seq_file *s, | |
455 | unsigned long config) | |
456 | { | |
457 | enum tegra_xusb_padctl_param param; | |
458 | const char *name = "unknown"; | |
459 | unsigned long value; | |
460 | unsigned int i; | |
461 | ||
462 | param = TEGRA_XUSB_PADCTL_UNPACK_PARAM(config); | |
463 | value = TEGRA_XUSB_PADCTL_UNPACK_VALUE(config); | |
464 | ||
465 | for (i = 0; i < ARRAY_SIZE(properties); i++) { | |
466 | if (properties[i].param == param) { | |
467 | name = properties[i].name; | |
468 | break; | |
469 | } | |
470 | } | |
471 | ||
472 | seq_printf(s, "%s=%lu", strip_prefix(name), value); | |
473 | } | |
474 | #endif | |
475 | ||
476 | static const struct pinconf_ops tegra_xusb_padctl_pinconf_ops = { | |
477 | .pin_config_group_get = tegra_xusb_padctl_pinconf_group_get, | |
478 | .pin_config_group_set = tegra_xusb_padctl_pinconf_group_set, | |
479 | #ifdef CONFIG_DEBUG_FS | |
480 | .pin_config_group_dbg_show = tegra_xusb_padctl_pinconf_group_dbg_show, | |
481 | .pin_config_config_dbg_show = tegra_xusb_padctl_pinconf_config_dbg_show, | |
482 | #endif | |
483 | }; | |
484 | ||
485 | static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl) | |
486 | { | |
487 | u32 value; | |
488 | ||
489 | mutex_lock(&padctl->lock); | |
490 | ||
491 | if (padctl->enable++ > 0) | |
492 | goto out; | |
493 | ||
494 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
495 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; | |
496 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
497 | ||
498 | usleep_range(100, 200); | |
499 | ||
500 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
501 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; | |
502 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
503 | ||
504 | usleep_range(100, 200); | |
505 | ||
506 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
507 | value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; | |
508 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
509 | ||
510 | out: | |
511 | mutex_unlock(&padctl->lock); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) | |
516 | { | |
517 | u32 value; | |
518 | ||
519 | mutex_lock(&padctl->lock); | |
520 | ||
521 | if (WARN_ON(padctl->enable == 0)) | |
522 | goto out; | |
523 | ||
524 | if (--padctl->enable > 0) | |
525 | goto out; | |
526 | ||
527 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
528 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; | |
529 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
530 | ||
531 | usleep_range(100, 200); | |
532 | ||
533 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
534 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; | |
535 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
536 | ||
537 | usleep_range(100, 200); | |
538 | ||
539 | value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); | |
540 | value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; | |
541 | padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); | |
542 | ||
543 | out: | |
544 | mutex_unlock(&padctl->lock); | |
545 | return 0; | |
546 | } | |
547 | ||
548 | static int tegra_xusb_phy_init(struct phy *phy) | |
549 | { | |
550 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
551 | ||
552 | return tegra_xusb_padctl_enable(padctl); | |
553 | } | |
554 | ||
555 | static int tegra_xusb_phy_exit(struct phy *phy) | |
556 | { | |
557 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
558 | ||
559 | return tegra_xusb_padctl_disable(padctl); | |
560 | } | |
561 | ||
562 | static int pcie_phy_power_on(struct phy *phy) | |
563 | { | |
564 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
565 | unsigned long timeout; | |
566 | int err = -ETIMEDOUT; | |
567 | u32 value; | |
568 | ||
569 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
570 | value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK; | |
571 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
572 | ||
573 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); | |
574 | value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN | | |
575 | XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN | | |
576 | XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL; | |
577 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2); | |
578 | ||
579 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
580 | value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; | |
581 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
582 | ||
583 | timeout = jiffies + msecs_to_jiffies(50); | |
584 | ||
585 | while (time_before(jiffies, timeout)) { | |
586 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
587 | if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) { | |
588 | err = 0; | |
589 | break; | |
590 | } | |
591 | ||
592 | usleep_range(100, 200); | |
593 | } | |
594 | ||
595 | return err; | |
596 | } | |
597 | ||
598 | static int pcie_phy_power_off(struct phy *phy) | |
599 | { | |
600 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
601 | u32 value; | |
602 | ||
603 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
604 | value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST; | |
605 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static const struct phy_ops pcie_phy_ops = { | |
611 | .init = tegra_xusb_phy_init, | |
612 | .exit = tegra_xusb_phy_exit, | |
613 | .power_on = pcie_phy_power_on, | |
614 | .power_off = pcie_phy_power_off, | |
615 | .owner = THIS_MODULE, | |
616 | }; | |
617 | ||
618 | static int sata_phy_power_on(struct phy *phy) | |
619 | { | |
620 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
621 | unsigned long timeout; | |
622 | int err = -ETIMEDOUT; | |
623 | u32 value; | |
624 | ||
625 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
626 | value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; | |
627 | value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; | |
628 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
629 | ||
630 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
631 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; | |
632 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; | |
633 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
634 | ||
635 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
636 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; | |
637 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
638 | ||
639 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
640 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; | |
641 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
642 | ||
643 | timeout = jiffies + msecs_to_jiffies(50); | |
644 | ||
645 | while (time_before(jiffies, timeout)) { | |
646 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
647 | if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) { | |
648 | err = 0; | |
649 | break; | |
650 | } | |
651 | ||
652 | usleep_range(100, 200); | |
653 | } | |
654 | ||
655 | return err; | |
656 | } | |
657 | ||
658 | static int sata_phy_power_off(struct phy *phy) | |
659 | { | |
660 | struct tegra_xusb_padctl *padctl = phy_get_drvdata(phy); | |
661 | u32 value; | |
662 | ||
663 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
664 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST; | |
665 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
666 | ||
667 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
668 | value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE; | |
669 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
670 | ||
671 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
672 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD; | |
673 | value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ; | |
674 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1); | |
675 | ||
676 | value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
677 | value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD; | |
678 | value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ; | |
679 | padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static const struct phy_ops sata_phy_ops = { | |
685 | .init = tegra_xusb_phy_init, | |
686 | .exit = tegra_xusb_phy_exit, | |
687 | .power_on = sata_phy_power_on, | |
688 | .power_off = sata_phy_power_off, | |
689 | .owner = THIS_MODULE, | |
690 | }; | |
691 | ||
692 | static struct phy *tegra_xusb_padctl_xlate(struct device *dev, | |
693 | struct of_phandle_args *args) | |
694 | { | |
695 | struct tegra_xusb_padctl *padctl = dev_get_drvdata(dev); | |
696 | unsigned int index = args->args[0]; | |
697 | ||
698 | if (args->args_count <= 0) | |
699 | return ERR_PTR(-EINVAL); | |
700 | ||
8e1594db | 701 | if (index >= ARRAY_SIZE(padctl->phys)) |
dc0a3938 TR |
702 | return ERR_PTR(-EINVAL); |
703 | ||
704 | return padctl->phys[index]; | |
705 | } | |
706 | ||
707 | #define PIN_OTG_0 0 | |
708 | #define PIN_OTG_1 1 | |
709 | #define PIN_OTG_2 2 | |
710 | #define PIN_ULPI_0 3 | |
711 | #define PIN_HSIC_0 4 | |
712 | #define PIN_HSIC_1 5 | |
713 | #define PIN_PCIE_0 6 | |
714 | #define PIN_PCIE_1 7 | |
715 | #define PIN_PCIE_2 8 | |
716 | #define PIN_PCIE_3 9 | |
717 | #define PIN_PCIE_4 10 | |
718 | #define PIN_SATA_0 11 | |
719 | ||
720 | static const struct pinctrl_pin_desc tegra124_pins[] = { | |
721 | PINCTRL_PIN(PIN_OTG_0, "otg-0"), | |
722 | PINCTRL_PIN(PIN_OTG_1, "otg-1"), | |
723 | PINCTRL_PIN(PIN_OTG_2, "otg-2"), | |
724 | PINCTRL_PIN(PIN_ULPI_0, "ulpi-0"), | |
725 | PINCTRL_PIN(PIN_HSIC_0, "hsic-0"), | |
726 | PINCTRL_PIN(PIN_HSIC_1, "hsic-1"), | |
727 | PINCTRL_PIN(PIN_PCIE_0, "pcie-0"), | |
728 | PINCTRL_PIN(PIN_PCIE_1, "pcie-1"), | |
729 | PINCTRL_PIN(PIN_PCIE_2, "pcie-2"), | |
730 | PINCTRL_PIN(PIN_PCIE_3, "pcie-3"), | |
731 | PINCTRL_PIN(PIN_PCIE_4, "pcie-4"), | |
732 | PINCTRL_PIN(PIN_SATA_0, "sata-0"), | |
733 | }; | |
734 | ||
735 | static const char * const tegra124_snps_groups[] = { | |
736 | "otg-0", | |
737 | "otg-1", | |
738 | "otg-2", | |
739 | "ulpi-0", | |
740 | "hsic-0", | |
741 | "hsic-1", | |
742 | }; | |
743 | ||
744 | static const char * const tegra124_xusb_groups[] = { | |
745 | "otg-0", | |
746 | "otg-1", | |
747 | "otg-2", | |
748 | "ulpi-0", | |
749 | "hsic-0", | |
750 | "hsic-1", | |
751 | }; | |
752 | ||
753 | static const char * const tegra124_uart_groups[] = { | |
754 | "otg-0", | |
755 | "otg-1", | |
756 | "otg-2", | |
757 | }; | |
758 | ||
759 | static const char * const tegra124_pcie_groups[] = { | |
760 | "pcie-0", | |
761 | "pcie-1", | |
762 | "pcie-2", | |
763 | "pcie-3", | |
764 | "pcie-4", | |
dc0a3938 TR |
765 | }; |
766 | ||
767 | static const char * const tegra124_usb3_groups[] = { | |
768 | "pcie-0", | |
769 | "pcie-1", | |
dc0a3938 TR |
770 | "sata-0", |
771 | }; | |
772 | ||
773 | static const char * const tegra124_sata_groups[] = { | |
dc0a3938 TR |
774 | "sata-0", |
775 | }; | |
776 | ||
777 | static const char * const tegra124_rsvd_groups[] = { | |
778 | "otg-0", | |
779 | "otg-1", | |
780 | "otg-2", | |
781 | "pcie-0", | |
782 | "pcie-1", | |
783 | "pcie-2", | |
784 | "pcie-3", | |
785 | "pcie-4", | |
786 | "sata-0", | |
787 | }; | |
788 | ||
789 | #define TEGRA124_FUNCTION(_name) \ | |
790 | { \ | |
791 | .name = #_name, \ | |
792 | .num_groups = ARRAY_SIZE(tegra124_##_name##_groups), \ | |
793 | .groups = tegra124_##_name##_groups, \ | |
794 | } | |
795 | ||
796 | static struct tegra_xusb_padctl_function tegra124_functions[] = { | |
797 | TEGRA124_FUNCTION(snps), | |
798 | TEGRA124_FUNCTION(xusb), | |
799 | TEGRA124_FUNCTION(uart), | |
800 | TEGRA124_FUNCTION(pcie), | |
801 | TEGRA124_FUNCTION(usb3), | |
802 | TEGRA124_FUNCTION(sata), | |
803 | TEGRA124_FUNCTION(rsvd), | |
804 | }; | |
805 | ||
806 | enum tegra124_function { | |
807 | TEGRA124_FUNC_SNPS, | |
808 | TEGRA124_FUNC_XUSB, | |
809 | TEGRA124_FUNC_UART, | |
810 | TEGRA124_FUNC_PCIE, | |
811 | TEGRA124_FUNC_USB3, | |
812 | TEGRA124_FUNC_SATA, | |
813 | TEGRA124_FUNC_RSVD, | |
814 | }; | |
815 | ||
816 | static const unsigned int tegra124_otg_functions[] = { | |
817 | TEGRA124_FUNC_SNPS, | |
818 | TEGRA124_FUNC_XUSB, | |
819 | TEGRA124_FUNC_UART, | |
820 | TEGRA124_FUNC_RSVD, | |
821 | }; | |
822 | ||
823 | static const unsigned int tegra124_usb_functions[] = { | |
824 | TEGRA124_FUNC_SNPS, | |
825 | TEGRA124_FUNC_XUSB, | |
826 | }; | |
827 | ||
828 | static const unsigned int tegra124_pci_functions[] = { | |
829 | TEGRA124_FUNC_PCIE, | |
830 | TEGRA124_FUNC_USB3, | |
831 | TEGRA124_FUNC_SATA, | |
832 | TEGRA124_FUNC_RSVD, | |
833 | }; | |
834 | ||
835 | #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ | |
836 | { \ | |
837 | .name = _name, \ | |
838 | .offset = _offset, \ | |
839 | .shift = _shift, \ | |
840 | .mask = _mask, \ | |
841 | .iddq = _iddq, \ | |
842 | .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \ | |
843 | .funcs = tegra124_##_funcs##_functions, \ | |
844 | } | |
845 | ||
846 | static const struct tegra_xusb_padctl_lane tegra124_lanes[] = { | |
847 | TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg), | |
848 | TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg), | |
849 | TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg), | |
850 | TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb), | |
851 | TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb), | |
852 | TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb), | |
853 | TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci), | |
854 | TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci), | |
855 | TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci), | |
856 | TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci), | |
857 | TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci), | |
858 | TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci), | |
859 | }; | |
860 | ||
861 | static const struct tegra_xusb_padctl_soc tegra124_soc = { | |
862 | .num_pins = ARRAY_SIZE(tegra124_pins), | |
863 | .pins = tegra124_pins, | |
864 | .num_functions = ARRAY_SIZE(tegra124_functions), | |
865 | .functions = tegra124_functions, | |
866 | .num_lanes = ARRAY_SIZE(tegra124_lanes), | |
867 | .lanes = tegra124_lanes, | |
868 | }; | |
869 | ||
870 | static const struct of_device_id tegra_xusb_padctl_of_match[] = { | |
871 | { .compatible = "nvidia,tegra124-xusb-padctl", .data = &tegra124_soc }, | |
872 | { } | |
873 | }; | |
874 | MODULE_DEVICE_TABLE(of, tegra_xusb_padctl_of_match); | |
875 | ||
876 | static int tegra_xusb_padctl_probe(struct platform_device *pdev) | |
877 | { | |
878 | struct tegra_xusb_padctl *padctl; | |
879 | const struct of_device_id *match; | |
880 | struct resource *res; | |
881 | struct phy *phy; | |
882 | int err; | |
883 | ||
884 | padctl = devm_kzalloc(&pdev->dev, sizeof(*padctl), GFP_KERNEL); | |
885 | if (!padctl) | |
886 | return -ENOMEM; | |
887 | ||
888 | platform_set_drvdata(pdev, padctl); | |
889 | mutex_init(&padctl->lock); | |
890 | padctl->dev = &pdev->dev; | |
891 | ||
892 | match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node); | |
893 | padctl->soc = match->data; | |
894 | ||
895 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
896 | padctl->regs = devm_ioremap_resource(&pdev->dev, res); | |
897 | if (IS_ERR(padctl->regs)) | |
898 | return PTR_ERR(padctl->regs); | |
899 | ||
900 | padctl->rst = devm_reset_control_get(&pdev->dev, NULL); | |
901 | if (IS_ERR(padctl->rst)) | |
902 | return PTR_ERR(padctl->rst); | |
903 | ||
904 | err = reset_control_deassert(padctl->rst); | |
905 | if (err < 0) | |
906 | return err; | |
907 | ||
908 | memset(&padctl->desc, 0, sizeof(padctl->desc)); | |
909 | padctl->desc.name = dev_name(padctl->dev); | |
8480c2e7 JH |
910 | padctl->desc.pins = tegra124_pins; |
911 | padctl->desc.npins = ARRAY_SIZE(tegra124_pins); | |
dc0a3938 TR |
912 | padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops; |
913 | padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops; | |
914 | padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops; | |
915 | padctl->desc.owner = THIS_MODULE; | |
916 | ||
917 | padctl->pinctrl = pinctrl_register(&padctl->desc, &pdev->dev, padctl); | |
323de9ef | 918 | if (IS_ERR(padctl->pinctrl)) { |
dc0a3938 | 919 | dev_err(&pdev->dev, "failed to register pincontrol\n"); |
323de9ef | 920 | err = PTR_ERR(padctl->pinctrl); |
dc0a3938 TR |
921 | goto reset; |
922 | } | |
923 | ||
dbc98635 | 924 | phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops); |
dc0a3938 TR |
925 | if (IS_ERR(phy)) { |
926 | err = PTR_ERR(phy); | |
927 | goto unregister; | |
928 | } | |
929 | ||
930 | padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; | |
931 | phy_set_drvdata(phy, padctl); | |
932 | ||
dbc98635 | 933 | phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops); |
dc0a3938 TR |
934 | if (IS_ERR(phy)) { |
935 | err = PTR_ERR(phy); | |
936 | goto unregister; | |
937 | } | |
938 | ||
939 | padctl->phys[TEGRA_XUSB_PADCTL_SATA] = phy; | |
940 | phy_set_drvdata(phy, padctl); | |
941 | ||
942 | padctl->provider = devm_of_phy_provider_register(&pdev->dev, | |
943 | tegra_xusb_padctl_xlate); | |
8a3cfb7c DC |
944 | if (IS_ERR(padctl->provider)) { |
945 | err = PTR_ERR(padctl->provider); | |
dc0a3938 TR |
946 | dev_err(&pdev->dev, "failed to register PHYs: %d\n", err); |
947 | goto unregister; | |
948 | } | |
949 | ||
950 | return 0; | |
951 | ||
952 | unregister: | |
953 | pinctrl_unregister(padctl->pinctrl); | |
954 | reset: | |
955 | reset_control_assert(padctl->rst); | |
956 | return err; | |
957 | } | |
958 | ||
959 | static int tegra_xusb_padctl_remove(struct platform_device *pdev) | |
960 | { | |
961 | struct tegra_xusb_padctl *padctl = platform_get_drvdata(pdev); | |
962 | int err; | |
963 | ||
964 | pinctrl_unregister(padctl->pinctrl); | |
965 | ||
966 | err = reset_control_assert(padctl->rst); | |
967 | if (err < 0) | |
968 | dev_err(&pdev->dev, "failed to assert reset: %d\n", err); | |
969 | ||
970 | return err; | |
971 | } | |
972 | ||
973 | static struct platform_driver tegra_xusb_padctl_driver = { | |
974 | .driver = { | |
975 | .name = "tegra-xusb-padctl", | |
976 | .of_match_table = tegra_xusb_padctl_of_match, | |
977 | }, | |
978 | .probe = tegra_xusb_padctl_probe, | |
979 | .remove = tegra_xusb_padctl_remove, | |
980 | }; | |
981 | module_platform_driver(tegra_xusb_padctl_driver); | |
982 | ||
983 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
984 | MODULE_DESCRIPTION("Tegra 124 XUSB Pad Control driver"); | |
985 | MODULE_LICENSE("GPL v2"); |