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1 | /* |
2 | * Driver for the NVIDIA Tegra pinmux | |
3 | * | |
4 | * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | */ | |
15 | ||
16 | #ifndef __PINMUX_TEGRA_H__ | |
17 | #define __PINMUX_TEGRA_H__ | |
18 | ||
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19 | enum tegra_pinconf_param { |
20 | /* argument: tegra_pinconf_pull */ | |
21 | TEGRA_PINCONF_PARAM_PULL, | |
22 | /* argument: tegra_pinconf_tristate */ | |
23 | TEGRA_PINCONF_PARAM_TRISTATE, | |
24 | /* argument: Boolean */ | |
25 | TEGRA_PINCONF_PARAM_ENABLE_INPUT, | |
26 | /* argument: Boolean */ | |
27 | TEGRA_PINCONF_PARAM_OPEN_DRAIN, | |
28 | /* argument: Boolean */ | |
29 | TEGRA_PINCONF_PARAM_LOCK, | |
30 | /* argument: Boolean */ | |
31 | TEGRA_PINCONF_PARAM_IORESET, | |
32 | /* argument: Boolean */ | |
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33 | TEGRA_PINCONF_PARAM_RCV_SEL, |
34 | /* argument: Boolean */ | |
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35 | TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, |
36 | /* argument: Boolean */ | |
37 | TEGRA_PINCONF_PARAM_SCHMITT, | |
38 | /* argument: Boolean */ | |
39 | TEGRA_PINCONF_PARAM_LOW_POWER_MODE, | |
40 | /* argument: Integer, range is HW-dependant */ | |
41 | TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, | |
42 | /* argument: Integer, range is HW-dependant */ | |
43 | TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, | |
44 | /* argument: Integer, range is HW-dependant */ | |
45 | TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, | |
46 | /* argument: Integer, range is HW-dependant */ | |
47 | TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, | |
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48 | /* argument: Integer, range is HW-dependant */ |
49 | TEGRA_PINCONF_PARAM_DRIVE_TYPE, | |
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50 | }; |
51 | ||
52 | enum tegra_pinconf_pull { | |
53 | TEGRA_PINCONFIG_PULL_NONE, | |
54 | TEGRA_PINCONFIG_PULL_DOWN, | |
55 | TEGRA_PINCONFIG_PULL_UP, | |
56 | }; | |
57 | ||
58 | enum tegra_pinconf_tristate { | |
59 | TEGRA_PINCONFIG_DRIVEN, | |
60 | TEGRA_PINCONFIG_TRISTATE, | |
61 | }; | |
62 | ||
63 | #define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) | |
64 | #define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) | |
65 | #define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) | |
66 | ||
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67 | /** |
68 | * struct tegra_function - Tegra pinctrl mux function | |
69 | * @name: The name of the function, exported to pinctrl core. | |
70 | * @groups: An array of pin groups that may select this function. | |
71 | * @ngroups: The number of entries in @groups. | |
72 | */ | |
73 | struct tegra_function { | |
74 | const char *name; | |
75 | const char * const *groups; | |
76 | unsigned ngroups; | |
77 | }; | |
78 | ||
79 | /** | |
80 | * struct tegra_pingroup - Tegra pin group | |
81 | * @mux_reg: Mux register offset. -1 if unsupported. | |
82 | * @mux_bank: Mux register bank. 0 if unsupported. | |
83 | * @mux_bit: Mux register bit. 0 if unsupported. | |
84 | * @pupd_reg: Pull-up/down register offset. -1 if unsupported. | |
85 | * @pupd_bank: Pull-up/down register bank. 0 if unsupported. | |
86 | * @pupd_bit: Pull-up/down register bit. 0 if unsupported. | |
87 | * @tri_reg: Tri-state register offset. -1 if unsupported. | |
88 | * @tri_bank: Tri-state register bank. 0 if unsupported. | |
89 | * @tri_bit: Tri-state register bit. 0 if unsupported. | |
90 | * @einput_reg: Enable-input register offset. -1 if unsupported. | |
91 | * @einput_bank: Enable-input register bank. 0 if unsupported. | |
92 | * @einput_bit: Enable-input register bit. 0 if unsupported. | |
93 | * @odrain_reg: Open-drain register offset. -1 if unsupported. | |
94 | * @odrain_bank: Open-drain register bank. 0 if unsupported. | |
95 | * @odrain_bit: Open-drain register bit. 0 if unsupported. | |
96 | * @lock_reg: Lock register offset. -1 if unsupported. | |
97 | * @lock_bank: Lock register bank. 0 if unsupported. | |
98 | * @lock_bit: Lock register bit. 0 if unsupported. | |
99 | * @ioreset_reg: IO reset register offset. -1 if unsupported. | |
100 | * @ioreset_bank: IO reset register bank. 0 if unsupported. | |
101 | * @ioreset_bit: IO reset register bit. 0 if unsupported. | |
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102 | * @rcv_sel_reg: Receiver select offset. -1 if unsupported. |
103 | * @rcv_sel_bank: Receiver select bank. 0 if unsupported. | |
104 | * @rcv_sel_bit: Receiver select bit. 0 if unsupported. | |
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105 | * @drv_reg: Drive fields register offset. -1 if unsupported. |
106 | * This register contains the hsm, schmitt, lpmd, drvdn, | |
107 | * drvup, slwr, and slwf parameters. | |
108 | * @drv_bank: Drive fields register bank. 0 if unsupported. | |
109 | * @hsm_bit: High Speed Mode register bit. 0 if unsupported. | |
110 | * @schmitt_bit: Scmitt register bit. 0 if unsupported. | |
111 | * @lpmd_bit: Low Power Mode register bit. 0 if unsupported. | |
112 | * @drvdn_bit: Drive Down register bit. 0 if unsupported. | |
113 | * @drvdn_width: Drive Down field width. 0 if unsupported. | |
114 | * @drvup_bit: Drive Up register bit. 0 if unsupported. | |
115 | * @drvup_width: Drive Up field width. 0 if unsupported. | |
116 | * @slwr_bit: Slew Rising register bit. 0 if unsupported. | |
117 | * @slwr_width: Slew Rising field width. 0 if unsupported. | |
118 | * @slwf_bit: Slew Falling register bit. 0 if unsupported. | |
119 | * @slwf_width: Slew Falling field width. 0 if unsupported. | |
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120 | * @drvtype_reg: Drive type fields register offset. -1 if unsupported. |
121 | * @drvtype_bank: Drive type fields register bank. 0 if unsupported. | |
122 | * @drvtype_bit: Drive type register bit. 0 if unsupported. | |
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123 | * |
124 | * A representation of a group of pins (possibly just one pin) in the Tegra | |
125 | * pin controller. Each group allows some parameter or parameters to be | |
126 | * configured. The most common is mux function selection. Many others exist | |
127 | * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; | |
128 | * certain groups may only support configuring certain parameters, hence | |
129 | * each parameter is optional, represented by a -1 "reg" value. | |
130 | */ | |
131 | struct tegra_pingroup { | |
132 | const char *name; | |
133 | const unsigned *pins; | |
134 | unsigned npins; | |
135 | unsigned funcs[4]; | |
136 | unsigned func_safe; | |
137 | s16 mux_reg; | |
138 | s16 pupd_reg; | |
139 | s16 tri_reg; | |
140 | s16 einput_reg; | |
141 | s16 odrain_reg; | |
142 | s16 lock_reg; | |
143 | s16 ioreset_reg; | |
348d1bf7 | 144 | s16 rcv_sel_reg; |
971dac71 | 145 | s16 drv_reg; |
348d1bf7 | 146 | s16 drvtype_reg; |
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147 | u32 mux_bank:2; |
148 | u32 pupd_bank:2; | |
149 | u32 tri_bank:2; | |
150 | u32 einput_bank:2; | |
151 | u32 odrain_bank:2; | |
152 | u32 ioreset_bank:2; | |
348d1bf7 | 153 | u32 rcv_sel_bank:2; |
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154 | u32 lock_bank:2; |
155 | u32 drv_bank:2; | |
348d1bf7 | 156 | u32 drvtype_bank:2; |
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157 | u32 mux_bit:5; |
158 | u32 pupd_bit:5; | |
159 | u32 tri_bit:5; | |
160 | u32 einput_bit:5; | |
161 | u32 odrain_bit:5; | |
162 | u32 lock_bit:5; | |
163 | u32 ioreset_bit:5; | |
348d1bf7 | 164 | u32 rcv_sel_bit:5; |
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165 | u32 hsm_bit:5; |
166 | u32 schmitt_bit:5; | |
167 | u32 lpmd_bit:5; | |
168 | u32 drvdn_bit:5; | |
169 | u32 drvup_bit:5; | |
170 | u32 slwr_bit:5; | |
171 | u32 slwf_bit:5; | |
348d1bf7 | 172 | u32 drvtype_bit:5; |
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173 | u32 drvdn_width:6; |
174 | u32 drvup_width:6; | |
175 | u32 slwr_width:6; | |
176 | u32 slwf_width:6; | |
177 | }; | |
178 | ||
179 | /** | |
180 | * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration | |
181 | * @ngpios: The number of GPIO pins the pin controller HW affects. | |
182 | * @pins: An array describing all pins the pin controller affects. | |
183 | * All pins which are also GPIOs must be listed first within the | |
184 | * array, and be numbered identically to the GPIO controller's | |
185 | * numbering. | |
186 | * @npins: The numbmer of entries in @pins. | |
187 | * @functions: An array describing all mux functions the SoC supports. | |
188 | * @nfunctions: The numbmer of entries in @functions. | |
189 | * @groups: An array describing all pin groups the pin SoC supports. | |
190 | * @ngroups: The numbmer of entries in @groups. | |
191 | */ | |
192 | struct tegra_pinctrl_soc_data { | |
193 | unsigned ngpios; | |
194 | const struct pinctrl_pin_desc *pins; | |
195 | unsigned npins; | |
196 | const struct tegra_function *functions; | |
197 | unsigned nfunctions; | |
198 | const struct tegra_pingroup *groups; | |
199 | unsigned ngroups; | |
200 | }; | |
201 | ||
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202 | int tegra_pinctrl_probe(struct platform_device *pdev, |
203 | const struct tegra_pinctrl_soc_data *soc_data); | |
204 | int tegra_pinctrl_remove(struct platform_device *pdev); | |
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205 | |
206 | #endif |