Commit | Line | Data |
---|---|---|
b58f0273 JH |
1 | /* |
2 | * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins | |
3 | * | |
4 | * Copyright (c) 2013, Imagination Technologies Ltd. | |
5 | * | |
6 | * Derived from Tegra code: | |
7 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. | |
8 | * | |
9 | * Derived from code: | |
10 | * Copyright (C) 2010 Google, Inc. | |
11 | * Copyright (C) 2010 NVIDIA Corporation | |
12 | * Copyright (C) 2009-2011 ST-Ericsson AB | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms and conditions of the GNU General Public License, | |
16 | * version 2, as published by the Free Software Foundation. | |
17 | * | |
18 | * This program is distributed in the hope it will be useful, but WITHOUT | |
19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
21 | * more details. | |
22 | */ | |
23 | ||
24 | #include <linux/bitops.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/of.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/pinctrl/machine.h> | |
30 | #include <linux/pinctrl/pinconf-generic.h> | |
31 | #include <linux/pinctrl/pinctrl.h> | |
32 | #include <linux/pinctrl/pinmux.h> | |
33 | #include <linux/slab.h> | |
34 | ||
35 | /* | |
36 | * The registers may be shared with other threads/cores, so we need to use the | |
37 | * metag global lock2 for atomicity. | |
38 | */ | |
39 | #include <asm/global_lock.h> | |
40 | ||
41 | #include "core.h" | |
42 | #include "pinconf.h" | |
43 | ||
44 | /* Register offsets from bank base address */ | |
45 | #define REG_GPIO_CONTROL0 0x00 | |
46 | #define REG_GPIO_CONTROL2 0x08 | |
47 | ||
48 | /* Register field information */ | |
49 | #define REG_GPIO_CONTROL2_PU_PD_S 16 | |
50 | #define REG_GPIO_CONTROL2_PDC_POS_S 4 | |
51 | #define REG_GPIO_CONTROL2_PDC_DR_S 2 | |
52 | #define REG_GPIO_CONTROL2_PDC_SR_S 1 | |
53 | #define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0 | |
54 | ||
55 | /* PU_PD field values */ | |
56 | #define REG_PU_PD_TRISTATE 0 | |
57 | #define REG_PU_PD_UP 1 | |
58 | #define REG_PU_PD_DOWN 2 | |
59 | #define REG_PU_PD_REPEATER 3 | |
60 | ||
61 | /* DR field values */ | |
62 | #define REG_DR_2mA 0 | |
63 | #define REG_DR_4mA 1 | |
64 | #define REG_DR_8mA 2 | |
65 | #define REG_DR_12mA 3 | |
66 | ||
67 | /** | |
68 | * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function | |
69 | * @name: The name of the function, exported to pinctrl core. | |
70 | * @groups: An array of pin groups that may select this function. | |
71 | * @ngroups: The number of entries in @groups. | |
72 | */ | |
73 | struct tz1090_pdc_function { | |
74 | const char *name; | |
75 | const char * const *groups; | |
76 | unsigned int ngroups; | |
77 | }; | |
78 | ||
79 | /** | |
80 | * struct tz1090_pdc_pingroup - TZ1090 PDC pin group | |
81 | * @name: Name of pin group. | |
82 | * @pins: Array of pin numbers in this pin group. | |
83 | * @npins: Number of pins in this pin group. | |
84 | * @func: Function enabled by the mux. | |
85 | * @reg: Mux register offset. | |
86 | * @bit: Mux register bit. | |
87 | * @drv: Drive control supported, otherwise it's a mux. | |
88 | * This means Schmitt, Slew, and Drive strength. | |
89 | * | |
90 | * A representation of a group of pins (possibly just one pin) in the TZ1090 | |
91 | * PDC pin controller. Each group allows some parameter or parameters to be | |
92 | * configured. The most common is mux function selection. | |
93 | */ | |
94 | struct tz1090_pdc_pingroup { | |
95 | const char *name; | |
96 | const unsigned int *pins; | |
97 | unsigned int npins; | |
98 | int func; | |
99 | u16 reg; | |
100 | u8 bit; | |
101 | bool drv; | |
102 | }; | |
103 | ||
104 | /* | |
105 | * All PDC pins can be GPIOs. Define these first to match how the GPIO driver | |
106 | * names/numbers its pins. | |
107 | */ | |
108 | ||
109 | enum tz1090_pdc_pin { | |
110 | TZ1090_PDC_PIN_GPIO0, | |
111 | TZ1090_PDC_PIN_GPIO1, | |
112 | TZ1090_PDC_PIN_SYS_WAKE0, | |
113 | TZ1090_PDC_PIN_SYS_WAKE1, | |
114 | TZ1090_PDC_PIN_SYS_WAKE2, | |
115 | TZ1090_PDC_PIN_IR_DATA, | |
116 | TZ1090_PDC_PIN_EXT_POWER, | |
117 | }; | |
118 | ||
119 | /* Pin names */ | |
120 | ||
121 | static const struct pinctrl_pin_desc tz1090_pdc_pins[] = { | |
122 | /* PDC GPIOs */ | |
123 | PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"), | |
124 | PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"), | |
125 | PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"), | |
126 | PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"), | |
127 | PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"), | |
128 | PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"), | |
129 | PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"), | |
130 | }; | |
131 | ||
132 | /* Pin group pins */ | |
133 | ||
134 | static const unsigned int gpio0_pins[] = { | |
135 | TZ1090_PDC_PIN_GPIO0, | |
136 | }; | |
137 | ||
138 | static const unsigned int gpio1_pins[] = { | |
139 | TZ1090_PDC_PIN_GPIO1, | |
140 | }; | |
141 | ||
142 | static const unsigned int pdc_pins[] = { | |
143 | TZ1090_PDC_PIN_GPIO0, | |
144 | TZ1090_PDC_PIN_GPIO1, | |
145 | TZ1090_PDC_PIN_SYS_WAKE0, | |
146 | TZ1090_PDC_PIN_SYS_WAKE1, | |
147 | TZ1090_PDC_PIN_SYS_WAKE2, | |
148 | TZ1090_PDC_PIN_IR_DATA, | |
149 | TZ1090_PDC_PIN_EXT_POWER, | |
150 | }; | |
151 | ||
152 | /* Mux functions */ | |
153 | ||
154 | enum tz1090_pdc_mux { | |
155 | /* PDC_GPIO0 mux */ | |
156 | TZ1090_PDC_MUX_IR_MOD_STABLE_OUT, | |
157 | /* PDC_GPIO1 mux */ | |
158 | TZ1090_PDC_MUX_IR_MOD_POWER_OUT, | |
159 | }; | |
160 | ||
161 | /* Pin groups a function can be muxed to */ | |
162 | ||
163 | static const char * const gpio0_groups[] = { | |
164 | "gpio0", | |
165 | }; | |
166 | ||
167 | static const char * const gpio1_groups[] = { | |
168 | "gpio1", | |
169 | }; | |
170 | ||
171 | #define FUNCTION(mux, fname, group) \ | |
172 | [(TZ1090_PDC_MUX_ ## mux)] = { \ | |
173 | .name = #fname, \ | |
174 | .groups = group##_groups, \ | |
175 | .ngroups = ARRAY_SIZE(group##_groups), \ | |
176 | } | |
177 | ||
178 | /* Must correlate with enum tz1090_pdc_mux */ | |
179 | static const struct tz1090_pdc_function tz1090_pdc_functions[] = { | |
180 | /* MUX fn pingroups */ | |
181 | FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0), | |
182 | FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1), | |
183 | }; | |
184 | ||
185 | /** | |
186 | * MUX_PG() - Initialise a pin group with mux control | |
187 | * @pg_name: Pin group name (stringified, _pins appended to get pins array) | |
188 | * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended) | |
189 | * @mux_r: Mux register (REG_PINCTRL_ is prepended) | |
190 | * @mux_b: Bit number in register of mux field | |
191 | */ | |
192 | #define MUX_PG(pg_name, f0, mux_r, mux_b) \ | |
193 | { \ | |
194 | .name = #pg_name, \ | |
195 | .pins = pg_name##_pins, \ | |
196 | .npins = ARRAY_SIZE(pg_name##_pins), \ | |
197 | .func = TZ1090_PDC_MUX_ ## f0, \ | |
198 | .reg = (REG_ ## mux_r), \ | |
199 | .bit = (mux_b), \ | |
200 | } | |
201 | ||
202 | /** | |
203 | * DRV_PG() - Initialise a pin group with drive control | |
204 | * @pg_name: Pin group name (stringified, _pins appended to get pins array) | |
205 | */ | |
206 | #define DRV_PG(pg_name) \ | |
207 | { \ | |
208 | .name = #pg_name, \ | |
209 | .pins = pg_name##_pins, \ | |
210 | .npins = ARRAY_SIZE(pg_name##_pins), \ | |
211 | .drv = true, \ | |
212 | } | |
213 | ||
214 | static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = { | |
215 | /* Muxing pin groups */ | |
216 | /* pg_name, f0, mux register, mux bit */ | |
217 | MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7), | |
218 | MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6), | |
219 | ||
220 | /* Drive pin groups */ | |
221 | /* pg_name */ | |
222 | DRV_PG(pdc), | |
223 | }; | |
224 | ||
225 | /** | |
226 | * struct tz1090_pdc_pmx - Private pinctrl data | |
227 | * @dev: Platform device | |
228 | * @pctl: Pin control device | |
229 | * @regs: Register region | |
230 | * @lock: Lock protecting coherency of mux_en and gpio_en | |
231 | * @mux_en: Muxes that have been enabled | |
232 | * @gpio_en: Muxable GPIOs that have been enabled | |
233 | */ | |
234 | struct tz1090_pdc_pmx { | |
235 | struct device *dev; | |
236 | struct pinctrl_dev *pctl; | |
237 | void __iomem *regs; | |
238 | spinlock_t lock; | |
239 | u32 mux_en; | |
240 | u32 gpio_en; | |
241 | }; | |
242 | ||
243 | static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg) | |
244 | { | |
245 | return ioread32(pmx->regs + reg); | |
246 | } | |
247 | ||
248 | static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg) | |
249 | { | |
250 | iowrite32(val, pmx->regs + reg); | |
251 | } | |
252 | ||
253 | /* | |
254 | * Pin control operations | |
255 | */ | |
256 | ||
257 | static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
258 | { | |
259 | return ARRAY_SIZE(tz1090_pdc_groups); | |
260 | } | |
261 | ||
262 | static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl, | |
263 | unsigned int group) | |
264 | { | |
265 | return tz1090_pdc_groups[group].name; | |
266 | } | |
267 | ||
268 | static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
269 | unsigned int group, | |
270 | const unsigned int **pins, | |
271 | unsigned int *num_pins) | |
272 | { | |
273 | *pins = tz1090_pdc_groups[group].pins; | |
274 | *num_pins = tz1090_pdc_groups[group].npins; | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | #ifdef CONFIG_DEBUG_FS | |
280 | static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, | |
281 | struct seq_file *s, | |
282 | unsigned int offset) | |
283 | { | |
284 | seq_printf(s, " %s", dev_name(pctldev->dev)); | |
285 | } | |
286 | #endif | |
287 | ||
288 | static int reserve_map(struct device *dev, struct pinctrl_map **map, | |
289 | unsigned int *reserved_maps, unsigned int *num_maps, | |
290 | unsigned int reserve) | |
291 | { | |
292 | unsigned int old_num = *reserved_maps; | |
293 | unsigned int new_num = *num_maps + reserve; | |
294 | struct pinctrl_map *new_map; | |
295 | ||
296 | if (old_num >= new_num) | |
297 | return 0; | |
298 | ||
299 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | |
300 | if (!new_map) { | |
301 | dev_err(dev, "krealloc(map) failed\n"); | |
302 | return -ENOMEM; | |
303 | } | |
304 | ||
305 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | |
306 | ||
307 | *map = new_map; | |
308 | *reserved_maps = new_num; | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, | |
314 | unsigned int *num_maps, const char *group, | |
315 | const char *function) | |
316 | { | |
317 | if (WARN_ON(*num_maps == *reserved_maps)) | |
318 | return -ENOSPC; | |
319 | ||
320 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
321 | (*map)[*num_maps].data.mux.group = group; | |
322 | (*map)[*num_maps].data.mux.function = function; | |
323 | (*num_maps)++; | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | /** | |
329 | * get_group_selector() - returns the group selector for a group | |
330 | * @pin_group: the pin group to look up | |
331 | * | |
332 | * This is the same as pinctrl_get_group_selector except it doesn't produce an | |
333 | * error message if the group isn't found or debug messages. | |
334 | */ | |
335 | static int get_group_selector(const char *pin_group) | |
336 | { | |
337 | unsigned int group; | |
338 | ||
339 | for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group) | |
340 | if (!strcmp(tz1090_pdc_groups[group].name, pin_group)) | |
341 | return group; | |
342 | ||
343 | return -EINVAL; | |
344 | } | |
345 | ||
346 | static int add_map_configs(struct device *dev, | |
347 | struct pinctrl_map **map, | |
348 | unsigned int *reserved_maps, unsigned int *num_maps, | |
349 | const char *group, unsigned long *configs, | |
350 | unsigned int num_configs) | |
351 | { | |
352 | unsigned long *dup_configs; | |
353 | enum pinctrl_map_type type; | |
354 | ||
355 | if (WARN_ON(*num_maps == *reserved_maps)) | |
356 | return -ENOSPC; | |
357 | ||
358 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
359 | GFP_KERNEL); | |
360 | if (!dup_configs) { | |
361 | dev_err(dev, "kmemdup(configs) failed\n"); | |
362 | return -ENOMEM; | |
363 | } | |
364 | ||
365 | /* | |
366 | * We support both pins and pin groups, but we need to figure out which | |
367 | * one we have. | |
368 | */ | |
369 | if (get_group_selector(group) >= 0) | |
370 | type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
371 | else | |
372 | type = PIN_MAP_TYPE_CONFIGS_PIN; | |
373 | (*map)[*num_maps].type = type; | |
374 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
375 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
376 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
377 | (*num_maps)++; | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, | |
383 | struct pinctrl_map *map, | |
384 | unsigned int num_maps) | |
385 | { | |
386 | int i; | |
387 | ||
388 | for (i = 0; i < num_maps; i++) | |
389 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) | |
390 | kfree(map[i].data.configs.configs); | |
391 | ||
392 | kfree(map); | |
393 | } | |
394 | ||
395 | static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, | |
396 | struct device_node *np, | |
397 | struct pinctrl_map **map, | |
398 | unsigned int *reserved_maps, | |
399 | unsigned int *num_maps) | |
400 | { | |
401 | int ret; | |
402 | const char *function; | |
403 | unsigned long *configs = NULL; | |
404 | unsigned int num_configs = 0; | |
405 | unsigned int reserve; | |
406 | struct property *prop; | |
407 | const char *group; | |
408 | ||
409 | ret = of_property_read_string(np, "tz1090,function", &function); | |
410 | if (ret < 0) { | |
411 | /* EINVAL=missing, which is fine since it's optional */ | |
412 | if (ret != -EINVAL) | |
413 | dev_err(dev, | |
414 | "could not parse property function\n"); | |
415 | function = NULL; | |
416 | } | |
417 | ||
418 | ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); | |
419 | if (ret) | |
420 | return ret; | |
421 | ||
422 | reserve = 0; | |
423 | if (function != NULL) | |
424 | reserve++; | |
425 | if (num_configs) | |
426 | reserve++; | |
427 | ret = of_property_count_strings(np, "tz1090,pins"); | |
428 | if (ret < 0) { | |
429 | dev_err(dev, "could not parse property pins\n"); | |
430 | goto exit; | |
431 | } | |
432 | reserve *= ret; | |
433 | ||
434 | ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); | |
435 | if (ret < 0) | |
436 | goto exit; | |
437 | ||
438 | of_property_for_each_string(np, "tz1090,pins", prop, group) { | |
439 | if (function) { | |
440 | ret = add_map_mux(map, reserved_maps, num_maps, | |
441 | group, function); | |
442 | if (ret < 0) | |
443 | goto exit; | |
444 | } | |
445 | ||
446 | if (num_configs) { | |
447 | ret = add_map_configs(dev, map, reserved_maps, | |
448 | num_maps, group, configs, | |
449 | num_configs); | |
450 | if (ret < 0) | |
451 | goto exit; | |
452 | } | |
453 | } | |
454 | ||
455 | ret = 0; | |
456 | ||
457 | exit: | |
458 | kfree(configs); | |
459 | return ret; | |
460 | } | |
461 | ||
462 | static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
463 | struct device_node *np_config, | |
464 | struct pinctrl_map **map, | |
465 | unsigned int *num_maps) | |
466 | { | |
467 | unsigned int reserved_maps; | |
468 | struct device_node *np; | |
469 | int ret; | |
470 | ||
471 | reserved_maps = 0; | |
472 | *map = NULL; | |
473 | *num_maps = 0; | |
474 | ||
475 | for_each_child_of_node(np_config, np) { | |
476 | ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np, | |
477 | map, &reserved_maps, | |
478 | num_maps); | |
479 | if (ret < 0) { | |
480 | tz1090_pdc_pinctrl_dt_free_map(pctldev, *map, | |
481 | *num_maps); | |
482 | return ret; | |
483 | } | |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static struct pinctrl_ops tz1090_pdc_pinctrl_ops = { | |
490 | .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, | |
491 | .get_group_name = tz1090_pdc_pinctrl_get_group_name, | |
492 | .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, | |
493 | #ifdef CONFIG_DEBUG_FS | |
494 | .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show, | |
495 | #endif | |
496 | .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map, | |
497 | .dt_free_map = tz1090_pdc_pinctrl_dt_free_map, | |
498 | }; | |
499 | ||
500 | /* | |
501 | * Pin mux operations | |
502 | */ | |
503 | ||
504 | static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) | |
505 | { | |
506 | return ARRAY_SIZE(tz1090_pdc_functions); | |
507 | } | |
508 | ||
509 | static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev, | |
510 | unsigned int function) | |
511 | { | |
512 | return tz1090_pdc_functions[function].name; | |
513 | } | |
514 | ||
515 | static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, | |
516 | unsigned int function, | |
517 | const char * const **groups, | |
518 | unsigned int * const num_groups) | |
519 | { | |
520 | *groups = tz1090_pdc_functions[function].groups; | |
521 | *num_groups = tz1090_pdc_functions[function].ngroups; | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | /** | |
527 | * tz1090_pdc_pinctrl_mux() - update mux bit | |
528 | * @pmx: Pinmux data | |
529 | * @grp: Pin mux group | |
530 | */ | |
531 | static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, | |
532 | const struct tz1090_pdc_pingroup *grp) | |
533 | { | |
534 | u32 reg, select; | |
535 | unsigned int pin_shift = grp->pins[0]; | |
536 | unsigned long flags; | |
537 | ||
538 | /* select = mux && !gpio */ | |
539 | select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1; | |
540 | ||
541 | /* set up the mux */ | |
542 | __global_lock2(flags); | |
543 | reg = pmx_read(pmx, grp->reg); | |
544 | reg &= ~BIT(grp->bit); | |
545 | reg |= select << grp->bit; | |
546 | pmx_write(pmx, reg, grp->reg); | |
547 | __global_unlock2(flags); | |
548 | } | |
549 | ||
03e9f0ca LW |
550 | static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev, |
551 | unsigned int function, | |
552 | unsigned int group) | |
b58f0273 JH |
553 | { |
554 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
555 | const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; | |
556 | ||
557 | dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", | |
558 | __func__, | |
559 | function, tz1090_pdc_functions[function].name, | |
560 | group, tz1090_pdc_groups[group].name); | |
561 | ||
562 | /* is it even a mux? */ | |
563 | if (grp->drv) | |
564 | return -EINVAL; | |
565 | ||
566 | /* does this group even control the function? */ | |
567 | if (function != grp->func) | |
568 | return -EINVAL; | |
569 | ||
570 | /* record the pin being muxed and update mux bit */ | |
571 | spin_lock(&pmx->lock); | |
572 | pmx->mux_en |= BIT(grp->pins[0]); | |
573 | tz1090_pdc_pinctrl_mux(pmx, grp); | |
574 | spin_unlock(&pmx->lock); | |
575 | return 0; | |
576 | } | |
577 | ||
b58f0273 JH |
578 | static const struct tz1090_pdc_pingroup *find_mux_group( |
579 | struct tz1090_pdc_pmx *pmx, | |
580 | unsigned int pin) | |
581 | { | |
582 | const struct tz1090_pdc_pingroup *grp; | |
583 | unsigned int group; | |
584 | ||
585 | grp = tz1090_pdc_groups; | |
586 | for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) { | |
587 | /* only match muxes */ | |
588 | if (grp->drv) | |
589 | continue; | |
590 | ||
591 | /* with a matching pin */ | |
592 | if (grp->pins[0] == pin) | |
593 | return grp; | |
594 | } | |
595 | ||
596 | return NULL; | |
597 | } | |
598 | ||
599 | static int tz1090_pdc_pinctrl_gpio_request_enable( | |
600 | struct pinctrl_dev *pctldev, | |
601 | struct pinctrl_gpio_range *range, | |
602 | unsigned int pin) | |
603 | { | |
604 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
605 | const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); | |
606 | ||
607 | if (grp) { | |
608 | /* record the pin in GPIO use and update mux bit */ | |
609 | spin_lock(&pmx->lock); | |
610 | pmx->gpio_en |= BIT(pin); | |
611 | tz1090_pdc_pinctrl_mux(pmx, grp); | |
612 | spin_unlock(&pmx->lock); | |
613 | } | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static void tz1090_pdc_pinctrl_gpio_disable_free( | |
618 | struct pinctrl_dev *pctldev, | |
619 | struct pinctrl_gpio_range *range, | |
620 | unsigned int pin) | |
621 | { | |
622 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
623 | const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); | |
624 | ||
625 | if (grp) { | |
626 | /* record the pin not in GPIO use and update mux bit */ | |
627 | spin_lock(&pmx->lock); | |
628 | pmx->gpio_en &= ~BIT(pin); | |
629 | tz1090_pdc_pinctrl_mux(pmx, grp); | |
630 | spin_unlock(&pmx->lock); | |
631 | } | |
632 | } | |
633 | ||
634 | static struct pinmux_ops tz1090_pdc_pinmux_ops = { | |
635 | .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, | |
636 | .get_function_name = tz1090_pdc_pinctrl_get_func_name, | |
637 | .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, | |
03e9f0ca | 638 | .set_mux = tz1090_pdc_pinctrl_set_mux, |
b58f0273 JH |
639 | .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, |
640 | .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, | |
641 | }; | |
642 | ||
643 | /* | |
644 | * Pin config operations | |
645 | */ | |
646 | ||
647 | static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, | |
648 | unsigned int pin, | |
649 | enum pin_config_param param, | |
650 | bool report_err, | |
651 | u32 *reg, u32 *width, u32 *mask, u32 *shift, | |
652 | u32 *val) | |
653 | { | |
654 | /* Find information about parameter's register */ | |
655 | switch (param) { | |
656 | case PIN_CONFIG_BIAS_DISABLE: | |
657 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
658 | *val = REG_PU_PD_TRISTATE; | |
659 | break; | |
660 | case PIN_CONFIG_BIAS_PULL_UP: | |
661 | *val = REG_PU_PD_UP; | |
662 | break; | |
663 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
664 | *val = REG_PU_PD_DOWN; | |
665 | break; | |
666 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
667 | *val = REG_PU_PD_REPEATER; | |
668 | break; | |
669 | default: | |
670 | return -ENOTSUPP; | |
671 | }; | |
672 | ||
673 | /* Only input bias parameters supported */ | |
674 | *reg = REG_GPIO_CONTROL2; | |
675 | *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; | |
676 | *width = 2; | |
677 | ||
678 | /* Calculate field information */ | |
679 | *mask = (BIT(*width) - 1) << *shift; | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, | |
685 | unsigned int pin, unsigned long *config) | |
686 | { | |
687 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
688 | enum pin_config_param param = pinconf_to_config_param(*config); | |
689 | int ret; | |
690 | u32 reg, width, mask, shift, val, tmp, arg; | |
691 | ||
692 | /* Get register information */ | |
693 | ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, | |
694 | ®, &width, &mask, &shift, &val); | |
695 | if (ret < 0) | |
696 | return ret; | |
697 | ||
698 | /* Extract field from register */ | |
699 | tmp = pmx_read(pmx, reg); | |
700 | arg = ((tmp & mask) >> shift) == val; | |
701 | ||
702 | /* Config not active */ | |
703 | if (!arg) | |
704 | return -EINVAL; | |
705 | ||
706 | /* And pack config */ | |
707 | *config = pinconf_to_config_packed(param, arg); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
713 | unsigned int pin, unsigned long *configs, |
714 | unsigned num_configs) | |
b58f0273 JH |
715 | { |
716 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
03b054e9 SY |
717 | enum pin_config_param param; |
718 | unsigned int arg; | |
b58f0273 JH |
719 | int ret; |
720 | u32 reg, width, mask, shift, val, tmp; | |
721 | unsigned long flags; | |
03b054e9 | 722 | int i; |
b58f0273 | 723 | |
03b054e9 SY |
724 | for (i = 0; i < num_configs; i++) { |
725 | param = pinconf_to_config_param(configs[i]); | |
726 | arg = pinconf_to_config_argument(configs[i]); | |
b58f0273 | 727 | |
03b054e9 SY |
728 | dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", |
729 | __func__, tz1090_pdc_pins[pin].name, configs[i]); | |
b58f0273 | 730 | |
03b054e9 SY |
731 | /* Get register information */ |
732 | ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, | |
733 | ®, &width, &mask, &shift, &val); | |
734 | if (ret < 0) | |
735 | return ret; | |
b58f0273 | 736 | |
03b054e9 SY |
737 | /* Unpack argument and range check it */ |
738 | if (arg > 1) { | |
739 | dev_dbg(pctldev->dev, "%s: arg %u out of range\n", | |
740 | __func__, arg); | |
741 | return -EINVAL; | |
742 | } | |
743 | ||
744 | /* Write register field */ | |
745 | __global_lock2(flags); | |
746 | tmp = pmx_read(pmx, reg); | |
747 | tmp &= ~mask; | |
748 | if (arg) | |
749 | tmp |= val << shift; | |
750 | pmx_write(pmx, tmp, reg); | |
751 | __global_unlock2(flags); | |
752 | } /* for each config */ | |
b58f0273 JH |
753 | |
754 | return 0; | |
755 | } | |
756 | ||
757 | static const int tz1090_pdc_boolean_map[] = { | |
758 | [0] = -EINVAL, | |
759 | [1] = 1, | |
760 | }; | |
761 | ||
762 | static const int tz1090_pdc_dr_map[] = { | |
763 | [REG_DR_2mA] = 2, | |
764 | [REG_DR_4mA] = 4, | |
765 | [REG_DR_8mA] = 8, | |
766 | [REG_DR_12mA] = 12, | |
767 | }; | |
768 | ||
769 | static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, | |
770 | const struct tz1090_pdc_pingroup *g, | |
771 | enum pin_config_param param, | |
772 | bool report_err, u32 *reg, u32 *width, | |
773 | u32 *mask, u32 *shift, const int **map) | |
774 | { | |
775 | /* Drive configuration applies in groups, but not to all groups. */ | |
776 | if (!g->drv) { | |
777 | if (report_err) | |
778 | dev_dbg(pctldev->dev, | |
779 | "%s: group %s has no drive control\n", | |
780 | __func__, g->name); | |
781 | return -ENOTSUPP; | |
782 | } | |
783 | ||
784 | /* Find information about drive parameter's register */ | |
785 | *reg = REG_GPIO_CONTROL2; | |
786 | switch (param) { | |
787 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
788 | *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S; | |
789 | *width = 1; | |
790 | *map = tz1090_pdc_boolean_map; | |
791 | break; | |
b58f0273 JH |
792 | case PIN_CONFIG_DRIVE_STRENGTH: |
793 | *shift = REG_GPIO_CONTROL2_PDC_DR_S; | |
794 | *width = 2; | |
795 | *map = tz1090_pdc_dr_map; | |
796 | break; | |
797 | case PIN_CONFIG_LOW_POWER_MODE: | |
798 | *shift = REG_GPIO_CONTROL2_PDC_POS_S; | |
799 | *width = 1; | |
800 | *map = tz1090_pdc_boolean_map; | |
801 | break; | |
802 | default: | |
803 | return -ENOTSUPP; | |
804 | }; | |
805 | ||
806 | /* Calculate field information */ | |
807 | *mask = (BIT(*width) - 1) << *shift; | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, | |
813 | unsigned int group, | |
814 | unsigned long *config) | |
815 | { | |
816 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
817 | const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; | |
818 | enum pin_config_param param = pinconf_to_config_param(*config); | |
819 | int ret, arg; | |
820 | u32 reg, width, mask, shift, val; | |
821 | const int *map; | |
822 | ||
823 | /* Get register information */ | |
824 | ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, | |
825 | ®, &width, &mask, &shift, &map); | |
826 | if (ret < 0) | |
827 | return ret; | |
828 | ||
829 | /* Extract field from register */ | |
830 | val = pmx_read(pmx, reg); | |
831 | arg = map[(val & mask) >> shift]; | |
832 | if (arg < 0) | |
833 | return arg; | |
834 | ||
835 | /* And pack config */ | |
836 | *config = pinconf_to_config_packed(param, arg); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, | |
842 | unsigned int group, | |
03b054e9 SY |
843 | unsigned long *configs, |
844 | unsigned num_configs) | |
b58f0273 JH |
845 | { |
846 | struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | |
847 | const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; | |
03b054e9 | 848 | enum pin_config_param param; |
b58f0273 JH |
849 | const unsigned int *pit; |
850 | unsigned int i; | |
851 | int ret, arg; | |
852 | u32 reg, width, mask, shift, val; | |
853 | unsigned long flags; | |
854 | const int *map; | |
03b054e9 | 855 | int j; |
b58f0273 | 856 | |
03b054e9 SY |
857 | for (j = 0; j < num_configs; j++) { |
858 | param = pinconf_to_config_param(configs[j]); | |
b58f0273 | 859 | |
03b054e9 SY |
860 | dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", |
861 | __func__, g->name, configs[j]); | |
b58f0273 | 862 | |
03b054e9 SY |
863 | /* Get register information */ |
864 | ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, | |
865 | ®, &width, &mask, &shift, | |
866 | &map); | |
867 | if (ret < 0) { | |
868 | /* | |
869 | * Maybe we're trying to set a per-pin configuration | |
870 | * of a group, so do the pins one by one. This is | |
871 | * mainly as a convenience. | |
872 | */ | |
873 | for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { | |
874 | ret = tz1090_pdc_pinconf_set(pctldev, *pit, | |
875 | configs, num_configs); | |
876 | if (ret) | |
877 | return ret; | |
878 | } | |
b58f0273 JH |
879 | return 0; |
880 | } | |
b58f0273 | 881 | |
03b054e9 SY |
882 | /* Unpack argument and map it to register value */ |
883 | arg = pinconf_to_config_argument(configs[j]); | |
884 | for (i = 0; i < BIT(width); ++i) { | |
885 | if (map[i] == arg || (map[i] == -EINVAL && !arg)) { | |
886 | /* Write register field */ | |
887 | __global_lock2(flags); | |
888 | val = pmx_read(pmx, reg); | |
889 | val &= ~mask; | |
890 | val |= i << shift; | |
891 | pmx_write(pmx, val, reg); | |
892 | __global_unlock2(flags); | |
893 | goto next_config; | |
894 | } | |
895 | } | |
896 | ||
897 | dev_dbg(pctldev->dev, "%s: arg %u not supported\n", | |
898 | __func__, arg); | |
899 | return 0; | |
900 | ||
901 | next_config: | |
902 | ; | |
903 | } /* for each config */ | |
904 | ||
b58f0273 JH |
905 | return 0; |
906 | } | |
907 | ||
908 | static struct pinconf_ops tz1090_pdc_pinconf_ops = { | |
909 | .is_generic = true, | |
910 | .pin_config_get = tz1090_pdc_pinconf_get, | |
911 | .pin_config_set = tz1090_pdc_pinconf_set, | |
912 | .pin_config_group_get = tz1090_pdc_pinconf_group_get, | |
913 | .pin_config_group_set = tz1090_pdc_pinconf_group_set, | |
914 | .pin_config_config_dbg_show = pinconf_generic_dump_config, | |
915 | }; | |
916 | ||
917 | /* | |
918 | * Pin control driver setup | |
919 | */ | |
920 | ||
921 | static struct pinctrl_desc tz1090_pdc_pinctrl_desc = { | |
922 | .pctlops = &tz1090_pdc_pinctrl_ops, | |
923 | .pmxops = &tz1090_pdc_pinmux_ops, | |
924 | .confops = &tz1090_pdc_pinconf_ops, | |
925 | .owner = THIS_MODULE, | |
926 | }; | |
927 | ||
928 | static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) | |
929 | { | |
930 | struct tz1090_pdc_pmx *pmx; | |
931 | struct resource *res; | |
932 | ||
933 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); | |
934 | if (!pmx) { | |
935 | dev_err(&pdev->dev, "Can't alloc tz1090_pdc_pmx\n"); | |
936 | return -ENOMEM; | |
937 | } | |
938 | pmx->dev = &pdev->dev; | |
939 | spin_lock_init(&pmx->lock); | |
940 | ||
941 | tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev); | |
942 | tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins; | |
943 | tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins); | |
944 | ||
945 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
f5ba9c52 AL |
946 | pmx->regs = devm_ioremap_resource(&pdev->dev, res); |
947 | if (IS_ERR(pmx->regs)) | |
948 | return PTR_ERR(pmx->regs); | |
b58f0273 JH |
949 | |
950 | pmx->pctl = pinctrl_register(&tz1090_pdc_pinctrl_desc, &pdev->dev, pmx); | |
951 | if (!pmx->pctl) { | |
952 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
953 | return -ENODEV; | |
954 | } | |
955 | ||
956 | platform_set_drvdata(pdev, pmx); | |
957 | ||
958 | dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n"); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev) | |
964 | { | |
965 | struct tz1090_pdc_pmx *pmx = platform_get_drvdata(pdev); | |
966 | ||
967 | pinctrl_unregister(pmx->pctl); | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static struct of_device_id tz1090_pdc_pinctrl_of_match[] = { | |
973 | { .compatible = "img,tz1090-pdc-pinctrl", }, | |
974 | { }, | |
975 | }; | |
976 | ||
977 | static struct platform_driver tz1090_pdc_pinctrl_driver = { | |
978 | .driver = { | |
979 | .name = "tz1090-pdc-pinctrl", | |
980 | .owner = THIS_MODULE, | |
981 | .of_match_table = tz1090_pdc_pinctrl_of_match, | |
982 | }, | |
983 | .probe = tz1090_pdc_pinctrl_probe, | |
984 | .remove = tz1090_pdc_pinctrl_remove, | |
985 | }; | |
986 | ||
987 | static int __init tz1090_pdc_pinctrl_init(void) | |
988 | { | |
989 | return platform_driver_register(&tz1090_pdc_pinctrl_driver); | |
990 | } | |
991 | arch_initcall(tz1090_pdc_pinctrl_init); | |
992 | ||
993 | static void __exit tz1090_pdc_pinctrl_exit(void) | |
994 | { | |
995 | platform_driver_unregister(&tz1090_pdc_pinctrl_driver); | |
996 | } | |
997 | module_exit(tz1090_pdc_pinctrl_exit); | |
998 | ||
999 | MODULE_AUTHOR("Imagination Technologies Ltd."); | |
1000 | MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver"); | |
1001 | MODULE_LICENSE("GPL v2"); | |
1002 | MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match); |