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f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
32745581 | 15 | #include <linux/delay.h> |
f365be09 | 16 | #include <linux/err.h> |
f365be09 BA |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
f365be09 | 29 | #include <linux/spinlock.h> |
cf1fc187 | 30 | #include <linux/reboot.h> |
ad644987 | 31 | #include <linux/pm.h> |
47a01ee9 | 32 | #include <linux/log2.h> |
32745581 | 33 | |
69b78b8d LW |
34 | #include "../core.h" |
35 | #include "../pinconf.h" | |
f365be09 | 36 | #include "pinctrl-msm.h" |
69b78b8d | 37 | #include "../pinctrl-utils.h" |
f365be09 | 38 | |
408e3c66 | 39 | #define MAX_NR_GPIO 300 |
32745581 | 40 | #define PS_HOLD_OFFSET 0x820 |
408e3c66 | 41 | |
f365be09 BA |
42 | /** |
43 | * struct msm_pinctrl - state for a pinctrl-msm device | |
44 | * @dev: device handle. | |
45 | * @pctrl: pinctrl handle. | |
f365be09 | 46 | * @chip: gpiochip handle. |
cf1fc187 | 47 | * @restart_nb: restart notifier block. |
f365be09 BA |
48 | * @irq: parent irq for the TLMM irq_chip. |
49 | * @lock: Spinlock to protect register resources as well | |
50 | * as msm_pinctrl data structures. | |
51 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
52 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
53 | * detection. | |
f365be09 BA |
54 | * @soc; Reference to soc_data of platform specific data. |
55 | * @regs: Base address for the TLMM register map. | |
56 | */ | |
57 | struct msm_pinctrl { | |
58 | struct device *dev; | |
59 | struct pinctrl_dev *pctrl; | |
f365be09 | 60 | struct gpio_chip chip; |
cf1fc187 | 61 | struct notifier_block restart_nb; |
f393e489 | 62 | int irq; |
f365be09 BA |
63 | |
64 | spinlock_t lock; | |
65 | ||
408e3c66 BA |
66 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
67 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
f365be09 BA |
68 | |
69 | const struct msm_pinctrl_soc_data *soc; | |
70 | void __iomem *regs; | |
71 | }; | |
72 | ||
73 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) | |
74 | { | |
75 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
76 | ||
77 | return pctrl->soc->ngroups; | |
78 | } | |
79 | ||
80 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
81 | unsigned group) | |
82 | { | |
83 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
84 | ||
85 | return pctrl->soc->groups[group].name; | |
86 | } | |
87 | ||
88 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
89 | unsigned group, | |
90 | const unsigned **pins, | |
91 | unsigned *num_pins) | |
92 | { | |
93 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
94 | ||
95 | *pins = pctrl->soc->groups[group].pins; | |
96 | *num_pins = pctrl->soc->groups[group].npins; | |
97 | return 0; | |
98 | } | |
99 | ||
1f2b2398 | 100 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
101 | .get_groups_count = msm_get_groups_count, |
102 | .get_group_name = msm_get_group_name, | |
103 | .get_group_pins = msm_get_group_pins, | |
104 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
d32f7fd3 | 105 | .dt_free_map = pinctrl_utils_free_map, |
f365be09 BA |
106 | }; |
107 | ||
108 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
109 | { | |
110 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
111 | ||
112 | return pctrl->soc->nfunctions; | |
113 | } | |
114 | ||
115 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
116 | unsigned function) | |
117 | { | |
118 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
119 | ||
120 | return pctrl->soc->functions[function].name; | |
121 | } | |
122 | ||
123 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
124 | unsigned function, | |
125 | const char * const **groups, | |
126 | unsigned * const num_groups) | |
127 | { | |
128 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
129 | ||
130 | *groups = pctrl->soc->functions[function].groups; | |
131 | *num_groups = pctrl->soc->functions[function].ngroups; | |
132 | return 0; | |
133 | } | |
134 | ||
03e9f0ca LW |
135 | static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, |
136 | unsigned function, | |
137 | unsigned group) | |
f365be09 BA |
138 | { |
139 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
140 | const struct msm_pingroup *g; | |
141 | unsigned long flags; | |
47a01ee9 | 142 | u32 val, mask; |
f365be09 BA |
143 | int i; |
144 | ||
145 | g = &pctrl->soc->groups[group]; | |
47a01ee9 | 146 | mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); |
f365be09 | 147 | |
3c25381f | 148 | for (i = 0; i < g->nfuncs; i++) { |
f365be09 BA |
149 | if (g->funcs[i] == function) |
150 | break; | |
151 | } | |
152 | ||
3c25381f | 153 | if (WARN_ON(i == g->nfuncs)) |
f365be09 BA |
154 | return -EINVAL; |
155 | ||
156 | spin_lock_irqsave(&pctrl->lock, flags); | |
157 | ||
158 | val = readl(pctrl->regs + g->ctl_reg); | |
47a01ee9 | 159 | val &= mask; |
f365be09 BA |
160 | val |= i << g->mux_bit; |
161 | writel(val, pctrl->regs + g->ctl_reg); | |
162 | ||
163 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
1f2b2398 | 168 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
169 | .get_functions_count = msm_get_functions_count, |
170 | .get_function_name = msm_get_function_name, | |
171 | .get_function_groups = msm_get_function_groups, | |
03e9f0ca | 172 | .set_mux = msm_pinmux_set_mux, |
f365be09 BA |
173 | }; |
174 | ||
175 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
176 | const struct msm_pingroup *g, | |
177 | unsigned param, | |
f365be09 BA |
178 | unsigned *mask, |
179 | unsigned *bit) | |
180 | { | |
181 | switch (param) { | |
182 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 183 | case PIN_CONFIG_BIAS_PULL_DOWN: |
b831a15e | 184 | case PIN_CONFIG_BIAS_BUS_HOLD: |
f365be09 | 185 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
186 | *bit = g->pull_bit; |
187 | *mask = 3; | |
188 | break; | |
189 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
190 | *bit = g->drv_bit; |
191 | *mask = 7; | |
192 | break; | |
ed118a5f | 193 | case PIN_CONFIG_OUTPUT: |
407f5e39 | 194 | case PIN_CONFIG_INPUT_ENABLE: |
ed118a5f BA |
195 | *bit = g->oe_bit; |
196 | *mask = 1; | |
197 | break; | |
f365be09 | 198 | default: |
f365be09 BA |
199 | return -ENOTSUPP; |
200 | } | |
201 | ||
f365be09 BA |
202 | return 0; |
203 | } | |
204 | ||
f365be09 BA |
205 | #define MSM_NO_PULL 0 |
206 | #define MSM_PULL_DOWN 1 | |
b831a15e | 207 | #define MSM_KEEPER 2 |
f365be09 BA |
208 | #define MSM_PULL_UP 3 |
209 | ||
7cc34e2e SB |
210 | static unsigned msm_regval_to_drive(u32 val) |
211 | { | |
212 | return (val + 1) * 2; | |
213 | } | |
f365be09 BA |
214 | |
215 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
216 | unsigned int group, | |
217 | unsigned long *config) | |
218 | { | |
219 | const struct msm_pingroup *g; | |
220 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
221 | unsigned param = pinconf_to_config_param(*config); | |
222 | unsigned mask; | |
223 | unsigned arg; | |
224 | unsigned bit; | |
f365be09 BA |
225 | int ret; |
226 | u32 val; | |
227 | ||
228 | g = &pctrl->soc->groups[group]; | |
229 | ||
051a58b4 | 230 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
231 | if (ret < 0) |
232 | return ret; | |
233 | ||
051a58b4 | 234 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
235 | arg = (val >> bit) & mask; |
236 | ||
237 | /* Convert register value to pinconf value */ | |
238 | switch (param) { | |
239 | case PIN_CONFIG_BIAS_DISABLE: | |
240 | arg = arg == MSM_NO_PULL; | |
241 | break; | |
242 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
243 | arg = arg == MSM_PULL_DOWN; | |
244 | break; | |
b831a15e AG |
245 | case PIN_CONFIG_BIAS_BUS_HOLD: |
246 | arg = arg == MSM_KEEPER; | |
247 | break; | |
f365be09 BA |
248 | case PIN_CONFIG_BIAS_PULL_UP: |
249 | arg = arg == MSM_PULL_UP; | |
250 | break; | |
251 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 252 | arg = msm_regval_to_drive(arg); |
f365be09 | 253 | break; |
ed118a5f BA |
254 | case PIN_CONFIG_OUTPUT: |
255 | /* Pin is not output */ | |
256 | if (!arg) | |
257 | return -EINVAL; | |
258 | ||
259 | val = readl(pctrl->regs + g->io_reg); | |
260 | arg = !!(val & BIT(g->in_bit)); | |
261 | break; | |
407f5e39 SV |
262 | case PIN_CONFIG_INPUT_ENABLE: |
263 | /* Pin is output */ | |
264 | if (arg) | |
265 | return -EINVAL; | |
266 | arg = 1; | |
267 | break; | |
f365be09 | 268 | default: |
38d756af | 269 | return -ENOTSUPP; |
f365be09 BA |
270 | } |
271 | ||
272 | *config = pinconf_to_config_packed(param, arg); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
278 | unsigned group, | |
279 | unsigned long *configs, | |
280 | unsigned num_configs) | |
281 | { | |
282 | const struct msm_pingroup *g; | |
283 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
284 | unsigned long flags; | |
285 | unsigned param; | |
286 | unsigned mask; | |
287 | unsigned arg; | |
288 | unsigned bit; | |
f365be09 BA |
289 | int ret; |
290 | u32 val; | |
291 | int i; | |
292 | ||
293 | g = &pctrl->soc->groups[group]; | |
294 | ||
295 | for (i = 0; i < num_configs; i++) { | |
296 | param = pinconf_to_config_param(configs[i]); | |
297 | arg = pinconf_to_config_argument(configs[i]); | |
298 | ||
051a58b4 | 299 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
300 | if (ret < 0) |
301 | return ret; | |
302 | ||
303 | /* Convert pinconf values to register values */ | |
304 | switch (param) { | |
305 | case PIN_CONFIG_BIAS_DISABLE: | |
306 | arg = MSM_NO_PULL; | |
307 | break; | |
308 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
309 | arg = MSM_PULL_DOWN; | |
310 | break; | |
b831a15e AG |
311 | case PIN_CONFIG_BIAS_BUS_HOLD: |
312 | arg = MSM_KEEPER; | |
313 | break; | |
f365be09 BA |
314 | case PIN_CONFIG_BIAS_PULL_UP: |
315 | arg = MSM_PULL_UP; | |
316 | break; | |
317 | case PIN_CONFIG_DRIVE_STRENGTH: | |
318 | /* Check for invalid values */ | |
7cc34e2e | 319 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
320 | arg = -1; |
321 | else | |
7cc34e2e | 322 | arg = (arg / 2) - 1; |
f365be09 | 323 | break; |
ed118a5f BA |
324 | case PIN_CONFIG_OUTPUT: |
325 | /* set output value */ | |
326 | spin_lock_irqsave(&pctrl->lock, flags); | |
327 | val = readl(pctrl->regs + g->io_reg); | |
328 | if (arg) | |
329 | val |= BIT(g->out_bit); | |
330 | else | |
331 | val &= ~BIT(g->out_bit); | |
332 | writel(val, pctrl->regs + g->io_reg); | |
333 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
334 | ||
335 | /* enable output */ | |
336 | arg = 1; | |
337 | break; | |
407f5e39 SV |
338 | case PIN_CONFIG_INPUT_ENABLE: |
339 | /* disable output */ | |
340 | arg = 0; | |
341 | break; | |
f365be09 BA |
342 | default: |
343 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
344 | param); | |
345 | return -EINVAL; | |
346 | } | |
347 | ||
348 | /* Range-check user-supplied value */ | |
349 | if (arg & ~mask) { | |
350 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
351 | return -EINVAL; | |
352 | } | |
353 | ||
354 | spin_lock_irqsave(&pctrl->lock, flags); | |
051a58b4 | 355 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
356 | val &= ~(mask << bit); |
357 | val |= arg << bit; | |
051a58b4 | 358 | writel(val, pctrl->regs + g->ctl_reg); |
f365be09 BA |
359 | spin_unlock_irqrestore(&pctrl->lock, flags); |
360 | } | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
1f2b2398 | 365 | static const struct pinconf_ops msm_pinconf_ops = { |
38d756af | 366 | .is_generic = true, |
f365be09 BA |
367 | .pin_config_group_get = msm_config_group_get, |
368 | .pin_config_group_set = msm_config_group_set, | |
369 | }; | |
370 | ||
371 | static struct pinctrl_desc msm_pinctrl_desc = { | |
372 | .pctlops = &msm_pinctrl_ops, | |
373 | .pmxops = &msm_pinmux_ops, | |
374 | .confops = &msm_pinconf_ops, | |
375 | .owner = THIS_MODULE, | |
376 | }; | |
377 | ||
378 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
379 | { | |
380 | const struct msm_pingroup *g; | |
fded3f40 | 381 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
382 | unsigned long flags; |
383 | u32 val; | |
384 | ||
f365be09 | 385 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
386 | |
387 | spin_lock_irqsave(&pctrl->lock, flags); | |
388 | ||
389 | val = readl(pctrl->regs + g->ctl_reg); | |
390 | val &= ~BIT(g->oe_bit); | |
391 | writel(val, pctrl->regs + g->ctl_reg); | |
392 | ||
393 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
399 | { | |
400 | const struct msm_pingroup *g; | |
fded3f40 | 401 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
402 | unsigned long flags; |
403 | u32 val; | |
404 | ||
f365be09 | 405 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
406 | |
407 | spin_lock_irqsave(&pctrl->lock, flags); | |
408 | ||
e476e77f AL |
409 | val = readl(pctrl->regs + g->io_reg); |
410 | if (value) | |
411 | val |= BIT(g->out_bit); | |
412 | else | |
413 | val &= ~BIT(g->out_bit); | |
414 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
415 | |
416 | val = readl(pctrl->regs + g->ctl_reg); | |
417 | val |= BIT(g->oe_bit); | |
418 | writel(val, pctrl->regs + g->ctl_reg); | |
419 | ||
420 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
426 | { | |
427 | const struct msm_pingroup *g; | |
fded3f40 | 428 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
429 | u32 val; |
430 | ||
f365be09 BA |
431 | g = &pctrl->soc->groups[offset]; |
432 | ||
433 | val = readl(pctrl->regs + g->io_reg); | |
434 | return !!(val & BIT(g->in_bit)); | |
435 | } | |
436 | ||
437 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
438 | { | |
439 | const struct msm_pingroup *g; | |
fded3f40 | 440 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
441 | unsigned long flags; |
442 | u32 val; | |
443 | ||
f365be09 BA |
444 | g = &pctrl->soc->groups[offset]; |
445 | ||
446 | spin_lock_irqsave(&pctrl->lock, flags); | |
447 | ||
448 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
449 | if (value) |
450 | val |= BIT(g->out_bit); | |
451 | else | |
452 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
453 | writel(val, pctrl->regs + g->io_reg); |
454 | ||
455 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
456 | } | |
457 | ||
f365be09 BA |
458 | #ifdef CONFIG_DEBUG_FS |
459 | #include <linux/seq_file.h> | |
460 | ||
461 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
462 | struct pinctrl_dev *pctldev, | |
463 | struct gpio_chip *chip, | |
464 | unsigned offset, | |
465 | unsigned gpio) | |
466 | { | |
467 | const struct msm_pingroup *g; | |
fded3f40 | 468 | struct msm_pinctrl *pctrl = gpiochip_get_data(chip); |
f365be09 BA |
469 | unsigned func; |
470 | int is_out; | |
471 | int drive; | |
472 | int pull; | |
473 | u32 ctl_reg; | |
474 | ||
1f2b2398 | 475 | static const char * const pulls[] = { |
f365be09 BA |
476 | "no pull", |
477 | "pull down", | |
478 | "keeper", | |
479 | "pull up" | |
480 | }; | |
481 | ||
482 | g = &pctrl->soc->groups[offset]; | |
483 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
484 | ||
485 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
486 | func = (ctl_reg >> g->mux_bit) & 7; | |
487 | drive = (ctl_reg >> g->drv_bit) & 7; | |
488 | pull = (ctl_reg >> g->pull_bit) & 3; | |
489 | ||
490 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
7cc34e2e | 491 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
f365be09 BA |
492 | seq_printf(s, " %s", pulls[pull]); |
493 | } | |
494 | ||
495 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
496 | { | |
497 | unsigned gpio = chip->base; | |
498 | unsigned i; | |
499 | ||
500 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
501 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 502 | seq_puts(s, "\n"); |
f365be09 BA |
503 | } |
504 | } | |
505 | ||
506 | #else | |
507 | #define msm_gpio_dbg_show NULL | |
508 | #endif | |
509 | ||
510 | static struct gpio_chip msm_gpio_template = { | |
511 | .direction_input = msm_gpio_direction_input, | |
512 | .direction_output = msm_gpio_direction_output, | |
513 | .get = msm_gpio_get, | |
514 | .set = msm_gpio_set, | |
98c85d58 JG |
515 | .request = gpiochip_generic_request, |
516 | .free = gpiochip_generic_free, | |
f365be09 BA |
517 | .dbg_show = msm_gpio_dbg_show, |
518 | }; | |
519 | ||
520 | /* For dual-edge interrupts in software, since some hardware has no | |
521 | * such support: | |
522 | * | |
523 | * At appropriate moments, this function may be called to flip the polarity | |
524 | * settings of both-edge irq lines to try and catch the next edge. | |
525 | * | |
526 | * The attempt is considered successful if: | |
527 | * - the status bit goes high, indicating that an edge was caught, or | |
528 | * - the input value of the gpio doesn't change during the attempt. | |
529 | * If the value changes twice during the process, that would cause the first | |
530 | * test to fail but would force the second, as two opposite | |
531 | * transitions would cause a detection no matter the polarity setting. | |
532 | * | |
533 | * The do-loop tries to sledge-hammer closed the timing hole between | |
534 | * the initial value-read and the polarity-write - if the line value changes | |
535 | * during that window, an interrupt is lost, the new polarity setting is | |
536 | * incorrect, and the first success test will fail, causing a retry. | |
537 | * | |
538 | * Algorithm comes from Google's msmgpio driver. | |
539 | */ | |
540 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
541 | const struct msm_pingroup *g, | |
542 | struct irq_data *d) | |
543 | { | |
544 | int loop_limit = 100; | |
545 | unsigned val, val2, intstat; | |
546 | unsigned pol; | |
547 | ||
548 | do { | |
549 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
550 | ||
551 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
552 | pol ^= BIT(g->intr_polarity_bit); | |
553 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
554 | ||
555 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
556 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
557 | if (intstat || (val == val2)) | |
558 | return; | |
559 | } while (loop_limit-- > 0); | |
560 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
561 | val, val2); | |
562 | } | |
563 | ||
564 | static void msm_gpio_irq_mask(struct irq_data *d) | |
565 | { | |
cdcb0ab6 | 566 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 567 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 568 | const struct msm_pingroup *g; |
f365be09 BA |
569 | unsigned long flags; |
570 | u32 val; | |
571 | ||
f365be09 BA |
572 | g = &pctrl->soc->groups[d->hwirq]; |
573 | ||
574 | spin_lock_irqsave(&pctrl->lock, flags); | |
575 | ||
576 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
577 | val &= ~BIT(g->intr_enable_bit); | |
578 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
579 | ||
580 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
581 | ||
582 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
583 | } | |
584 | ||
585 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
586 | { | |
cdcb0ab6 | 587 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 588 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 589 | const struct msm_pingroup *g; |
f365be09 BA |
590 | unsigned long flags; |
591 | u32 val; | |
592 | ||
f365be09 BA |
593 | g = &pctrl->soc->groups[d->hwirq]; |
594 | ||
595 | spin_lock_irqsave(&pctrl->lock, flags); | |
596 | ||
597 | val = readl(pctrl->regs + g->intr_status_reg); | |
598 | val &= ~BIT(g->intr_status_bit); | |
599 | writel(val, pctrl->regs + g->intr_status_reg); | |
600 | ||
601 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
602 | val |= BIT(g->intr_enable_bit); | |
603 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
604 | ||
605 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
606 | ||
607 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
608 | } | |
609 | ||
610 | static void msm_gpio_irq_ack(struct irq_data *d) | |
611 | { | |
cdcb0ab6 | 612 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 613 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 614 | const struct msm_pingroup *g; |
f365be09 BA |
615 | unsigned long flags; |
616 | u32 val; | |
617 | ||
f365be09 BA |
618 | g = &pctrl->soc->groups[d->hwirq]; |
619 | ||
620 | spin_lock_irqsave(&pctrl->lock, flags); | |
621 | ||
622 | val = readl(pctrl->regs + g->intr_status_reg); | |
48f15e94 BA |
623 | if (g->intr_ack_high) |
624 | val |= BIT(g->intr_status_bit); | |
625 | else | |
626 | val &= ~BIT(g->intr_status_bit); | |
f365be09 BA |
627 | writel(val, pctrl->regs + g->intr_status_reg); |
628 | ||
629 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
630 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
631 | ||
632 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
633 | } | |
634 | ||
f365be09 BA |
635 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
636 | { | |
cdcb0ab6 | 637 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 638 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 639 | const struct msm_pingroup *g; |
f365be09 BA |
640 | unsigned long flags; |
641 | u32 val; | |
642 | ||
f365be09 BA |
643 | g = &pctrl->soc->groups[d->hwirq]; |
644 | ||
645 | spin_lock_irqsave(&pctrl->lock, flags); | |
646 | ||
647 | /* | |
648 | * For hw without possibility of detecting both edges | |
649 | */ | |
650 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
651 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
652 | else | |
653 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
654 | ||
655 | /* Route interrupts to application cpu */ | |
656 | val = readl(pctrl->regs + g->intr_target_reg); | |
657 | val &= ~(7 << g->intr_target_bit); | |
f712c554 | 658 | val |= g->intr_target_kpss_val << g->intr_target_bit; |
f365be09 BA |
659 | writel(val, pctrl->regs + g->intr_target_reg); |
660 | ||
661 | /* Update configuration for gpio. | |
662 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
663 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
664 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
665 | */ | |
666 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
667 | val |= BIT(g->intr_raw_status_bit); | |
668 | if (g->intr_detection_width == 2) { | |
669 | val &= ~(3 << g->intr_detection_bit); | |
670 | val &= ~(1 << g->intr_polarity_bit); | |
671 | switch (type) { | |
672 | case IRQ_TYPE_EDGE_RISING: | |
673 | val |= 1 << g->intr_detection_bit; | |
674 | val |= BIT(g->intr_polarity_bit); | |
675 | break; | |
676 | case IRQ_TYPE_EDGE_FALLING: | |
677 | val |= 2 << g->intr_detection_bit; | |
678 | val |= BIT(g->intr_polarity_bit); | |
679 | break; | |
680 | case IRQ_TYPE_EDGE_BOTH: | |
681 | val |= 3 << g->intr_detection_bit; | |
682 | val |= BIT(g->intr_polarity_bit); | |
683 | break; | |
684 | case IRQ_TYPE_LEVEL_LOW: | |
685 | break; | |
686 | case IRQ_TYPE_LEVEL_HIGH: | |
687 | val |= BIT(g->intr_polarity_bit); | |
688 | break; | |
689 | } | |
690 | } else if (g->intr_detection_width == 1) { | |
691 | val &= ~(1 << g->intr_detection_bit); | |
692 | val &= ~(1 << g->intr_polarity_bit); | |
693 | switch (type) { | |
694 | case IRQ_TYPE_EDGE_RISING: | |
695 | val |= BIT(g->intr_detection_bit); | |
696 | val |= BIT(g->intr_polarity_bit); | |
697 | break; | |
698 | case IRQ_TYPE_EDGE_FALLING: | |
699 | val |= BIT(g->intr_detection_bit); | |
700 | break; | |
701 | case IRQ_TYPE_EDGE_BOTH: | |
702 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 703 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
704 | break; |
705 | case IRQ_TYPE_LEVEL_LOW: | |
706 | break; | |
707 | case IRQ_TYPE_LEVEL_HIGH: | |
708 | val |= BIT(g->intr_polarity_bit); | |
709 | break; | |
710 | } | |
711 | } else { | |
712 | BUG(); | |
713 | } | |
714 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
715 | ||
716 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
717 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
718 | ||
719 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
720 | ||
721 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
34c0ad84 | 722 | irq_set_handler_locked(d, handle_level_irq); |
f365be09 | 723 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
34c0ad84 | 724 | irq_set_handler_locked(d, handle_edge_irq); |
f365be09 BA |
725 | |
726 | return 0; | |
727 | } | |
728 | ||
729 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
730 | { | |
cdcb0ab6 | 731 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
fded3f40 | 732 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
f365be09 | 733 | unsigned long flags; |
f365be09 | 734 | |
f365be09 BA |
735 | spin_lock_irqsave(&pctrl->lock, flags); |
736 | ||
6aced33f | 737 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 BA |
738 | |
739 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
f365be09 BA |
744 | static struct irq_chip msm_gpio_irq_chip = { |
745 | .name = "msmgpio", | |
746 | .irq_mask = msm_gpio_irq_mask, | |
747 | .irq_unmask = msm_gpio_irq_unmask, | |
748 | .irq_ack = msm_gpio_irq_ack, | |
749 | .irq_set_type = msm_gpio_irq_set_type, | |
750 | .irq_set_wake = msm_gpio_irq_set_wake, | |
f365be09 BA |
751 | }; |
752 | ||
bd0b9ac4 | 753 | static void msm_gpio_irq_handler(struct irq_desc *desc) |
f365be09 | 754 | { |
cdcb0ab6 | 755 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
f365be09 | 756 | const struct msm_pingroup *g; |
fded3f40 | 757 | struct msm_pinctrl *pctrl = gpiochip_get_data(gc); |
5663bb27 | 758 | struct irq_chip *chip = irq_desc_get_chip(desc); |
f365be09 BA |
759 | int irq_pin; |
760 | int handled = 0; | |
761 | u32 val; | |
762 | int i; | |
763 | ||
764 | chained_irq_enter(chip, desc); | |
765 | ||
766 | /* | |
1f2b2398 | 767 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
768 | * enabled_irq bitmap to limit the number of reads. |
769 | */ | |
770 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
771 | g = &pctrl->soc->groups[i]; | |
772 | val = readl(pctrl->regs + g->intr_status_reg); | |
773 | if (val & BIT(g->intr_status_bit)) { | |
cdcb0ab6 | 774 | irq_pin = irq_find_mapping(gc->irqdomain, i); |
f365be09 BA |
775 | generic_handle_irq(irq_pin); |
776 | handled++; | |
777 | } | |
778 | } | |
779 | ||
1f2b2398 | 780 | /* No interrupts were flagged */ |
f365be09 | 781 | if (handled == 0) |
bd0b9ac4 | 782 | handle_bad_irq(desc); |
f365be09 BA |
783 | |
784 | chained_irq_exit(chip, desc); | |
785 | } | |
786 | ||
787 | static int msm_gpio_init(struct msm_pinctrl *pctrl) | |
788 | { | |
789 | struct gpio_chip *chip; | |
f365be09 | 790 | int ret; |
dcd278b8 SB |
791 | unsigned ngpio = pctrl->soc->ngpios; |
792 | ||
793 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
794 | return -EINVAL; | |
f365be09 BA |
795 | |
796 | chip = &pctrl->chip; | |
797 | chip->base = 0; | |
dcd278b8 | 798 | chip->ngpio = ngpio; |
f365be09 | 799 | chip->label = dev_name(pctrl->dev); |
58383c78 | 800 | chip->parent = pctrl->dev; |
f365be09 BA |
801 | chip->owner = THIS_MODULE; |
802 | chip->of_node = pctrl->dev->of_node; | |
803 | ||
fded3f40 | 804 | ret = gpiochip_add_data(&pctrl->chip, pctrl); |
f365be09 BA |
805 | if (ret) { |
806 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
807 | return ret; | |
808 | } | |
809 | ||
810 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
811 | if (ret) { | |
812 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
c6e927a2 | 813 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
814 | return ret; |
815 | } | |
816 | ||
cdcb0ab6 LW |
817 | ret = gpiochip_irqchip_add(chip, |
818 | &msm_gpio_irq_chip, | |
819 | 0, | |
820 | handle_edge_irq, | |
821 | IRQ_TYPE_NONE); | |
822 | if (ret) { | |
823 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); | |
c6e927a2 | 824 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
825 | return -ENOSYS; |
826 | } | |
827 | ||
cdcb0ab6 LW |
828 | gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, |
829 | msm_gpio_irq_handler); | |
f365be09 BA |
830 | |
831 | return 0; | |
832 | } | |
833 | ||
cf1fc187 JC |
834 | static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, |
835 | void *data) | |
32745581 | 836 | { |
cf1fc187 JC |
837 | struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); |
838 | ||
839 | writel(0, pctrl->regs + PS_HOLD_OFFSET); | |
840 | mdelay(1000); | |
841 | return NOTIFY_DONE; | |
32745581 PG |
842 | } |
843 | ||
ad644987 SB |
844 | static struct msm_pinctrl *poweroff_pctrl; |
845 | ||
846 | static void msm_ps_hold_poweroff(void) | |
847 | { | |
848 | msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); | |
849 | } | |
850 | ||
32745581 PG |
851 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) |
852 | { | |
bcd53f85 | 853 | int i; |
32745581 PG |
854 | const struct msm_function *func = pctrl->soc->functions; |
855 | ||
bcd53f85 | 856 | for (i = 0; i < pctrl->soc->nfunctions; i++) |
32745581 | 857 | if (!strcmp(func[i].name, "ps_hold")) { |
cf1fc187 JC |
858 | pctrl->restart_nb.notifier_call = msm_ps_hold_restart; |
859 | pctrl->restart_nb.priority = 128; | |
860 | if (register_restart_handler(&pctrl->restart_nb)) | |
861 | dev_err(pctrl->dev, | |
862 | "failed to setup restart handler.\n"); | |
ad644987 SB |
863 | poweroff_pctrl = pctrl; |
864 | pm_power_off = msm_ps_hold_poweroff; | |
cf1fc187 | 865 | break; |
32745581 PG |
866 | } |
867 | } | |
32745581 | 868 | |
f365be09 BA |
869 | int msm_pinctrl_probe(struct platform_device *pdev, |
870 | const struct msm_pinctrl_soc_data *soc_data) | |
871 | { | |
872 | struct msm_pinctrl *pctrl; | |
873 | struct resource *res; | |
874 | int ret; | |
875 | ||
876 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
877 | if (!pctrl) { | |
878 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
879 | return -ENOMEM; | |
880 | } | |
881 | pctrl->dev = &pdev->dev; | |
882 | pctrl->soc = soc_data; | |
883 | pctrl->chip = msm_gpio_template; | |
884 | ||
885 | spin_lock_init(&pctrl->lock); | |
886 | ||
887 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
888 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
889 | if (IS_ERR(pctrl->regs)) | |
890 | return PTR_ERR(pctrl->regs); | |
891 | ||
32745581 PG |
892 | msm_pinctrl_setup_pm_reset(pctrl); |
893 | ||
f393e489 | 894 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
895 | if (pctrl->irq < 0) { |
896 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
897 | return pctrl->irq; | |
898 | } | |
899 | ||
900 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
901 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
902 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
fe0267f4 LD |
903 | pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc, |
904 | pctrl); | |
323de9ef | 905 | if (IS_ERR(pctrl->pctrl)) { |
f365be09 | 906 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); |
323de9ef | 907 | return PTR_ERR(pctrl->pctrl); |
f365be09 BA |
908 | } |
909 | ||
910 | ret = msm_gpio_init(pctrl); | |
fe0267f4 | 911 | if (ret) |
f365be09 | 912 | return ret; |
f365be09 BA |
913 | |
914 | platform_set_drvdata(pdev, pctrl); | |
915 | ||
916 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
917 | ||
918 | return 0; | |
919 | } | |
920 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
921 | ||
922 | int msm_pinctrl_remove(struct platform_device *pdev) | |
923 | { | |
924 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
f393e489 | 925 | |
2fcea6ce | 926 | gpiochip_remove(&pctrl->chip); |
f365be09 | 927 | |
cf1fc187 JC |
928 | unregister_restart_handler(&pctrl->restart_nb); |
929 | ||
f365be09 BA |
930 | return 0; |
931 | } | |
932 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
933 |