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f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
32745581 | 15 | #include <linux/delay.h> |
f365be09 | 16 | #include <linux/err.h> |
f365be09 BA |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
f365be09 | 29 | #include <linux/spinlock.h> |
cf1fc187 | 30 | #include <linux/reboot.h> |
32745581 | 31 | |
69b78b8d LW |
32 | #include "../core.h" |
33 | #include "../pinconf.h" | |
f365be09 | 34 | #include "pinctrl-msm.h" |
69b78b8d | 35 | #include "../pinctrl-utils.h" |
f365be09 | 36 | |
408e3c66 | 37 | #define MAX_NR_GPIO 300 |
32745581 | 38 | #define PS_HOLD_OFFSET 0x820 |
408e3c66 | 39 | |
f365be09 BA |
40 | /** |
41 | * struct msm_pinctrl - state for a pinctrl-msm device | |
42 | * @dev: device handle. | |
43 | * @pctrl: pinctrl handle. | |
f365be09 | 44 | * @chip: gpiochip handle. |
cf1fc187 | 45 | * @restart_nb: restart notifier block. |
f365be09 BA |
46 | * @irq: parent irq for the TLMM irq_chip. |
47 | * @lock: Spinlock to protect register resources as well | |
48 | * as msm_pinctrl data structures. | |
49 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
50 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
51 | * detection. | |
f365be09 BA |
52 | * @soc; Reference to soc_data of platform specific data. |
53 | * @regs: Base address for the TLMM register map. | |
54 | */ | |
55 | struct msm_pinctrl { | |
56 | struct device *dev; | |
57 | struct pinctrl_dev *pctrl; | |
f365be09 | 58 | struct gpio_chip chip; |
cf1fc187 | 59 | struct notifier_block restart_nb; |
f393e489 | 60 | int irq; |
f365be09 BA |
61 | |
62 | spinlock_t lock; | |
63 | ||
408e3c66 BA |
64 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
65 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
f365be09 BA |
66 | |
67 | const struct msm_pinctrl_soc_data *soc; | |
68 | void __iomem *regs; | |
69 | }; | |
70 | ||
cdcb0ab6 LW |
71 | static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) |
72 | { | |
73 | return container_of(gc, struct msm_pinctrl, chip); | |
74 | } | |
75 | ||
f365be09 BA |
76 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) |
77 | { | |
78 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
79 | ||
80 | return pctrl->soc->ngroups; | |
81 | } | |
82 | ||
83 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
84 | unsigned group) | |
85 | { | |
86 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
87 | ||
88 | return pctrl->soc->groups[group].name; | |
89 | } | |
90 | ||
91 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
92 | unsigned group, | |
93 | const unsigned **pins, | |
94 | unsigned *num_pins) | |
95 | { | |
96 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
97 | ||
98 | *pins = pctrl->soc->groups[group].pins; | |
99 | *num_pins = pctrl->soc->groups[group].npins; | |
100 | return 0; | |
101 | } | |
102 | ||
1f2b2398 | 103 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
104 | .get_groups_count = msm_get_groups_count, |
105 | .get_group_name = msm_get_group_name, | |
106 | .get_group_pins = msm_get_group_pins, | |
107 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
108 | .dt_free_map = pinctrl_utils_dt_free_map, | |
109 | }; | |
110 | ||
111 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
112 | { | |
113 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
114 | ||
115 | return pctrl->soc->nfunctions; | |
116 | } | |
117 | ||
118 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
119 | unsigned function) | |
120 | { | |
121 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
122 | ||
123 | return pctrl->soc->functions[function].name; | |
124 | } | |
125 | ||
126 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
127 | unsigned function, | |
128 | const char * const **groups, | |
129 | unsigned * const num_groups) | |
130 | { | |
131 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
132 | ||
133 | *groups = pctrl->soc->functions[function].groups; | |
134 | *num_groups = pctrl->soc->functions[function].ngroups; | |
135 | return 0; | |
136 | } | |
137 | ||
03e9f0ca LW |
138 | static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, |
139 | unsigned function, | |
140 | unsigned group) | |
f365be09 BA |
141 | { |
142 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
143 | const struct msm_pingroup *g; | |
144 | unsigned long flags; | |
145 | u32 val; | |
146 | int i; | |
147 | ||
148 | g = &pctrl->soc->groups[group]; | |
149 | ||
3c25381f | 150 | for (i = 0; i < g->nfuncs; i++) { |
f365be09 BA |
151 | if (g->funcs[i] == function) |
152 | break; | |
153 | } | |
154 | ||
3c25381f | 155 | if (WARN_ON(i == g->nfuncs)) |
f365be09 BA |
156 | return -EINVAL; |
157 | ||
158 | spin_lock_irqsave(&pctrl->lock, flags); | |
159 | ||
160 | val = readl(pctrl->regs + g->ctl_reg); | |
161 | val &= ~(0x7 << g->mux_bit); | |
162 | val |= i << g->mux_bit; | |
163 | writel(val, pctrl->regs + g->ctl_reg); | |
164 | ||
165 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
1f2b2398 | 170 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
171 | .get_functions_count = msm_get_functions_count, |
172 | .get_function_name = msm_get_function_name, | |
173 | .get_function_groups = msm_get_function_groups, | |
03e9f0ca | 174 | .set_mux = msm_pinmux_set_mux, |
f365be09 BA |
175 | }; |
176 | ||
177 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
178 | const struct msm_pingroup *g, | |
179 | unsigned param, | |
f365be09 BA |
180 | unsigned *mask, |
181 | unsigned *bit) | |
182 | { | |
183 | switch (param) { | |
184 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 185 | case PIN_CONFIG_BIAS_PULL_DOWN: |
b831a15e | 186 | case PIN_CONFIG_BIAS_BUS_HOLD: |
f365be09 | 187 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
188 | *bit = g->pull_bit; |
189 | *mask = 3; | |
190 | break; | |
191 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
192 | *bit = g->drv_bit; |
193 | *mask = 7; | |
194 | break; | |
ed118a5f | 195 | case PIN_CONFIG_OUTPUT: |
ed118a5f BA |
196 | *bit = g->oe_bit; |
197 | *mask = 1; | |
198 | break; | |
f365be09 | 199 | default: |
f365be09 BA |
200 | return -ENOTSUPP; |
201 | } | |
202 | ||
f365be09 BA |
203 | return 0; |
204 | } | |
205 | ||
f365be09 BA |
206 | #define MSM_NO_PULL 0 |
207 | #define MSM_PULL_DOWN 1 | |
b831a15e | 208 | #define MSM_KEEPER 2 |
f365be09 BA |
209 | #define MSM_PULL_UP 3 |
210 | ||
7cc34e2e SB |
211 | static unsigned msm_regval_to_drive(u32 val) |
212 | { | |
213 | return (val + 1) * 2; | |
214 | } | |
f365be09 BA |
215 | |
216 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
217 | unsigned int group, | |
218 | unsigned long *config) | |
219 | { | |
220 | const struct msm_pingroup *g; | |
221 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
222 | unsigned param = pinconf_to_config_param(*config); | |
223 | unsigned mask; | |
224 | unsigned arg; | |
225 | unsigned bit; | |
f365be09 BA |
226 | int ret; |
227 | u32 val; | |
228 | ||
229 | g = &pctrl->soc->groups[group]; | |
230 | ||
051a58b4 | 231 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
232 | if (ret < 0) |
233 | return ret; | |
234 | ||
051a58b4 | 235 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
236 | arg = (val >> bit) & mask; |
237 | ||
238 | /* Convert register value to pinconf value */ | |
239 | switch (param) { | |
240 | case PIN_CONFIG_BIAS_DISABLE: | |
241 | arg = arg == MSM_NO_PULL; | |
242 | break; | |
243 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
244 | arg = arg == MSM_PULL_DOWN; | |
245 | break; | |
b831a15e AG |
246 | case PIN_CONFIG_BIAS_BUS_HOLD: |
247 | arg = arg == MSM_KEEPER; | |
248 | break; | |
f365be09 BA |
249 | case PIN_CONFIG_BIAS_PULL_UP: |
250 | arg = arg == MSM_PULL_UP; | |
251 | break; | |
252 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 253 | arg = msm_regval_to_drive(arg); |
f365be09 | 254 | break; |
ed118a5f BA |
255 | case PIN_CONFIG_OUTPUT: |
256 | /* Pin is not output */ | |
257 | if (!arg) | |
258 | return -EINVAL; | |
259 | ||
260 | val = readl(pctrl->regs + g->io_reg); | |
261 | arg = !!(val & BIT(g->in_bit)); | |
262 | break; | |
f365be09 | 263 | default: |
38d756af | 264 | return -ENOTSUPP; |
f365be09 BA |
265 | } |
266 | ||
267 | *config = pinconf_to_config_packed(param, arg); | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
272 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
273 | unsigned group, | |
274 | unsigned long *configs, | |
275 | unsigned num_configs) | |
276 | { | |
277 | const struct msm_pingroup *g; | |
278 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
279 | unsigned long flags; | |
280 | unsigned param; | |
281 | unsigned mask; | |
282 | unsigned arg; | |
283 | unsigned bit; | |
f365be09 BA |
284 | int ret; |
285 | u32 val; | |
286 | int i; | |
287 | ||
288 | g = &pctrl->soc->groups[group]; | |
289 | ||
290 | for (i = 0; i < num_configs; i++) { | |
291 | param = pinconf_to_config_param(configs[i]); | |
292 | arg = pinconf_to_config_argument(configs[i]); | |
293 | ||
051a58b4 | 294 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
295 | if (ret < 0) |
296 | return ret; | |
297 | ||
298 | /* Convert pinconf values to register values */ | |
299 | switch (param) { | |
300 | case PIN_CONFIG_BIAS_DISABLE: | |
301 | arg = MSM_NO_PULL; | |
302 | break; | |
303 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
304 | arg = MSM_PULL_DOWN; | |
305 | break; | |
b831a15e AG |
306 | case PIN_CONFIG_BIAS_BUS_HOLD: |
307 | arg = MSM_KEEPER; | |
308 | break; | |
f365be09 BA |
309 | case PIN_CONFIG_BIAS_PULL_UP: |
310 | arg = MSM_PULL_UP; | |
311 | break; | |
312 | case PIN_CONFIG_DRIVE_STRENGTH: | |
313 | /* Check for invalid values */ | |
7cc34e2e | 314 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
315 | arg = -1; |
316 | else | |
7cc34e2e | 317 | arg = (arg / 2) - 1; |
f365be09 | 318 | break; |
ed118a5f BA |
319 | case PIN_CONFIG_OUTPUT: |
320 | /* set output value */ | |
321 | spin_lock_irqsave(&pctrl->lock, flags); | |
322 | val = readl(pctrl->regs + g->io_reg); | |
323 | if (arg) | |
324 | val |= BIT(g->out_bit); | |
325 | else | |
326 | val &= ~BIT(g->out_bit); | |
327 | writel(val, pctrl->regs + g->io_reg); | |
328 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
329 | ||
330 | /* enable output */ | |
331 | arg = 1; | |
332 | break; | |
f365be09 BA |
333 | default: |
334 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
335 | param); | |
336 | return -EINVAL; | |
337 | } | |
338 | ||
339 | /* Range-check user-supplied value */ | |
340 | if (arg & ~mask) { | |
341 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
342 | return -EINVAL; | |
343 | } | |
344 | ||
345 | spin_lock_irqsave(&pctrl->lock, flags); | |
051a58b4 | 346 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
347 | val &= ~(mask << bit); |
348 | val |= arg << bit; | |
051a58b4 | 349 | writel(val, pctrl->regs + g->ctl_reg); |
f365be09 BA |
350 | spin_unlock_irqrestore(&pctrl->lock, flags); |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
1f2b2398 | 356 | static const struct pinconf_ops msm_pinconf_ops = { |
38d756af | 357 | .is_generic = true, |
f365be09 BA |
358 | .pin_config_group_get = msm_config_group_get, |
359 | .pin_config_group_set = msm_config_group_set, | |
360 | }; | |
361 | ||
362 | static struct pinctrl_desc msm_pinctrl_desc = { | |
363 | .pctlops = &msm_pinctrl_ops, | |
364 | .pmxops = &msm_pinmux_ops, | |
365 | .confops = &msm_pinconf_ops, | |
366 | .owner = THIS_MODULE, | |
367 | }; | |
368 | ||
369 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
370 | { | |
371 | const struct msm_pingroup *g; | |
372 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
373 | unsigned long flags; | |
374 | u32 val; | |
375 | ||
f365be09 | 376 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
377 | |
378 | spin_lock_irqsave(&pctrl->lock, flags); | |
379 | ||
380 | val = readl(pctrl->regs + g->ctl_reg); | |
381 | val &= ~BIT(g->oe_bit); | |
382 | writel(val, pctrl->regs + g->ctl_reg); | |
383 | ||
384 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
390 | { | |
391 | const struct msm_pingroup *g; | |
392 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
393 | unsigned long flags; | |
394 | u32 val; | |
395 | ||
f365be09 | 396 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
397 | |
398 | spin_lock_irqsave(&pctrl->lock, flags); | |
399 | ||
e476e77f AL |
400 | val = readl(pctrl->regs + g->io_reg); |
401 | if (value) | |
402 | val |= BIT(g->out_bit); | |
403 | else | |
404 | val &= ~BIT(g->out_bit); | |
405 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
406 | |
407 | val = readl(pctrl->regs + g->ctl_reg); | |
408 | val |= BIT(g->oe_bit); | |
409 | writel(val, pctrl->regs + g->ctl_reg); | |
410 | ||
411 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
417 | { | |
418 | const struct msm_pingroup *g; | |
419 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
420 | u32 val; | |
421 | ||
f365be09 BA |
422 | g = &pctrl->soc->groups[offset]; |
423 | ||
424 | val = readl(pctrl->regs + g->io_reg); | |
425 | return !!(val & BIT(g->in_bit)); | |
426 | } | |
427 | ||
428 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
429 | { | |
430 | const struct msm_pingroup *g; | |
431 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
432 | unsigned long flags; | |
433 | u32 val; | |
434 | ||
f365be09 BA |
435 | g = &pctrl->soc->groups[offset]; |
436 | ||
437 | spin_lock_irqsave(&pctrl->lock, flags); | |
438 | ||
439 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
440 | if (value) |
441 | val |= BIT(g->out_bit); | |
442 | else | |
443 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
444 | writel(val, pctrl->regs + g->io_reg); |
445 | ||
446 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
447 | } | |
448 | ||
f365be09 BA |
449 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
450 | { | |
451 | int gpio = chip->base + offset; | |
452 | return pinctrl_request_gpio(gpio); | |
453 | } | |
454 | ||
455 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | |
456 | { | |
457 | int gpio = chip->base + offset; | |
458 | return pinctrl_free_gpio(gpio); | |
459 | } | |
460 | ||
461 | #ifdef CONFIG_DEBUG_FS | |
462 | #include <linux/seq_file.h> | |
463 | ||
464 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
465 | struct pinctrl_dev *pctldev, | |
466 | struct gpio_chip *chip, | |
467 | unsigned offset, | |
468 | unsigned gpio) | |
469 | { | |
470 | const struct msm_pingroup *g; | |
471 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
472 | unsigned func; | |
473 | int is_out; | |
474 | int drive; | |
475 | int pull; | |
476 | u32 ctl_reg; | |
477 | ||
1f2b2398 | 478 | static const char * const pulls[] = { |
f365be09 BA |
479 | "no pull", |
480 | "pull down", | |
481 | "keeper", | |
482 | "pull up" | |
483 | }; | |
484 | ||
485 | g = &pctrl->soc->groups[offset]; | |
486 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
487 | ||
488 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
489 | func = (ctl_reg >> g->mux_bit) & 7; | |
490 | drive = (ctl_reg >> g->drv_bit) & 7; | |
491 | pull = (ctl_reg >> g->pull_bit) & 3; | |
492 | ||
493 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
7cc34e2e | 494 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
f365be09 BA |
495 | seq_printf(s, " %s", pulls[pull]); |
496 | } | |
497 | ||
498 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
499 | { | |
500 | unsigned gpio = chip->base; | |
501 | unsigned i; | |
502 | ||
503 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
504 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 505 | seq_puts(s, "\n"); |
f365be09 BA |
506 | } |
507 | } | |
508 | ||
509 | #else | |
510 | #define msm_gpio_dbg_show NULL | |
511 | #endif | |
512 | ||
513 | static struct gpio_chip msm_gpio_template = { | |
514 | .direction_input = msm_gpio_direction_input, | |
515 | .direction_output = msm_gpio_direction_output, | |
516 | .get = msm_gpio_get, | |
517 | .set = msm_gpio_set, | |
f365be09 BA |
518 | .request = msm_gpio_request, |
519 | .free = msm_gpio_free, | |
520 | .dbg_show = msm_gpio_dbg_show, | |
521 | }; | |
522 | ||
523 | /* For dual-edge interrupts in software, since some hardware has no | |
524 | * such support: | |
525 | * | |
526 | * At appropriate moments, this function may be called to flip the polarity | |
527 | * settings of both-edge irq lines to try and catch the next edge. | |
528 | * | |
529 | * The attempt is considered successful if: | |
530 | * - the status bit goes high, indicating that an edge was caught, or | |
531 | * - the input value of the gpio doesn't change during the attempt. | |
532 | * If the value changes twice during the process, that would cause the first | |
533 | * test to fail but would force the second, as two opposite | |
534 | * transitions would cause a detection no matter the polarity setting. | |
535 | * | |
536 | * The do-loop tries to sledge-hammer closed the timing hole between | |
537 | * the initial value-read and the polarity-write - if the line value changes | |
538 | * during that window, an interrupt is lost, the new polarity setting is | |
539 | * incorrect, and the first success test will fail, causing a retry. | |
540 | * | |
541 | * Algorithm comes from Google's msmgpio driver. | |
542 | */ | |
543 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
544 | const struct msm_pingroup *g, | |
545 | struct irq_data *d) | |
546 | { | |
547 | int loop_limit = 100; | |
548 | unsigned val, val2, intstat; | |
549 | unsigned pol; | |
550 | ||
551 | do { | |
552 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
553 | ||
554 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
555 | pol ^= BIT(g->intr_polarity_bit); | |
556 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
557 | ||
558 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
559 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
560 | if (intstat || (val == val2)) | |
561 | return; | |
562 | } while (loop_limit-- > 0); | |
563 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
564 | val, val2); | |
565 | } | |
566 | ||
567 | static void msm_gpio_irq_mask(struct irq_data *d) | |
568 | { | |
cdcb0ab6 LW |
569 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
570 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 571 | const struct msm_pingroup *g; |
f365be09 BA |
572 | unsigned long flags; |
573 | u32 val; | |
574 | ||
f365be09 BA |
575 | g = &pctrl->soc->groups[d->hwirq]; |
576 | ||
577 | spin_lock_irqsave(&pctrl->lock, flags); | |
578 | ||
579 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
580 | val &= ~BIT(g->intr_enable_bit); | |
581 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
582 | ||
583 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
584 | ||
585 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
586 | } | |
587 | ||
588 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
589 | { | |
cdcb0ab6 LW |
590 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
591 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 592 | const struct msm_pingroup *g; |
f365be09 BA |
593 | unsigned long flags; |
594 | u32 val; | |
595 | ||
f365be09 BA |
596 | g = &pctrl->soc->groups[d->hwirq]; |
597 | ||
598 | spin_lock_irqsave(&pctrl->lock, flags); | |
599 | ||
600 | val = readl(pctrl->regs + g->intr_status_reg); | |
601 | val &= ~BIT(g->intr_status_bit); | |
602 | writel(val, pctrl->regs + g->intr_status_reg); | |
603 | ||
604 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
605 | val |= BIT(g->intr_enable_bit); | |
606 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
607 | ||
608 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
609 | ||
610 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
611 | } | |
612 | ||
613 | static void msm_gpio_irq_ack(struct irq_data *d) | |
614 | { | |
cdcb0ab6 LW |
615 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
616 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 617 | const struct msm_pingroup *g; |
f365be09 BA |
618 | unsigned long flags; |
619 | u32 val; | |
620 | ||
f365be09 BA |
621 | g = &pctrl->soc->groups[d->hwirq]; |
622 | ||
623 | spin_lock_irqsave(&pctrl->lock, flags); | |
624 | ||
625 | val = readl(pctrl->regs + g->intr_status_reg); | |
48f15e94 BA |
626 | if (g->intr_ack_high) |
627 | val |= BIT(g->intr_status_bit); | |
628 | else | |
629 | val &= ~BIT(g->intr_status_bit); | |
f365be09 BA |
630 | writel(val, pctrl->regs + g->intr_status_reg); |
631 | ||
632 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
633 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
634 | ||
635 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
636 | } | |
637 | ||
f365be09 BA |
638 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
639 | { | |
cdcb0ab6 LW |
640 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
641 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 642 | const struct msm_pingroup *g; |
f365be09 BA |
643 | unsigned long flags; |
644 | u32 val; | |
645 | ||
f365be09 BA |
646 | g = &pctrl->soc->groups[d->hwirq]; |
647 | ||
648 | spin_lock_irqsave(&pctrl->lock, flags); | |
649 | ||
650 | /* | |
651 | * For hw without possibility of detecting both edges | |
652 | */ | |
653 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
654 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
655 | else | |
656 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
657 | ||
658 | /* Route interrupts to application cpu */ | |
659 | val = readl(pctrl->regs + g->intr_target_reg); | |
660 | val &= ~(7 << g->intr_target_bit); | |
f712c554 | 661 | val |= g->intr_target_kpss_val << g->intr_target_bit; |
f365be09 BA |
662 | writel(val, pctrl->regs + g->intr_target_reg); |
663 | ||
664 | /* Update configuration for gpio. | |
665 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
666 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
667 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
668 | */ | |
669 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
670 | val |= BIT(g->intr_raw_status_bit); | |
671 | if (g->intr_detection_width == 2) { | |
672 | val &= ~(3 << g->intr_detection_bit); | |
673 | val &= ~(1 << g->intr_polarity_bit); | |
674 | switch (type) { | |
675 | case IRQ_TYPE_EDGE_RISING: | |
676 | val |= 1 << g->intr_detection_bit; | |
677 | val |= BIT(g->intr_polarity_bit); | |
678 | break; | |
679 | case IRQ_TYPE_EDGE_FALLING: | |
680 | val |= 2 << g->intr_detection_bit; | |
681 | val |= BIT(g->intr_polarity_bit); | |
682 | break; | |
683 | case IRQ_TYPE_EDGE_BOTH: | |
684 | val |= 3 << g->intr_detection_bit; | |
685 | val |= BIT(g->intr_polarity_bit); | |
686 | break; | |
687 | case IRQ_TYPE_LEVEL_LOW: | |
688 | break; | |
689 | case IRQ_TYPE_LEVEL_HIGH: | |
690 | val |= BIT(g->intr_polarity_bit); | |
691 | break; | |
692 | } | |
693 | } else if (g->intr_detection_width == 1) { | |
694 | val &= ~(1 << g->intr_detection_bit); | |
695 | val &= ~(1 << g->intr_polarity_bit); | |
696 | switch (type) { | |
697 | case IRQ_TYPE_EDGE_RISING: | |
698 | val |= BIT(g->intr_detection_bit); | |
699 | val |= BIT(g->intr_polarity_bit); | |
700 | break; | |
701 | case IRQ_TYPE_EDGE_FALLING: | |
702 | val |= BIT(g->intr_detection_bit); | |
703 | break; | |
704 | case IRQ_TYPE_EDGE_BOTH: | |
705 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 706 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
707 | break; |
708 | case IRQ_TYPE_LEVEL_LOW: | |
709 | break; | |
710 | case IRQ_TYPE_LEVEL_HIGH: | |
711 | val |= BIT(g->intr_polarity_bit); | |
712 | break; | |
713 | } | |
714 | } else { | |
715 | BUG(); | |
716 | } | |
717 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
718 | ||
719 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
720 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
721 | ||
722 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
723 | ||
724 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
725 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
726 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
727 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
732 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
733 | { | |
cdcb0ab6 LW |
734 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
735 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 736 | unsigned long flags; |
f365be09 | 737 | |
f365be09 BA |
738 | spin_lock_irqsave(&pctrl->lock, flags); |
739 | ||
6aced33f | 740 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 BA |
741 | |
742 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
f365be09 BA |
747 | static struct irq_chip msm_gpio_irq_chip = { |
748 | .name = "msmgpio", | |
749 | .irq_mask = msm_gpio_irq_mask, | |
750 | .irq_unmask = msm_gpio_irq_unmask, | |
751 | .irq_ack = msm_gpio_irq_ack, | |
752 | .irq_set_type = msm_gpio_irq_set_type, | |
753 | .irq_set_wake = msm_gpio_irq_set_wake, | |
f365be09 BA |
754 | }; |
755 | ||
756 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
757 | { | |
cdcb0ab6 | 758 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
f365be09 | 759 | const struct msm_pingroup *g; |
cdcb0ab6 | 760 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); |
f365be09 BA |
761 | struct irq_chip *chip = irq_get_chip(irq); |
762 | int irq_pin; | |
763 | int handled = 0; | |
764 | u32 val; | |
765 | int i; | |
766 | ||
767 | chained_irq_enter(chip, desc); | |
768 | ||
769 | /* | |
1f2b2398 | 770 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
771 | * enabled_irq bitmap to limit the number of reads. |
772 | */ | |
773 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
774 | g = &pctrl->soc->groups[i]; | |
775 | val = readl(pctrl->regs + g->intr_status_reg); | |
776 | if (val & BIT(g->intr_status_bit)) { | |
cdcb0ab6 | 777 | irq_pin = irq_find_mapping(gc->irqdomain, i); |
f365be09 BA |
778 | generic_handle_irq(irq_pin); |
779 | handled++; | |
780 | } | |
781 | } | |
782 | ||
1f2b2398 | 783 | /* No interrupts were flagged */ |
f365be09 BA |
784 | if (handled == 0) |
785 | handle_bad_irq(irq, desc); | |
786 | ||
787 | chained_irq_exit(chip, desc); | |
788 | } | |
789 | ||
790 | static int msm_gpio_init(struct msm_pinctrl *pctrl) | |
791 | { | |
792 | struct gpio_chip *chip; | |
f365be09 | 793 | int ret; |
dcd278b8 SB |
794 | unsigned ngpio = pctrl->soc->ngpios; |
795 | ||
796 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
797 | return -EINVAL; | |
f365be09 BA |
798 | |
799 | chip = &pctrl->chip; | |
800 | chip->base = 0; | |
dcd278b8 | 801 | chip->ngpio = ngpio; |
f365be09 BA |
802 | chip->label = dev_name(pctrl->dev); |
803 | chip->dev = pctrl->dev; | |
804 | chip->owner = THIS_MODULE; | |
805 | chip->of_node = pctrl->dev->of_node; | |
806 | ||
f365be09 BA |
807 | ret = gpiochip_add(&pctrl->chip); |
808 | if (ret) { | |
809 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
810 | return ret; | |
811 | } | |
812 | ||
813 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
814 | if (ret) { | |
815 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
c6e927a2 | 816 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
817 | return ret; |
818 | } | |
819 | ||
cdcb0ab6 LW |
820 | ret = gpiochip_irqchip_add(chip, |
821 | &msm_gpio_irq_chip, | |
822 | 0, | |
823 | handle_edge_irq, | |
824 | IRQ_TYPE_NONE); | |
825 | if (ret) { | |
826 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); | |
c6e927a2 | 827 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
828 | return -ENOSYS; |
829 | } | |
830 | ||
cdcb0ab6 LW |
831 | gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, |
832 | msm_gpio_irq_handler); | |
f365be09 BA |
833 | |
834 | return 0; | |
835 | } | |
836 | ||
cf1fc187 JC |
837 | static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, |
838 | void *data) | |
32745581 | 839 | { |
cf1fc187 JC |
840 | struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); |
841 | ||
842 | writel(0, pctrl->regs + PS_HOLD_OFFSET); | |
843 | mdelay(1000); | |
844 | return NOTIFY_DONE; | |
32745581 PG |
845 | } |
846 | ||
847 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) | |
848 | { | |
bcd53f85 | 849 | int i; |
32745581 PG |
850 | const struct msm_function *func = pctrl->soc->functions; |
851 | ||
bcd53f85 | 852 | for (i = 0; i < pctrl->soc->nfunctions; i++) |
32745581 | 853 | if (!strcmp(func[i].name, "ps_hold")) { |
cf1fc187 JC |
854 | pctrl->restart_nb.notifier_call = msm_ps_hold_restart; |
855 | pctrl->restart_nb.priority = 128; | |
856 | if (register_restart_handler(&pctrl->restart_nb)) | |
857 | dev_err(pctrl->dev, | |
858 | "failed to setup restart handler.\n"); | |
859 | break; | |
32745581 PG |
860 | } |
861 | } | |
32745581 | 862 | |
f365be09 BA |
863 | int msm_pinctrl_probe(struct platform_device *pdev, |
864 | const struct msm_pinctrl_soc_data *soc_data) | |
865 | { | |
866 | struct msm_pinctrl *pctrl; | |
867 | struct resource *res; | |
868 | int ret; | |
869 | ||
870 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
871 | if (!pctrl) { | |
872 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
873 | return -ENOMEM; | |
874 | } | |
875 | pctrl->dev = &pdev->dev; | |
876 | pctrl->soc = soc_data; | |
877 | pctrl->chip = msm_gpio_template; | |
878 | ||
879 | spin_lock_init(&pctrl->lock); | |
880 | ||
881 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
882 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
883 | if (IS_ERR(pctrl->regs)) | |
884 | return PTR_ERR(pctrl->regs); | |
885 | ||
32745581 PG |
886 | msm_pinctrl_setup_pm_reset(pctrl); |
887 | ||
f393e489 | 888 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
889 | if (pctrl->irq < 0) { |
890 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
891 | return pctrl->irq; | |
892 | } | |
893 | ||
894 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
895 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
896 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
897 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); | |
898 | if (!pctrl->pctrl) { | |
899 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
900 | return -ENODEV; | |
901 | } | |
902 | ||
903 | ret = msm_gpio_init(pctrl); | |
904 | if (ret) { | |
905 | pinctrl_unregister(pctrl->pctrl); | |
906 | return ret; | |
907 | } | |
908 | ||
909 | platform_set_drvdata(pdev, pctrl); | |
910 | ||
911 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
912 | ||
913 | return 0; | |
914 | } | |
915 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
916 | ||
917 | int msm_pinctrl_remove(struct platform_device *pdev) | |
918 | { | |
919 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
f393e489 | 920 | |
2fcea6ce | 921 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
922 | pinctrl_unregister(pctrl->pctrl); |
923 | ||
cf1fc187 JC |
924 | unregister_restart_handler(&pctrl->restart_nb); |
925 | ||
f365be09 BA |
926 | return 0; |
927 | } | |
928 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
929 |