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cfb24f6e II |
1 | /* |
2 | * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/gpio.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
ab4256cf | 17 | #include <linux/of_irq.h> |
cfb24f6e II |
18 | #include <linux/pinctrl/pinconf-generic.h> |
19 | #include <linux/pinctrl/pinconf.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/types.h> | |
25 | ||
26 | #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> | |
27 | ||
28 | #include "../core.h" | |
29 | #include "../pinctrl-utils.h" | |
30 | ||
31 | #define PMIC_MPP_ADDRESS_RANGE 0x100 | |
32 | ||
33 | /* | |
34 | * Pull Up Values - it indicates whether a pull-up should be | |
35 | * applied for bidirectional mode only. The hardware ignores the | |
36 | * configuration when operating in other modes. | |
37 | */ | |
38 | #define PMIC_MPP_PULL_UP_0P6KOHM 0 | |
39 | #define PMIC_MPP_PULL_UP_10KOHM 1 | |
40 | #define PMIC_MPP_PULL_UP_30KOHM 2 | |
41 | #define PMIC_MPP_PULL_UP_OPEN 3 | |
42 | ||
43 | /* type registers base address bases */ | |
44 | #define PMIC_MPP_REG_TYPE 0x4 | |
45 | #define PMIC_MPP_REG_SUBTYPE 0x5 | |
46 | ||
47 | /* mpp peripheral type and subtype values */ | |
48 | #define PMIC_MPP_TYPE 0x11 | |
49 | #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 | |
50 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 | |
51 | #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 | |
52 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 | |
53 | #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 | |
54 | #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf | |
55 | ||
56 | #define PMIC_MPP_REG_RT_STS 0x10 | |
57 | #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 | |
58 | ||
59 | /* control register base address bases */ | |
60 | #define PMIC_MPP_REG_MODE_CTL 0x40 | |
61 | #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 | |
62 | #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 | |
63 | #define PMIC_MPP_REG_DIG_IN_CTL 0x43 | |
64 | #define PMIC_MPP_REG_EN_CTL 0x46 | |
099f3e4a | 65 | #define PMIC_MPP_REG_AOUT_CTL 0x48 |
cfb24f6e | 66 | #define PMIC_MPP_REG_AIN_CTL 0x4a |
0e948042 | 67 | #define PMIC_MPP_REG_SINK_CTL 0x4c |
cfb24f6e II |
68 | |
69 | /* PMIC_MPP_REG_MODE_CTL */ | |
70 | #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 | |
71 | #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 | |
72 | #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 | |
73 | #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 | |
74 | #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 | |
75 | ||
76 | /* PMIC_MPP_REG_DIG_VIN_CTL */ | |
77 | #define PMIC_MPP_REG_VIN_SHIFT 0 | |
78 | #define PMIC_MPP_REG_VIN_MASK 0x7 | |
79 | ||
80 | /* PMIC_MPP_REG_DIG_PULL_CTL */ | |
81 | #define PMIC_MPP_REG_PULL_SHIFT 0 | |
82 | #define PMIC_MPP_REG_PULL_MASK 0x7 | |
83 | ||
84 | /* PMIC_MPP_REG_EN_CTL */ | |
85 | #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 | |
86 | ||
87 | /* PMIC_MPP_REG_AIN_CTL */ | |
88 | #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 | |
89 | #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 | |
90 | ||
eaaf5dd4 BA |
91 | #define PMIC_MPP_MODE_DIGITAL_INPUT 0 |
92 | #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 | |
93 | #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 | |
94 | #define PMIC_MPP_MODE_ANALOG_BIDIR 3 | |
95 | #define PMIC_MPP_MODE_ANALOG_INPUT 4 | |
96 | #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 | |
97 | #define PMIC_MPP_MODE_CURRENT_SINK 6 | |
98 | ||
eb5c144c BA |
99 | #define PMIC_MPP_SELECTOR_NORMAL 0 |
100 | #define PMIC_MPP_SELECTOR_PAIRED 1 | |
101 | #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 | |
102 | ||
cfb24f6e II |
103 | #define PMIC_MPP_PHYSICAL_OFFSET 1 |
104 | ||
105 | /* Qualcomm specific pin configurations */ | |
106 | #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) | |
eb5c144c BA |
107 | #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) |
108 | #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) | |
109 | #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) | |
cfb24f6e II |
110 | |
111 | /** | |
112 | * struct pmic_mpp_pad - keep current MPP settings | |
113 | * @base: Address base in SPMI device. | |
114 | * @irq: IRQ number which this MPP generate. | |
115 | * @is_enabled: Set to false when MPP should be put in high Z state. | |
116 | * @out_value: Cached pin output value. | |
117 | * @output_enabled: Set to true if MPP output logic is enabled. | |
118 | * @input_enabled: Set to true if MPP input buffer logic is enabled. | |
eb5c144c | 119 | * @paired: Pin operates in paired mode |
ae6d54fd | 120 | * @has_pullup: Pin has support to configure pullup |
cfb24f6e II |
121 | * @num_sources: Number of power-sources supported by this MPP. |
122 | * @power_source: Current power-source used. | |
123 | * @amux_input: Set the source for analog input. | |
099f3e4a | 124 | * @aout_level: Analog output level |
cfb24f6e II |
125 | * @pullup: Pullup resistor value. Valid in Bidirectional mode only. |
126 | * @function: See pmic_mpp_functions[]. | |
0e948042 | 127 | * @drive_strength: Amount of current in sink mode |
eb5c144c | 128 | * @dtest: DTEST route selector |
cfb24f6e II |
129 | */ |
130 | struct pmic_mpp_pad { | |
131 | u16 base; | |
132 | int irq; | |
133 | bool is_enabled; | |
134 | bool out_value; | |
135 | bool output_enabled; | |
136 | bool input_enabled; | |
eb5c144c | 137 | bool paired; |
ae6d54fd | 138 | bool has_pullup; |
cfb24f6e II |
139 | unsigned int num_sources; |
140 | unsigned int power_source; | |
141 | unsigned int amux_input; | |
099f3e4a | 142 | unsigned int aout_level; |
cfb24f6e II |
143 | unsigned int pullup; |
144 | unsigned int function; | |
0e948042 | 145 | unsigned int drive_strength; |
eb5c144c | 146 | unsigned int dtest; |
cfb24f6e II |
147 | }; |
148 | ||
149 | struct pmic_mpp_state { | |
150 | struct device *dev; | |
151 | struct regmap *map; | |
152 | struct pinctrl_dev *ctrl; | |
153 | struct gpio_chip chip; | |
154 | }; | |
155 | ||
ba5f94cd BA |
156 | static const struct pinconf_generic_params pmic_mpp_bindings[] = { |
157 | {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, | |
099f3e4a | 158 | {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, |
eb5c144c BA |
159 | {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, |
160 | {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, | |
cfb24f6e II |
161 | }; |
162 | ||
ba5f94cd BA |
163 | #ifdef CONFIG_DEBUG_FS |
164 | static const struct pin_config_item pmic_conf_items[] = { | |
165 | PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), | |
099f3e4a | 166 | PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), |
eb5c144c BA |
167 | PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), |
168 | PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), | |
cfb24f6e | 169 | }; |
ba5f94cd | 170 | #endif |
cfb24f6e II |
171 | |
172 | static const char *const pmic_mpp_groups[] = { | |
173 | "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", | |
174 | }; | |
175 | ||
eb5c144c BA |
176 | #define PMIC_MPP_DIGITAL 0 |
177 | #define PMIC_MPP_ANALOG 1 | |
178 | #define PMIC_MPP_SINK 2 | |
179 | ||
cfb24f6e | 180 | static const char *const pmic_mpp_functions[] = { |
eb5c144c | 181 | "digital", "analog", "sink" |
cfb24f6e II |
182 | }; |
183 | ||
cfb24f6e II |
184 | static int pmic_mpp_read(struct pmic_mpp_state *state, |
185 | struct pmic_mpp_pad *pad, unsigned int addr) | |
186 | { | |
187 | unsigned int val; | |
188 | int ret; | |
189 | ||
190 | ret = regmap_read(state->map, pad->base + addr, &val); | |
191 | if (ret < 0) | |
192 | dev_err(state->dev, "read 0x%x failed\n", addr); | |
193 | else | |
194 | ret = val; | |
195 | ||
196 | return ret; | |
197 | } | |
198 | ||
199 | static int pmic_mpp_write(struct pmic_mpp_state *state, | |
200 | struct pmic_mpp_pad *pad, unsigned int addr, | |
201 | unsigned int val) | |
202 | { | |
203 | int ret; | |
204 | ||
205 | ret = regmap_write(state->map, pad->base + addr, val); | |
206 | if (ret < 0) | |
207 | dev_err(state->dev, "write 0x%x failed\n", addr); | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
212 | static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) | |
213 | { | |
214 | /* Every PIN is a group */ | |
215 | return pctldev->desc->npins; | |
216 | } | |
217 | ||
218 | static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, | |
219 | unsigned pin) | |
220 | { | |
221 | return pctldev->desc->pins[pin].name; | |
222 | } | |
223 | ||
224 | static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, | |
225 | unsigned pin, | |
226 | const unsigned **pins, unsigned *num_pins) | |
227 | { | |
228 | *pins = &pctldev->desc->pins[pin].number; | |
229 | *num_pins = 1; | |
230 | return 0; | |
231 | } | |
232 | ||
cfb24f6e II |
233 | static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { |
234 | .get_groups_count = pmic_mpp_get_groups_count, | |
235 | .get_group_name = pmic_mpp_get_group_name, | |
236 | .get_group_pins = pmic_mpp_get_group_pins, | |
ba5f94cd | 237 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
cfb24f6e II |
238 | .dt_free_map = pinctrl_utils_dt_free_map, |
239 | }; | |
240 | ||
241 | static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) | |
242 | { | |
243 | return ARRAY_SIZE(pmic_mpp_functions); | |
244 | } | |
245 | ||
246 | static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, | |
247 | unsigned function) | |
248 | { | |
249 | return pmic_mpp_functions[function]; | |
250 | } | |
251 | ||
252 | static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, | |
253 | unsigned function, | |
254 | const char *const **groups, | |
255 | unsigned *const num_qgroups) | |
256 | { | |
257 | *groups = pmic_mpp_groups; | |
258 | *num_qgroups = pctldev->desc->npins; | |
259 | return 0; | |
260 | } | |
261 | ||
0e948042 BA |
262 | static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, |
263 | struct pmic_mpp_pad *pad) | |
cfb24f6e | 264 | { |
eb5c144c BA |
265 | unsigned int mode; |
266 | unsigned int sel; | |
cfb24f6e | 267 | unsigned int val; |
eb5c144c BA |
268 | unsigned int en; |
269 | ||
270 | switch (pad->function) { | |
271 | case PMIC_MPP_ANALOG: | |
272 | if (pad->input_enabled && pad->output_enabled) | |
273 | mode = PMIC_MPP_MODE_ANALOG_BIDIR; | |
274 | else if (pad->input_enabled) | |
275 | mode = PMIC_MPP_MODE_ANALOG_INPUT; | |
276 | else | |
277 | mode = PMIC_MPP_MODE_ANALOG_OUTPUT; | |
278 | break; | |
279 | case PMIC_MPP_DIGITAL: | |
280 | if (pad->input_enabled && pad->output_enabled) | |
281 | mode = PMIC_MPP_MODE_DIGITAL_BIDIR; | |
282 | else if (pad->input_enabled) | |
283 | mode = PMIC_MPP_MODE_DIGITAL_INPUT; | |
284 | else | |
285 | mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; | |
286 | break; | |
287 | case PMIC_MPP_SINK: | |
288 | default: | |
289 | mode = PMIC_MPP_MODE_CURRENT_SINK; | |
290 | break; | |
cfb24f6e II |
291 | } |
292 | ||
eb5c144c BA |
293 | if (pad->dtest) |
294 | sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; | |
295 | else if (pad->paired) | |
296 | sel = PMIC_MPP_SELECTOR_PAIRED; | |
297 | else | |
298 | sel = PMIC_MPP_SELECTOR_NORMAL; | |
299 | ||
300 | en = !!pad->out_value; | |
301 | ||
302 | val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | | |
303 | sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | | |
304 | en; | |
cfb24f6e | 305 | |
0e948042 BA |
306 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); |
307 | } | |
308 | ||
309 | static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
310 | unsigned pin) | |
311 | { | |
312 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
313 | struct pmic_mpp_pad *pad; | |
314 | unsigned int val; | |
315 | int ret; | |
316 | ||
317 | pad = pctldev->desc->pins[pin].drv_data; | |
318 | ||
319 | pad->function = function; | |
320 | ||
321 | ret = pmic_mpp_write_mode_ctl(state, pad); | |
cfb24f6e II |
322 | |
323 | val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; | |
324 | ||
325 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); | |
326 | } | |
327 | ||
328 | static const struct pinmux_ops pmic_mpp_pinmux_ops = { | |
329 | .get_functions_count = pmic_mpp_get_functions_count, | |
330 | .get_function_name = pmic_mpp_get_function_name, | |
331 | .get_function_groups = pmic_mpp_get_function_groups, | |
332 | .set_mux = pmic_mpp_set_mux, | |
333 | }; | |
334 | ||
335 | static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, | |
336 | unsigned int pin, unsigned long *config) | |
337 | { | |
338 | unsigned param = pinconf_to_config_param(*config); | |
339 | struct pmic_mpp_pad *pad; | |
340 | unsigned arg = 0; | |
341 | ||
342 | pad = pctldev->desc->pins[pin].drv_data; | |
343 | ||
344 | switch (param) { | |
345 | case PIN_CONFIG_BIAS_DISABLE: | |
346 | arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN; | |
347 | break; | |
348 | case PIN_CONFIG_BIAS_PULL_UP: | |
349 | switch (pad->pullup) { | |
350 | case PMIC_MPP_PULL_UP_OPEN: | |
351 | arg = 0; | |
352 | break; | |
353 | case PMIC_MPP_PULL_UP_0P6KOHM: | |
354 | arg = 600; | |
355 | break; | |
356 | case PMIC_MPP_PULL_UP_10KOHM: | |
357 | arg = 10000; | |
358 | break; | |
359 | case PMIC_MPP_PULL_UP_30KOHM: | |
360 | arg = 30000; | |
361 | break; | |
362 | default: | |
363 | return -EINVAL; | |
364 | } | |
365 | break; | |
366 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
367 | arg = !pad->is_enabled; | |
368 | break; | |
369 | case PIN_CONFIG_POWER_SOURCE: | |
370 | arg = pad->power_source; | |
371 | break; | |
372 | case PIN_CONFIG_INPUT_ENABLE: | |
373 | arg = pad->input_enabled; | |
374 | break; | |
375 | case PIN_CONFIG_OUTPUT: | |
376 | arg = pad->out_value; | |
377 | break; | |
eb5c144c BA |
378 | case PMIC_MPP_CONF_DTEST_SELECTOR: |
379 | arg = pad->dtest; | |
380 | break; | |
cfb24f6e II |
381 | case PMIC_MPP_CONF_AMUX_ROUTE: |
382 | arg = pad->amux_input; | |
383 | break; | |
eb5c144c BA |
384 | case PMIC_MPP_CONF_PAIRED: |
385 | arg = pad->paired; | |
386 | break; | |
0e948042 BA |
387 | case PIN_CONFIG_DRIVE_STRENGTH: |
388 | arg = pad->drive_strength; | |
389 | break; | |
099f3e4a BA |
390 | case PMIC_MPP_CONF_ANALOG_LEVEL: |
391 | arg = pad->aout_level; | |
392 | break; | |
cfb24f6e II |
393 | default: |
394 | return -EINVAL; | |
395 | } | |
396 | ||
397 | /* Convert register value to pinconf value */ | |
398 | *config = pinconf_to_config_packed(param, arg); | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
403 | unsigned long *configs, unsigned nconfs) | |
404 | { | |
405 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
406 | struct pmic_mpp_pad *pad; | |
407 | unsigned param, arg; | |
408 | unsigned int val; | |
409 | int i, ret; | |
410 | ||
411 | pad = pctldev->desc->pins[pin].drv_data; | |
412 | ||
7682b374 BA |
413 | /* Make it possible to enable the pin, by not setting high impedance */ |
414 | pad->is_enabled = true; | |
415 | ||
cfb24f6e II |
416 | for (i = 0; i < nconfs; i++) { |
417 | param = pinconf_to_config_param(configs[i]); | |
418 | arg = pinconf_to_config_argument(configs[i]); | |
419 | ||
420 | switch (param) { | |
421 | case PIN_CONFIG_BIAS_DISABLE: | |
422 | pad->pullup = PMIC_MPP_PULL_UP_OPEN; | |
423 | break; | |
424 | case PIN_CONFIG_BIAS_PULL_UP: | |
425 | switch (arg) { | |
426 | case 600: | |
427 | pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; | |
428 | break; | |
429 | case 10000: | |
430 | pad->pullup = PMIC_MPP_PULL_UP_10KOHM; | |
431 | break; | |
432 | case 30000: | |
433 | pad->pullup = PMIC_MPP_PULL_UP_30KOHM; | |
434 | break; | |
435 | default: | |
436 | return -EINVAL; | |
437 | } | |
438 | break; | |
439 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
440 | pad->is_enabled = false; | |
441 | break; | |
442 | case PIN_CONFIG_POWER_SOURCE: | |
443 | if (arg >= pad->num_sources) | |
444 | return -EINVAL; | |
445 | pad->power_source = arg; | |
446 | break; | |
447 | case PIN_CONFIG_INPUT_ENABLE: | |
448 | pad->input_enabled = arg ? true : false; | |
449 | break; | |
450 | case PIN_CONFIG_OUTPUT: | |
451 | pad->output_enabled = true; | |
452 | pad->out_value = arg; | |
453 | break; | |
eb5c144c BA |
454 | case PMIC_MPP_CONF_DTEST_SELECTOR: |
455 | pad->dtest = arg; | |
456 | break; | |
0e948042 BA |
457 | case PIN_CONFIG_DRIVE_STRENGTH: |
458 | arg = pad->drive_strength; | |
459 | break; | |
cfb24f6e II |
460 | case PMIC_MPP_CONF_AMUX_ROUTE: |
461 | if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) | |
462 | return -EINVAL; | |
463 | pad->amux_input = arg; | |
464 | break; | |
099f3e4a BA |
465 | case PMIC_MPP_CONF_ANALOG_LEVEL: |
466 | pad->aout_level = arg; | |
467 | break; | |
eb5c144c BA |
468 | case PMIC_MPP_CONF_PAIRED: |
469 | pad->paired = !!arg; | |
cfb24f6e II |
470 | break; |
471 | default: | |
472 | return -EINVAL; | |
473 | } | |
474 | } | |
475 | ||
476 | val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; | |
477 | ||
478 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); | |
479 | if (ret < 0) | |
480 | return ret; | |
481 | ||
ae6d54fd SB |
482 | if (pad->has_pullup) { |
483 | val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; | |
cfb24f6e | 484 | |
ae6d54fd SB |
485 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, |
486 | val); | |
487 | if (ret < 0) | |
488 | return ret; | |
489 | } | |
cfb24f6e II |
490 | |
491 | val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; | |
492 | ||
493 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); | |
494 | if (ret < 0) | |
495 | return ret; | |
496 | ||
099f3e4a BA |
497 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); |
498 | if (ret < 0) | |
499 | return ret; | |
500 | ||
0e948042 | 501 | ret = pmic_mpp_write_mode_ctl(state, pad); |
7682b374 BA |
502 | if (ret < 0) |
503 | return ret; | |
504 | ||
505 | val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; | |
506 | ||
507 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); | |
cfb24f6e II |
508 | } |
509 | ||
510 | static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, | |
511 | struct seq_file *s, unsigned pin) | |
512 | { | |
513 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
514 | struct pmic_mpp_pad *pad; | |
7682b374 | 515 | int ret; |
cfb24f6e II |
516 | |
517 | static const char *const biases[] = { | |
518 | "0.6kOhm", "10kOhm", "30kOhm", "Disabled" | |
519 | }; | |
520 | ||
cfb24f6e II |
521 | pad = pctldev->desc->pins[pin].drv_data; |
522 | ||
523 | seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); | |
524 | ||
7682b374 | 525 | if (!pad->is_enabled) { |
cfb24f6e II |
526 | seq_puts(s, " ---"); |
527 | } else { | |
528 | ||
529 | if (pad->input_enabled) { | |
530 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
4e637ac2 II |
531 | if (ret < 0) |
532 | return; | |
533 | ||
534 | ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; | |
535 | pad->out_value = ret; | |
cfb24f6e II |
536 | } |
537 | ||
538 | seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); | |
cfb24f6e II |
539 | seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); |
540 | seq_printf(s, " vin-%d", pad->power_source); | |
099f3e4a | 541 | seq_printf(s, " %d", pad->aout_level); |
ae6d54fd SB |
542 | if (pad->has_pullup) |
543 | seq_printf(s, " %-8s", biases[pad->pullup]); | |
cfb24f6e | 544 | seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); |
eb5c144c BA |
545 | if (pad->dtest) |
546 | seq_printf(s, " dtest%d", pad->dtest); | |
547 | if (pad->paired) | |
548 | seq_puts(s, " paired"); | |
cfb24f6e II |
549 | } |
550 | } | |
551 | ||
552 | static const struct pinconf_ops pmic_mpp_pinconf_ops = { | |
ba5f94cd | 553 | .is_generic = true, |
cfb24f6e II |
554 | .pin_config_group_get = pmic_mpp_config_get, |
555 | .pin_config_group_set = pmic_mpp_config_set, | |
556 | .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, | |
557 | }; | |
558 | ||
559 | static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) | |
560 | { | |
064761d1 | 561 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
562 | unsigned long config; |
563 | ||
564 | config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); | |
565 | ||
566 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
567 | } | |
568 | ||
569 | static int pmic_mpp_direction_output(struct gpio_chip *chip, | |
570 | unsigned pin, int val) | |
571 | { | |
064761d1 | 572 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
573 | unsigned long config; |
574 | ||
575 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); | |
576 | ||
577 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
578 | } | |
579 | ||
580 | static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) | |
581 | { | |
064761d1 | 582 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
583 | struct pmic_mpp_pad *pad; |
584 | int ret; | |
585 | ||
586 | pad = state->ctrl->desc->pins[pin].drv_data; | |
587 | ||
588 | if (pad->input_enabled) { | |
589 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
590 | if (ret < 0) | |
591 | return ret; | |
592 | ||
593 | pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; | |
594 | } | |
595 | ||
59663a4c | 596 | return !!pad->out_value; |
cfb24f6e II |
597 | } |
598 | ||
599 | static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) | |
600 | { | |
064761d1 | 601 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
602 | unsigned long config; |
603 | ||
604 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); | |
605 | ||
606 | pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
607 | } | |
608 | ||
cfb24f6e II |
609 | static int pmic_mpp_of_xlate(struct gpio_chip *chip, |
610 | const struct of_phandle_args *gpio_desc, | |
611 | u32 *flags) | |
612 | { | |
613 | if (chip->of_gpio_n_cells < 2) | |
614 | return -EINVAL; | |
615 | ||
616 | if (flags) | |
617 | *flags = gpio_desc->args[1]; | |
618 | ||
619 | return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; | |
620 | } | |
621 | ||
622 | static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) | |
623 | { | |
064761d1 | 624 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
625 | struct pmic_mpp_pad *pad; |
626 | ||
627 | pad = state->ctrl->desc->pins[pin].drv_data; | |
628 | ||
629 | return pad->irq; | |
630 | } | |
631 | ||
632 | static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
633 | { | |
064761d1 | 634 | struct pmic_mpp_state *state = gpiochip_get_data(chip); |
cfb24f6e II |
635 | unsigned i; |
636 | ||
637 | for (i = 0; i < chip->ngpio; i++) { | |
638 | pmic_mpp_config_dbg_show(state->ctrl, s, i); | |
639 | seq_puts(s, "\n"); | |
640 | } | |
641 | } | |
642 | ||
643 | static const struct gpio_chip pmic_mpp_gpio_template = { | |
644 | .direction_input = pmic_mpp_direction_input, | |
645 | .direction_output = pmic_mpp_direction_output, | |
646 | .get = pmic_mpp_get, | |
647 | .set = pmic_mpp_set, | |
98c85d58 JG |
648 | .request = gpiochip_generic_request, |
649 | .free = gpiochip_generic_free, | |
cfb24f6e II |
650 | .of_xlate = pmic_mpp_of_xlate, |
651 | .to_irq = pmic_mpp_to_irq, | |
652 | .dbg_show = pmic_mpp_dbg_show, | |
653 | }; | |
654 | ||
655 | static int pmic_mpp_populate(struct pmic_mpp_state *state, | |
656 | struct pmic_mpp_pad *pad) | |
657 | { | |
658 | int type, subtype, val, dir; | |
eb5c144c | 659 | unsigned int sel; |
cfb24f6e II |
660 | |
661 | type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); | |
662 | if (type < 0) | |
663 | return type; | |
664 | ||
665 | if (type != PMIC_MPP_TYPE) { | |
666 | dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", | |
667 | type, pad->base); | |
668 | return -ENODEV; | |
669 | } | |
670 | ||
671 | subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); | |
672 | if (subtype < 0) | |
673 | return subtype; | |
674 | ||
675 | switch (subtype) { | |
676 | case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: | |
677 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: | |
678 | case PMIC_MPP_SUBTYPE_4CH_NO_SINK: | |
679 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: | |
680 | case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: | |
681 | pad->num_sources = 4; | |
682 | break; | |
683 | case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: | |
684 | pad->num_sources = 8; | |
685 | break; | |
686 | default: | |
687 | dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", | |
688 | subtype, pad->base); | |
689 | return -ENODEV; | |
690 | } | |
691 | ||
692 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); | |
693 | if (val < 0) | |
694 | return val; | |
695 | ||
696 | pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; | |
697 | ||
698 | dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; | |
699 | dir &= PMIC_MPP_REG_MODE_DIR_MASK; | |
700 | ||
701 | switch (dir) { | |
eaaf5dd4 | 702 | case PMIC_MPP_MODE_DIGITAL_INPUT: |
cfb24f6e II |
703 | pad->input_enabled = true; |
704 | pad->output_enabled = false; | |
eb5c144c | 705 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 706 | break; |
eaaf5dd4 | 707 | case PMIC_MPP_MODE_DIGITAL_OUTPUT: |
cfb24f6e II |
708 | pad->input_enabled = false; |
709 | pad->output_enabled = true; | |
eb5c144c | 710 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 711 | break; |
eaaf5dd4 | 712 | case PMIC_MPP_MODE_DIGITAL_BIDIR: |
cfb24f6e II |
713 | pad->input_enabled = true; |
714 | pad->output_enabled = true; | |
eb5c144c | 715 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 716 | break; |
eaaf5dd4 | 717 | case PMIC_MPP_MODE_ANALOG_BIDIR: |
cfb24f6e II |
718 | pad->input_enabled = true; |
719 | pad->output_enabled = true; | |
eb5c144c | 720 | pad->function = PMIC_MPP_ANALOG; |
cfb24f6e | 721 | break; |
eaaf5dd4 | 722 | case PMIC_MPP_MODE_ANALOG_INPUT: |
cfb24f6e II |
723 | pad->input_enabled = true; |
724 | pad->output_enabled = false; | |
eb5c144c | 725 | pad->function = PMIC_MPP_ANALOG; |
cfb24f6e | 726 | break; |
eaaf5dd4 | 727 | case PMIC_MPP_MODE_ANALOG_OUTPUT: |
cfb24f6e II |
728 | pad->input_enabled = false; |
729 | pad->output_enabled = true; | |
eb5c144c | 730 | pad->function = PMIC_MPP_ANALOG; |
0e948042 BA |
731 | break; |
732 | case PMIC_MPP_MODE_CURRENT_SINK: | |
733 | pad->input_enabled = false; | |
734 | pad->output_enabled = true; | |
eb5c144c | 735 | pad->function = PMIC_MPP_SINK; |
cfb24f6e II |
736 | break; |
737 | default: | |
738 | dev_err(state->dev, "unknown MPP direction\n"); | |
739 | return -ENODEV; | |
740 | } | |
741 | ||
eb5c144c BA |
742 | sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; |
743 | sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; | |
744 | ||
745 | if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) | |
746 | pad->dtest = sel + 1; | |
747 | else if (sel == PMIC_MPP_SELECTOR_PAIRED) | |
748 | pad->paired = true; | |
cfb24f6e II |
749 | |
750 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); | |
751 | if (val < 0) | |
752 | return val; | |
753 | ||
754 | pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; | |
755 | pad->power_source &= PMIC_MPP_REG_VIN_MASK; | |
756 | ||
ae6d54fd SB |
757 | if (subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT && |
758 | subtype != PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK) { | |
759 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); | |
760 | if (val < 0) | |
761 | return val; | |
cfb24f6e | 762 | |
ae6d54fd SB |
763 | pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; |
764 | pad->pullup &= PMIC_MPP_REG_PULL_MASK; | |
765 | pad->has_pullup = true; | |
766 | } | |
cfb24f6e II |
767 | |
768 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); | |
769 | if (val < 0) | |
770 | return val; | |
771 | ||
772 | pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; | |
773 | pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; | |
774 | ||
0e948042 BA |
775 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); |
776 | if (val < 0) | |
777 | return val; | |
778 | ||
779 | pad->drive_strength = val; | |
780 | ||
099f3e4a BA |
781 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); |
782 | if (val < 0) | |
783 | return val; | |
784 | ||
785 | pad->aout_level = val; | |
786 | ||
7682b374 BA |
787 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); |
788 | if (val < 0) | |
789 | return val; | |
790 | ||
791 | pad->is_enabled = !!val; | |
792 | ||
cfb24f6e II |
793 | return 0; |
794 | } | |
795 | ||
796 | static int pmic_mpp_probe(struct platform_device *pdev) | |
797 | { | |
798 | struct device *dev = &pdev->dev; | |
799 | struct pinctrl_pin_desc *pindesc; | |
800 | struct pinctrl_desc *pctrldesc; | |
801 | struct pmic_mpp_pad *pad, *pads; | |
802 | struct pmic_mpp_state *state; | |
803 | int ret, npins, i; | |
ab4256cf | 804 | u32 reg; |
cfb24f6e | 805 | |
ab4256cf | 806 | ret = of_property_read_u32(dev->of_node, "reg", ®); |
cfb24f6e | 807 | if (ret < 0) { |
ab4256cf | 808 | dev_err(dev, "missing base address"); |
cfb24f6e II |
809 | return ret; |
810 | } | |
811 | ||
a5ea13f0 | 812 | npins = platform_irq_count(pdev); |
cfb24f6e II |
813 | if (!npins) |
814 | return -EINVAL; | |
a5ea13f0 SB |
815 | if (npins < 0) |
816 | return npins; | |
cfb24f6e II |
817 | |
818 | BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); | |
819 | ||
820 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); | |
821 | if (!state) | |
822 | return -ENOMEM; | |
823 | ||
824 | platform_set_drvdata(pdev, state); | |
825 | ||
826 | state->dev = &pdev->dev; | |
827 | state->map = dev_get_regmap(dev->parent, NULL); | |
828 | ||
829 | pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); | |
830 | if (!pindesc) | |
831 | return -ENOMEM; | |
832 | ||
833 | pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); | |
834 | if (!pads) | |
835 | return -ENOMEM; | |
836 | ||
837 | pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); | |
838 | if (!pctrldesc) | |
839 | return -ENOMEM; | |
840 | ||
841 | pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; | |
842 | pctrldesc->pmxops = &pmic_mpp_pinmux_ops; | |
843 | pctrldesc->confops = &pmic_mpp_pinconf_ops; | |
844 | pctrldesc->owner = THIS_MODULE; | |
845 | pctrldesc->name = dev_name(dev); | |
846 | pctrldesc->pins = pindesc; | |
847 | pctrldesc->npins = npins; | |
848 | ||
ba5f94cd BA |
849 | pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); |
850 | pctrldesc->custom_params = pmic_mpp_bindings; | |
851 | #ifdef CONFIG_DEBUG_FS | |
852 | pctrldesc->custom_conf_items = pmic_conf_items; | |
853 | #endif | |
854 | ||
cfb24f6e II |
855 | for (i = 0; i < npins; i++, pindesc++) { |
856 | pad = &pads[i]; | |
857 | pindesc->drv_data = pad; | |
858 | pindesc->number = i; | |
859 | pindesc->name = pmic_mpp_groups[i]; | |
860 | ||
861 | pad->irq = platform_get_irq(pdev, i); | |
862 | if (pad->irq < 0) | |
863 | return pad->irq; | |
864 | ||
ab4256cf | 865 | pad->base = reg + i * PMIC_MPP_ADDRESS_RANGE; |
cfb24f6e II |
866 | |
867 | ret = pmic_mpp_populate(state, pad); | |
868 | if (ret < 0) | |
869 | return ret; | |
870 | } | |
871 | ||
872 | state->chip = pmic_mpp_gpio_template; | |
58383c78 | 873 | state->chip.parent = dev; |
cfb24f6e II |
874 | state->chip.base = -1; |
875 | state->chip.ngpio = npins; | |
876 | state->chip.label = dev_name(dev); | |
877 | state->chip.of_gpio_n_cells = 2; | |
878 | state->chip.can_sleep = false; | |
879 | ||
880 | state->ctrl = pinctrl_register(pctrldesc, dev, state); | |
323de9ef MY |
881 | if (IS_ERR(state->ctrl)) |
882 | return PTR_ERR(state->ctrl); | |
cfb24f6e | 883 | |
064761d1 | 884 | ret = gpiochip_add_data(&state->chip, state); |
cfb24f6e II |
885 | if (ret) { |
886 | dev_err(state->dev, "can't add gpio chip\n"); | |
887 | goto err_chip; | |
888 | } | |
889 | ||
890 | ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); | |
891 | if (ret) { | |
892 | dev_err(dev, "failed to add pin range\n"); | |
893 | goto err_range; | |
894 | } | |
895 | ||
896 | return 0; | |
897 | ||
898 | err_range: | |
899 | gpiochip_remove(&state->chip); | |
900 | err_chip: | |
901 | pinctrl_unregister(state->ctrl); | |
902 | return ret; | |
903 | } | |
904 | ||
905 | static int pmic_mpp_remove(struct platform_device *pdev) | |
906 | { | |
907 | struct pmic_mpp_state *state = platform_get_drvdata(pdev); | |
908 | ||
909 | gpiochip_remove(&state->chip); | |
910 | pinctrl_unregister(state->ctrl); | |
911 | return 0; | |
912 | } | |
913 | ||
914 | static const struct of_device_id pmic_mpp_of_match[] = { | |
915 | { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ | |
7414b099 | 916 | { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ |
cfb24f6e | 917 | { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ |
eb9610f3 | 918 | { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ |
cfb24f6e II |
919 | { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ |
920 | { }, | |
921 | }; | |
922 | ||
923 | MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); | |
924 | ||
925 | static struct platform_driver pmic_mpp_driver = { | |
926 | .driver = { | |
927 | .name = "qcom-spmi-mpp", | |
928 | .of_match_table = pmic_mpp_of_match, | |
929 | }, | |
930 | .probe = pmic_mpp_probe, | |
931 | .remove = pmic_mpp_remove, | |
932 | }; | |
933 | ||
934 | module_platform_driver(pmic_mpp_driver); | |
935 | ||
936 | MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); | |
937 | MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); | |
938 | MODULE_ALIAS("platform:qcom-spmi-mpp"); | |
939 | MODULE_LICENSE("GPL v2"); |