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cfb24f6e II |
1 | /* |
2 | * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/gpio.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/pinctrl/pinconf-generic.h> | |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/types.h> | |
24 | ||
25 | #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> | |
26 | ||
27 | #include "../core.h" | |
28 | #include "../pinctrl-utils.h" | |
29 | ||
30 | #define PMIC_MPP_ADDRESS_RANGE 0x100 | |
31 | ||
32 | /* | |
33 | * Pull Up Values - it indicates whether a pull-up should be | |
34 | * applied for bidirectional mode only. The hardware ignores the | |
35 | * configuration when operating in other modes. | |
36 | */ | |
37 | #define PMIC_MPP_PULL_UP_0P6KOHM 0 | |
38 | #define PMIC_MPP_PULL_UP_10KOHM 1 | |
39 | #define PMIC_MPP_PULL_UP_30KOHM 2 | |
40 | #define PMIC_MPP_PULL_UP_OPEN 3 | |
41 | ||
42 | /* type registers base address bases */ | |
43 | #define PMIC_MPP_REG_TYPE 0x4 | |
44 | #define PMIC_MPP_REG_SUBTYPE 0x5 | |
45 | ||
46 | /* mpp peripheral type and subtype values */ | |
47 | #define PMIC_MPP_TYPE 0x11 | |
48 | #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 | |
49 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 | |
50 | #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 | |
51 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 | |
52 | #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 | |
53 | #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf | |
54 | ||
55 | #define PMIC_MPP_REG_RT_STS 0x10 | |
56 | #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 | |
57 | ||
58 | /* control register base address bases */ | |
59 | #define PMIC_MPP_REG_MODE_CTL 0x40 | |
60 | #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 | |
61 | #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 | |
62 | #define PMIC_MPP_REG_DIG_IN_CTL 0x43 | |
63 | #define PMIC_MPP_REG_EN_CTL 0x46 | |
64 | #define PMIC_MPP_REG_AIN_CTL 0x4a | |
65 | ||
66 | /* PMIC_MPP_REG_MODE_CTL */ | |
67 | #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 | |
68 | #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 | |
69 | #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 | |
70 | #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 | |
71 | #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 | |
72 | ||
73 | /* PMIC_MPP_REG_DIG_VIN_CTL */ | |
74 | #define PMIC_MPP_REG_VIN_SHIFT 0 | |
75 | #define PMIC_MPP_REG_VIN_MASK 0x7 | |
76 | ||
77 | /* PMIC_MPP_REG_DIG_PULL_CTL */ | |
78 | #define PMIC_MPP_REG_PULL_SHIFT 0 | |
79 | #define PMIC_MPP_REG_PULL_MASK 0x7 | |
80 | ||
81 | /* PMIC_MPP_REG_EN_CTL */ | |
82 | #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 | |
83 | ||
84 | /* PMIC_MPP_REG_AIN_CTL */ | |
85 | #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 | |
86 | #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 | |
87 | ||
88 | #define PMIC_MPP_PHYSICAL_OFFSET 1 | |
89 | ||
90 | /* Qualcomm specific pin configurations */ | |
91 | #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) | |
92 | #define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) | |
93 | ||
94 | /** | |
95 | * struct pmic_mpp_pad - keep current MPP settings | |
96 | * @base: Address base in SPMI device. | |
97 | * @irq: IRQ number which this MPP generate. | |
98 | * @is_enabled: Set to false when MPP should be put in high Z state. | |
99 | * @out_value: Cached pin output value. | |
100 | * @output_enabled: Set to true if MPP output logic is enabled. | |
101 | * @input_enabled: Set to true if MPP input buffer logic is enabled. | |
102 | * @analog_mode: Set to true when MPP should operate in Analog Input, Analog | |
103 | * Output or Bidirectional Analog mode. | |
104 | * @num_sources: Number of power-sources supported by this MPP. | |
105 | * @power_source: Current power-source used. | |
106 | * @amux_input: Set the source for analog input. | |
107 | * @pullup: Pullup resistor value. Valid in Bidirectional mode only. | |
108 | * @function: See pmic_mpp_functions[]. | |
109 | */ | |
110 | struct pmic_mpp_pad { | |
111 | u16 base; | |
112 | int irq; | |
113 | bool is_enabled; | |
114 | bool out_value; | |
115 | bool output_enabled; | |
116 | bool input_enabled; | |
117 | bool analog_mode; | |
118 | unsigned int num_sources; | |
119 | unsigned int power_source; | |
120 | unsigned int amux_input; | |
121 | unsigned int pullup; | |
122 | unsigned int function; | |
123 | }; | |
124 | ||
125 | struct pmic_mpp_state { | |
126 | struct device *dev; | |
127 | struct regmap *map; | |
128 | struct pinctrl_dev *ctrl; | |
129 | struct gpio_chip chip; | |
130 | }; | |
131 | ||
132 | struct pmic_mpp_bindings { | |
133 | const char *property; | |
134 | unsigned param; | |
135 | }; | |
136 | ||
137 | static struct pmic_mpp_bindings pmic_mpp_bindings[] = { | |
138 | {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE}, | |
139 | {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE}, | |
140 | }; | |
141 | ||
142 | static const char *const pmic_mpp_groups[] = { | |
143 | "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", | |
144 | }; | |
145 | ||
146 | static const char *const pmic_mpp_functions[] = { | |
147 | PMIC_MPP_FUNC_NORMAL, PMIC_MPP_FUNC_PAIRED, | |
148 | "reserved1", "reserved2", | |
149 | PMIC_MPP_FUNC_DTEST1, PMIC_MPP_FUNC_DTEST2, | |
150 | PMIC_MPP_FUNC_DTEST3, PMIC_MPP_FUNC_DTEST4, | |
151 | }; | |
152 | ||
153 | static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) | |
154 | { | |
155 | return container_of(chip, struct pmic_mpp_state, chip); | |
156 | }; | |
157 | ||
158 | static int pmic_mpp_read(struct pmic_mpp_state *state, | |
159 | struct pmic_mpp_pad *pad, unsigned int addr) | |
160 | { | |
161 | unsigned int val; | |
162 | int ret; | |
163 | ||
164 | ret = regmap_read(state->map, pad->base + addr, &val); | |
165 | if (ret < 0) | |
166 | dev_err(state->dev, "read 0x%x failed\n", addr); | |
167 | else | |
168 | ret = val; | |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
173 | static int pmic_mpp_write(struct pmic_mpp_state *state, | |
174 | struct pmic_mpp_pad *pad, unsigned int addr, | |
175 | unsigned int val) | |
176 | { | |
177 | int ret; | |
178 | ||
179 | ret = regmap_write(state->map, pad->base + addr, val); | |
180 | if (ret < 0) | |
181 | dev_err(state->dev, "write 0x%x failed\n", addr); | |
182 | ||
183 | return ret; | |
184 | } | |
185 | ||
186 | static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) | |
187 | { | |
188 | /* Every PIN is a group */ | |
189 | return pctldev->desc->npins; | |
190 | } | |
191 | ||
192 | static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, | |
193 | unsigned pin) | |
194 | { | |
195 | return pctldev->desc->pins[pin].name; | |
196 | } | |
197 | ||
198 | static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, | |
199 | unsigned pin, | |
200 | const unsigned **pins, unsigned *num_pins) | |
201 | { | |
202 | *pins = &pctldev->desc->pins[pin].number; | |
203 | *num_pins = 1; | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static int pmic_mpp_parse_dt_config(struct device_node *np, | |
208 | struct pinctrl_dev *pctldev, | |
209 | unsigned long **configs, | |
210 | unsigned int *nconfs) | |
211 | { | |
212 | struct pmic_mpp_bindings *par; | |
213 | unsigned long cfg; | |
214 | int ret, i; | |
215 | u32 val; | |
216 | ||
217 | for (i = 0; i < ARRAY_SIZE(pmic_mpp_bindings); i++) { | |
218 | par = &pmic_mpp_bindings[i]; | |
219 | ret = of_property_read_u32(np, par->property, &val); | |
220 | ||
221 | /* property not found */ | |
222 | if (ret == -EINVAL) | |
223 | continue; | |
224 | ||
225 | /* use zero as default value, when no value is specified */ | |
226 | if (ret) | |
227 | val = 0; | |
228 | ||
229 | dev_dbg(pctldev->dev, "found %s with value %u\n", | |
230 | par->property, val); | |
231 | ||
232 | cfg = pinconf_to_config_packed(par->param, val); | |
233 | ||
234 | ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg); | |
235 | if (ret) | |
236 | return ret; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static int pmic_mpp_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
243 | struct device_node *np, | |
244 | struct pinctrl_map **map, | |
245 | unsigned *reserv, unsigned *nmaps, | |
246 | enum pinctrl_map_type type) | |
247 | { | |
248 | unsigned long *configs = NULL; | |
249 | unsigned nconfs = 0; | |
250 | struct property *prop; | |
251 | const char *group; | |
252 | int ret; | |
253 | ||
254 | ret = pmic_mpp_parse_dt_config(np, pctldev, &configs, &nconfs); | |
255 | if (ret < 0) | |
256 | return ret; | |
257 | ||
258 | if (!nconfs) | |
259 | return 0; | |
260 | ||
261 | ret = of_property_count_strings(np, "pins"); | |
262 | if (ret < 0) | |
263 | goto exit; | |
264 | ||
265 | ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret); | |
266 | if (ret < 0) | |
267 | goto exit; | |
268 | ||
269 | of_property_for_each_string(np, "pins", prop, group) { | |
270 | ret = pinctrl_utils_add_map_configs(pctldev, map, | |
271 | reserv, nmaps, group, | |
272 | configs, nconfs, type); | |
273 | if (ret < 0) | |
274 | break; | |
275 | } | |
276 | exit: | |
277 | kfree(configs); | |
278 | return ret; | |
279 | } | |
280 | ||
281 | static int pmic_mpp_dt_node_to_map(struct pinctrl_dev *pctldev, | |
282 | struct device_node *np_config, | |
283 | struct pinctrl_map **map, unsigned *nmaps) | |
284 | { | |
285 | struct device_node *np; | |
286 | enum pinctrl_map_type type; | |
287 | unsigned reserv; | |
288 | int ret; | |
289 | ||
290 | ret = 0; | |
291 | *map = NULL; | |
292 | *nmaps = 0; | |
293 | reserv = 0; | |
294 | type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
295 | ||
296 | for_each_child_of_node(np_config, np) { | |
297 | ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, | |
298 | &reserv, nmaps, type); | |
299 | if (ret) | |
300 | break; | |
301 | ||
302 | ret = pmic_mpp_dt_subnode_to_map(pctldev, np, map, &reserv, | |
303 | nmaps, type); | |
304 | if (ret) | |
305 | break; | |
306 | } | |
307 | ||
308 | if (ret < 0) | |
309 | pinctrl_utils_dt_free_map(pctldev, *map, *nmaps); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
314 | static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { | |
315 | .get_groups_count = pmic_mpp_get_groups_count, | |
316 | .get_group_name = pmic_mpp_get_group_name, | |
317 | .get_group_pins = pmic_mpp_get_group_pins, | |
318 | .dt_node_to_map = pmic_mpp_dt_node_to_map, | |
319 | .dt_free_map = pinctrl_utils_dt_free_map, | |
320 | }; | |
321 | ||
322 | static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) | |
323 | { | |
324 | return ARRAY_SIZE(pmic_mpp_functions); | |
325 | } | |
326 | ||
327 | static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, | |
328 | unsigned function) | |
329 | { | |
330 | return pmic_mpp_functions[function]; | |
331 | } | |
332 | ||
333 | static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, | |
334 | unsigned function, | |
335 | const char *const **groups, | |
336 | unsigned *const num_qgroups) | |
337 | { | |
338 | *groups = pmic_mpp_groups; | |
339 | *num_qgroups = pctldev->desc->npins; | |
340 | return 0; | |
341 | } | |
342 | ||
343 | static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
344 | unsigned pin) | |
345 | { | |
346 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
347 | struct pmic_mpp_pad *pad; | |
348 | unsigned int val; | |
349 | int ret; | |
350 | ||
351 | pad = pctldev->desc->pins[pin].drv_data; | |
352 | ||
353 | pad->function = function; | |
354 | ||
355 | if (!pad->analog_mode) { | |
356 | val = 0; /* just digital input */ | |
357 | if (pad->output_enabled) { | |
358 | if (pad->input_enabled) | |
359 | val = 2; /* digital input and output */ | |
360 | else | |
361 | val = 1; /* just digital output */ | |
362 | } | |
363 | } else { | |
364 | val = 4; /* just analog input */ | |
365 | if (pad->output_enabled) { | |
366 | if (pad->input_enabled) | |
367 | val = 3; /* analog input and output */ | |
368 | else | |
369 | val = 5; /* just analog output */ | |
370 | } | |
371 | } | |
372 | ||
373 | val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; | |
374 | val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; | |
375 | ||
376 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); | |
377 | if (ret < 0) | |
378 | return ret; | |
379 | ||
380 | val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; | |
381 | ||
382 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); | |
383 | } | |
384 | ||
385 | static const struct pinmux_ops pmic_mpp_pinmux_ops = { | |
386 | .get_functions_count = pmic_mpp_get_functions_count, | |
387 | .get_function_name = pmic_mpp_get_function_name, | |
388 | .get_function_groups = pmic_mpp_get_function_groups, | |
389 | .set_mux = pmic_mpp_set_mux, | |
390 | }; | |
391 | ||
392 | static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, | |
393 | unsigned int pin, unsigned long *config) | |
394 | { | |
395 | unsigned param = pinconf_to_config_param(*config); | |
396 | struct pmic_mpp_pad *pad; | |
397 | unsigned arg = 0; | |
398 | ||
399 | pad = pctldev->desc->pins[pin].drv_data; | |
400 | ||
401 | switch (param) { | |
402 | case PIN_CONFIG_BIAS_DISABLE: | |
403 | arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN; | |
404 | break; | |
405 | case PIN_CONFIG_BIAS_PULL_UP: | |
406 | switch (pad->pullup) { | |
407 | case PMIC_MPP_PULL_UP_OPEN: | |
408 | arg = 0; | |
409 | break; | |
410 | case PMIC_MPP_PULL_UP_0P6KOHM: | |
411 | arg = 600; | |
412 | break; | |
413 | case PMIC_MPP_PULL_UP_10KOHM: | |
414 | arg = 10000; | |
415 | break; | |
416 | case PMIC_MPP_PULL_UP_30KOHM: | |
417 | arg = 30000; | |
418 | break; | |
419 | default: | |
420 | return -EINVAL; | |
421 | } | |
422 | break; | |
423 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
424 | arg = !pad->is_enabled; | |
425 | break; | |
426 | case PIN_CONFIG_POWER_SOURCE: | |
427 | arg = pad->power_source; | |
428 | break; | |
429 | case PIN_CONFIG_INPUT_ENABLE: | |
430 | arg = pad->input_enabled; | |
431 | break; | |
432 | case PIN_CONFIG_OUTPUT: | |
433 | arg = pad->out_value; | |
434 | break; | |
435 | case PMIC_MPP_CONF_AMUX_ROUTE: | |
436 | arg = pad->amux_input; | |
437 | break; | |
438 | case PMIC_MPP_CONF_ANALOG_MODE: | |
439 | arg = pad->analog_mode; | |
440 | break; | |
441 | default: | |
442 | return -EINVAL; | |
443 | } | |
444 | ||
445 | /* Convert register value to pinconf value */ | |
446 | *config = pinconf_to_config_packed(param, arg); | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
451 | unsigned long *configs, unsigned nconfs) | |
452 | { | |
453 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
454 | struct pmic_mpp_pad *pad; | |
455 | unsigned param, arg; | |
456 | unsigned int val; | |
457 | int i, ret; | |
458 | ||
459 | pad = pctldev->desc->pins[pin].drv_data; | |
460 | ||
461 | for (i = 0; i < nconfs; i++) { | |
462 | param = pinconf_to_config_param(configs[i]); | |
463 | arg = pinconf_to_config_argument(configs[i]); | |
464 | ||
465 | switch (param) { | |
466 | case PIN_CONFIG_BIAS_DISABLE: | |
467 | pad->pullup = PMIC_MPP_PULL_UP_OPEN; | |
468 | break; | |
469 | case PIN_CONFIG_BIAS_PULL_UP: | |
470 | switch (arg) { | |
471 | case 600: | |
472 | pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; | |
473 | break; | |
474 | case 10000: | |
475 | pad->pullup = PMIC_MPP_PULL_UP_10KOHM; | |
476 | break; | |
477 | case 30000: | |
478 | pad->pullup = PMIC_MPP_PULL_UP_30KOHM; | |
479 | break; | |
480 | default: | |
481 | return -EINVAL; | |
482 | } | |
483 | break; | |
484 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
485 | pad->is_enabled = false; | |
486 | break; | |
487 | case PIN_CONFIG_POWER_SOURCE: | |
488 | if (arg >= pad->num_sources) | |
489 | return -EINVAL; | |
490 | pad->power_source = arg; | |
491 | break; | |
492 | case PIN_CONFIG_INPUT_ENABLE: | |
493 | pad->input_enabled = arg ? true : false; | |
494 | break; | |
495 | case PIN_CONFIG_OUTPUT: | |
496 | pad->output_enabled = true; | |
497 | pad->out_value = arg; | |
498 | break; | |
499 | case PMIC_MPP_CONF_AMUX_ROUTE: | |
500 | if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) | |
501 | return -EINVAL; | |
502 | pad->amux_input = arg; | |
503 | break; | |
504 | case PMIC_MPP_CONF_ANALOG_MODE: | |
505 | pad->analog_mode = true; | |
506 | break; | |
507 | default: | |
508 | return -EINVAL; | |
509 | } | |
510 | } | |
511 | ||
512 | val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; | |
513 | ||
514 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); | |
515 | if (ret < 0) | |
516 | return ret; | |
517 | ||
518 | val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; | |
519 | ||
520 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val); | |
521 | if (ret < 0) | |
522 | return ret; | |
523 | ||
524 | val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; | |
525 | ||
526 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); | |
527 | if (ret < 0) | |
528 | return ret; | |
529 | ||
530 | if (!pad->analog_mode) { | |
531 | val = 0; /* just digital input */ | |
532 | if (pad->output_enabled) { | |
533 | if (pad->input_enabled) | |
534 | val = 2; /* digital input and output */ | |
535 | else | |
536 | val = 1; /* just digital output */ | |
537 | } | |
538 | } else { | |
539 | val = 4; /* just analog input */ | |
540 | if (pad->output_enabled) { | |
541 | if (pad->input_enabled) | |
542 | val = 3; /* analog input and output */ | |
543 | else | |
544 | val = 5; /* just analog output */ | |
545 | } | |
546 | } | |
547 | ||
548 | val = val << PMIC_MPP_REG_MODE_DIR_SHIFT; | |
549 | val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT; | |
550 | val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK; | |
551 | ||
552 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); | |
553 | } | |
554 | ||
555 | static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, | |
556 | struct seq_file *s, unsigned pin) | |
557 | { | |
558 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
559 | struct pmic_mpp_pad *pad; | |
560 | int ret, val; | |
561 | ||
562 | static const char *const biases[] = { | |
563 | "0.6kOhm", "10kOhm", "30kOhm", "Disabled" | |
564 | }; | |
565 | ||
566 | ||
567 | pad = pctldev->desc->pins[pin].drv_data; | |
568 | ||
569 | seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); | |
570 | ||
571 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); | |
572 | ||
573 | if (val < 0 || !(val >> PMIC_MPP_REG_MASTER_EN_SHIFT)) { | |
574 | seq_puts(s, " ---"); | |
575 | } else { | |
576 | ||
577 | if (pad->input_enabled) { | |
578 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
579 | if (!ret) { | |
580 | ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; | |
581 | pad->out_value = ret; | |
582 | } | |
583 | } | |
584 | ||
585 | seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); | |
586 | seq_printf(s, " %-4s", pad->analog_mode ? "ana" : "dig"); | |
587 | seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); | |
588 | seq_printf(s, " vin-%d", pad->power_source); | |
589 | seq_printf(s, " %-8s", biases[pad->pullup]); | |
590 | seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); | |
591 | } | |
592 | } | |
593 | ||
594 | static const struct pinconf_ops pmic_mpp_pinconf_ops = { | |
595 | .pin_config_group_get = pmic_mpp_config_get, | |
596 | .pin_config_group_set = pmic_mpp_config_set, | |
597 | .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, | |
598 | }; | |
599 | ||
600 | static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) | |
601 | { | |
602 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
603 | unsigned long config; | |
604 | ||
605 | config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); | |
606 | ||
607 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
608 | } | |
609 | ||
610 | static int pmic_mpp_direction_output(struct gpio_chip *chip, | |
611 | unsigned pin, int val) | |
612 | { | |
613 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
614 | unsigned long config; | |
615 | ||
616 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); | |
617 | ||
618 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
619 | } | |
620 | ||
621 | static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) | |
622 | { | |
623 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
624 | struct pmic_mpp_pad *pad; | |
625 | int ret; | |
626 | ||
627 | pad = state->ctrl->desc->pins[pin].drv_data; | |
628 | ||
629 | if (pad->input_enabled) { | |
630 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
631 | if (ret < 0) | |
632 | return ret; | |
633 | ||
634 | pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; | |
635 | } | |
636 | ||
637 | return pad->out_value; | |
638 | } | |
639 | ||
640 | static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) | |
641 | { | |
642 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
643 | unsigned long config; | |
644 | ||
645 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); | |
646 | ||
647 | pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
648 | } | |
649 | ||
650 | static int pmic_mpp_request(struct gpio_chip *chip, unsigned base) | |
651 | { | |
652 | return pinctrl_request_gpio(chip->base + base); | |
653 | } | |
654 | ||
655 | static void pmic_mpp_free(struct gpio_chip *chip, unsigned base) | |
656 | { | |
657 | pinctrl_free_gpio(chip->base + base); | |
658 | } | |
659 | ||
660 | static int pmic_mpp_of_xlate(struct gpio_chip *chip, | |
661 | const struct of_phandle_args *gpio_desc, | |
662 | u32 *flags) | |
663 | { | |
664 | if (chip->of_gpio_n_cells < 2) | |
665 | return -EINVAL; | |
666 | ||
667 | if (flags) | |
668 | *flags = gpio_desc->args[1]; | |
669 | ||
670 | return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; | |
671 | } | |
672 | ||
673 | static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) | |
674 | { | |
675 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
676 | struct pmic_mpp_pad *pad; | |
677 | ||
678 | pad = state->ctrl->desc->pins[pin].drv_data; | |
679 | ||
680 | return pad->irq; | |
681 | } | |
682 | ||
683 | static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
684 | { | |
685 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
686 | unsigned i; | |
687 | ||
688 | for (i = 0; i < chip->ngpio; i++) { | |
689 | pmic_mpp_config_dbg_show(state->ctrl, s, i); | |
690 | seq_puts(s, "\n"); | |
691 | } | |
692 | } | |
693 | ||
694 | static const struct gpio_chip pmic_mpp_gpio_template = { | |
695 | .direction_input = pmic_mpp_direction_input, | |
696 | .direction_output = pmic_mpp_direction_output, | |
697 | .get = pmic_mpp_get, | |
698 | .set = pmic_mpp_set, | |
699 | .request = pmic_mpp_request, | |
700 | .free = pmic_mpp_free, | |
701 | .of_xlate = pmic_mpp_of_xlate, | |
702 | .to_irq = pmic_mpp_to_irq, | |
703 | .dbg_show = pmic_mpp_dbg_show, | |
704 | }; | |
705 | ||
706 | static int pmic_mpp_populate(struct pmic_mpp_state *state, | |
707 | struct pmic_mpp_pad *pad) | |
708 | { | |
709 | int type, subtype, val, dir; | |
710 | ||
711 | type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); | |
712 | if (type < 0) | |
713 | return type; | |
714 | ||
715 | if (type != PMIC_MPP_TYPE) { | |
716 | dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", | |
717 | type, pad->base); | |
718 | return -ENODEV; | |
719 | } | |
720 | ||
721 | subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); | |
722 | if (subtype < 0) | |
723 | return subtype; | |
724 | ||
725 | switch (subtype) { | |
726 | case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: | |
727 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: | |
728 | case PMIC_MPP_SUBTYPE_4CH_NO_SINK: | |
729 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: | |
730 | case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: | |
731 | pad->num_sources = 4; | |
732 | break; | |
733 | case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: | |
734 | pad->num_sources = 8; | |
735 | break; | |
736 | default: | |
737 | dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", | |
738 | subtype, pad->base); | |
739 | return -ENODEV; | |
740 | } | |
741 | ||
742 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); | |
743 | if (val < 0) | |
744 | return val; | |
745 | ||
746 | pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; | |
747 | ||
748 | dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; | |
749 | dir &= PMIC_MPP_REG_MODE_DIR_MASK; | |
750 | ||
751 | switch (dir) { | |
752 | case 0: | |
753 | pad->input_enabled = true; | |
754 | pad->output_enabled = false; | |
755 | pad->analog_mode = false; | |
756 | break; | |
757 | case 1: | |
758 | pad->input_enabled = false; | |
759 | pad->output_enabled = true; | |
760 | pad->analog_mode = false; | |
761 | break; | |
762 | case 2: | |
763 | pad->input_enabled = true; | |
764 | pad->output_enabled = true; | |
765 | pad->analog_mode = false; | |
766 | break; | |
767 | case 3: | |
768 | pad->input_enabled = true; | |
769 | pad->output_enabled = true; | |
770 | pad->analog_mode = true; | |
771 | break; | |
772 | case 4: | |
773 | pad->input_enabled = true; | |
774 | pad->output_enabled = false; | |
775 | pad->analog_mode = true; | |
776 | break; | |
777 | case 5: | |
778 | pad->input_enabled = false; | |
779 | pad->output_enabled = true; | |
780 | pad->analog_mode = true; | |
781 | break; | |
782 | default: | |
783 | dev_err(state->dev, "unknown MPP direction\n"); | |
784 | return -ENODEV; | |
785 | } | |
786 | ||
787 | pad->function = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; | |
788 | pad->function &= PMIC_MPP_REG_MODE_FUNCTION_MASK; | |
789 | ||
790 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); | |
791 | if (val < 0) | |
792 | return val; | |
793 | ||
794 | pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; | |
795 | pad->power_source &= PMIC_MPP_REG_VIN_MASK; | |
796 | ||
797 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); | |
798 | if (val < 0) | |
799 | return val; | |
800 | ||
801 | pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; | |
802 | pad->pullup &= PMIC_MPP_REG_PULL_MASK; | |
803 | ||
804 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); | |
805 | if (val < 0) | |
806 | return val; | |
807 | ||
808 | pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; | |
809 | pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; | |
810 | ||
811 | /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ | |
812 | pad->is_enabled = true; | |
813 | return 0; | |
814 | } | |
815 | ||
816 | static int pmic_mpp_probe(struct platform_device *pdev) | |
817 | { | |
818 | struct device *dev = &pdev->dev; | |
819 | struct pinctrl_pin_desc *pindesc; | |
820 | struct pinctrl_desc *pctrldesc; | |
821 | struct pmic_mpp_pad *pad, *pads; | |
822 | struct pmic_mpp_state *state; | |
823 | int ret, npins, i; | |
824 | u32 res[2]; | |
825 | ||
826 | ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); | |
827 | if (ret < 0) { | |
828 | dev_err(dev, "missing base address and/or range"); | |
829 | return ret; | |
830 | } | |
831 | ||
832 | npins = res[1] / PMIC_MPP_ADDRESS_RANGE; | |
833 | if (!npins) | |
834 | return -EINVAL; | |
835 | ||
836 | BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); | |
837 | ||
838 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); | |
839 | if (!state) | |
840 | return -ENOMEM; | |
841 | ||
842 | platform_set_drvdata(pdev, state); | |
843 | ||
844 | state->dev = &pdev->dev; | |
845 | state->map = dev_get_regmap(dev->parent, NULL); | |
846 | ||
847 | pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); | |
848 | if (!pindesc) | |
849 | return -ENOMEM; | |
850 | ||
851 | pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); | |
852 | if (!pads) | |
853 | return -ENOMEM; | |
854 | ||
855 | pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); | |
856 | if (!pctrldesc) | |
857 | return -ENOMEM; | |
858 | ||
859 | pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; | |
860 | pctrldesc->pmxops = &pmic_mpp_pinmux_ops; | |
861 | pctrldesc->confops = &pmic_mpp_pinconf_ops; | |
862 | pctrldesc->owner = THIS_MODULE; | |
863 | pctrldesc->name = dev_name(dev); | |
864 | pctrldesc->pins = pindesc; | |
865 | pctrldesc->npins = npins; | |
866 | ||
867 | for (i = 0; i < npins; i++, pindesc++) { | |
868 | pad = &pads[i]; | |
869 | pindesc->drv_data = pad; | |
870 | pindesc->number = i; | |
871 | pindesc->name = pmic_mpp_groups[i]; | |
872 | ||
873 | pad->irq = platform_get_irq(pdev, i); | |
874 | if (pad->irq < 0) | |
875 | return pad->irq; | |
876 | ||
877 | pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE; | |
878 | ||
879 | ret = pmic_mpp_populate(state, pad); | |
880 | if (ret < 0) | |
881 | return ret; | |
882 | } | |
883 | ||
884 | state->chip = pmic_mpp_gpio_template; | |
885 | state->chip.dev = dev; | |
886 | state->chip.base = -1; | |
887 | state->chip.ngpio = npins; | |
888 | state->chip.label = dev_name(dev); | |
889 | state->chip.of_gpio_n_cells = 2; | |
890 | state->chip.can_sleep = false; | |
891 | ||
892 | state->ctrl = pinctrl_register(pctrldesc, dev, state); | |
893 | if (!state->ctrl) | |
894 | return -ENODEV; | |
895 | ||
896 | ret = gpiochip_add(&state->chip); | |
897 | if (ret) { | |
898 | dev_err(state->dev, "can't add gpio chip\n"); | |
899 | goto err_chip; | |
900 | } | |
901 | ||
902 | ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); | |
903 | if (ret) { | |
904 | dev_err(dev, "failed to add pin range\n"); | |
905 | goto err_range; | |
906 | } | |
907 | ||
908 | return 0; | |
909 | ||
910 | err_range: | |
911 | gpiochip_remove(&state->chip); | |
912 | err_chip: | |
913 | pinctrl_unregister(state->ctrl); | |
914 | return ret; | |
915 | } | |
916 | ||
917 | static int pmic_mpp_remove(struct platform_device *pdev) | |
918 | { | |
919 | struct pmic_mpp_state *state = platform_get_drvdata(pdev); | |
920 | ||
921 | gpiochip_remove(&state->chip); | |
922 | pinctrl_unregister(state->ctrl); | |
923 | return 0; | |
924 | } | |
925 | ||
926 | static const struct of_device_id pmic_mpp_of_match[] = { | |
927 | { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ | |
928 | { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ | |
929 | { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ | |
930 | { }, | |
931 | }; | |
932 | ||
933 | MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); | |
934 | ||
935 | static struct platform_driver pmic_mpp_driver = { | |
936 | .driver = { | |
937 | .name = "qcom-spmi-mpp", | |
938 | .of_match_table = pmic_mpp_of_match, | |
939 | }, | |
940 | .probe = pmic_mpp_probe, | |
941 | .remove = pmic_mpp_remove, | |
942 | }; | |
943 | ||
944 | module_platform_driver(pmic_mpp_driver); | |
945 | ||
946 | MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); | |
947 | MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); | |
948 | MODULE_ALIAS("platform:qcom-spmi-mpp"); | |
949 | MODULE_LICENSE("GPL v2"); |