Commit | Line | Data |
---|---|---|
cfb24f6e II |
1 | /* |
2 | * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/gpio.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/pinctrl/pinconf-generic.h> | |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/pinmux.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regmap.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/types.h> | |
24 | ||
25 | #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> | |
26 | ||
27 | #include "../core.h" | |
28 | #include "../pinctrl-utils.h" | |
29 | ||
30 | #define PMIC_MPP_ADDRESS_RANGE 0x100 | |
31 | ||
32 | /* | |
33 | * Pull Up Values - it indicates whether a pull-up should be | |
34 | * applied for bidirectional mode only. The hardware ignores the | |
35 | * configuration when operating in other modes. | |
36 | */ | |
37 | #define PMIC_MPP_PULL_UP_0P6KOHM 0 | |
38 | #define PMIC_MPP_PULL_UP_10KOHM 1 | |
39 | #define PMIC_MPP_PULL_UP_30KOHM 2 | |
40 | #define PMIC_MPP_PULL_UP_OPEN 3 | |
41 | ||
42 | /* type registers base address bases */ | |
43 | #define PMIC_MPP_REG_TYPE 0x4 | |
44 | #define PMIC_MPP_REG_SUBTYPE 0x5 | |
45 | ||
46 | /* mpp peripheral type and subtype values */ | |
47 | #define PMIC_MPP_TYPE 0x11 | |
48 | #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3 | |
49 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4 | |
50 | #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5 | |
51 | #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6 | |
52 | #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7 | |
53 | #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf | |
54 | ||
55 | #define PMIC_MPP_REG_RT_STS 0x10 | |
56 | #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 | |
57 | ||
58 | /* control register base address bases */ | |
59 | #define PMIC_MPP_REG_MODE_CTL 0x40 | |
60 | #define PMIC_MPP_REG_DIG_VIN_CTL 0x41 | |
61 | #define PMIC_MPP_REG_DIG_PULL_CTL 0x42 | |
62 | #define PMIC_MPP_REG_DIG_IN_CTL 0x43 | |
63 | #define PMIC_MPP_REG_EN_CTL 0x46 | |
099f3e4a | 64 | #define PMIC_MPP_REG_AOUT_CTL 0x48 |
cfb24f6e | 65 | #define PMIC_MPP_REG_AIN_CTL 0x4a |
0e948042 | 66 | #define PMIC_MPP_REG_SINK_CTL 0x4c |
cfb24f6e II |
67 | |
68 | /* PMIC_MPP_REG_MODE_CTL */ | |
69 | #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 | |
70 | #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1 | |
71 | #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7 | |
72 | #define PMIC_MPP_REG_MODE_DIR_SHIFT 4 | |
73 | #define PMIC_MPP_REG_MODE_DIR_MASK 0x7 | |
74 | ||
75 | /* PMIC_MPP_REG_DIG_VIN_CTL */ | |
76 | #define PMIC_MPP_REG_VIN_SHIFT 0 | |
77 | #define PMIC_MPP_REG_VIN_MASK 0x7 | |
78 | ||
79 | /* PMIC_MPP_REG_DIG_PULL_CTL */ | |
80 | #define PMIC_MPP_REG_PULL_SHIFT 0 | |
81 | #define PMIC_MPP_REG_PULL_MASK 0x7 | |
82 | ||
83 | /* PMIC_MPP_REG_EN_CTL */ | |
84 | #define PMIC_MPP_REG_MASTER_EN_SHIFT 7 | |
85 | ||
86 | /* PMIC_MPP_REG_AIN_CTL */ | |
87 | #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 | |
88 | #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 | |
89 | ||
eaaf5dd4 BA |
90 | #define PMIC_MPP_MODE_DIGITAL_INPUT 0 |
91 | #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1 | |
92 | #define PMIC_MPP_MODE_DIGITAL_BIDIR 2 | |
93 | #define PMIC_MPP_MODE_ANALOG_BIDIR 3 | |
94 | #define PMIC_MPP_MODE_ANALOG_INPUT 4 | |
95 | #define PMIC_MPP_MODE_ANALOG_OUTPUT 5 | |
96 | #define PMIC_MPP_MODE_CURRENT_SINK 6 | |
97 | ||
eb5c144c BA |
98 | #define PMIC_MPP_SELECTOR_NORMAL 0 |
99 | #define PMIC_MPP_SELECTOR_PAIRED 1 | |
100 | #define PMIC_MPP_SELECTOR_DTEST_FIRST 4 | |
101 | ||
cfb24f6e II |
102 | #define PMIC_MPP_PHYSICAL_OFFSET 1 |
103 | ||
104 | /* Qualcomm specific pin configurations */ | |
105 | #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) | |
eb5c144c BA |
106 | #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2) |
107 | #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3) | |
108 | #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4) | |
cfb24f6e II |
109 | |
110 | /** | |
111 | * struct pmic_mpp_pad - keep current MPP settings | |
112 | * @base: Address base in SPMI device. | |
113 | * @irq: IRQ number which this MPP generate. | |
114 | * @is_enabled: Set to false when MPP should be put in high Z state. | |
115 | * @out_value: Cached pin output value. | |
116 | * @output_enabled: Set to true if MPP output logic is enabled. | |
117 | * @input_enabled: Set to true if MPP input buffer logic is enabled. | |
eb5c144c | 118 | * @paired: Pin operates in paired mode |
cfb24f6e II |
119 | * @num_sources: Number of power-sources supported by this MPP. |
120 | * @power_source: Current power-source used. | |
121 | * @amux_input: Set the source for analog input. | |
099f3e4a | 122 | * @aout_level: Analog output level |
cfb24f6e II |
123 | * @pullup: Pullup resistor value. Valid in Bidirectional mode only. |
124 | * @function: See pmic_mpp_functions[]. | |
0e948042 | 125 | * @drive_strength: Amount of current in sink mode |
eb5c144c | 126 | * @dtest: DTEST route selector |
cfb24f6e II |
127 | */ |
128 | struct pmic_mpp_pad { | |
129 | u16 base; | |
130 | int irq; | |
131 | bool is_enabled; | |
132 | bool out_value; | |
133 | bool output_enabled; | |
134 | bool input_enabled; | |
eb5c144c | 135 | bool paired; |
cfb24f6e II |
136 | unsigned int num_sources; |
137 | unsigned int power_source; | |
138 | unsigned int amux_input; | |
099f3e4a | 139 | unsigned int aout_level; |
cfb24f6e II |
140 | unsigned int pullup; |
141 | unsigned int function; | |
0e948042 | 142 | unsigned int drive_strength; |
eb5c144c | 143 | unsigned int dtest; |
cfb24f6e II |
144 | }; |
145 | ||
146 | struct pmic_mpp_state { | |
147 | struct device *dev; | |
148 | struct regmap *map; | |
149 | struct pinctrl_dev *ctrl; | |
150 | struct gpio_chip chip; | |
151 | }; | |
152 | ||
ba5f94cd BA |
153 | static const struct pinconf_generic_params pmic_mpp_bindings[] = { |
154 | {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0}, | |
099f3e4a | 155 | {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0}, |
eb5c144c BA |
156 | {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0}, |
157 | {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0}, | |
cfb24f6e II |
158 | }; |
159 | ||
ba5f94cd BA |
160 | #ifdef CONFIG_DEBUG_FS |
161 | static const struct pin_config_item pmic_conf_items[] = { | |
162 | PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true), | |
099f3e4a | 163 | PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true), |
eb5c144c BA |
164 | PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true), |
165 | PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false), | |
cfb24f6e | 166 | }; |
ba5f94cd | 167 | #endif |
cfb24f6e II |
168 | |
169 | static const char *const pmic_mpp_groups[] = { | |
170 | "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", | |
171 | }; | |
172 | ||
eb5c144c BA |
173 | #define PMIC_MPP_DIGITAL 0 |
174 | #define PMIC_MPP_ANALOG 1 | |
175 | #define PMIC_MPP_SINK 2 | |
176 | ||
cfb24f6e | 177 | static const char *const pmic_mpp_functions[] = { |
eb5c144c | 178 | "digital", "analog", "sink" |
cfb24f6e II |
179 | }; |
180 | ||
181 | static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) | |
182 | { | |
183 | return container_of(chip, struct pmic_mpp_state, chip); | |
184 | }; | |
185 | ||
186 | static int pmic_mpp_read(struct pmic_mpp_state *state, | |
187 | struct pmic_mpp_pad *pad, unsigned int addr) | |
188 | { | |
189 | unsigned int val; | |
190 | int ret; | |
191 | ||
192 | ret = regmap_read(state->map, pad->base + addr, &val); | |
193 | if (ret < 0) | |
194 | dev_err(state->dev, "read 0x%x failed\n", addr); | |
195 | else | |
196 | ret = val; | |
197 | ||
198 | return ret; | |
199 | } | |
200 | ||
201 | static int pmic_mpp_write(struct pmic_mpp_state *state, | |
202 | struct pmic_mpp_pad *pad, unsigned int addr, | |
203 | unsigned int val) | |
204 | { | |
205 | int ret; | |
206 | ||
207 | ret = regmap_write(state->map, pad->base + addr, val); | |
208 | if (ret < 0) | |
209 | dev_err(state->dev, "write 0x%x failed\n", addr); | |
210 | ||
211 | return ret; | |
212 | } | |
213 | ||
214 | static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev) | |
215 | { | |
216 | /* Every PIN is a group */ | |
217 | return pctldev->desc->npins; | |
218 | } | |
219 | ||
220 | static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev, | |
221 | unsigned pin) | |
222 | { | |
223 | return pctldev->desc->pins[pin].name; | |
224 | } | |
225 | ||
226 | static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev, | |
227 | unsigned pin, | |
228 | const unsigned **pins, unsigned *num_pins) | |
229 | { | |
230 | *pins = &pctldev->desc->pins[pin].number; | |
231 | *num_pins = 1; | |
232 | return 0; | |
233 | } | |
234 | ||
cfb24f6e II |
235 | static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { |
236 | .get_groups_count = pmic_mpp_get_groups_count, | |
237 | .get_group_name = pmic_mpp_get_group_name, | |
238 | .get_group_pins = pmic_mpp_get_group_pins, | |
ba5f94cd | 239 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
cfb24f6e II |
240 | .dt_free_map = pinctrl_utils_dt_free_map, |
241 | }; | |
242 | ||
243 | static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev) | |
244 | { | |
245 | return ARRAY_SIZE(pmic_mpp_functions); | |
246 | } | |
247 | ||
248 | static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev, | |
249 | unsigned function) | |
250 | { | |
251 | return pmic_mpp_functions[function]; | |
252 | } | |
253 | ||
254 | static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev, | |
255 | unsigned function, | |
256 | const char *const **groups, | |
257 | unsigned *const num_qgroups) | |
258 | { | |
259 | *groups = pmic_mpp_groups; | |
260 | *num_qgroups = pctldev->desc->npins; | |
261 | return 0; | |
262 | } | |
263 | ||
0e948042 BA |
264 | static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state, |
265 | struct pmic_mpp_pad *pad) | |
cfb24f6e | 266 | { |
eb5c144c BA |
267 | unsigned int mode; |
268 | unsigned int sel; | |
cfb24f6e | 269 | unsigned int val; |
eb5c144c BA |
270 | unsigned int en; |
271 | ||
272 | switch (pad->function) { | |
273 | case PMIC_MPP_ANALOG: | |
274 | if (pad->input_enabled && pad->output_enabled) | |
275 | mode = PMIC_MPP_MODE_ANALOG_BIDIR; | |
276 | else if (pad->input_enabled) | |
277 | mode = PMIC_MPP_MODE_ANALOG_INPUT; | |
278 | else | |
279 | mode = PMIC_MPP_MODE_ANALOG_OUTPUT; | |
280 | break; | |
281 | case PMIC_MPP_DIGITAL: | |
282 | if (pad->input_enabled && pad->output_enabled) | |
283 | mode = PMIC_MPP_MODE_DIGITAL_BIDIR; | |
284 | else if (pad->input_enabled) | |
285 | mode = PMIC_MPP_MODE_DIGITAL_INPUT; | |
286 | else | |
287 | mode = PMIC_MPP_MODE_DIGITAL_OUTPUT; | |
288 | break; | |
289 | case PMIC_MPP_SINK: | |
290 | default: | |
291 | mode = PMIC_MPP_MODE_CURRENT_SINK; | |
292 | break; | |
cfb24f6e II |
293 | } |
294 | ||
eb5c144c BA |
295 | if (pad->dtest) |
296 | sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1; | |
297 | else if (pad->paired) | |
298 | sel = PMIC_MPP_SELECTOR_PAIRED; | |
299 | else | |
300 | sel = PMIC_MPP_SELECTOR_NORMAL; | |
301 | ||
302 | en = !!pad->out_value; | |
303 | ||
304 | val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT | | |
305 | sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT | | |
306 | en; | |
cfb24f6e | 307 | |
0e948042 BA |
308 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); |
309 | } | |
310 | ||
311 | static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
312 | unsigned pin) | |
313 | { | |
314 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
315 | struct pmic_mpp_pad *pad; | |
316 | unsigned int val; | |
317 | int ret; | |
318 | ||
319 | pad = pctldev->desc->pins[pin].drv_data; | |
320 | ||
321 | pad->function = function; | |
322 | ||
323 | ret = pmic_mpp_write_mode_ctl(state, pad); | |
cfb24f6e II |
324 | |
325 | val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; | |
326 | ||
327 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); | |
328 | } | |
329 | ||
330 | static const struct pinmux_ops pmic_mpp_pinmux_ops = { | |
331 | .get_functions_count = pmic_mpp_get_functions_count, | |
332 | .get_function_name = pmic_mpp_get_function_name, | |
333 | .get_function_groups = pmic_mpp_get_function_groups, | |
334 | .set_mux = pmic_mpp_set_mux, | |
335 | }; | |
336 | ||
337 | static int pmic_mpp_config_get(struct pinctrl_dev *pctldev, | |
338 | unsigned int pin, unsigned long *config) | |
339 | { | |
340 | unsigned param = pinconf_to_config_param(*config); | |
341 | struct pmic_mpp_pad *pad; | |
342 | unsigned arg = 0; | |
343 | ||
344 | pad = pctldev->desc->pins[pin].drv_data; | |
345 | ||
346 | switch (param) { | |
347 | case PIN_CONFIG_BIAS_DISABLE: | |
348 | arg = pad->pullup == PMIC_MPP_PULL_UP_OPEN; | |
349 | break; | |
350 | case PIN_CONFIG_BIAS_PULL_UP: | |
351 | switch (pad->pullup) { | |
352 | case PMIC_MPP_PULL_UP_OPEN: | |
353 | arg = 0; | |
354 | break; | |
355 | case PMIC_MPP_PULL_UP_0P6KOHM: | |
356 | arg = 600; | |
357 | break; | |
358 | case PMIC_MPP_PULL_UP_10KOHM: | |
359 | arg = 10000; | |
360 | break; | |
361 | case PMIC_MPP_PULL_UP_30KOHM: | |
362 | arg = 30000; | |
363 | break; | |
364 | default: | |
365 | return -EINVAL; | |
366 | } | |
367 | break; | |
368 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
369 | arg = !pad->is_enabled; | |
370 | break; | |
371 | case PIN_CONFIG_POWER_SOURCE: | |
372 | arg = pad->power_source; | |
373 | break; | |
374 | case PIN_CONFIG_INPUT_ENABLE: | |
375 | arg = pad->input_enabled; | |
376 | break; | |
377 | case PIN_CONFIG_OUTPUT: | |
378 | arg = pad->out_value; | |
379 | break; | |
eb5c144c BA |
380 | case PMIC_MPP_CONF_DTEST_SELECTOR: |
381 | arg = pad->dtest; | |
382 | break; | |
cfb24f6e II |
383 | case PMIC_MPP_CONF_AMUX_ROUTE: |
384 | arg = pad->amux_input; | |
385 | break; | |
eb5c144c BA |
386 | case PMIC_MPP_CONF_PAIRED: |
387 | arg = pad->paired; | |
388 | break; | |
0e948042 BA |
389 | case PIN_CONFIG_DRIVE_STRENGTH: |
390 | arg = pad->drive_strength; | |
391 | break; | |
099f3e4a BA |
392 | case PMIC_MPP_CONF_ANALOG_LEVEL: |
393 | arg = pad->aout_level; | |
394 | break; | |
cfb24f6e II |
395 | default: |
396 | return -EINVAL; | |
397 | } | |
398 | ||
399 | /* Convert register value to pinconf value */ | |
400 | *config = pinconf_to_config_packed(param, arg); | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
405 | unsigned long *configs, unsigned nconfs) | |
406 | { | |
407 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
408 | struct pmic_mpp_pad *pad; | |
409 | unsigned param, arg; | |
410 | unsigned int val; | |
411 | int i, ret; | |
412 | ||
413 | pad = pctldev->desc->pins[pin].drv_data; | |
414 | ||
7682b374 BA |
415 | /* Make it possible to enable the pin, by not setting high impedance */ |
416 | pad->is_enabled = true; | |
417 | ||
cfb24f6e II |
418 | for (i = 0; i < nconfs; i++) { |
419 | param = pinconf_to_config_param(configs[i]); | |
420 | arg = pinconf_to_config_argument(configs[i]); | |
421 | ||
422 | switch (param) { | |
423 | case PIN_CONFIG_BIAS_DISABLE: | |
424 | pad->pullup = PMIC_MPP_PULL_UP_OPEN; | |
425 | break; | |
426 | case PIN_CONFIG_BIAS_PULL_UP: | |
427 | switch (arg) { | |
428 | case 600: | |
429 | pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM; | |
430 | break; | |
431 | case 10000: | |
432 | pad->pullup = PMIC_MPP_PULL_UP_10KOHM; | |
433 | break; | |
434 | case 30000: | |
435 | pad->pullup = PMIC_MPP_PULL_UP_30KOHM; | |
436 | break; | |
437 | default: | |
438 | return -EINVAL; | |
439 | } | |
440 | break; | |
441 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: | |
442 | pad->is_enabled = false; | |
443 | break; | |
444 | case PIN_CONFIG_POWER_SOURCE: | |
445 | if (arg >= pad->num_sources) | |
446 | return -EINVAL; | |
447 | pad->power_source = arg; | |
448 | break; | |
449 | case PIN_CONFIG_INPUT_ENABLE: | |
450 | pad->input_enabled = arg ? true : false; | |
451 | break; | |
452 | case PIN_CONFIG_OUTPUT: | |
453 | pad->output_enabled = true; | |
454 | pad->out_value = arg; | |
455 | break; | |
eb5c144c BA |
456 | case PMIC_MPP_CONF_DTEST_SELECTOR: |
457 | pad->dtest = arg; | |
458 | break; | |
0e948042 BA |
459 | case PIN_CONFIG_DRIVE_STRENGTH: |
460 | arg = pad->drive_strength; | |
461 | break; | |
cfb24f6e II |
462 | case PMIC_MPP_CONF_AMUX_ROUTE: |
463 | if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) | |
464 | return -EINVAL; | |
465 | pad->amux_input = arg; | |
466 | break; | |
099f3e4a BA |
467 | case PMIC_MPP_CONF_ANALOG_LEVEL: |
468 | pad->aout_level = arg; | |
469 | break; | |
eb5c144c BA |
470 | case PMIC_MPP_CONF_PAIRED: |
471 | pad->paired = !!arg; | |
cfb24f6e II |
472 | break; |
473 | default: | |
474 | return -EINVAL; | |
475 | } | |
476 | } | |
477 | ||
478 | val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT; | |
479 | ||
480 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val); | |
481 | if (ret < 0) | |
482 | return ret; | |
483 | ||
484 | val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT; | |
485 | ||
486 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val); | |
487 | if (ret < 0) | |
488 | return ret; | |
489 | ||
490 | val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK; | |
491 | ||
492 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val); | |
493 | if (ret < 0) | |
494 | return ret; | |
495 | ||
099f3e4a BA |
496 | ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level); |
497 | if (ret < 0) | |
498 | return ret; | |
499 | ||
0e948042 | 500 | ret = pmic_mpp_write_mode_ctl(state, pad); |
7682b374 BA |
501 | if (ret < 0) |
502 | return ret; | |
503 | ||
504 | val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; | |
505 | ||
506 | return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val); | |
cfb24f6e II |
507 | } |
508 | ||
509 | static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, | |
510 | struct seq_file *s, unsigned pin) | |
511 | { | |
512 | struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); | |
513 | struct pmic_mpp_pad *pad; | |
7682b374 | 514 | int ret; |
cfb24f6e II |
515 | |
516 | static const char *const biases[] = { | |
517 | "0.6kOhm", "10kOhm", "30kOhm", "Disabled" | |
518 | }; | |
519 | ||
cfb24f6e II |
520 | pad = pctldev->desc->pins[pin].drv_data; |
521 | ||
522 | seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); | |
523 | ||
7682b374 | 524 | if (!pad->is_enabled) { |
cfb24f6e II |
525 | seq_puts(s, " ---"); |
526 | } else { | |
527 | ||
528 | if (pad->input_enabled) { | |
529 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
4e637ac2 II |
530 | if (ret < 0) |
531 | return; | |
532 | ||
533 | ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; | |
534 | pad->out_value = ret; | |
cfb24f6e II |
535 | } |
536 | ||
537 | seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); | |
cfb24f6e II |
538 | seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); |
539 | seq_printf(s, " vin-%d", pad->power_source); | |
099f3e4a | 540 | seq_printf(s, " %d", pad->aout_level); |
cfb24f6e II |
541 | seq_printf(s, " %-8s", biases[pad->pullup]); |
542 | seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); | |
eb5c144c BA |
543 | if (pad->dtest) |
544 | seq_printf(s, " dtest%d", pad->dtest); | |
545 | if (pad->paired) | |
546 | seq_puts(s, " paired"); | |
cfb24f6e II |
547 | } |
548 | } | |
549 | ||
550 | static const struct pinconf_ops pmic_mpp_pinconf_ops = { | |
ba5f94cd | 551 | .is_generic = true, |
cfb24f6e II |
552 | .pin_config_group_get = pmic_mpp_config_get, |
553 | .pin_config_group_set = pmic_mpp_config_set, | |
554 | .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, | |
555 | }; | |
556 | ||
557 | static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin) | |
558 | { | |
559 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
560 | unsigned long config; | |
561 | ||
562 | config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); | |
563 | ||
564 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
565 | } | |
566 | ||
567 | static int pmic_mpp_direction_output(struct gpio_chip *chip, | |
568 | unsigned pin, int val) | |
569 | { | |
570 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
571 | unsigned long config; | |
572 | ||
573 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); | |
574 | ||
575 | return pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
576 | } | |
577 | ||
578 | static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin) | |
579 | { | |
580 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
581 | struct pmic_mpp_pad *pad; | |
582 | int ret; | |
583 | ||
584 | pad = state->ctrl->desc->pins[pin].drv_data; | |
585 | ||
586 | if (pad->input_enabled) { | |
587 | ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS); | |
588 | if (ret < 0) | |
589 | return ret; | |
590 | ||
591 | pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; | |
592 | } | |
593 | ||
59663a4c | 594 | return !!pad->out_value; |
cfb24f6e II |
595 | } |
596 | ||
597 | static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value) | |
598 | { | |
599 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
600 | unsigned long config; | |
601 | ||
602 | config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); | |
603 | ||
604 | pmic_mpp_config_set(state->ctrl, pin, &config, 1); | |
605 | } | |
606 | ||
cfb24f6e II |
607 | static int pmic_mpp_of_xlate(struct gpio_chip *chip, |
608 | const struct of_phandle_args *gpio_desc, | |
609 | u32 *flags) | |
610 | { | |
611 | if (chip->of_gpio_n_cells < 2) | |
612 | return -EINVAL; | |
613 | ||
614 | if (flags) | |
615 | *flags = gpio_desc->args[1]; | |
616 | ||
617 | return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET; | |
618 | } | |
619 | ||
620 | static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin) | |
621 | { | |
622 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
623 | struct pmic_mpp_pad *pad; | |
624 | ||
625 | pad = state->ctrl->desc->pins[pin].drv_data; | |
626 | ||
627 | return pad->irq; | |
628 | } | |
629 | ||
630 | static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
631 | { | |
632 | struct pmic_mpp_state *state = to_mpp_state(chip); | |
633 | unsigned i; | |
634 | ||
635 | for (i = 0; i < chip->ngpio; i++) { | |
636 | pmic_mpp_config_dbg_show(state->ctrl, s, i); | |
637 | seq_puts(s, "\n"); | |
638 | } | |
639 | } | |
640 | ||
641 | static const struct gpio_chip pmic_mpp_gpio_template = { | |
642 | .direction_input = pmic_mpp_direction_input, | |
643 | .direction_output = pmic_mpp_direction_output, | |
644 | .get = pmic_mpp_get, | |
645 | .set = pmic_mpp_set, | |
98c85d58 JG |
646 | .request = gpiochip_generic_request, |
647 | .free = gpiochip_generic_free, | |
cfb24f6e II |
648 | .of_xlate = pmic_mpp_of_xlate, |
649 | .to_irq = pmic_mpp_to_irq, | |
650 | .dbg_show = pmic_mpp_dbg_show, | |
651 | }; | |
652 | ||
653 | static int pmic_mpp_populate(struct pmic_mpp_state *state, | |
654 | struct pmic_mpp_pad *pad) | |
655 | { | |
656 | int type, subtype, val, dir; | |
eb5c144c | 657 | unsigned int sel; |
cfb24f6e II |
658 | |
659 | type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); | |
660 | if (type < 0) | |
661 | return type; | |
662 | ||
663 | if (type != PMIC_MPP_TYPE) { | |
664 | dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", | |
665 | type, pad->base); | |
666 | return -ENODEV; | |
667 | } | |
668 | ||
669 | subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE); | |
670 | if (subtype < 0) | |
671 | return subtype; | |
672 | ||
673 | switch (subtype) { | |
674 | case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT: | |
675 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT: | |
676 | case PMIC_MPP_SUBTYPE_4CH_NO_SINK: | |
677 | case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK: | |
678 | case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC: | |
679 | pad->num_sources = 4; | |
680 | break; | |
681 | case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC: | |
682 | pad->num_sources = 8; | |
683 | break; | |
684 | default: | |
685 | dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n", | |
686 | subtype, pad->base); | |
687 | return -ENODEV; | |
688 | } | |
689 | ||
690 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL); | |
691 | if (val < 0) | |
692 | return val; | |
693 | ||
694 | pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK; | |
695 | ||
696 | dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT; | |
697 | dir &= PMIC_MPP_REG_MODE_DIR_MASK; | |
698 | ||
699 | switch (dir) { | |
eaaf5dd4 | 700 | case PMIC_MPP_MODE_DIGITAL_INPUT: |
cfb24f6e II |
701 | pad->input_enabled = true; |
702 | pad->output_enabled = false; | |
eb5c144c | 703 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 704 | break; |
eaaf5dd4 | 705 | case PMIC_MPP_MODE_DIGITAL_OUTPUT: |
cfb24f6e II |
706 | pad->input_enabled = false; |
707 | pad->output_enabled = true; | |
eb5c144c | 708 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 709 | break; |
eaaf5dd4 | 710 | case PMIC_MPP_MODE_DIGITAL_BIDIR: |
cfb24f6e II |
711 | pad->input_enabled = true; |
712 | pad->output_enabled = true; | |
eb5c144c | 713 | pad->function = PMIC_MPP_DIGITAL; |
cfb24f6e | 714 | break; |
eaaf5dd4 | 715 | case PMIC_MPP_MODE_ANALOG_BIDIR: |
cfb24f6e II |
716 | pad->input_enabled = true; |
717 | pad->output_enabled = true; | |
eb5c144c | 718 | pad->function = PMIC_MPP_ANALOG; |
cfb24f6e | 719 | break; |
eaaf5dd4 | 720 | case PMIC_MPP_MODE_ANALOG_INPUT: |
cfb24f6e II |
721 | pad->input_enabled = true; |
722 | pad->output_enabled = false; | |
eb5c144c | 723 | pad->function = PMIC_MPP_ANALOG; |
cfb24f6e | 724 | break; |
eaaf5dd4 | 725 | case PMIC_MPP_MODE_ANALOG_OUTPUT: |
cfb24f6e II |
726 | pad->input_enabled = false; |
727 | pad->output_enabled = true; | |
eb5c144c | 728 | pad->function = PMIC_MPP_ANALOG; |
0e948042 BA |
729 | break; |
730 | case PMIC_MPP_MODE_CURRENT_SINK: | |
731 | pad->input_enabled = false; | |
732 | pad->output_enabled = true; | |
eb5c144c | 733 | pad->function = PMIC_MPP_SINK; |
cfb24f6e II |
734 | break; |
735 | default: | |
736 | dev_err(state->dev, "unknown MPP direction\n"); | |
737 | return -ENODEV; | |
738 | } | |
739 | ||
eb5c144c BA |
740 | sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; |
741 | sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK; | |
742 | ||
743 | if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST) | |
744 | pad->dtest = sel + 1; | |
745 | else if (sel == PMIC_MPP_SELECTOR_PAIRED) | |
746 | pad->paired = true; | |
cfb24f6e II |
747 | |
748 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); | |
749 | if (val < 0) | |
750 | return val; | |
751 | ||
752 | pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT; | |
753 | pad->power_source &= PMIC_MPP_REG_VIN_MASK; | |
754 | ||
755 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL); | |
756 | if (val < 0) | |
757 | return val; | |
758 | ||
759 | pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT; | |
760 | pad->pullup &= PMIC_MPP_REG_PULL_MASK; | |
761 | ||
762 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL); | |
763 | if (val < 0) | |
764 | return val; | |
765 | ||
766 | pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; | |
767 | pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; | |
768 | ||
0e948042 BA |
769 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL); |
770 | if (val < 0) | |
771 | return val; | |
772 | ||
773 | pad->drive_strength = val; | |
774 | ||
099f3e4a BA |
775 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL); |
776 | if (val < 0) | |
777 | return val; | |
778 | ||
779 | pad->aout_level = val; | |
780 | ||
7682b374 BA |
781 | val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); |
782 | if (val < 0) | |
783 | return val; | |
784 | ||
785 | pad->is_enabled = !!val; | |
786 | ||
cfb24f6e II |
787 | return 0; |
788 | } | |
789 | ||
790 | static int pmic_mpp_probe(struct platform_device *pdev) | |
791 | { | |
792 | struct device *dev = &pdev->dev; | |
793 | struct pinctrl_pin_desc *pindesc; | |
794 | struct pinctrl_desc *pctrldesc; | |
795 | struct pmic_mpp_pad *pad, *pads; | |
796 | struct pmic_mpp_state *state; | |
797 | int ret, npins, i; | |
798 | u32 res[2]; | |
799 | ||
800 | ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); | |
801 | if (ret < 0) { | |
802 | dev_err(dev, "missing base address and/or range"); | |
803 | return ret; | |
804 | } | |
805 | ||
806 | npins = res[1] / PMIC_MPP_ADDRESS_RANGE; | |
807 | if (!npins) | |
808 | return -EINVAL; | |
809 | ||
810 | BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups)); | |
811 | ||
812 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); | |
813 | if (!state) | |
814 | return -ENOMEM; | |
815 | ||
816 | platform_set_drvdata(pdev, state); | |
817 | ||
818 | state->dev = &pdev->dev; | |
819 | state->map = dev_get_regmap(dev->parent, NULL); | |
820 | ||
821 | pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); | |
822 | if (!pindesc) | |
823 | return -ENOMEM; | |
824 | ||
825 | pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); | |
826 | if (!pads) | |
827 | return -ENOMEM; | |
828 | ||
829 | pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); | |
830 | if (!pctrldesc) | |
831 | return -ENOMEM; | |
832 | ||
833 | pctrldesc->pctlops = &pmic_mpp_pinctrl_ops; | |
834 | pctrldesc->pmxops = &pmic_mpp_pinmux_ops; | |
835 | pctrldesc->confops = &pmic_mpp_pinconf_ops; | |
836 | pctrldesc->owner = THIS_MODULE; | |
837 | pctrldesc->name = dev_name(dev); | |
838 | pctrldesc->pins = pindesc; | |
839 | pctrldesc->npins = npins; | |
840 | ||
ba5f94cd BA |
841 | pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings); |
842 | pctrldesc->custom_params = pmic_mpp_bindings; | |
843 | #ifdef CONFIG_DEBUG_FS | |
844 | pctrldesc->custom_conf_items = pmic_conf_items; | |
845 | #endif | |
846 | ||
cfb24f6e II |
847 | for (i = 0; i < npins; i++, pindesc++) { |
848 | pad = &pads[i]; | |
849 | pindesc->drv_data = pad; | |
850 | pindesc->number = i; | |
851 | pindesc->name = pmic_mpp_groups[i]; | |
852 | ||
853 | pad->irq = platform_get_irq(pdev, i); | |
854 | if (pad->irq < 0) | |
855 | return pad->irq; | |
856 | ||
857 | pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE; | |
858 | ||
859 | ret = pmic_mpp_populate(state, pad); | |
860 | if (ret < 0) | |
861 | return ret; | |
862 | } | |
863 | ||
864 | state->chip = pmic_mpp_gpio_template; | |
58383c78 | 865 | state->chip.parent = dev; |
cfb24f6e II |
866 | state->chip.base = -1; |
867 | state->chip.ngpio = npins; | |
868 | state->chip.label = dev_name(dev); | |
869 | state->chip.of_gpio_n_cells = 2; | |
870 | state->chip.can_sleep = false; | |
871 | ||
872 | state->ctrl = pinctrl_register(pctrldesc, dev, state); | |
323de9ef MY |
873 | if (IS_ERR(state->ctrl)) |
874 | return PTR_ERR(state->ctrl); | |
cfb24f6e II |
875 | |
876 | ret = gpiochip_add(&state->chip); | |
877 | if (ret) { | |
878 | dev_err(state->dev, "can't add gpio chip\n"); | |
879 | goto err_chip; | |
880 | } | |
881 | ||
882 | ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); | |
883 | if (ret) { | |
884 | dev_err(dev, "failed to add pin range\n"); | |
885 | goto err_range; | |
886 | } | |
887 | ||
888 | return 0; | |
889 | ||
890 | err_range: | |
891 | gpiochip_remove(&state->chip); | |
892 | err_chip: | |
893 | pinctrl_unregister(state->ctrl); | |
894 | return ret; | |
895 | } | |
896 | ||
897 | static int pmic_mpp_remove(struct platform_device *pdev) | |
898 | { | |
899 | struct pmic_mpp_state *state = platform_get_drvdata(pdev); | |
900 | ||
901 | gpiochip_remove(&state->chip); | |
902 | pinctrl_unregister(state->ctrl); | |
903 | return 0; | |
904 | } | |
905 | ||
906 | static const struct of_device_id pmic_mpp_of_match[] = { | |
907 | { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ | |
7414b099 | 908 | { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */ |
cfb24f6e II |
909 | { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ |
910 | { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ | |
911 | { }, | |
912 | }; | |
913 | ||
914 | MODULE_DEVICE_TABLE(of, pmic_mpp_of_match); | |
915 | ||
916 | static struct platform_driver pmic_mpp_driver = { | |
917 | .driver = { | |
918 | .name = "qcom-spmi-mpp", | |
919 | .of_match_table = pmic_mpp_of_match, | |
920 | }, | |
921 | .probe = pmic_mpp_probe, | |
922 | .remove = pmic_mpp_remove, | |
923 | }; | |
924 | ||
925 | module_platform_driver(pmic_mpp_driver); | |
926 | ||
927 | MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); | |
928 | MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver"); | |
929 | MODULE_ALIAS("platform:qcom-spmi-mpp"); | |
930 | MODULE_LICENSE("GPL v2"); |