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f0b9a7e5 TA |
1 | /* |
2 | * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/err.h> | |
dbf09b0a | 18 | #include <linux/gpio/driver.h> |
f0b9a7e5 TA |
19 | #include <linux/device.h> |
20 | #include <linux/pinctrl/pinctrl.h> | |
21 | #include <linux/pinctrl/pinmux.h> | |
22 | #include <linux/pinctrl/pinconf.h> | |
8dc3568d TA |
23 | #include <linux/interrupt.h> |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/of_irq.h> | |
ebe629a3 | 26 | #include "../core.h" |
f0b9a7e5 TA |
27 | |
28 | /* EXYNOS5440 GPIO and Pinctrl register offsets */ | |
29 | #define GPIO_MUX 0x00 | |
30 | #define GPIO_IE 0x04 | |
31 | #define GPIO_INT 0x08 | |
32 | #define GPIO_TYPE 0x0C | |
33 | #define GPIO_VAL 0x10 | |
34 | #define GPIO_OE 0x14 | |
35 | #define GPIO_IN 0x18 | |
36 | #define GPIO_PE 0x1C | |
37 | #define GPIO_PS 0x20 | |
38 | #define GPIO_SR 0x24 | |
39 | #define GPIO_DS0 0x28 | |
40 | #define GPIO_DS1 0x2C | |
41 | ||
42 | #define EXYNOS5440_MAX_PINS 23 | |
8dc3568d | 43 | #define EXYNOS5440_MAX_GPIO_INT 8 |
f0b9a7e5 TA |
44 | #define PIN_NAME_LENGTH 10 |
45 | ||
46 | #define GROUP_SUFFIX "-grp" | |
f0b9a7e5 | 47 | #define FUNCTION_SUFFIX "-mux" |
f0b9a7e5 TA |
48 | |
49 | /* | |
50 | * pin configuration type and its value are packed together into a 16-bits. | |
51 | * The upper 8-bits represent the configuration type and the lower 8-bits | |
52 | * hold the value of the configuration type. | |
53 | */ | |
54 | #define PINCFG_TYPE_MASK 0xFF | |
55 | #define PINCFG_VALUE_SHIFT 8 | |
56 | #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) | |
57 | #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) | |
58 | #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) | |
59 | #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ | |
60 | PINCFG_VALUE_SHIFT) | |
61 | ||
62 | /** | |
63 | * enum pincfg_type - possible pin configuration types supported. | |
64 | * @PINCFG_TYPE_PUD: Pull up/down configuration. | |
65 | * @PINCFG_TYPE_DRV: Drive strength configuration. | |
66 | * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration. | |
67 | * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration. | |
68 | */ | |
69 | enum pincfg_type { | |
70 | PINCFG_TYPE_PUD, | |
71 | PINCFG_TYPE_DRV, | |
72 | PINCFG_TYPE_SKEW_RATE, | |
73 | PINCFG_TYPE_INPUT_TYPE | |
74 | }; | |
75 | ||
76 | /** | |
77 | * struct exynos5440_pin_group: represent group of pins for pincfg setting. | |
78 | * @name: name of the pin group, used to lookup the group. | |
79 | * @pins: the pins included in this group. | |
80 | * @num_pins: number of pins included in this group. | |
81 | */ | |
82 | struct exynos5440_pin_group { | |
83 | const char *name; | |
84 | const unsigned int *pins; | |
85 | u8 num_pins; | |
86 | }; | |
87 | ||
88 | /** | |
89 | * struct exynos5440_pmx_func: represent a pin function. | |
90 | * @name: name of the pin function, used to lookup the function. | |
91 | * @groups: one or more names of pin groups that provide this function. | |
92 | * @num_groups: number of groups included in @groups. | |
93 | * @function: the function number to be programmed when selected. | |
94 | */ | |
95 | struct exynos5440_pmx_func { | |
96 | const char *name; | |
97 | const char **groups; | |
98 | u8 num_groups; | |
99 | unsigned long function; | |
100 | }; | |
101 | ||
102 | /** | |
103 | * struct exynos5440_pinctrl_priv_data: driver's private runtime data. | |
104 | * @reg_base: ioremapped based address of the register space. | |
105 | * @gc: gpio chip registered with gpiolib. | |
106 | * @pin_groups: list of pin groups parsed from device tree. | |
107 | * @nr_groups: number of pin groups available. | |
108 | * @pmx_functions: list of pin functions parsed from device tree. | |
109 | * @nr_functions: number of pin functions available. | |
71324fdc | 110 | * @range: gpio range to register with pinctrl |
f0b9a7e5 TA |
111 | */ |
112 | struct exynos5440_pinctrl_priv_data { | |
113 | void __iomem *reg_base; | |
114 | struct gpio_chip *gc; | |
8dc3568d | 115 | struct irq_domain *irq_domain; |
f0b9a7e5 TA |
116 | |
117 | const struct exynos5440_pin_group *pin_groups; | |
118 | unsigned int nr_groups; | |
119 | const struct exynos5440_pmx_func *pmx_functions; | |
120 | unsigned int nr_functions; | |
71324fdc | 121 | struct pinctrl_gpio_range range; |
f0b9a7e5 TA |
122 | }; |
123 | ||
8dc3568d TA |
124 | /** |
125 | * struct exynos5440_gpio_intr_data: private data for gpio interrupts. | |
126 | * @priv: driver's private runtime data. | |
127 | * @gpio_int: gpio interrupt number. | |
128 | */ | |
129 | struct exynos5440_gpio_intr_data { | |
130 | struct exynos5440_pinctrl_priv_data *priv; | |
131 | unsigned int gpio_int; | |
132 | }; | |
133 | ||
f0b9a7e5 | 134 | /* list of all possible config options supported */ |
d5fd5da2 | 135 | static struct pin_config { |
f0b9a7e5 TA |
136 | char *prop_cfg; |
137 | unsigned int cfg_type; | |
138 | } pcfgs[] = { | |
139 | { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD }, | |
140 | { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV }, | |
141 | { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE }, | |
142 | { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE }, | |
143 | }; | |
144 | ||
145 | /* check if the selector is a valid pin group selector */ | |
146 | static int exynos5440_get_group_count(struct pinctrl_dev *pctldev) | |
147 | { | |
148 | struct exynos5440_pinctrl_priv_data *priv; | |
149 | ||
150 | priv = pinctrl_dev_get_drvdata(pctldev); | |
151 | return priv->nr_groups; | |
152 | } | |
153 | ||
154 | /* return the name of the group selected by the group selector */ | |
155 | static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev, | |
156 | unsigned selector) | |
157 | { | |
158 | struct exynos5440_pinctrl_priv_data *priv; | |
159 | ||
160 | priv = pinctrl_dev_get_drvdata(pctldev); | |
161 | return priv->pin_groups[selector].name; | |
162 | } | |
163 | ||
164 | /* return the pin numbers associated with the specified group */ | |
165 | static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev, | |
166 | unsigned selector, const unsigned **pins, unsigned *num_pins) | |
167 | { | |
168 | struct exynos5440_pinctrl_priv_data *priv; | |
169 | ||
170 | priv = pinctrl_dev_get_drvdata(pctldev); | |
171 | *pins = priv->pin_groups[selector].pins; | |
172 | *num_pins = priv->pin_groups[selector].num_pins; | |
173 | return 0; | |
174 | } | |
175 | ||
176 | /* create pinctrl_map entries by parsing device tree nodes */ | |
177 | static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev, | |
178 | struct device_node *np, struct pinctrl_map **maps, | |
179 | unsigned *nmaps) | |
180 | { | |
181 | struct device *dev = pctldev->dev; | |
182 | struct pinctrl_map *map; | |
183 | unsigned long *cfg = NULL; | |
184 | char *gname, *fname; | |
185 | int cfg_cnt = 0, map_cnt = 0, idx = 0; | |
186 | ||
187 | /* count the number of config options specfied in the node */ | |
188 | for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++) | |
189 | if (of_find_property(np, pcfgs[idx].prop_cfg, NULL)) | |
190 | cfg_cnt++; | |
191 | ||
192 | /* | |
193 | * Find out the number of map entries to create. All the config options | |
194 | * can be accomadated into a single config map entry. | |
195 | */ | |
196 | if (cfg_cnt) | |
197 | map_cnt = 1; | |
198 | if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) | |
199 | map_cnt++; | |
200 | if (!map_cnt) { | |
201 | dev_err(dev, "node %s does not have either config or function " | |
202 | "configurations\n", np->name); | |
203 | return -EINVAL; | |
204 | } | |
205 | ||
206 | /* Allocate memory for pin-map entries */ | |
207 | map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); | |
583facb6 | 208 | if (!map) |
f0b9a7e5 | 209 | return -ENOMEM; |
f0b9a7e5 TA |
210 | *nmaps = 0; |
211 | ||
212 | /* | |
213 | * Allocate memory for pin group name. The pin group name is derived | |
214 | * from the node name from which these map entries are be created. | |
215 | */ | |
8749f8ed | 216 | gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX); |
583facb6 | 217 | if (!gname) |
f0b9a7e5 | 218 | goto free_map; |
f0b9a7e5 TA |
219 | |
220 | /* | |
221 | * don't have config options? then skip over to creating function | |
222 | * map entries. | |
223 | */ | |
224 | if (!cfg_cnt) | |
225 | goto skip_cfgs; | |
226 | ||
227 | /* Allocate memory for config entries */ | |
228 | cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); | |
583facb6 | 229 | if (!cfg) |
f0b9a7e5 | 230 | goto free_gname; |
f0b9a7e5 TA |
231 | |
232 | /* Prepare a list of config settings */ | |
233 | for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { | |
234 | u32 value; | |
235 | if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value)) | |
236 | cfg[cfg_cnt++] = | |
237 | PINCFG_PACK(pcfgs[idx].cfg_type, value); | |
238 | } | |
239 | ||
240 | /* create the config map entry */ | |
241 | map[*nmaps].data.configs.group_or_pin = gname; | |
242 | map[*nmaps].data.configs.configs = cfg; | |
243 | map[*nmaps].data.configs.num_configs = cfg_cnt; | |
244 | map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
245 | *nmaps += 1; | |
246 | ||
247 | skip_cfgs: | |
248 | /* create the function map entry */ | |
249 | if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { | |
8749f8ed DC |
250 | fname = kasprintf(GFP_KERNEL, |
251 | "%s%s", np->name, FUNCTION_SUFFIX); | |
583facb6 | 252 | if (!fname) |
f0b9a7e5 | 253 | goto free_cfg; |
f0b9a7e5 TA |
254 | |
255 | map[*nmaps].data.mux.group = gname; | |
256 | map[*nmaps].data.mux.function = fname; | |
257 | map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP; | |
258 | *nmaps += 1; | |
259 | } | |
260 | ||
261 | *maps = map; | |
262 | return 0; | |
263 | ||
264 | free_cfg: | |
265 | kfree(cfg); | |
266 | free_gname: | |
267 | kfree(gname); | |
268 | free_map: | |
269 | kfree(map); | |
270 | return -ENOMEM; | |
271 | } | |
272 | ||
273 | /* free the memory allocated to hold the pin-map table */ | |
274 | static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev, | |
275 | struct pinctrl_map *map, unsigned num_maps) | |
276 | { | |
277 | int idx; | |
278 | ||
279 | for (idx = 0; idx < num_maps; idx++) { | |
280 | if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) { | |
281 | kfree(map[idx].data.mux.function); | |
282 | if (!idx) | |
283 | kfree(map[idx].data.mux.group); | |
284 | } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) { | |
285 | kfree(map[idx].data.configs.configs); | |
286 | if (!idx) | |
287 | kfree(map[idx].data.configs.group_or_pin); | |
288 | } | |
be2cbd4d | 289 | } |
f0b9a7e5 TA |
290 | |
291 | kfree(map); | |
292 | } | |
293 | ||
294 | /* list of pinctrl callbacks for the pinctrl core */ | |
022ab148 | 295 | static const struct pinctrl_ops exynos5440_pctrl_ops = { |
f0b9a7e5 TA |
296 | .get_groups_count = exynos5440_get_group_count, |
297 | .get_group_name = exynos5440_get_group_name, | |
298 | .get_group_pins = exynos5440_get_group_pins, | |
299 | .dt_node_to_map = exynos5440_dt_node_to_map, | |
300 | .dt_free_map = exynos5440_dt_free_map, | |
301 | }; | |
302 | ||
303 | /* check if the selector is a valid pin function selector */ | |
304 | static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev) | |
305 | { | |
306 | struct exynos5440_pinctrl_priv_data *priv; | |
307 | ||
308 | priv = pinctrl_dev_get_drvdata(pctldev); | |
309 | return priv->nr_functions; | |
310 | } | |
311 | ||
312 | /* return the name of the pin function specified */ | |
313 | static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev, | |
314 | unsigned selector) | |
315 | { | |
316 | struct exynos5440_pinctrl_priv_data *priv; | |
317 | ||
318 | priv = pinctrl_dev_get_drvdata(pctldev); | |
319 | return priv->pmx_functions[selector].name; | |
320 | } | |
321 | ||
322 | /* return the groups associated for the specified function selector */ | |
323 | static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev, | |
324 | unsigned selector, const char * const **groups, | |
325 | unsigned * const num_groups) | |
326 | { | |
327 | struct exynos5440_pinctrl_priv_data *priv; | |
328 | ||
329 | priv = pinctrl_dev_get_drvdata(pctldev); | |
330 | *groups = priv->pmx_functions[selector].groups; | |
331 | *num_groups = priv->pmx_functions[selector].num_groups; | |
332 | return 0; | |
333 | } | |
334 | ||
335 | /* enable or disable a pinmux function */ | |
336 | static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector, | |
337 | unsigned group, bool enable) | |
338 | { | |
339 | struct exynos5440_pinctrl_priv_data *priv; | |
340 | void __iomem *base; | |
341 | u32 function; | |
342 | u32 data; | |
343 | ||
344 | priv = pinctrl_dev_get_drvdata(pctldev); | |
345 | base = priv->reg_base; | |
346 | function = priv->pmx_functions[selector].function; | |
347 | ||
348 | data = readl(base + GPIO_MUX); | |
349 | if (enable) | |
350 | data |= (1 << function); | |
351 | else | |
352 | data &= ~(1 << function); | |
353 | writel(data, base + GPIO_MUX); | |
354 | } | |
355 | ||
356 | /* enable a specified pinmux by writing to registers */ | |
03e9f0ca LW |
357 | static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev, |
358 | unsigned selector, | |
359 | unsigned group) | |
f0b9a7e5 TA |
360 | { |
361 | exynos5440_pinmux_setup(pctldev, selector, group, true); | |
362 | return 0; | |
363 | } | |
364 | ||
f0b9a7e5 TA |
365 | /* |
366 | * The calls to gpio_direction_output() and gpio_direction_input() | |
367 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
368 | * function called from the gpiolib interface). | |
369 | */ | |
370 | static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, | |
371 | struct pinctrl_gpio_range *range, unsigned offset, bool input) | |
372 | { | |
373 | return 0; | |
374 | } | |
375 | ||
376 | /* list of pinmux callbacks for the pinmux vertical in pinctrl core */ | |
022ab148 | 377 | static const struct pinmux_ops exynos5440_pinmux_ops = { |
f0b9a7e5 TA |
378 | .get_functions_count = exynos5440_get_functions_count, |
379 | .get_function_name = exynos5440_pinmux_get_fname, | |
380 | .get_function_groups = exynos5440_pinmux_get_groups, | |
03e9f0ca | 381 | .set_mux = exynos5440_pinmux_set_mux, |
f0b9a7e5 TA |
382 | .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, |
383 | }; | |
384 | ||
385 | /* set the pin config settings for a specified pin */ | |
386 | static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 SY |
387 | unsigned long *configs, |
388 | unsigned num_configs) | |
f0b9a7e5 TA |
389 | { |
390 | struct exynos5440_pinctrl_priv_data *priv; | |
391 | void __iomem *base; | |
03b054e9 SY |
392 | enum pincfg_type cfg_type; |
393 | u32 cfg_value; | |
f0b9a7e5 | 394 | u32 data; |
03b054e9 | 395 | int i; |
f0b9a7e5 TA |
396 | |
397 | priv = pinctrl_dev_get_drvdata(pctldev); | |
398 | base = priv->reg_base; | |
399 | ||
03b054e9 SY |
400 | for (i = 0; i < num_configs; i++) { |
401 | cfg_type = PINCFG_UNPACK_TYPE(configs[i]); | |
402 | cfg_value = PINCFG_UNPACK_VALUE(configs[i]); | |
403 | ||
404 | switch (cfg_type) { | |
405 | case PINCFG_TYPE_PUD: | |
406 | /* first set pull enable/disable bit */ | |
407 | data = readl(base + GPIO_PE); | |
408 | data &= ~(1 << pin); | |
409 | if (cfg_value) | |
410 | data |= (1 << pin); | |
411 | writel(data, base + GPIO_PE); | |
412 | ||
413 | /* then set pull up/down bit */ | |
414 | data = readl(base + GPIO_PS); | |
415 | data &= ~(1 << pin); | |
416 | if (cfg_value == 2) | |
417 | data |= (1 << pin); | |
418 | writel(data, base + GPIO_PS); | |
419 | break; | |
420 | ||
421 | case PINCFG_TYPE_DRV: | |
422 | /* set the first bit of the drive strength */ | |
423 | data = readl(base + GPIO_DS0); | |
424 | data &= ~(1 << pin); | |
425 | data |= ((cfg_value & 1) << pin); | |
426 | writel(data, base + GPIO_DS0); | |
427 | cfg_value >>= 1; | |
428 | ||
429 | /* set the second bit of the driver strength */ | |
430 | data = readl(base + GPIO_DS1); | |
431 | data &= ~(1 << pin); | |
432 | data |= ((cfg_value & 1) << pin); | |
433 | writel(data, base + GPIO_DS1); | |
434 | break; | |
435 | case PINCFG_TYPE_SKEW_RATE: | |
436 | data = readl(base + GPIO_SR); | |
437 | data &= ~(1 << pin); | |
438 | data |= ((cfg_value & 1) << pin); | |
439 | writel(data, base + GPIO_SR); | |
440 | break; | |
441 | case PINCFG_TYPE_INPUT_TYPE: | |
442 | data = readl(base + GPIO_TYPE); | |
443 | data &= ~(1 << pin); | |
444 | data |= ((cfg_value & 1) << pin); | |
445 | writel(data, base + GPIO_TYPE); | |
446 | break; | |
447 | default: | |
448 | WARN_ON(1); | |
449 | return -EINVAL; | |
450 | } | |
451 | } /* for each config */ | |
f0b9a7e5 TA |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
456 | /* get the pin config settings for a specified pin */ | |
457 | static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
458 | unsigned long *config) | |
459 | { | |
460 | struct exynos5440_pinctrl_priv_data *priv; | |
461 | void __iomem *base; | |
462 | enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); | |
463 | u32 data; | |
464 | ||
465 | priv = pinctrl_dev_get_drvdata(pctldev); | |
466 | base = priv->reg_base; | |
467 | ||
468 | switch (cfg_type) { | |
469 | case PINCFG_TYPE_PUD: | |
470 | data = readl(base + GPIO_PE); | |
471 | data = (data >> pin) & 1; | |
472 | if (!data) | |
473 | *config = 0; | |
474 | else | |
475 | *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1; | |
476 | break; | |
477 | case PINCFG_TYPE_DRV: | |
478 | data = readl(base + GPIO_DS0); | |
479 | data = (data >> pin) & 1; | |
480 | *config = data; | |
481 | data = readl(base + GPIO_DS1); | |
482 | data = (data >> pin) & 1; | |
483 | *config |= (data << 1); | |
484 | break; | |
485 | case PINCFG_TYPE_SKEW_RATE: | |
486 | data = readl(base + GPIO_SR); | |
487 | *config = (data >> pin) & 1; | |
488 | break; | |
489 | case PINCFG_TYPE_INPUT_TYPE: | |
490 | data = readl(base + GPIO_TYPE); | |
491 | *config = (data >> pin) & 1; | |
492 | break; | |
493 | default: | |
494 | WARN_ON(1); | |
495 | return -EINVAL; | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | /* set the pin config settings for a specified pin group */ | |
502 | static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
503 | unsigned group, unsigned long *configs, |
504 | unsigned num_configs) | |
f0b9a7e5 TA |
505 | { |
506 | struct exynos5440_pinctrl_priv_data *priv; | |
507 | const unsigned int *pins; | |
508 | unsigned int cnt; | |
509 | ||
510 | priv = pinctrl_dev_get_drvdata(pctldev); | |
511 | pins = priv->pin_groups[group].pins; | |
512 | ||
513 | for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++) | |
03b054e9 SY |
514 | exynos5440_pinconf_set(pctldev, pins[cnt], configs, |
515 | num_configs); | |
f0b9a7e5 TA |
516 | |
517 | return 0; | |
518 | } | |
519 | ||
520 | /* get the pin config settings for a specified pin group */ | |
521 | static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev, | |
522 | unsigned int group, unsigned long *config) | |
523 | { | |
524 | struct exynos5440_pinctrl_priv_data *priv; | |
525 | const unsigned int *pins; | |
526 | ||
527 | priv = pinctrl_dev_get_drvdata(pctldev); | |
528 | pins = priv->pin_groups[group].pins; | |
529 | exynos5440_pinconf_get(pctldev, pins[0], config); | |
530 | return 0; | |
531 | } | |
532 | ||
533 | /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ | |
022ab148 | 534 | static const struct pinconf_ops exynos5440_pinconf_ops = { |
f0b9a7e5 TA |
535 | .pin_config_get = exynos5440_pinconf_get, |
536 | .pin_config_set = exynos5440_pinconf_set, | |
537 | .pin_config_group_get = exynos5440_pinconf_group_get, | |
538 | .pin_config_group_set = exynos5440_pinconf_group_set, | |
539 | }; | |
540 | ||
541 | /* gpiolib gpio_set callback function */ | |
542 | static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value) | |
543 | { | |
dbf09b0a | 544 | struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc); |
f0b9a7e5 TA |
545 | void __iomem *base = priv->reg_base; |
546 | u32 data; | |
547 | ||
548 | data = readl(base + GPIO_VAL); | |
549 | data &= ~(1 << offset); | |
550 | if (value) | |
551 | data |= 1 << offset; | |
552 | writel(data, base + GPIO_VAL); | |
553 | } | |
554 | ||
555 | /* gpiolib gpio_get callback function */ | |
556 | static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset) | |
557 | { | |
dbf09b0a | 558 | struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc); |
f0b9a7e5 TA |
559 | void __iomem *base = priv->reg_base; |
560 | u32 data; | |
561 | ||
562 | data = readl(base + GPIO_IN); | |
563 | data >>= offset; | |
564 | data &= 1; | |
565 | return data; | |
566 | } | |
567 | ||
568 | /* gpiolib gpio_direction_input callback function */ | |
569 | static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
570 | { | |
dbf09b0a | 571 | struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc); |
f0b9a7e5 TA |
572 | void __iomem *base = priv->reg_base; |
573 | u32 data; | |
574 | ||
575 | /* first disable the data output enable on this pin */ | |
576 | data = readl(base + GPIO_OE); | |
577 | data &= ~(1 << offset); | |
578 | writel(data, base + GPIO_OE); | |
579 | ||
580 | /* now enable input on this pin */ | |
581 | data = readl(base + GPIO_IE); | |
582 | data |= 1 << offset; | |
583 | writel(data, base + GPIO_IE); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | /* gpiolib gpio_direction_output callback function */ | |
588 | static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset, | |
589 | int value) | |
590 | { | |
dbf09b0a | 591 | struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc); |
f0b9a7e5 TA |
592 | void __iomem *base = priv->reg_base; |
593 | u32 data; | |
594 | ||
595 | exynos5440_gpio_set(gc, offset, value); | |
596 | ||
597 | /* first disable the data input enable on this pin */ | |
598 | data = readl(base + GPIO_IE); | |
599 | data &= ~(1 << offset); | |
600 | writel(data, base + GPIO_IE); | |
601 | ||
602 | /* now enable output on this pin */ | |
603 | data = readl(base + GPIO_OE); | |
604 | data |= 1 << offset; | |
605 | writel(data, base + GPIO_OE); | |
606 | return 0; | |
607 | } | |
608 | ||
8dc3568d TA |
609 | /* gpiolib gpio_to_irq callback function */ |
610 | static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
611 | { | |
dbf09b0a | 612 | struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc); |
8dc3568d TA |
613 | unsigned int virq; |
614 | ||
615 | if (offset < 16 || offset > 23) | |
616 | return -ENXIO; | |
617 | ||
618 | if (!priv->irq_domain) | |
619 | return -ENXIO; | |
620 | ||
621 | virq = irq_create_mapping(priv->irq_domain, offset - 16); | |
622 | return virq ? : -ENXIO; | |
623 | } | |
624 | ||
f0b9a7e5 | 625 | /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */ |
312b00e5 | 626 | static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev, |
f0b9a7e5 TA |
627 | struct device_node *cfg_np, unsigned int **pin_list, |
628 | unsigned int *npins) | |
629 | { | |
630 | struct device *dev = &pdev->dev; | |
631 | struct property *prop; | |
632 | ||
633 | prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL); | |
634 | if (!prop) | |
635 | return -ENOENT; | |
636 | ||
637 | *npins = prop->length / sizeof(unsigned long); | |
638 | if (!*npins) { | |
639 | dev_err(dev, "invalid pin list in %s node", cfg_np->name); | |
640 | return -EINVAL; | |
641 | } | |
642 | ||
643 | *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); | |
583facb6 | 644 | if (!*pin_list) |
f0b9a7e5 | 645 | return -ENOMEM; |
f0b9a7e5 TA |
646 | |
647 | return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", | |
648 | *pin_list, *npins); | |
649 | } | |
650 | ||
651 | /* | |
652 | * Parse the information about all the available pin groups and pin functions | |
653 | * from device node of the pin-controller. | |
654 | */ | |
312b00e5 | 655 | static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev, |
f0b9a7e5 TA |
656 | struct exynos5440_pinctrl_priv_data *priv) |
657 | { | |
658 | struct device *dev = &pdev->dev; | |
659 | struct device_node *dev_np = dev->of_node; | |
660 | struct device_node *cfg_np; | |
661 | struct exynos5440_pin_group *groups, *grp; | |
662 | struct exynos5440_pmx_func *functions, *func; | |
663 | unsigned *pin_list; | |
664 | unsigned int npins, grp_cnt, func_idx = 0; | |
665 | char *gname, *fname; | |
666 | int ret; | |
667 | ||
668 | grp_cnt = of_get_child_count(dev_np); | |
669 | if (!grp_cnt) | |
670 | return -EINVAL; | |
671 | ||
672 | groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); | |
583facb6 | 673 | if (!groups) |
f0b9a7e5 | 674 | return -EINVAL; |
583facb6 | 675 | |
f0b9a7e5 TA |
676 | grp = groups; |
677 | ||
678 | functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); | |
583facb6 | 679 | if (!functions) |
f0b9a7e5 | 680 | return -EINVAL; |
583facb6 | 681 | |
f0b9a7e5 TA |
682 | func = functions; |
683 | ||
684 | /* | |
685 | * Iterate over all the child nodes of the pin controller node | |
686 | * and create pin groups and pin function lists. | |
687 | */ | |
688 | for_each_child_of_node(dev_np, cfg_np) { | |
689 | u32 function; | |
690 | ||
691 | ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np, | |
692 | &pin_list, &npins); | |
f9819739 TA |
693 | if (ret) { |
694 | gname = NULL; | |
695 | goto skip_to_pin_function; | |
696 | } | |
f0b9a7e5 TA |
697 | |
698 | /* derive pin group name from the node name */ | |
8749f8ed DC |
699 | gname = devm_kasprintf(dev, GFP_KERNEL, |
700 | "%s%s", cfg_np->name, GROUP_SUFFIX); | |
583facb6 | 701 | if (!gname) |
f0b9a7e5 | 702 | return -ENOMEM; |
f0b9a7e5 TA |
703 | |
704 | grp->name = gname; | |
705 | grp->pins = pin_list; | |
706 | grp->num_pins = npins; | |
707 | grp++; | |
708 | ||
f9819739 | 709 | skip_to_pin_function: |
f0b9a7e5 TA |
710 | ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function", |
711 | &function); | |
712 | if (ret) | |
713 | continue; | |
714 | ||
715 | /* derive function name from the node name */ | |
8749f8ed DC |
716 | fname = devm_kasprintf(dev, GFP_KERNEL, |
717 | "%s%s", cfg_np->name, FUNCTION_SUFFIX); | |
583facb6 | 718 | if (!fname) |
f0b9a7e5 | 719 | return -ENOMEM; |
f0b9a7e5 TA |
720 | |
721 | func->name = fname; | |
722 | func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); | |
583facb6 | 723 | if (!func->groups) |
f0b9a7e5 | 724 | return -ENOMEM; |
f0b9a7e5 | 725 | func->groups[0] = gname; |
f9819739 | 726 | func->num_groups = gname ? 1 : 0; |
f0b9a7e5 TA |
727 | func->function = function; |
728 | func++; | |
729 | func_idx++; | |
730 | } | |
731 | ||
732 | priv->pin_groups = groups; | |
733 | priv->nr_groups = grp_cnt; | |
734 | priv->pmx_functions = functions; | |
735 | priv->nr_functions = func_idx; | |
736 | return 0; | |
737 | } | |
738 | ||
739 | /* register the pinctrl interface with the pinctrl subsystem */ | |
312b00e5 | 740 | static int exynos5440_pinctrl_register(struct platform_device *pdev, |
f0b9a7e5 TA |
741 | struct exynos5440_pinctrl_priv_data *priv) |
742 | { | |
743 | struct device *dev = &pdev->dev; | |
744 | struct pinctrl_desc *ctrldesc; | |
745 | struct pinctrl_dev *pctl_dev; | |
746 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
f0b9a7e5 TA |
747 | char *pin_names; |
748 | int pin, ret; | |
749 | ||
750 | ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); | |
583facb6 | 751 | if (!ctrldesc) |
f0b9a7e5 | 752 | return -ENOMEM; |
f0b9a7e5 TA |
753 | |
754 | ctrldesc->name = "exynos5440-pinctrl"; | |
755 | ctrldesc->owner = THIS_MODULE; | |
756 | ctrldesc->pctlops = &exynos5440_pctrl_ops; | |
757 | ctrldesc->pmxops = &exynos5440_pinmux_ops; | |
758 | ctrldesc->confops = &exynos5440_pinconf_ops; | |
759 | ||
760 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
761 | EXYNOS5440_MAX_PINS, GFP_KERNEL); | |
583facb6 | 762 | if (!pindesc) |
f0b9a7e5 | 763 | return -ENOMEM; |
f0b9a7e5 TA |
764 | ctrldesc->pins = pindesc; |
765 | ctrldesc->npins = EXYNOS5440_MAX_PINS; | |
766 | ||
767 | /* dynamically populate the pin number and pin name for pindesc */ | |
768 | for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) | |
769 | pdesc->number = pin; | |
770 | ||
771 | /* | |
772 | * allocate space for storing the dynamically generated names for all | |
773 | * the pins which belong to this pin-controller. | |
774 | */ | |
775 | pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * | |
776 | ctrldesc->npins, GFP_KERNEL); | |
583facb6 | 777 | if (!pin_names) |
f0b9a7e5 | 778 | return -ENOMEM; |
f0b9a7e5 TA |
779 | |
780 | /* for each pin, set the name of the pin */ | |
781 | for (pin = 0; pin < ctrldesc->npins; pin++) { | |
79bae27f | 782 | snprintf(pin_names, 6, "gpio%02d", pin); |
f0b9a7e5 TA |
783 | pdesc = pindesc + pin; |
784 | pdesc->name = pin_names; | |
785 | pin_names += PIN_NAME_LENGTH; | |
786 | } | |
787 | ||
788 | ret = exynos5440_pinctrl_parse_dt(pdev, priv); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
40011bfe | 792 | pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, priv); |
323de9ef | 793 | if (IS_ERR(pctl_dev)) { |
f0b9a7e5 | 794 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); |
323de9ef | 795 | return PTR_ERR(pctl_dev); |
f0b9a7e5 TA |
796 | } |
797 | ||
71324fdc AJ |
798 | priv->range.name = "exynos5440-pctrl-gpio-range"; |
799 | priv->range.id = 0; | |
800 | priv->range.base = 0; | |
801 | priv->range.npins = EXYNOS5440_MAX_PINS; | |
802 | priv->range.gc = priv->gc; | |
803 | pinctrl_add_gpio_range(pctl_dev, &priv->range); | |
f0b9a7e5 TA |
804 | return 0; |
805 | } | |
806 | ||
807 | /* register the gpiolib interface with the gpiolib subsystem */ | |
312b00e5 | 808 | static int exynos5440_gpiolib_register(struct platform_device *pdev, |
f0b9a7e5 TA |
809 | struct exynos5440_pinctrl_priv_data *priv) |
810 | { | |
811 | struct gpio_chip *gc; | |
812 | int ret; | |
813 | ||
814 | gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); | |
583facb6 | 815 | if (!gc) |
f0b9a7e5 | 816 | return -ENOMEM; |
f0b9a7e5 TA |
817 | |
818 | priv->gc = gc; | |
819 | gc->base = 0; | |
820 | gc->ngpio = EXYNOS5440_MAX_PINS; | |
58383c78 | 821 | gc->parent = &pdev->dev; |
f0b9a7e5 TA |
822 | gc->set = exynos5440_gpio_set; |
823 | gc->get = exynos5440_gpio_get; | |
824 | gc->direction_input = exynos5440_gpio_direction_input; | |
825 | gc->direction_output = exynos5440_gpio_direction_output; | |
8dc3568d | 826 | gc->to_irq = exynos5440_gpio_to_irq; |
f0b9a7e5 TA |
827 | gc->label = "gpiolib-exynos5440"; |
828 | gc->owner = THIS_MODULE; | |
dbf09b0a | 829 | ret = gpiochip_add_data(gc, priv); |
f0b9a7e5 TA |
830 | if (ret) { |
831 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error " | |
832 | "code: %d\n", gc->label, ret); | |
833 | return ret; | |
834 | } | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | /* unregister the gpiolib interface with the gpiolib subsystem */ | |
312b00e5 | 840 | static int exynos5440_gpiolib_unregister(struct platform_device *pdev, |
f0b9a7e5 TA |
841 | struct exynos5440_pinctrl_priv_data *priv) |
842 | { | |
2fcea6ce | 843 | gpiochip_remove(priv->gc); |
f0b9a7e5 TA |
844 | return 0; |
845 | } | |
846 | ||
8dc3568d TA |
847 | static void exynos5440_gpio_irq_unmask(struct irq_data *irqd) |
848 | { | |
849 | struct exynos5440_pinctrl_priv_data *d; | |
850 | unsigned long gpio_int; | |
851 | ||
852 | d = irq_data_get_irq_chip_data(irqd); | |
853 | gpio_int = readl(d->reg_base + GPIO_INT); | |
854 | gpio_int |= 1 << irqd->hwirq; | |
855 | writel(gpio_int, d->reg_base + GPIO_INT); | |
856 | } | |
857 | ||
858 | static void exynos5440_gpio_irq_mask(struct irq_data *irqd) | |
859 | { | |
860 | struct exynos5440_pinctrl_priv_data *d; | |
861 | unsigned long gpio_int; | |
862 | ||
863 | d = irq_data_get_irq_chip_data(irqd); | |
864 | gpio_int = readl(d->reg_base + GPIO_INT); | |
865 | gpio_int &= ~(1 << irqd->hwirq); | |
866 | writel(gpio_int, d->reg_base + GPIO_INT); | |
867 | } | |
868 | ||
869 | /* irq_chip for gpio interrupts */ | |
870 | static struct irq_chip exynos5440_gpio_irq_chip = { | |
871 | .name = "exynos5440_gpio_irq_chip", | |
872 | .irq_unmask = exynos5440_gpio_irq_unmask, | |
873 | .irq_mask = exynos5440_gpio_irq_mask, | |
874 | }; | |
875 | ||
876 | /* interrupt handler for GPIO interrupts 0..7 */ | |
877 | static irqreturn_t exynos5440_gpio_irq(int irq, void *data) | |
878 | { | |
879 | struct exynos5440_gpio_intr_data *intd = data; | |
880 | struct exynos5440_pinctrl_priv_data *d = intd->priv; | |
881 | int virq; | |
882 | ||
883 | virq = irq_linear_revmap(d->irq_domain, intd->gpio_int); | |
884 | if (!virq) | |
885 | return IRQ_NONE; | |
886 | generic_handle_irq(virq); | |
887 | return IRQ_HANDLED; | |
888 | } | |
889 | ||
890 | static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq, | |
891 | irq_hw_number_t hw) | |
892 | { | |
893 | struct exynos5440_pinctrl_priv_data *d = h->host_data; | |
894 | ||
895 | irq_set_chip_data(virq, d); | |
896 | irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, | |
897 | handle_level_irq); | |
8dc3568d TA |
898 | return 0; |
899 | } | |
900 | ||
901 | /* irq domain callbacks for gpio interrupt controller */ | |
902 | static const struct irq_domain_ops exynos5440_gpio_irqd_ops = { | |
903 | .map = exynos5440_gpio_irq_map, | |
904 | .xlate = irq_domain_xlate_twocell, | |
905 | }; | |
906 | ||
907 | /* setup handling of gpio interrupts */ | |
908 | static int exynos5440_gpio_irq_init(struct platform_device *pdev, | |
909 | struct exynos5440_pinctrl_priv_data *priv) | |
910 | { | |
911 | struct device *dev = &pdev->dev; | |
912 | struct exynos5440_gpio_intr_data *intd; | |
913 | int i, irq, ret; | |
914 | ||
915 | intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, | |
916 | GFP_KERNEL); | |
583facb6 | 917 | if (!intd) |
8dc3568d | 918 | return -ENOMEM; |
8dc3568d TA |
919 | |
920 | for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { | |
921 | irq = irq_of_parse_and_map(dev->of_node, i); | |
922 | if (irq <= 0) { | |
923 | dev_err(dev, "irq parsing failed\n"); | |
924 | return -EINVAL; | |
925 | } | |
926 | ||
927 | intd->gpio_int = i; | |
928 | intd->priv = priv; | |
929 | ret = devm_request_irq(dev, irq, exynos5440_gpio_irq, | |
930 | 0, dev_name(dev), intd++); | |
931 | if (ret) { | |
932 | dev_err(dev, "irq request failed\n"); | |
933 | return -ENXIO; | |
934 | } | |
935 | } | |
936 | ||
937 | priv->irq_domain = irq_domain_add_linear(dev->of_node, | |
938 | EXYNOS5440_MAX_GPIO_INT, | |
939 | &exynos5440_gpio_irqd_ops, priv); | |
940 | if (!priv->irq_domain) { | |
941 | dev_err(dev, "failed to create irq domain\n"); | |
942 | return -ENXIO; | |
943 | } | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
150632b0 | 948 | static int exynos5440_pinctrl_probe(struct platform_device *pdev) |
f0b9a7e5 TA |
949 | { |
950 | struct device *dev = &pdev->dev; | |
951 | struct exynos5440_pinctrl_priv_data *priv; | |
952 | struct resource *res; | |
953 | int ret; | |
954 | ||
955 | if (!dev->of_node) { | |
956 | dev_err(dev, "device tree node not found\n"); | |
957 | return -ENODEV; | |
958 | } | |
959 | ||
c078d78a | 960 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
583facb6 | 961 | if (!priv) |
f0b9a7e5 | 962 | return -ENOMEM; |
f0b9a7e5 TA |
963 | |
964 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
9e0c1fb2 TR |
965 | priv->reg_base = devm_ioremap_resource(&pdev->dev, res); |
966 | if (IS_ERR(priv->reg_base)) | |
967 | return PTR_ERR(priv->reg_base); | |
f0b9a7e5 TA |
968 | |
969 | ret = exynos5440_gpiolib_register(pdev, priv); | |
970 | if (ret) | |
971 | return ret; | |
972 | ||
973 | ret = exynos5440_pinctrl_register(pdev, priv); | |
974 | if (ret) { | |
975 | exynos5440_gpiolib_unregister(pdev, priv); | |
976 | return ret; | |
8dc3568d TA |
977 | } |
978 | ||
979 | ret = exynos5440_gpio_irq_init(pdev, priv); | |
980 | if (ret) { | |
981 | dev_err(dev, "failed to setup gpio interrupts\n"); | |
982 | return ret; | |
f0b9a7e5 TA |
983 | } |
984 | ||
985 | platform_set_drvdata(pdev, priv); | |
986 | dev_info(dev, "EXYNOS5440 pinctrl driver registered\n"); | |
987 | return 0; | |
988 | } | |
989 | ||
990 | static const struct of_device_id exynos5440_pinctrl_dt_match[] = { | |
991 | { .compatible = "samsung,exynos5440-pinctrl" }, | |
992 | {}, | |
993 | }; | |
994 | MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); | |
995 | ||
996 | static struct platform_driver exynos5440_pinctrl_driver = { | |
997 | .probe = exynos5440_pinctrl_probe, | |
998 | .driver = { | |
999 | .name = "exynos5440-pinctrl", | |
606fca94 | 1000 | .of_match_table = exynos5440_pinctrl_dt_match, |
f0b9a7e5 TA |
1001 | }, |
1002 | }; | |
1003 | ||
1004 | static int __init exynos5440_pinctrl_drv_register(void) | |
1005 | { | |
1006 | return platform_driver_register(&exynos5440_pinctrl_driver); | |
1007 | } | |
1008 | postcore_initcall(exynos5440_pinctrl_drv_register); | |
1009 | ||
1010 | static void __exit exynos5440_pinctrl_drv_unregister(void) | |
1011 | { | |
1012 | platform_driver_unregister(&exynos5440_pinctrl_driver); | |
1013 | } | |
1014 | module_exit(exynos5440_pinctrl_drv_unregister); | |
1015 | ||
1016 | MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>"); | |
1017 | MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); | |
1018 | MODULE_LICENSE("GPL v2"); |