[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_map_resources(struct sh_pfc *pfc,
				struct platform_device *pdev)
{
	unsigned int num_windows = 0;
	unsigned int num_irqs = 0;
	struct sh_pfc_window *windows;
	unsigned int *irqs = NULL;
	struct resource *res;
	unsigned int i;

	/* Count the MEM and IRQ resources. */
	for (i = 0; i < pdev->num_resources; ++i) {
		switch (resource_type(&pdev->resource[i])) {
		case IORESOURCE_MEM:
			num_windows++;
			break;

		case IORESOURCE_IRQ:
			num_irqs++;
			break;
		}
	}

	if (num_windows == 0)
		return -EINVAL;

	/* Allocate memory windows and IRQs arrays. */
	windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
			       GFP_KERNEL);
	if (windows == NULL)
		return -ENOMEM;

	pfc->num_windows = num_windows;
	pfc->windows = windows;

	if (num_irqs) {
		irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
				    GFP_KERNEL);
		if (irqs == NULL)
			return -ENOMEM;

		pfc->num_irqs = num_irqs;
		pfc->irqs = irqs;
	}

	/* Fill them. */
	for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
		switch (resource_type(res)) {
		case IORESOURCE_MEM:
			windows->phys = res->start;
			windows->size = resource_size(res);
			windows->virt = devm_ioremap_resource(pfc->dev, res);
			if (IS_ERR(windows->virt))
				return -ENOMEM;
			windows++;
			break;

		case IORESOURCE_IRQ:
			*irqs++ = res->start;
			break;
		}
	}

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
{
	struct sh_pfc_window *window;
	phys_addr_t address = reg;
	unsigned int i;

	/* scan through physical windows and convert address */
	for (i = 0; i < pfc->num_windows; i++) {
		window = pfc->windows + i;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	BUG();
	return NULL;
}

int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
	unsigned int offset;
	unsigned int i;

	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
		const struct sh_pfc_pin_range *range = &pfc->ranges[i];

		if (pin <= range->end)
			return pin >= range->start
			     ? offset + pin - range->start : -1;

		offset += range->end - range->start + 1;
	}

	return -EINVAL;
}

static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
			  u32 data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     const struct pinmux_cfg_reg *crp,
				     unsigned int in_pos,
				     void __iomem **mapped_regp, u32 *maskp,
				     unsigned int *posp)
{
	unsigned int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    const struct pinmux_cfg_reg *crp,
				    unsigned int field, u32 value)
{
	void __iomem *mapped_reg;
	unsigned int pos;
	u32 mask, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
		"r_width = %u, f_width = %u\n",
		crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
				 const struct pinmux_cfg_reg **crp,
				 unsigned int *fieldp, u32 *valuep)
{
	unsigned int k = 0;

	while (1) {
		const struct pinmux_cfg_reg *config_reg =
			pfc->info->cfg_regs + k;
		unsigned int r_width = config_reg->reg_width;
		unsigned int f_width = config_reg->field_width;
		unsigned int curr_width;
		unsigned int bit_pos;
		unsigned int pos = 0;
		unsigned int m = 0;

		if (!r_width)
			break;

		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			u32 ncomb;
			u32 n;

			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -EINVAL;
}

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
			      u16 *enum_idp)
{
	const u16 *data = pfc->info->gpio_data;
	unsigned int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->gpio_data_size; k++) {
		if (data[k] == mark) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
		mark);
	return -EINVAL;
}

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
	const struct pinmux_range *range;
	int pos = 0;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	default:
		return -EINVAL;
	}

	/* Iterate over all the configuration fields we need to update. */
	while (1) {
		const struct pinmux_cfg_reg *cr;
		unsigned int field;
		u16 enum_id;
		u32 value;
		int in_range;
		int ret;

		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
		if (pos < 0)
			return pos;

		if (!enum_id)
			break;

		/* Check if the configuration field selects a function. If it
		 * doesn't, skip the field if it's not applicable to the
		 * requested pinmux type.
		 */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
				/* Functions are allowed to modify all
				 * fields.
				 */
				in_range = 1;
			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
				/* Input/output types can only modify fields
				 * that correspond to their respective ranges.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			}
			/* GPIOs are only allowed to modify function fields. */
		}

		if (!in_range)
			continue;

		ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
		if (ret < 0)
			return ret;

		sh_pfc_write_config_reg(pfc, cr, field, value);
	}

	return 0;
}

static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
	struct sh_pfc_pin_range *range;
	unsigned int nr_ranges;
	unsigned int i;

	if (pfc->info->pins[0].pin == (u16)-1) {
		/* Pin number -1 denotes that the SoC doesn't report pin numbers
		 * in its pin arrays yet. Consider the pin numbers range as
		 * continuous and allocate a single range.
		 */
		pfc->nr_ranges = 1;
		pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
					   GFP_KERNEL);
		if (pfc->ranges == NULL)
			return -ENOMEM;

		pfc->ranges->start = 0;
		pfc->ranges->end = pfc->info->nr_pins - 1;
		pfc->nr_gpio_pins = pfc->info->nr_pins;

		return 0;
	}

	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	 * be sorted by pin numbers, and pins without a GPIO port must come
	 * last.
	 */
	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
			nr_ranges++;
	}

	pfc->nr_ranges = nr_ranges;
	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
				   GFP_KERNEL);
	if (pfc->ranges == NULL)
		return -ENOMEM;

	range = pfc->ranges;
	range->start = pfc->info->pins[0].pin;

	for (i = 1; i < pfc->info->nr_pins; ++i) {
		if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
			continue;

		range->end = pfc->info->pins[i-1].pin;
		if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
			pfc->nr_gpio_pins = range->end + 1;

		range++;
		range->start = pfc->info->pins[i].pin;
	}

	range->end = pfc->info->pins[i-1].pin;
	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
		pfc->nr_gpio_pins = range->end + 1;

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_EMEV2
	{
		.compatible = "renesas,pfc-emev2",
		.data = &emev2_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{
		.compatible = "renesas,pfc-r8a73a4",
		.data = &r8a73a4_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{
		.compatible = "renesas,pfc-r8a7740",
		.data = &r8a7740_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{
		.compatible = "renesas,pfc-r8a7778",
		.data = &r8a7778_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{
		.compatible = "renesas,pfc-r8a7779",
		.data = &r8a7779_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{
		.compatible = "renesas,pfc-r8a7790",
		.data = &r8a7790_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7791
	{
		.compatible = "renesas,pfc-r8a7791",
		.data = &r8a7791_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7793
	{
		.compatible = "renesas,pfc-r8a7793",
		.data = &r8a7793_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7794
	{
		.compatible = "renesas,pfc-r8a7794",
		.data = &r8a7794_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{
		.compatible = "renesas,pfc-sh73a0",
		.data = &sh73a0_pinmux_info,
	},
#endif
	{ },
};
MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif

static int sh_pfc_probe(struct platform_device *pdev)
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
#ifdef CONFIG_OF
	struct device_node *np = pdev->dev.of_node;
#endif
	const struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

#ifdef CONFIG_OF
	if (np)
		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	else
#endif
		info = platid ? (const void *)platid->driver_data : NULL;

	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_map_resources(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	if (info->ops && info->ops->init) {
		ret = info->ops->init(pfc);
		if (ret < 0)
			return ret;
	}

	pinctrl_provide_dummies();

	ret = sh_pfc_init_ranges(pfc);
	if (ret < 0)
		return ret;

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		return ret;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	dev_info(pfc->dev, "%s support registered\n", info->name);

	return 0;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.of_match_table = of_match_ptr(sh_pfc_of_table),
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
b72421d8	13
90efde22	14	#include <linux/bitops.h>
2967dab1	15	#include <linux/err.h>
90efde22	16	#include <linux/errno.h>
2967dab1	17	#include <linux/io.h>
b0e10211	18	#include <linux/ioport.h>
90efde22 LP	19	#include <linux/kernel.h>
90efde22 LP	20	#include <linux/module.h>
fe1c9a82 LP	21	#include <linux/of.h>
fe1c9a82 LP	22	#include <linux/of_device.h>
ca5481c6	23	#include <linux/pinctrl/machine.h>
c6193eac	24	#include <linux/platform_device.h>
90efde22	25	#include <linux/slab.h>
b0e10211	26
f9165132 LP	27	#include "core.h"
f9165132 LP	28
70c8f01a LP	29	static int sh_pfc_map_resources(struct sh_pfc *pfc,
70c8f01a LP	30	struct platform_device *pdev)
b0e10211	31	{
70c8f01a LP	32	unsigned int num_windows = 0;
	33	unsigned int num_irqs = 0;
	34	struct sh_pfc_window *windows;
	35	unsigned int *irqs = NULL;
b0e10211	36	struct resource *res;
70c8f01a LP	37	unsigned int i;
	38
	39	/* Count the MEM and IRQ resources. */
	40	for (i = 0; i < pdev->num_resources; ++i) {
	41	switch (resource_type(&pdev->resource[i])) {
	42	case IORESOURCE_MEM:
	43	num_windows++;
	44	break;
	45
	46	case IORESOURCE_IRQ:
	47	num_irqs++;
	48	break;
	49	}
	50	}
b0e10211	51
70c8f01a	52	if (num_windows == 0)
bee9f22b	53	return -EINVAL;
b0e10211	54
70c8f01a LP	55	/* Allocate memory windows and IRQs arrays. */
	56	windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
	57	GFP_KERNEL);
	58	if (windows == NULL)
1724acfd	59	return -ENOMEM;
b0e10211	60
70c8f01a LP	61	pfc->num_windows = num_windows;
70c8f01a LP	62	pfc->windows = windows;
973931ae	63
70c8f01a LP	64	if (num_irqs) {
	65	irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
	66	GFP_KERNEL);
	67	if (irqs == NULL)
1724acfd	68	return -ENOMEM;
70c8f01a LP	69
	70	pfc->num_irqs = num_irqs;
	71	pfc->irqs = irqs;
	72	}
	73
	74	/* Fill them. */
	75	for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
	76	switch (resource_type(res)) {
	77	case IORESOURCE_MEM:
	78	windows->phys = res->start;
	79	windows->size = resource_size(res);
	80	windows->virt = devm_ioremap_resource(pfc->dev, res);
	81	if (IS_ERR(windows->virt))
	82	return -ENOMEM;
	83	windows++;
	84	break;
	85
	86	case IORESOURCE_IRQ:
	87	*irqs++ = res->start;
	88	break;
	89	}
b0e10211 MD	90	}
	91
	92	return 0;
b0e10211 MD	93	}
b0e10211 MD	94
1f34de05	95	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc, u32 reg)
b0e10211	96	{
4aeacd5b	97	struct sh_pfc_window *window;
1f34de05	98	phys_addr_t address = reg;
bee9f22b	99	unsigned int i;
b0e10211 MD	100
b0e10211 MD	101	/* scan through physical windows and convert address */
bee9f22b	102	for (i = 0; i < pfc->num_windows; i++) {
5b46ac3a	103	window = pfc->windows + i;
b0e10211 MD	104
	105	if (address < window->phys)
	106	continue;
	107
	108	if (address >= (window->phys + window->size))
	109	continue;
	110
	111	return window->virt + (address - window->phys);
	112	}
	113
bee9f22b	114	BUG();
1960d580	115	return NULL;
b0e10211	116	}
2967dab1	117
1a0039dc	118	int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b	119	{
63d57383 LP	120	unsigned int offset;
	121	unsigned int i;
	122
acac8ed5 LP	123	for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
acac8ed5 LP	124	const struct sh_pfc_pin_range *range = &pfc->ranges[i];
63d57383 LP	125
63d57383 LP	126	if (pin <= range->end)
acac8ed5 LP	127	return pin >= range->start
acac8ed5 LP	128	? offset + pin - range->start : -1;
63d57383	129
acac8ed5	130	offset += range->end - range->start + 1;
63d57383 LP	131	}
63d57383 LP	132
b705c054	133	return -EINVAL;
934cb02b LP	134	}
934cb02b LP	135
533743dc	136	static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1 MD	137	{
	138	if (enum_id < r->begin)
	139	return 0;
	140
	141	if (enum_id > r->end)
	142	return 0;
	143
	144	return 1;
	145	}
	146
cef28a28	147	u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
3292094e MD	148	{
	149	switch (reg_width) {
	150	case 8:
b0e10211	151	return ioread8(mapped_reg);
3292094e	152	case 16:
b0e10211	153	return ioread16(mapped_reg);
3292094e	154	case 32:
b0e10211	155	return ioread32(mapped_reg);
3292094e MD	156	}
	157
	158	BUG();
	159	return 0;
	160	}
	161
cef28a28	162	void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
fc88936a	163	u32 data)
3292094e MD	164	{
	165	switch (reg_width) {
	166	case 8:
b0e10211	167	iowrite8(data, mapped_reg);
3292094e MD	168	return;
3292094e MD	169	case 16:
b0e10211	170	iowrite16(data, mapped_reg);
3292094e MD	171	return;
3292094e MD	172	case 32:
b0e10211	173	iowrite32(data, mapped_reg);
3292094e MD	174	return;
	175	}
	176
	177	BUG();
	178	}
	179
4aeacd5b	180	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee	181	const struct pinmux_cfg_reg *crp,
cef28a28	182	unsigned int in_pos,
fc88936a	183	void __iomem *mapped_regp, u32 maskp,
cef28a28	184	unsigned int *posp)
2967dab1	185	{
8d72a7fc	186	unsigned int k;
f78a26f5	187
4aeacd5b	188	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	189
f78a26f5 MD	190	if (crp->field_width) {
	191	*maskp = (1 << crp->field_width) - 1;
	192	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	193	} else {
	194	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	195	*posp = crp->reg_width;
	196	for (k = 0; k <= in_pos; k++)
	197	*posp -= crp->var_field_width[k];
	198	}
18925e11 MD	199	}
18925e11 MD	200
4aeacd5b	201	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee	202	const struct pinmux_cfg_reg *crp,
cef28a28	203	unsigned int field, u32 value)
0fc64cc0	204	{
18925e11	205	void __iomem *mapped_reg;
cef28a28	206	unsigned int pos;
fc88936a	207	u32 mask, data;
0fc64cc0	208
4aeacd5b	209	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	210
1f34de05	211	dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
dc700715	212	"r_width = %u, f_width = %u\n",
9a643c9a	213	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	214
	215	mask = ~(mask << pos);
	216	value = value << pos;
2967dab1	217
4aeacd5b	218	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	219	data &= mask;
	220	data \|= value;
	221
19bb7fe3	222	if (pfc->info->unlock_reg)
4aeacd5b	223	sh_pfc_write_raw_reg(
19bb7fe3	224	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	225	~data);
e499ada8	226
4aeacd5b	227	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	228	}
2967dab1 MD	229
533743dc	230	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cef28a28 GU	231	const struct pinmux_cfg_reg **crp,
cef28a28 GU	232	unsigned int fieldp, u32 valuep)
2967dab1	233	{
cef28a28	234	unsigned int k = 0;
2967dab1	235
2967dab1	236	while (1) {
cef28a28 GU	237	const struct pinmux_cfg_reg *config_reg =
	238	pfc->info->cfg_regs + k;
	239	unsigned int r_width = config_reg->reg_width;
	240	unsigned int f_width = config_reg->field_width;
	241	unsigned int curr_width;
	242	unsigned int bit_pos;
	243	unsigned int pos = 0;
	244	unsigned int m = 0;
2967dab1 MD	245
	246	if (!r_width)
	247	break;
f78a26f5	248
f78a26f5	249	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
cef28a28 GU	250	u32 ncomb;
	251	u32 n;
	252
f78a26f5 MD	253	if (f_width)
	254	curr_width = f_width;
	255	else
	256	curr_width = config_reg->var_field_width[m];
	257
	258	ncomb = 1 << curr_width;
	259	for (n = 0; n < ncomb; n++) {
	260	if (config_reg->enum_ids[pos + n] == enum_id) {
	261	*crp = config_reg;
	262	*fieldp = m;
	263	*valuep = n;
f78a26f5 MD	264	return 0;
f78a26f5 MD	265	}
2967dab1	266	}
f78a26f5 MD	267	pos += ncomb;
f78a26f5 MD	268	m++;
2967dab1 MD	269	}
	270	k++;
	271	}
	272
b705c054	273	return -EINVAL;
2967dab1 MD	274	}
2967dab1 MD	275
533743dc LP	276	static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
533743dc LP	277	u16 *enum_idp)
2967dab1	278	{
533743dc	279	const u16 *data = pfc->info->gpio_data;
8d72a7fc	280	unsigned int k;
2967dab1	281
2967dab1 MD	282	if (pos) {
	283	*enum_idp = data[pos + 1];
	284	return pos + 1;
	285	}
	286
19bb7fe3	287	for (k = 0; k < pfc->info->gpio_data_size; k++) {
a68fdca9	288	if (data[k] == mark) {
2967dab1 MD	289	*enum_idp = data[k + 1];
	290	return k + 1;
	291	}
	292	}
	293
9a643c9a LP	294	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
9a643c9a LP	295	mark);
b705c054	296	return -EINVAL;
2967dab1 MD	297	}
2967dab1 MD	298
861601de	299	int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1	300	{
cd3c1bee	301	const struct pinmux_range *range;
cef28a28	302	int pos = 0;
2967dab1 MD	303
2967dab1 MD	304	switch (pinmux_type) {
e3c47051	305	case PINMUX_TYPE_GPIO:
2967dab1 MD	306	case PINMUX_TYPE_FUNCTION:
	307	range = NULL;
	308	break;
	309
	310	case PINMUX_TYPE_OUTPUT:
19bb7fe3	311	range = &pfc->info->output;
2967dab1 MD	312	break;
	313
	314	case PINMUX_TYPE_INPUT:
19bb7fe3	315	range = &pfc->info->input;
2967dab1 MD	316	break;
2967dab1 MD	317
2967dab1	318	default:
b705c054	319	return -EINVAL;
2967dab1 MD	320	}
2967dab1 MD	321
e3c47051	322	/* Iterate over all the configuration fields we need to update. */
2967dab1	323	while (1) {
cef28a28 GU	324	const struct pinmux_cfg_reg *cr;
	325	unsigned int field;
	326	u16 enum_id;
	327	u32 value;
	328	int in_range;
	329	int ret;
	330
a68fdca9	331	pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054 LP	332	if (pos < 0)
b705c054 LP	333	return pos;
2967dab1 MD	334
	335	if (!enum_id)
	336	break;
	337
e3c47051 LP	338	/* Check if the configuration field selects a function. If it
	339	* doesn't, skip the field if it's not applicable to the
	340	* requested pinmux type.
	341	*/
19bb7fe3	342	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145	343	if (!in_range) {
e3c47051 LP	344	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
	345	/* Functions are allowed to modify all
	346	* fields.
	347	*/
	348	in_range = 1;
	349	} else if (pinmux_type != PINMUX_TYPE_GPIO) {
	350	/* Input/output types can only modify fields
	351	* that correspond to their respective ranges.
50dd3145	352	*/
4aeacd5b	353	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	354
	355	/*
	356	* special case pass through for fixed
	357	* input-only or output-only pins without
	358	* function enum register association.
	359	*/
	360	if (in_range && enum_id == range->force)
	361	continue;
50dd3145	362	}
e3c47051	363	/* GPIOs are only allowed to modify function fields. */
42eed42b MD	364	}
42eed42b MD	365
2967dab1 MD	366	if (!in_range)
	367	continue;
	368
b705c054 LP	369	ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
	370	if (ret < 0)
	371	return ret;
2967dab1	372
861601de	373	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	374	}
	375
	376	return 0;
2967dab1 MD	377	}
2967dab1 MD	378
acac8ed5 LP	379	static int sh_pfc_init_ranges(struct sh_pfc *pfc)
	380	{
	381	struct sh_pfc_pin_range *range;
	382	unsigned int nr_ranges;
	383	unsigned int i;
	384
	385	if (pfc->info->pins[0].pin == (u16)-1) {
	386	/* Pin number -1 denotes that the SoC doesn't report pin numbers
	387	* in its pin arrays yet. Consider the pin numbers range as
	388	* continuous and allocate a single range.
	389	*/
	390	pfc->nr_ranges = 1;
	391	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
	392	GFP_KERNEL);
	393	if (pfc->ranges == NULL)
	394	return -ENOMEM;
	395
	396	pfc->ranges->start = 0;
	397	pfc->ranges->end = pfc->info->nr_pins - 1;
	398	pfc->nr_gpio_pins = pfc->info->nr_pins;
	399
	400	return 0;
	401	}
	402
4f82e3ee LP	403	/* Count, allocate and fill the ranges. The PFC SoC data pins array must
	404	* be sorted by pin numbers, and pins without a GPIO port must come
	405	* last.
	406	*/
acac8ed5 LP	407	for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
	408	if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
	409	nr_ranges++;
	410	}
	411
	412	pfc->nr_ranges = nr_ranges;
	413	pfc->ranges = devm_kzalloc(pfc->dev, sizeof(pfc->ranges) nr_ranges,
	414	GFP_KERNEL);
	415	if (pfc->ranges == NULL)
	416	return -ENOMEM;
	417
	418	range = pfc->ranges;
	419	range->start = pfc->info->pins[0].pin;
	420
	421	for (i = 1; i < pfc->info->nr_pins; ++i) {
4f82e3ee LP	422	if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
	423	continue;
	424
	425	range->end = pfc->info->pins[i-1].pin;
	426	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
	427	pfc->nr_gpio_pins = range->end + 1;
	428
	429	range++;
	430	range->start = pfc->info->pins[i].pin;
acac8ed5 LP	431	}
	432
	433	range->end = pfc->info->pins[i-1].pin;
4f82e3ee LP	434	if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
4f82e3ee LP	435	pfc->nr_gpio_pins = range->end + 1;
acac8ed5 LP	436
	437	return 0;
	438	}
	439
fe1c9a82 LP	440	#ifdef CONFIG_OF
fe1c9a82 LP	441	static const struct of_device_id sh_pfc_of_table[] = {
1e7d5d84 NS	442	#ifdef CONFIG_PINCTRL_PFC_EMEV2
	443	{
	444	.compatible = "renesas,pfc-emev2",
	445	.data = &emev2_pinmux_info,
	446	},
	447	#endif
fe1c9a82 LP	448	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	449	{
	450	.compatible = "renesas,pfc-r8a73a4",
	451	.data = &r8a73a4_pinmux_info,
	452	},
	453	#endif
	454	#ifdef CONFIG_PINCTRL_PFC_R8A7740
	455	{
	456	.compatible = "renesas,pfc-r8a7740",
	457	.data = &r8a7740_pinmux_info,
	458	},
	459	#endif
	460	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	461	{
	462	.compatible = "renesas,pfc-r8a7778",
	463	.data = &r8a7778_pinmux_info,
	464	},
	465	#endif
	466	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	467	{
	468	.compatible = "renesas,pfc-r8a7779",
	469	.data = &r8a7779_pinmux_info,
	470	},
	471	#endif
	472	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	473	{
	474	.compatible = "renesas,pfc-r8a7790",
	475	.data = &r8a7790_pinmux_info,
	476	},
	477	#endif
50884519 HN	478	#ifdef CONFIG_PINCTRL_PFC_R8A7791
	479	{
	480	.compatible = "renesas,pfc-r8a7791",
	481	.data = &r8a7791_pinmux_info,
	482	},
	483	#endif
19e1e98f UH	484	#ifdef CONFIG_PINCTRL_PFC_R8A7793
	485	{
	486	.compatible = "renesas,pfc-r8a7793",
	487	.data = &r8a7793_pinmux_info,
	488	},
	489	#endif
43c4436e HN	490	#ifdef CONFIG_PINCTRL_PFC_R8A7794
	491	{
	492	.compatible = "renesas,pfc-r8a7794",
	493	.data = &r8a7794_pinmux_info,
	494	},
	495	#endif
fe1c9a82 LP	496	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	497	{
	498	.compatible = "renesas,pfc-sh73a0",
	499	.data = &sh73a0_pinmux_info,
	500	},
	501	#endif
	502	{ },
	503	};
	504	MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
	505	#endif
	506
c6193eac	507	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	508	{
fe1c9a82 LP	509	const struct platform_device_id *platid = platform_get_device_id(pdev);
	510	#ifdef CONFIG_OF
	511	struct device_node *np = pdev->dev.of_node;
	512	#endif
cd3c1bee	513	const struct sh_pfc_soc_info *info;
c6193eac	514	struct sh_pfc *pfc;
0fc64cc0	515	int ret;
2967dab1	516
fe1c9a82 LP	517	#ifdef CONFIG_OF
	518	if (np)
	519	info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	520	else
	521	#endif
	522	info = platid ? (const void *)platid->driver_data : NULL;
	523
19bb7fe3	524	if (info == NULL)
c6193eac	525	return -ENODEV;
2967dab1	526
8c43fcc7	527	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	528	if (pfc == NULL)
c6193eac LP	529	return -ENOMEM;
d4e62d00	530
19bb7fe3	531	pfc->info = info;
c6193eac LP	532	pfc->dev = &pdev->dev;
c6193eac LP	533
70c8f01a	534	ret = sh_pfc_map_resources(pfc, pdev);
c6193eac	535	if (unlikely(ret < 0))
b0e10211 MD	536	return ret;
b0e10211 MD	537
c6193eac	538	spin_lock_init(&pfc->lock);
69edbba0	539
0c151062 LP	540	if (info->ops && info->ops->init) {
	541	ret = info->ops->init(pfc);
	542	if (ret < 0)
	543	return ret;
	544	}
	545
ca5481c6	546	pinctrl_provide_dummies();
b0e10211	547
acac8ed5 LP	548	ret = sh_pfc_init_ranges(pfc);
	549	if (ret < 0)
	550	return ret;
	551
ca5481c6 PM	552	/*
	553	* Initialize pinctrl bindings first
	554	*/
c6193eac	555	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	556	if (unlikely(ret != 0))
0a332c96	557	return ret;
ca5481c6	558
6f6a4a68	559	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	560	/*
	561	* Then the GPIO chip
	562	*/
c6193eac	563	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	564	if (unlikely(ret != 0)) {
ca5481c6 PM	565	/*
	566	* If the GPIO chip fails to come up we still leave the
	567	* PFC state as it is, given that there are already
	568	* extant users of it that have succeeded by this point.
	569	*/
9a643c9a	570	dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7	571	}
6f6a4a68	572	#endif
b72421d8	573
c6193eac LP	574	platform_set_drvdata(pdev, pfc);
c6193eac LP	575
9a643c9a	576	dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6	577
b3c185a7	578	return 0;
b72421d8	579	}
6f6a4a68	580
c6193eac LP	581	static int sh_pfc_remove(struct platform_device *pdev)
	582	{
	583	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	584
	585	#ifdef CONFIG_GPIO_SH_PFC
	586	sh_pfc_unregister_gpiochip(pfc);
	587	#endif
	588	sh_pfc_unregister_pinctrl(pfc);
	589
c6193eac LP	590	return 0;
	591	}
	592
	593	static const struct platform_device_id sh_pfc_id_table[] = {
d5b1521a LP	594	#ifdef CONFIG_PINCTRL_PFC_R8A7740
d5b1521a LP	595	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
881023d2	596	#endif
87f8c988 KM	597	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	598	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
	599	#endif
881023d2 LP	600	#ifdef CONFIG_PINCTRL_PFC_R8A7779
881023d2 LP	601	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
6e5469a6	602	#endif
ccda552e LP	603	#ifdef CONFIG_PINCTRL_PFC_SH7203
	604	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	605	#endif
a8d42fc4 LP	606	#ifdef CONFIG_PINCTRL_PFC_SH7264
	607	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	608	#endif
f5e811f2 LP	609	#ifdef CONFIG_PINCTRL_PFC_SH7269
	610	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	611	#endif
5d5166dc LP	612	#ifdef CONFIG_PINCTRL_PFC_SH73A0
5d5166dc LP	613	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
74cad605 LP	614	#endif
	615	#ifdef CONFIG_PINCTRL_PFC_SH7720
	616	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	617	#endif
	618	#ifdef CONFIG_PINCTRL_PFC_SH7722
	619	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	620	#endif
	621	#ifdef CONFIG_PINCTRL_PFC_SH7723
	622	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	623	#endif
	624	#ifdef CONFIG_PINCTRL_PFC_SH7724
	625	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	626	#endif
	627	#ifdef CONFIG_PINCTRL_PFC_SH7734
	628	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	629	#endif
	630	#ifdef CONFIG_PINCTRL_PFC_SH7757
	631	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	632	#endif
	633	#ifdef CONFIG_PINCTRL_PFC_SH7785
	634	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	635	#endif
	636	#ifdef CONFIG_PINCTRL_PFC_SH7786
	637	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	638	#endif
	639	#ifdef CONFIG_PINCTRL_PFC_SHX3
	640	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	641	#endif
c6193eac LP	642	{ "sh-pfc", 0 },
	643	{ },
	644	};
	645	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	646
	647	static struct platform_driver sh_pfc_driver = {
	648	.probe = sh_pfc_probe,
	649	.remove = sh_pfc_remove,
	650	.id_table = sh_pfc_id_table,
	651	.driver = {
	652	.name = DRV_NAME,
fe1c9a82	653	.of_match_table = of_match_ptr(sh_pfc_of_table),
c6193eac LP	654	},
	655	};
	656
40ee6fce LP	657	static int __init sh_pfc_init(void)
	658	{
	659	return platform_driver_register(&sh_pfc_driver);
c6193eac	660	}
40ee6fce	661	postcore_initcall(sh_pfc_init);
c6193eac LP	662
	663	static void __exit sh_pfc_exit(void)
	664	{
	665	platform_driver_unregister(&sh_pfc_driver);
	666	}
	667	module_exit(sh_pfc_exit);
	668
6f6a4a68 LP	669	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	670	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	671	MODULE_LICENSE("GPL v2");