[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
{
	struct resource *res;
	int k;

	if (pdev->num_resources == 0)
		return -EINVAL;

	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
				   sizeof(*pfc->window), GFP_NOWAIT);
	if (!pfc->window)
		return -ENOMEM;

	pfc->num_windows = pdev->num_resources;

	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
		WARN_ON(resource_type(res) != IORESOURCE_MEM);
		pfc->window[k].phys = res->start;
		pfc->window[k].size = resource_size(res);
		pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
							   resource_size(res));
		if (!pfc->window[k].virt)
			return -ENOMEM;
	}

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
					 unsigned long address)
{
	struct sh_pfc_window *window;
	unsigned int i;

	/* scan through physical windows and convert address */
	for (i = 0; i < pfc->num_windows; i++) {
		window = pfc->window + i;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	BUG();
	return NULL;
}

int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
	unsigned int offset;
	unsigned int i;

	if (pfc->info->ranges == NULL)
		return pin;

	for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
		const struct pinmux_range *range = &pfc->info->ranges[i];

		if (pin <= range->end)
			return pin >= range->begin
			     ? offset + pin - range->begin : -1;

		offset += range->end - range->begin + 1;
	}

	return -EINVAL;
}

static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
				  unsigned long reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
			  unsigned long data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     const struct pinmux_cfg_reg *crp,
				     unsigned long in_pos,
				     void __iomem **mapped_regp,
				     unsigned long *maskp,
				     unsigned long *posp)
{
	int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    const struct pinmux_cfg_reg *crp,
				    unsigned long field, unsigned long value)
{
	void __iomem *mapped_reg;
	unsigned long mask, pos, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
		"r_width = %ld, f_width = %ld\n",
		crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
				 const struct pinmux_cfg_reg **crp, int *fieldp,
				 int *valuep)
{
	const struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;

	k = 0;
	while (1) {
		config_reg = pfc->info->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;

		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -EINVAL;
}

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
			      u16 *enum_idp)
{
	const u16 *data = pfc->info->gpio_data;
	int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->gpio_data_size; k++) {
		if (data[k] == mark) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
		mark);
	return -EINVAL;
}

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
	const struct pinmux_cfg_reg *cr = NULL;
	u16 enum_id;
	const struct pinmux_range *range;
	int in_range, pos, field, value;
	int ret;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	default:
		return -EINVAL;
	}

	pos = 0;
	enum_id = 0;
	field = 0;
	value = 0;

	/* Iterate over all the configuration fields we need to update. */
	while (1) {
		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
		if (pos < 0)
			return pos;

		if (!enum_id)
			break;

		/* Check if the configuration field selects a function. If it
		 * doesn't, skip the field if it's not applicable to the
		 * requested pinmux type.
		 */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			if (pinmux_type == PINMUX_TYPE_FUNCTION) {
				/* Functions are allowed to modify all
				 * fields.
				 */
				in_range = 1;
			} else if (pinmux_type != PINMUX_TYPE_GPIO) {
				/* Input/output types can only modify fields
				 * that correspond to their respective ranges.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			}
			/* GPIOs are only allowed to modify function fields. */
		}

		if (!in_range)
			continue;

		ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
		if (ret < 0)
			return ret;

		sh_pfc_write_config_reg(pfc, cr, field, value);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{
		.compatible = "renesas,pfc-r8a73a4",
		.data = &r8a73a4_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{
		.compatible = "renesas,pfc-r8a7740",
		.data = &r8a7740_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{
		.compatible = "renesas,pfc-r8a7778",
		.data = &r8a7778_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{
		.compatible = "renesas,pfc-r8a7779",
		.data = &r8a7779_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{
		.compatible = "renesas,pfc-r8a7790",
		.data = &r8a7790_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{
		.compatible = "renesas,pfc-sh7372",
		.data = &sh7372_pinmux_info,
	},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{
		.compatible = "renesas,pfc-sh73a0",
		.data = &sh73a0_pinmux_info,
	},
#endif
	{ },
};
MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
#endif

static int sh_pfc_probe(struct platform_device *pdev)
{
	const struct platform_device_id *platid = platform_get_device_id(pdev);
#ifdef CONFIG_OF
	struct device_node *np = pdev->dev.of_node;
#endif
	const struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

#ifdef CONFIG_OF
	if (np)
		info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	else
#endif
		info = platid ? (const void *)platid->driver_data : NULL;

	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_ioremap(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	if (info->ops && info->ops->init) {
		ret = info->ops->init(pfc);
		if (ret < 0)
			return ret;
	}

	pinctrl_provide_dummies();

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		goto error;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	dev_info(pfc->dev, "%s support registered\n", info->name);

	return 0;

error:
	if (info->ops && info->ops->exit)
		info->ops->exit(pfc);
	return ret;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	if (pfc->info->ops && pfc->info->ops->exit)
		pfc->info->ops->exit(pfc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
	{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(sh_pfc_of_table),
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
b72421d8	13
90efde22	14	#include <linux/bitops.h>
2967dab1	15	#include <linux/err.h>
90efde22	16	#include <linux/errno.h>
2967dab1	17	#include <linux/io.h>
b0e10211	18	#include <linux/ioport.h>
90efde22 LP	19	#include <linux/kernel.h>
90efde22 LP	20	#include <linux/module.h>
fe1c9a82 LP	21	#include <linux/of.h>
fe1c9a82 LP	22	#include <linux/of_device.h>
ca5481c6	23	#include <linux/pinctrl/machine.h>
c6193eac	24	#include <linux/platform_device.h>
90efde22	25	#include <linux/slab.h>
b0e10211	26
f9165132 LP	27	#include "core.h"
f9165132 LP	28
973931ae	29	static int sh_pfc_ioremap(struct sh_pfc pfc, struct platform_device pdev)
b0e10211 MD	30	{
	31	struct resource *res;
	32	int k;
	33
bee9f22b LP	34	if (pdev->num_resources == 0)
bee9f22b LP	35	return -EINVAL;
b0e10211	36
56dc04af	37	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
1724acfd	38	sizeof(*pfc->window), GFP_NOWAIT);
b3c185a7	39	if (!pfc->window)
1724acfd	40	return -ENOMEM;
b0e10211	41
56dc04af	42	pfc->num_windows = pdev->num_resources;
973931ae	43
56dc04af	44	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
b0e10211	45	WARN_ON(resource_type(res) != IORESOURCE_MEM);
b3c185a7 PM	46	pfc->window[k].phys = res->start;
b3c185a7 PM	47	pfc->window[k].size = resource_size(res);
c9fa88e2 LP	48	pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
	49	resource_size(res));
	50	if (!pfc->window[k].virt)
1724acfd	51	return -ENOMEM;
b0e10211 MD	52	}
	53
	54	return 0;
b0e10211 MD	55	}
b0e10211 MD	56
e51d5343 LP	57	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc,
e51d5343 LP	58	unsigned long address)
b0e10211	59	{
4aeacd5b	60	struct sh_pfc_window *window;
bee9f22b	61	unsigned int i;
b0e10211 MD	62
b0e10211 MD	63	/* scan through physical windows and convert address */
bee9f22b LP	64	for (i = 0; i < pfc->num_windows; i++) {
bee9f22b LP	65	window = pfc->window + i;
b0e10211 MD	66
	67	if (address < window->phys)
	68	continue;
	69
	70	if (address >= (window->phys + window->size))
	71	continue;
	72
	73	return window->virt + (address - window->phys);
	74	}
	75
bee9f22b	76	BUG();
1960d580	77	return NULL;
b0e10211	78	}
2967dab1	79
1a0039dc	80	int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b	81	{
63d57383 LP	82	unsigned int offset;
	83	unsigned int i;
	84
	85	if (pfc->info->ranges == NULL)
1a0039dc	86	return pin;
63d57383 LP	87
	88	for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
	89	const struct pinmux_range *range = &pfc->info->ranges[i];
	90
	91	if (pin <= range->end)
	92	return pin >= range->begin
1a0039dc	93	? offset + pin - range->begin : -1;
63d57383 LP	94
	95	offset += range->end - range->begin + 1;
	96	}
	97
b705c054	98	return -EINVAL;
934cb02b LP	99	}
934cb02b LP	100
533743dc	101	static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
2967dab1 MD	102	{
	103	if (enum_id < r->begin)
	104	return 0;
	105
	106	if (enum_id > r->end)
	107	return 0;
	108
	109	return 1;
	110	}
	111
41f1219f LP	112	unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
41f1219f LP	113	unsigned long reg_width)
3292094e MD	114	{
	115	switch (reg_width) {
	116	case 8:
b0e10211	117	return ioread8(mapped_reg);
3292094e	118	case 16:
b0e10211	119	return ioread16(mapped_reg);
3292094e	120	case 32:
b0e10211	121	return ioread32(mapped_reg);
3292094e MD	122	}
	123
	124	BUG();
	125	return 0;
	126	}
	127
41f1219f LP	128	void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
41f1219f LP	129	unsigned long data)
3292094e MD	130	{
	131	switch (reg_width) {
	132	case 8:
b0e10211	133	iowrite8(data, mapped_reg);
3292094e MD	134	return;
3292094e MD	135	case 16:
b0e10211	136	iowrite16(data, mapped_reg);
3292094e MD	137	return;
3292094e MD	138	case 32:
b0e10211	139	iowrite32(data, mapped_reg);
3292094e MD	140	return;
	141	}
	142
	143	BUG();
	144	}
	145
4aeacd5b	146	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
cd3c1bee	147	const struct pinmux_cfg_reg *crp,
4aeacd5b LP	148	unsigned long in_pos,
	149	void __iomem **mapped_regp,
	150	unsigned long *maskp,
	151	unsigned long *posp)
2967dab1	152	{
f78a26f5 MD	153	int k;
f78a26f5 MD	154
4aeacd5b	155	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	156
f78a26f5 MD	157	if (crp->field_width) {
	158	*maskp = (1 << crp->field_width) - 1;
	159	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	160	} else {
	161	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	162	*posp = crp->reg_width;
	163	for (k = 0; k <= in_pos; k++)
	164	*posp -= crp->var_field_width[k];
	165	}
18925e11 MD	166	}
18925e11 MD	167
4aeacd5b	168	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
cd3c1bee	169	const struct pinmux_cfg_reg *crp,
4aeacd5b	170	unsigned long field, unsigned long value)
0fc64cc0	171	{
18925e11	172	void __iomem *mapped_reg;
e499ada8	173	unsigned long mask, pos, data;
0fc64cc0	174
4aeacd5b	175	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	176
9a643c9a LP	177	dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
	178	"r_width = %ld, f_width = %ld\n",
	179	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	180
	181	mask = ~(mask << pos);
	182	value = value << pos;
2967dab1	183
4aeacd5b	184	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	185	data &= mask;
	186	data \|= value;
	187
19bb7fe3	188	if (pfc->info->unlock_reg)
4aeacd5b	189	sh_pfc_write_raw_reg(
19bb7fe3	190	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	191	~data);
e499ada8	192
4aeacd5b	193	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	194	}
2967dab1 MD	195
533743dc	196	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
cd3c1bee	197	const struct pinmux_cfg_reg *crp, int fieldp,
861601de	198	int *valuep)
2967dab1	199	{
cd3c1bee	200	const struct pinmux_cfg_reg *config_reg;
f78a26f5 MD	201	unsigned long r_width, f_width, curr_width, ncomb;
f78a26f5 MD	202	int k, m, n, pos, bit_pos;
2967dab1 MD	203
	204	k = 0;
	205	while (1) {
19bb7fe3	206	config_reg = pfc->info->cfg_regs + k;
2967dab1 MD	207
	208	r_width = config_reg->reg_width;
	209	f_width = config_reg->field_width;
	210
	211	if (!r_width)
	212	break;
f78a26f5 MD	213
	214	pos = 0;
	215	m = 0;
	216	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
	217	if (f_width)
	218	curr_width = f_width;
	219	else
	220	curr_width = config_reg->var_field_width[m];
	221
	222	ncomb = 1 << curr_width;
	223	for (n = 0; n < ncomb; n++) {
	224	if (config_reg->enum_ids[pos + n] == enum_id) {
	225	*crp = config_reg;
	226	*fieldp = m;
	227	*valuep = n;
f78a26f5 MD	228	return 0;
f78a26f5 MD	229	}
2967dab1	230	}
f78a26f5 MD	231	pos += ncomb;
f78a26f5 MD	232	m++;
2967dab1 MD	233	}
	234	k++;
	235	}
	236
b705c054	237	return -EINVAL;
2967dab1 MD	238	}
2967dab1 MD	239
533743dc LP	240	static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
533743dc LP	241	u16 *enum_idp)
2967dab1	242	{
533743dc	243	const u16 *data = pfc->info->gpio_data;
2967dab1 MD	244	int k;
2967dab1 MD	245
2967dab1 MD	246	if (pos) {
	247	*enum_idp = data[pos + 1];
	248	return pos + 1;
	249	}
	250
19bb7fe3	251	for (k = 0; k < pfc->info->gpio_data_size; k++) {
a68fdca9	252	if (data[k] == mark) {
2967dab1 MD	253	*enum_idp = data[k + 1];
	254	return k + 1;
	255	}
	256	}
	257
9a643c9a LP	258	dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
9a643c9a LP	259	mark);
b705c054	260	return -EINVAL;
2967dab1 MD	261	}
2967dab1 MD	262
861601de	263	int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1	264	{
cd3c1bee	265	const struct pinmux_cfg_reg *cr = NULL;
533743dc	266	u16 enum_id;
cd3c1bee	267	const struct pinmux_range *range;
ad4a07ff	268	int in_range, pos, field, value;
b705c054	269	int ret;
2967dab1 MD	270
2967dab1 MD	271	switch (pinmux_type) {
e3c47051	272	case PINMUX_TYPE_GPIO:
2967dab1 MD	273	case PINMUX_TYPE_FUNCTION:
	274	range = NULL;
	275	break;
	276
	277	case PINMUX_TYPE_OUTPUT:
19bb7fe3	278	range = &pfc->info->output;
2967dab1 MD	279	break;
	280
	281	case PINMUX_TYPE_INPUT:
19bb7fe3	282	range = &pfc->info->input;
2967dab1 MD	283	break;
2967dab1 MD	284
2967dab1	285	default:
b705c054	286	return -EINVAL;
2967dab1 MD	287	}
	288
	289	pos = 0;
	290	enum_id = 0;
ad4a07ff MD	291	field = 0;
ad4a07ff MD	292	value = 0;
e3c47051 LP	293
e3c47051 LP	294	/* Iterate over all the configuration fields we need to update. */
2967dab1	295	while (1) {
a68fdca9	296	pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
b705c054 LP	297	if (pos < 0)
b705c054 LP	298	return pos;
2967dab1 MD	299
	300	if (!enum_id)
	301	break;
	302
e3c47051 LP	303	/* Check if the configuration field selects a function. If it
	304	* doesn't, skip the field if it's not applicable to the
	305	* requested pinmux type.
	306	*/
19bb7fe3	307	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145	308	if (!in_range) {
e3c47051 LP	309	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
	310	/* Functions are allowed to modify all
	311	* fields.
	312	*/
	313	in_range = 1;
	314	} else if (pinmux_type != PINMUX_TYPE_GPIO) {
	315	/* Input/output types can only modify fields
	316	* that correspond to their respective ranges.
50dd3145	317	*/
4aeacd5b	318	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	319
	320	/*
	321	* special case pass through for fixed
	322	* input-only or output-only pins without
	323	* function enum register association.
	324	*/
	325	if (in_range && enum_id == range->force)
	326	continue;
50dd3145	327	}
e3c47051	328	/* GPIOs are only allowed to modify function fields. */
42eed42b MD	329	}
42eed42b MD	330
2967dab1 MD	331	if (!in_range)
	332	continue;
	333
b705c054 LP	334	ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
	335	if (ret < 0)
	336	return ret;
2967dab1	337
861601de	338	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	339	}
	340
	341	return 0;
2967dab1 MD	342	}
2967dab1 MD	343
fe1c9a82 LP	344	#ifdef CONFIG_OF
	345	static const struct of_device_id sh_pfc_of_table[] = {
	346	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	347	{
	348	.compatible = "renesas,pfc-r8a73a4",
	349	.data = &r8a73a4_pinmux_info,
	350	},
	351	#endif
	352	#ifdef CONFIG_PINCTRL_PFC_R8A7740
	353	{
	354	.compatible = "renesas,pfc-r8a7740",
	355	.data = &r8a7740_pinmux_info,
	356	},
	357	#endif
	358	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	359	{
	360	.compatible = "renesas,pfc-r8a7778",
	361	.data = &r8a7778_pinmux_info,
	362	},
	363	#endif
	364	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	365	{
	366	.compatible = "renesas,pfc-r8a7779",
	367	.data = &r8a7779_pinmux_info,
	368	},
	369	#endif
	370	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	371	{
	372	.compatible = "renesas,pfc-r8a7790",
	373	.data = &r8a7790_pinmux_info,
	374	},
	375	#endif
	376	#ifdef CONFIG_PINCTRL_PFC_SH7372
	377	{
	378	.compatible = "renesas,pfc-sh7372",
	379	.data = &sh7372_pinmux_info,
	380	},
	381	#endif
	382	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	383	{
	384	.compatible = "renesas,pfc-sh73a0",
	385	.data = &sh73a0_pinmux_info,
	386	},
	387	#endif
	388	{ },
	389	};
	390	MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
	391	#endif
	392
c6193eac	393	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	394	{
fe1c9a82 LP	395	const struct platform_device_id *platid = platform_get_device_id(pdev);
	396	#ifdef CONFIG_OF
	397	struct device_node *np = pdev->dev.of_node;
	398	#endif
cd3c1bee	399	const struct sh_pfc_soc_info *info;
c6193eac	400	struct sh_pfc *pfc;
0fc64cc0	401	int ret;
2967dab1	402
fe1c9a82 LP	403	#ifdef CONFIG_OF
	404	if (np)
	405	info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
	406	else
	407	#endif
	408	info = platid ? (const void *)platid->driver_data : NULL;
	409
19bb7fe3	410	if (info == NULL)
c6193eac	411	return -ENODEV;
2967dab1	412
8c43fcc7	413	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	414	if (pfc == NULL)
c6193eac LP	415	return -ENOMEM;
d4e62d00	416
19bb7fe3	417	pfc->info = info;
c6193eac LP	418	pfc->dev = &pdev->dev;
c6193eac LP	419
973931ae	420	ret = sh_pfc_ioremap(pfc, pdev);
c6193eac	421	if (unlikely(ret < 0))
b0e10211 MD	422	return ret;
b0e10211 MD	423
c6193eac	424	spin_lock_init(&pfc->lock);
69edbba0	425
0c151062 LP	426	if (info->ops && info->ops->init) {
	427	ret = info->ops->init(pfc);
	428	if (ret < 0)
	429	return ret;
	430	}
	431
ca5481c6	432	pinctrl_provide_dummies();
b0e10211	433
ca5481c6 PM	434	/*
	435	* Initialize pinctrl bindings first
	436	*/
c6193eac	437	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	438	if (unlikely(ret != 0))
0c151062	439	goto error;
ca5481c6	440
6f6a4a68	441	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	442	/*
	443	* Then the GPIO chip
	444	*/
c6193eac	445	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	446	if (unlikely(ret != 0)) {
ca5481c6 PM	447	/*
	448	* If the GPIO chip fails to come up we still leave the
	449	* PFC state as it is, given that there are already
	450	* extant users of it that have succeeded by this point.
	451	*/
9a643c9a	452	dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
b3c185a7	453	}
6f6a4a68	454	#endif
b72421d8	455
c6193eac LP	456	platform_set_drvdata(pdev, pfc);
c6193eac LP	457
9a643c9a	458	dev_info(pfc->dev, "%s support registered\n", info->name);
ca5481c6	459
b3c185a7	460	return 0;
0c151062 LP	461
	462	error:
	463	if (info->ops && info->ops->exit)
	464	info->ops->exit(pfc);
	465	return ret;
b72421d8	466	}
6f6a4a68	467
c6193eac LP	468	static int sh_pfc_remove(struct platform_device *pdev)
	469	{
	470	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	471
	472	#ifdef CONFIG_GPIO_SH_PFC
	473	sh_pfc_unregister_gpiochip(pfc);
	474	#endif
	475	sh_pfc_unregister_pinctrl(pfc);
	476
0c151062 LP	477	if (pfc->info->ops && pfc->info->ops->exit)
	478	pfc->info->ops->exit(pfc);
	479
c6193eac LP	480	platform_set_drvdata(pdev, NULL);
	481
	482	return 0;
	483	}
	484
	485	static const struct platform_device_id sh_pfc_id_table[] = {
c98f6c21 MD	486	#ifdef CONFIG_PINCTRL_PFC_R8A73A4
	487	{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
	488	#endif
d5b1521a LP	489	#ifdef CONFIG_PINCTRL_PFC_R8A7740
d5b1521a LP	490	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
881023d2	491	#endif
87f8c988 KM	492	#ifdef CONFIG_PINCTRL_PFC_R8A7778
	493	{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
	494	#endif
881023d2 LP	495	#ifdef CONFIG_PINCTRL_PFC_R8A7779
881023d2 LP	496	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
6e5469a6	497	#endif
58c229e1 KM	498	#ifdef CONFIG_PINCTRL_PFC_R8A7790
	499	{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
	500	#endif
ccda552e LP	501	#ifdef CONFIG_PINCTRL_PFC_SH7203
	502	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	503	#endif
a8d42fc4 LP	504	#ifdef CONFIG_PINCTRL_PFC_SH7264
	505	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	506	#endif
f5e811f2 LP	507	#ifdef CONFIG_PINCTRL_PFC_SH7269
	508	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	509	#endif
6e5469a6 LP	510	#ifdef CONFIG_PINCTRL_PFC_SH7372
6e5469a6 LP	511	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
5d5166dc LP	512	#endif
	513	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	514	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
74cad605 LP	515	#endif
	516	#ifdef CONFIG_PINCTRL_PFC_SH7720
	517	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	518	#endif
	519	#ifdef CONFIG_PINCTRL_PFC_SH7722
	520	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	521	#endif
	522	#ifdef CONFIG_PINCTRL_PFC_SH7723
	523	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	524	#endif
	525	#ifdef CONFIG_PINCTRL_PFC_SH7724
	526	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	527	#endif
	528	#ifdef CONFIG_PINCTRL_PFC_SH7734
	529	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	530	#endif
	531	#ifdef CONFIG_PINCTRL_PFC_SH7757
	532	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	533	#endif
	534	#ifdef CONFIG_PINCTRL_PFC_SH7785
	535	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	536	#endif
	537	#ifdef CONFIG_PINCTRL_PFC_SH7786
	538	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	539	#endif
	540	#ifdef CONFIG_PINCTRL_PFC_SHX3
	541	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	542	#endif
c6193eac LP	543	{ "sh-pfc", 0 },
	544	{ },
	545	};
	546	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	547
	548	static struct platform_driver sh_pfc_driver = {
	549	.probe = sh_pfc_probe,
	550	.remove = sh_pfc_remove,
	551	.id_table = sh_pfc_id_table,
	552	.driver = {
	553	.name = DRV_NAME,
	554	.owner = THIS_MODULE,
fe1c9a82	555	.of_match_table = of_match_ptr(sh_pfc_of_table),
c6193eac LP	556	},
	557	};
	558
40ee6fce LP	559	static int __init sh_pfc_init(void)
	560	{
	561	return platform_driver_register(&sh_pfc_driver);
c6193eac	562	}
40ee6fce	563	postcore_initcall(sh_pfc_init);
c6193eac LP	564
	565	static void __exit sh_pfc_exit(void)
	566	{
	567	platform_driver_unregister(&sh_pfc_driver);
	568	}
	569	module_exit(sh_pfc_exit);
	570
6f6a4a68 LP	571	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	572	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	573	MODULE_LICENSE("GPL v2");