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VFIO: platform: clear IRQ_NOAUTOEN when de-assigning the IRQ
[deliverable/linux.git] / drivers / pinctrl / sh-pfc / pfc-r8a7790.c
CommitLineData
58c229e1
KM		 1/*
2 * R8A7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
12 * License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
1627769b 23
58c229e1 24#include <linux/kernel.h>
1627769b
LP		 25#include <linux/platform_data/gpio-rcar.h>
26
58c229e1
KM		 27#include "core.h"
28#include "sh_pfc.h"
29
b5599df2
LP		 30#define PORT_GP_30(bank, fn, sfx) \
31 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
32 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
33 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
34 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
35 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
36 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
37 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
38 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
39 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
40 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
41 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
42 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
43 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
44 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
45 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx)
46
ed3e2604
LP		 47#define CPU_ALL_PORT(fn, sfx) \
48 PORT_GP_32(0, fn, sfx), \
b5599df2
LP		 49 PORT_GP_30(1, fn, sfx), \
50 PORT_GP_30(2, fn, sfx), \
ed3e2604
LP		 51 PORT_GP_32(3, fn, sfx), \
52 PORT_GP_32(4, fn, sfx), \
53 PORT_GP_32(5, fn, sfx)
54
58c229e1
KM		 55enum {
56 PINMUX_RESERVED = 0,
57
58 PINMUX_DATA_BEGIN,
59 GP_ALL(DATA),
60 PINMUX_DATA_END,
61
58c229e1
KM		 62 PINMUX_FUNCTION_BEGIN,
63 GP_ALL(FN),
64
65 /* GPSR0 */
66 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
67 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
68 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
69 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
70 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
71 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
72 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
73 FN_IP3_14_12, FN_IP3_17_15,
74
75 /* GPSR1 */
76 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
77 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
78 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
79 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
80 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
81 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
82 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
83
84 /* GPSR2 */
85 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
86 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
87 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
88 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
89 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
90 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
91 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
92
93 /* GPSR3 */
94 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
95 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
96 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
97 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
98 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
99 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
100 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
101
102 /* GPSR4 */
103 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
104 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
105 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
106 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
107 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
108 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
109 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
110 FN_IP14_15_12, FN_IP14_18_16,
111
112 /* GPSR5 */
113 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
114 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
115 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
116 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
117 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
118 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
119 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
120
121 /* IPSR0 */
122 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
123 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
124 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
125 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
126 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
127 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
128 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
129 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
130 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
c4721249
SK		 131 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
132 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
05bcb07b 133 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
9f2edd41 134 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
58c229e1
KM		 135 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
136
137 /* IPSR1 */
9f2edd41 138 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
58c229e1 139 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
9f2edd41 140 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
58c229e1 141 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
9f2edd41 142 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
58c229e1
KM		 143 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
144 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
145 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
146 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
147 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
148 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
149 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
150 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
151 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
152 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
153
154 /* IPSR2 */
155 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
156 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
157 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
158 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
159 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
160 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 161 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1 162 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 163 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 164 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
165 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
166
167 /* IPSR3 */
168 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
169 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
170 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
171 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
172 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
173 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
174 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
175 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
176 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
177 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
178 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
179 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
180 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
181
182 /* IPSR4 */
183 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
184 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
185 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
186 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
187 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
188 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
189 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
190 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
191 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
192 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
193 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
194 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
195 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
196 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
197 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
198
199 /* IPSR5 */
200 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
201 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 202 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
203 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
58c229e1 204 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
c4721249
SK		 205 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
206 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
58c229e1
KM		 207 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
208 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
209 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
210 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
211 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
212 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
213 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
214 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
215 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
216 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
217 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
218 FN_SSI_WS78_B,
219
220 /* IPSR6 */
221 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
222 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
223 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
224 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
225 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
226 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
227 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
228 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
9f2edd41 229 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
c4721249 230 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
9f2edd41 231 FN_I2C2_SCL_E, FN_ETH_RX_ER,
58c229e1 232 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
9f2edd41 233 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
58c229e1
KM		 234 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
235 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
9f2edd41 236 FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1 237 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
9f2edd41 238 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
58c229e1 239 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
9f2edd41 240 FN_ETH_REF_CLK, FN_HCTS0_N_E,
58c229e1
KM		 241 FN_STP_IVCXO27_1_B, FN_HRX0_F,
242
243 /* IPSR7 */
9f2edd41 244 FN_ETH_MDIO, FN_HRTS0_N_E,
58c229e1 245 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
14da999b 246 FN_HTX0_F, FN_BPFCLK_G,
9f2edd41
SK		 247 FN_ETH_TX_EN, FN_SIM0_CLK_C,
248 FN_HRTS0_N_F, FN_ETH_MAGIC,
249 FN_SIM0_RST_C, FN_ETH_TXD0,
58c229e1 250 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
9f2edd41 251 FN_ETH_MDC, FN_STP_ISD_1_B,
58c229e1
KM		 252 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
253 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
254 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
255 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
256 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
f0681209 257 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
58c229e1 258 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
9f2edd41 259 FN_ATACS00_N, FN_AVB_RXD1,
58c229e1 260 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
58c229e1
KM		 261
262 /* IPSR8 */
263 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
9f2edd41 264 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
58c229e1
KM		 265 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
266 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
267 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
268 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
9f2edd41
SK		 269 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
270 FN_VI1_CLK, FN_AVB_RX_DV,
271 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
272 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
273 FN_SCIFA1_RXD_D, FN_AVB_MDC,
58c229e1 274 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
9f2edd41 275 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
58c229e1 276 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 277 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
58c229e1
KM		 278 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
279 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
280 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
281
282 /* IPSR9 */
283 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
284 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
285 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
286 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
287 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 288 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
289 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
58c229e1 290 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 291 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
292 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
9f2edd41
SK		 293 FN_AVB_TX_EN, FN_SD1_CMD,
294 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
295 FN_SD1_DAT0, FN_AVB_TX_CLK,
58c229e1 296 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
9f2edd41
SK		 297 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
298 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
299 FN_SD1_DAT3, FN_AVB_RXD0,
58c229e1
KM		 300 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
301 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
c4721249 302 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
58c229e1
KM		 303 FN_VI3_CLK_B,
304
305 /* IPSR10 */
306 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 307 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 308 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
309 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
310 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
311 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
312 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
313 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
314 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
315 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
14da999b 316 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
58c229e1
KM		 317 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
318 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
14da999b 319 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
58c229e1
KM		 320 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
321 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
322 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
323 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
324 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
325 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
326 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
327 FN_GLO_I0_B, FN_VI3_DATA6_B,
328
329 /* IPSR11 */
330 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
331 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
332 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
333 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
334 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
335 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
336 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
337 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
338 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
339 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b
SK		 340 FN_FMIN_E, FN_FMIN_F,
341 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
c4721249 342 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
7d2b2854 343 FN_I2C2_SDA_B, FN_MLB_DAT,
58c229e1 344 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 345 FN_SSI_SCK0129, FN_CAN_CLK_B,
58c229e1
KM		 346 FN_MOUT0,
347
348 /* IPSR12 */
349 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
350 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
351 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
352 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
353 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
354 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
355 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
356 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
357 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
358 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
359 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
360 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
361 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
362 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
363 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
364 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
365 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
366 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
367 FN_CAN_DEBUGOUT4,
368
369 /* IPSR13 */
370 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
371 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
14da999b 372 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
58c229e1 373 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 374 FN_BPFCLK_F, FN_SSI_WS6,
58c229e1
KM		 375 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
376 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
14da999b 377 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 378 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
379 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
380 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
381 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
382 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
383 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
384 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
14da999b
SK		 385 FN_BPFCLK_E, FN_SSI_SDATA7_B,
386 FN_FMIN_G, FN_SSI_SDATA8,
58c229e1
KM		 387 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
388 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
389 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
390 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
391 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
392
393 /* IPSR14 */
394 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
395 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
396 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
c4721249
SK		 397 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
398 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
58c229e1
KM		 399 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
400 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
401 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
c4721249 402 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
bcec7475 403 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 404 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
405 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
406 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
407 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
408 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
409 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
bcec7475 410 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 411 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
412 FN_HRTS0_N_C,
413
414 /* IPSR15 */
1ddb66cd 415 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1 416 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
1ddb66cd
SK		 417 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
418 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 419 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
58c229e1
KM		 420 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
421 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
422 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
423 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
424 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
425 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
426 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
5de880dd 427 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
58c229e1
KM		 428 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
429 FN_DU2_DG6, FN_LCDOUT14,
430
431 /* IPSR16 */
432 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
433 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
434 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 435 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
58c229e1
KM		 436 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
437 FN_TCLK1_B,
438
439 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
440 FN_SEL_SCIF1_4,
441 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
442 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
443 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
444 FN_SEL_SCIFB1_4,
445 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
446 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
447 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
448 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
449 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
450 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
451 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
452 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
453 FN_SEL_VI3_0, FN_SEL_VI3_1,
454 FN_SEL_VI2_0, FN_SEL_VI2_1,
455 FN_SEL_VI1_0, FN_SEL_VI1_1,
456 FN_SEL_VI0_0, FN_SEL_VI0_1,
457 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
458 FN_SEL_LBS_0, FN_SEL_LBS_1,
459 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
460 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
461 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
462
463 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
464 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
465 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
466 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
467 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
468 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
469 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
1ddb66cd 470 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 471 FN_SEL_ADI_0, FN_SEL_ADI_1,
472 FN_SEL_SSP_0, FN_SEL_SSP_1,
473 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
474 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
475 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
476 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
477 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
58c229e1
KM		 478 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
479 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
480
481 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
482 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
483 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
484 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
485 FN_SEL_IIC2_4,
486 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
487 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
488 FN_SEL_I2C2_4,
489 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
490 PINMUX_FUNCTION_END,
491
492 PINMUX_MARK_BEGIN,
493
494 VI1_DATA7_VI1_B7_MARK,
495
496 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
497 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
498 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
499
500 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
501 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
502 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
503 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
504 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
505 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
506 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
507 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
508 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
c4721249
SK		 509 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
510 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
05bcb07b 511 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
9f2edd41 512 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
58c229e1
KM		 513 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
514
9f2edd41 515 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
58c229e1 516 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
9f2edd41 517 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
58c229e1 518 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
9f2edd41 519 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
58c229e1
KM		 520 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
521 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
522 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
523 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
524 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
525 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
526 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
527 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
528 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
529 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
530
531 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
532 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
533 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
534 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
535 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
536 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
1ddb66cd 537 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
58c229e1 538 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
1ddb66cd 539 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
58c229e1
KM		 540 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
541 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
542
543 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
544 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
545 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
546 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
547 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
548 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
549 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
550 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
551 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
552 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
553 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
554 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
555 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
556
557 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
558 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
559 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
560 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
561 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
562 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
563 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
564 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
565 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
566 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
567 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
568 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
569 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
570 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
571 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
572
573 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
574 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
575 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
c4721249
SK		 576 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
577 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
58c229e1 578 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
c4721249
SK		 579 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
580 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
58c229e1
KM		 581 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
582 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
583 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
584 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
585 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
586 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
587 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
588 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
589 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
590 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
591 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
592 SSI_WS78_B_MARK,
593
594 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
595 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
596 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
597 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
598 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
599 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
600 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
601 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
9f2edd41 602 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
c4721249 603 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
9f2edd41 604 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
58c229e1 605 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
9f2edd41 606 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
58c229e1
KM		 607 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
608 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
9f2edd41 609 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
58c229e1 610 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
9f2edd41 611 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
58c229e1 612 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
9f2edd41 613 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
58c229e1
KM		 614 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
615
9f2edd41 616 ETH_MDIO_MARK, HRTS0_N_E_MARK,
58c229e1 617 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
14da999b 618 HTX0_F_MARK, BPFCLK_G_MARK,
9f2edd41
SK		 619 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
620 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
621 SIM0_RST_C_MARK, ETH_TXD0_MARK,
58c229e1 622 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
9f2edd41 623 ETH_MDC_MARK, STP_ISD_1_B_MARK,
58c229e1
KM		 624 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
625 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
626 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
627 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
628 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
f0681209 629 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
58c229e1 630 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
9f2edd41 631 ATACS00_N_MARK, AVB_RXD1_MARK,
58c229e1 632 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
58c229e1
KM		 633
634 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
9f2edd41 635 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
58c229e1
KM		 636 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
637 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
638 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
639 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
9f2edd41
SK		 640 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
641 VI1_CLK_MARK, AVB_RX_DV_MARK,
642 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
643 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
644 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
58c229e1 645 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
9f2edd41 646 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
58c229e1 647 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
9f2edd41 648 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
58c229e1
KM		 649 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
650 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
651 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
652
653 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
654 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
655 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
656 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
657 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
c4721249
SK		 658 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
659 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
58c229e1 660 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
c4721249
SK		 661 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
662 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
9f2edd41
SK		 663 AVB_TX_EN_MARK, SD1_CMD_MARK,
664 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
665 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
58c229e1 666 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
9f2edd41
SK		 667 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
668 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
669 SD1_DAT3_MARK, AVB_RXD0_MARK,
58c229e1
KM		 670 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
671 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
c4721249 672 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
58c229e1
KM		 673 VI3_CLK_B_MARK,
674
675 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
c4721249 676 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
58c229e1
KM		 677 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
678 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
679 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
680 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
681 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
682 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
683 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
684 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
14da999b 685 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
58c229e1
KM		 686 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
687 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
14da999b 688 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
58c229e1
KM		 689 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
690 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
691 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
692 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
693 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
694 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
695 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
696 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
697
698 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
699 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
700 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
701 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
702 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
703 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
704 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
705 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
706 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
707 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
14da999b
SK		 708 FMIN_E_MARK, FMIN_F_MARK,
709 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
c4721249 710 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
7d2b2854 711 I2C2_SDA_B_MARK, MLB_DAT_MARK,
58c229e1 712 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
14da999b 713 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
58c229e1
KM		 714 MOUT0_MARK,
715
716 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
717 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
718 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
719 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
720 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
721 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
722 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
723 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
724 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
725 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
726 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
727 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
728 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
729 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
730 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
731 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
732 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
733 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
734 CAN_DEBUGOUT4_MARK,
735
736 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
737 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
14da999b 738 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
58c229e1 739 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
14da999b 740 BPFCLK_F_MARK, SSI_WS6_MARK,
58c229e1
KM		 741 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
742 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
14da999b 743 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
58c229e1
KM		 744 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
745 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
746 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
747 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
748 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
749 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
750 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
14da999b
SK		 751 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
752 FMIN_G_MARK, SSI_SDATA8_MARK,
58c229e1
KM		 753 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
754 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
755 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
756 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
757 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
758
759 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
760 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
761 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
c4721249
SK		 762 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
763 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
58c229e1
KM		 764 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
765 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
766 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
c4721249 767 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
bcec7475 768 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
58c229e1
KM		 769 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
770 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
771 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
772 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
773 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
774 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
bcec7475 775 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
58c229e1
KM		 776 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
777 HRTS0_N_C_MARK,
778
1ddb66cd 779 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
58c229e1 780 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
1ddb66cd
SK		 781 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
782 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
c4721249 783 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
58c229e1
KM		 784 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
785 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
786 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
787 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
788 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
789 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
790 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
5de880dd 791 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
58c229e1
KM		 792 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
793 DU2_DG6_MARK, LCDOUT14_MARK,
794
795 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
796 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
797 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
5de880dd 798 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
58c229e1
KM		 799 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
800 TCLK1_B_MARK,
f6aaaac9 801
a16b81dc
WS		 802 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
803 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
58c229e1
KM		 804 PINMUX_MARK_END,
805};
806
533743dc 807static const u16 pinmux_data[] = {
58c229e1
KM		 808 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
809
810 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
811 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
812 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
813 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
814 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
815 PINMUX_DATA(AVS1_MARK, FN_AVS1),
816 PINMUX_DATA(AVS2_MARK, FN_AVS2),
817 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
818 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
819
820 PINMUX_IPSR_DATA(IP0_2_0, D0),
821 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
822 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
823 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
824 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
825 PINMUX_IPSR_DATA(IP0_5_3, D1),
826 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
827 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
828 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
829 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
830 PINMUX_IPSR_DATA(IP0_8_6, D2),
831 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
832 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
833 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
834 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
835 PINMUX_IPSR_DATA(IP0_11_9, D3),
836 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
837 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
838 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
839 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
840 PINMUX_IPSR_DATA(IP0_15_12, D4),
841 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
842 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
843 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
844 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
845 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
846 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
847 PINMUX_IPSR_DATA(IP0_19_16, D5),
848 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
849 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
850 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
851 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
852 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
853 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
854 PINMUX_IPSR_DATA(IP0_22_20, D6),
c4721249 855 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
58c229e1
KM		 856 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
857 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
858 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
c4721249 859 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
58c229e1
KM		 860 PINMUX_IPSR_DATA(IP0_26_23, D7),
861 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
c4721249 862 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
58c229e1
KM		 863 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
864 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
865 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
c4721249 866 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
05bcb07b 867 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
58c229e1
KM		 868 PINMUX_IPSR_DATA(IP0_30_27, D8),
869 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
58c229e1
KM		 871 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
872 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
873 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
874
875 PINMUX_IPSR_DATA(IP1_3_0, D9),
876 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
58c229e1
KM		 878 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
880 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
881 PINMUX_IPSR_DATA(IP1_7_4, D10),
882 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
883 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
58c229e1
KM		 884 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
886 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
887 PINMUX_IPSR_DATA(IP1_11_8, D11),
888 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
889 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
58c229e1
KM		 890 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
891 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
892 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
893 PINMUX_IPSR_DATA(IP1_14_12, D12),
894 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
895 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
896 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
897 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
898 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
899 PINMUX_IPSR_DATA(IP1_17_15, D13),
0a664e3d 900 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
58c229e1
KM		 901 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
902 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
903 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
904 PINMUX_IPSR_DATA(IP1_21_18, D14),
905 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
906 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
907 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
908 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
909 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
910 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
911 PINMUX_IPSR_DATA(IP1_25_22, D15),
912 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
913 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
914 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
915 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
916 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
917 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
918 PINMUX_IPSR_DATA(IP1_27_26, A0),
919 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
920 PINMUX_IPSR_DATA(IP1_29_28, A1),
921 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
922
923 PINMUX_IPSR_DATA(IP2_2_0, A2),
924 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
925 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
926 PINMUX_IPSR_DATA(IP2_5_3, A3),
927 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
928 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
929 PINMUX_IPSR_DATA(IP2_8_6, A4),
930 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
931 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
932 PINMUX_IPSR_DATA(IP2_11_9, A5),
933 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
935 PINMUX_IPSR_DATA(IP2_14_12, A6),
936 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
937 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
938 PINMUX_IPSR_DATA(IP2_17_15, A7),
939 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
940 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
941 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
942 PINMUX_IPSR_DATA(IP2_21_18, A8),
943 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
944 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
945 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
946 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
947 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
1ddb66cd 948 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
58c229e1
KM		 949 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
950 PINMUX_IPSR_DATA(IP2_25_22, A9),
951 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
952 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
953 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
954 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
955 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
1ddb66cd 956 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
58c229e1
KM		 957 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
958 PINMUX_IPSR_DATA(IP2_28_26, A10),
959 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
960 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
961 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
962 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
963 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
964
965 PINMUX_IPSR_DATA(IP3_3_0, A11),
966 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
967 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
968 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
969 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
970 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
0a664e3d 971 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
58c229e1
KM		 972 PINMUX_IPSR_DATA(IP3_7_4, A12),
973 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
974 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
975 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
976 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
977 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
0a664e3d 978 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
58c229e1
KM		 979 PINMUX_IPSR_DATA(IP3_11_8, A13),
980 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
981 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
982 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
983 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
984 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
985 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
0a664e3d 986 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
58c229e1
KM		 987 PINMUX_IPSR_DATA(IP3_14_12, A14),
988 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
989 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
990 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
991 PINMUX_IPSR_DATA(IP3_17_15, A15),
992 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
993 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
994 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
995 PINMUX_IPSR_DATA(IP3_19_18, A16),
996 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
997 PINMUX_IPSR_DATA(IP3_22_20, A17),
998 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
999 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1000 PINMUX_IPSR_DATA(IP3_25_23, A18),
1001 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1002 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1003 PINMUX_IPSR_DATA(IP3_28_26, A19),
1004 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1005 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1006 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1007 PINMUX_IPSR_DATA(IP3_31_29, A20),
1008 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1009 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
1010 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1011 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1012
1013 PINMUX_IPSR_DATA(IP4_2_0, A21),
1014 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1017 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1018 PINMUX_IPSR_DATA(IP4_5_3, A22),
1019 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1022 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1023 PINMUX_IPSR_DATA(IP4_8_6, A23),
1024 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1025 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1026 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1027 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1028 PINMUX_IPSR_DATA(IP4_11_9, A24),
1029 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1030 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1032 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1033 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1034 PINMUX_IPSR_DATA(IP4_14_12, A25),
1035 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1037 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1039 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1040 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1041 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1042 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1043 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1044 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1045 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1046 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1047 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1048 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1049 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1050 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1051 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1052 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1053 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1055 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1056 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1057 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1058 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1059 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1060 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1061 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1063 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1064 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1065 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1066 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1067 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1068 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1069 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1070 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1071
1072 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1073 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1074 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1076 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1077 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
0a664e3d 1078 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
58c229e1
KM		 1079 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1080 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
c4721249 1082 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
58c229e1
KM		 1083 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1084 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
c4721249 1085 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
58c229e1
KM		 1086 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1087 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1089 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1090 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1091 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1092 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
c4721249 1093 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
58c229e1 1094 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
c4721249 1095 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
58c229e1
KM		 1096 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1097 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1098 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1099 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1100 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1101 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1102 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1103 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1104 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1105 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1106 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1107 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1108 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1109 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1110 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1111 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1113 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1114 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1115 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1117 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1118 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1120 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1121 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1122 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1123 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1124 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
0a664e3d 1125 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
58c229e1
KM		 1126 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1127 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1128 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1129 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1130 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1132 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1133 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1134 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1135 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1136 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1137 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1138
1139 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1140 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1141 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1142 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1143 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1144 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1145 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1146 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1147 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1149 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1150 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1151 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1152 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1153 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1154 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1155 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1156 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1157 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1160 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1161 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1162 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1164 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1166 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
58c229e1
KM		 1167 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
c4721249
SK		 1170 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1171 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
58c229e1 1172 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
58c229e1
KM		 1173 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1174 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
c4721249
SK		 1176 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1177 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
58c229e1 1178 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
58c229e1
KM		 1179 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1180 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1182 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1183 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1184 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
58c229e1
KM		 1185 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1186 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1187 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1188 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1189 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1190 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1191 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
58c229e1
KM		 1192 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1193 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1195 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1196 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
58c229e1
KM		 1197 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1198 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1200
1201 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
58c229e1
KM		 1202 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1203 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1205 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
0a664e3d
SK		 1206 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
58c229e1 1208 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
58c229e1
KM		 1209 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1211 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
58c229e1
KM		 1212 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1213 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
58c229e1
KM		 1214 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1215 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1217 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
58c229e1
KM		 1218 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1219 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1220 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1221 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1222 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1223 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1225 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1226 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1227 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1228 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1229 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1230 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1231 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1232 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1233 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1234 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1235 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1236 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
f0681209 1237 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
58c229e1
KM		 1238 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1239 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1240 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1241 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1242 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
58c229e1
KM		 1243 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1244 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1245 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
58c229e1
KM		 1246
1247 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1248 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1249 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
58c229e1
KM		 1250 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1251 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1252 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1253 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1254 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1255 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1256 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1257 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1258 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1259 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1260 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1261 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1263 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
58c229e1
KM		 1264 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1265 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
58c229e1
KM		 1266 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1267 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
58c229e1
KM		 1268 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1269 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1270 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
58c229e1
KM		 1271 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1273 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
58c229e1
KM		 1274 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1275 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1276 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
58c229e1
KM		 1277 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1278 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1279 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1280 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1282 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
58c229e1 1283 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
0a664e3d 1284 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
58c229e1
KM		 1285 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1286 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1287 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1288 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1289 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1290 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1291 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1292
1293 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1296 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1297 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1299 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1302 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1305 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1306 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1307 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1308 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1309 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
c4721249
SK		 1311 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1312 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
58c229e1
KM		 1313 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1314 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1315 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1316 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1317 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1319 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
c4721249
SK		 1320 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1321 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
58c229e1
KM		 1322 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1323 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1324 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
58c229e1
KM		 1325 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1326 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
58c229e1
KM		 1327 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1328 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1329 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
58c229e1
KM		 1330 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1331 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1332 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
58c229e1
KM		 1333 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1334 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1335 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
58c229e1
KM		 1336 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1337 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1338 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
58c229e1
KM		 1339 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1340 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1341 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1342 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1343 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1344 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
c4721249
SK		 1346 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1347 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
58c229e1
KM		 1348 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1350
1351 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1352 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1354 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
c4721249
SK		 1357 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1358 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
58c229e1
KM		 1359 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1360 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1361 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1367 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1368 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1376 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1377 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1378 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1381 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1382 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1385 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1386 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1387 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
58c229e1
KM		 1388 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1389 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1390 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1391 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1392 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1394 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1395 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1396 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
58c229e1
KM		 1397 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1402 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1403 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1404 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1405 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1406 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1407 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1408 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1410 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1411 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1412 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1413 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1414 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1415 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1417 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1418 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1419 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1420
1421 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1422 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1423 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1424 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1425 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1426 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1429 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1430 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1431 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1432 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1433 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1434 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1435 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1436 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1437 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1438 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1439 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1440 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1441 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1442 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1443 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1444 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1445 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1446 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1447 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1448 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1449 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1450 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1451 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1452 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1453 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1454 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1455 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1456 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1457 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1458 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
58c229e1 1459 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
58c229e1 1460 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
58c229e1 1461 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
c4721249
SK		 1462 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1463 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
58c229e1
KM		 1464 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1465 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1466 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
c4721249
SK		 1467 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1468 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
58c229e1 1469 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
58c229e1
KM		 1470 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1471 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1472 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
58c229e1
KM		 1473 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1474 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1475 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1476
1477 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1479 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1480 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1481 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1482 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1483 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1485 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1486 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1487 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
0a664e3d 1488 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
58c229e1
KM		 1489 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1490 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1491 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1492 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1493 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1494 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1495 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1498 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1499 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1500 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1501 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1502 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1503 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1504 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1505 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1506 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1507 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1508 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1509 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1510 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1511 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1512 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1513 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1514 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1515 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1516 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1517 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1518 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1519 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1520 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1521 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1522 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1523 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1524 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1525 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1526 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1527 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1528 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1529 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1530 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1531 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1532 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1533
1534 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1537 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1538 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1539 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1542 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
58c229e1
KM		 1543 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1544 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1545 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1546 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
58c229e1
KM		 1547 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1548 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1550 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1551 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1552 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1553 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1554 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
58c229e1
KM		 1555 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1556 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1557 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1558 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1559 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1560 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1562 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1563 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1564 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1565 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1566 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1568 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1569 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1570 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1571 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1572 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1573 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1575 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1576 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1577 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1578 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1579 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
58c229e1
KM		 1580 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1581 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
58c229e1
KM		 1582 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1583 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1586 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1587 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1588 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1589 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1590 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1591 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1592 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1593 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1594 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1595 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1596 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1597
1598 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1599 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1600 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1601 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1603 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1604 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1607 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1608 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1609 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1610 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
c4721249
SK		 1611 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1612 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
58c229e1
KM		 1613 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1614 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1616 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1617 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1618 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1619 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1620 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1621 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1622 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1623 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1624 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
0a664e3d 1625 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
58c229e1
KM		 1626 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1627 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
0a664e3d
SK		 1628 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1629 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
c4721249
SK		 1630 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
58c229e1
KM		 1632 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
bcec7475 1634 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
58c229e1
KM		 1635 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1636 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1637 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1638 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1639 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1640 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1641 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1642 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1643 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1644 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1645 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1647 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1648 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1649 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1650 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1651 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1652 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1653 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1654 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1655 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1656 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
bcec7475 1657 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
58c229e1
KM		 1658 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1659 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1660 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1661 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1662
1663 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1664 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1ddb66cd 1665 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
58c229e1
KM		 1666 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1667 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1668 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
0a664e3d 1669 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
58c229e1
KM		 1670 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1671 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1ddb66cd 1672 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
58c229e1
KM		 1673 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1674 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
c4721249
SK		 1675 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1676 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
58c229e1
KM		 1677 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1678 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1ddb66cd 1679 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
58c229e1
KM		 1680 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1681 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
c4721249
SK		 1682 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1683 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
58c229e1
KM		 1684 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1685 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1686 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1687 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
0a664e3d 1688 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
58c229e1
KM		 1689 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1690 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1691 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1692 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1693 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1694 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1695 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1696 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1697 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1698 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1699 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1700 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1701 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1702 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1703 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1704 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1705 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1706 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1707 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1708 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1709 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1710 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1711 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1712 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1713 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
5de880dd 1714 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
58c229e1
KM		 1715 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1716 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1717 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1718 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1719 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1720 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1721 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1722 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1723
1724 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1725 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1726 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1727 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1728 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1729 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1730 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1731 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1732 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1733 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1734 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1735 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1736 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
5de880dd 1737 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
58c229e1
KM		 1738 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1739 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1740 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1741 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
f6aaaac9 1742
a16b81dc
WS		 1743 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1744 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
35a493de
WS		 1745 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1746 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1747
a16b81dc
WS		 1748 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1749 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
f6aaaac9
GL		 1750 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1751 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
58c229e1
KM		 1752};
1753
f6aaaac9
GL		 1754/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1755#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1756#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1757#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1758
44a45b55 1759static const struct sh_pfc_pin pinmux_pins[] = {
58c229e1 1760 PINMUX_GPIO_GP_ALL(),
f6aaaac9
GL		 1761
1762 /* Pins not associated with a GPIO port */
35a493de
WS		 1763 SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1764 SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
f6aaaac9 1765 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
35a493de 1766 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
58c229e1
KM		 1767};
1768
fcec5b22
KM		 1769/* - AUDIO CLOCK ------------------------------------------------------------ */
1770static const unsigned int audio_clk_a_pins[] = {
1771 /* CLK A */
1772 RCAR_GP_PIN(4, 25),
1773};
1774static const unsigned int audio_clk_a_mux[] = {
1775 AUDIO_CLKA_MARK,
1776};
1777static const unsigned int audio_clk_b_pins[] = {
1778 /* CLK B */
1779 RCAR_GP_PIN(4, 26),
1780};
1781static const unsigned int audio_clk_b_mux[] = {
1782 AUDIO_CLKB_MARK,
1783};
1784static const unsigned int audio_clk_c_pins[] = {
1785 /* CLK C */
1786 RCAR_GP_PIN(5, 27),
1787};
1788static const unsigned int audio_clk_c_mux[] = {
1789 AUDIO_CLKC_MARK,
1790};
1791static const unsigned int audio_clkout_pins[] = {
1792 /* CLK OUT */
1793 RCAR_GP_PIN(5, 16),
1794};
1795static const unsigned int audio_clkout_mux[] = {
1796 AUDIO_CLKOUT_MARK,
1797};
1798static const unsigned int audio_clkout_b_pins[] = {
1799 /* CLK OUT B */
1800 RCAR_GP_PIN(0, 23),
1801};
1802static const unsigned int audio_clkout_b_mux[] = {
1803 AUDIO_CLKOUT_B_MARK,
1804};
1805static const unsigned int audio_clkout_c_pins[] = {
1806 /* CLK OUT C */
1807 RCAR_GP_PIN(5, 27),
1808};
1809static const unsigned int audio_clkout_c_mux[] = {
1810 AUDIO_CLKOUT_C_MARK,
1811};
1812static const unsigned int audio_clkout_d_pins[] = {
1813 /* CLK OUT D */
1814 RCAR_GP_PIN(5, 20),
1815};
1816static const unsigned int audio_clkout_d_mux[] = {
1817 AUDIO_CLKOUT_D_MARK,
1818};
19ef697d
SS		 1819/* - AVB -------------------------------------------------------------------- */
1820static const unsigned int avb_link_pins[] = {
1821 RCAR_GP_PIN(3, 11),
1822};
1823static const unsigned int avb_link_mux[] = {
1824 AVB_LINK_MARK,
1825};
1826static const unsigned int avb_magic_pins[] = {
1827 RCAR_GP_PIN(2, 14),
1828};
1829static const unsigned int avb_magic_mux[] = {
1830 AVB_MAGIC_MARK,
1831};
1832static const unsigned int avb_phy_int_pins[] = {
1833 RCAR_GP_PIN(2, 15),
1834};
1835static const unsigned int avb_phy_int_mux[] = {
1836 AVB_PHY_INT_MARK,
1837};
1838static const unsigned int avb_mdio_pins[] = {
1839 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1840};
1841static const unsigned int avb_mdio_mux[] = {
1842 AVB_MDC_MARK, AVB_MDIO_MARK,
1843};
1844static const unsigned int avb_mii_pins[] = {
1845 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1846 RCAR_GP_PIN(0, 11),
1847
1848 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1849 RCAR_GP_PIN(2, 2),
1850
1851 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1852 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1853 RCAR_GP_PIN(3, 12),
1854};
1855static const unsigned int avb_mii_mux[] = {
1856 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1857 AVB_TXD3_MARK,
1858
1859 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1860 AVB_RXD3_MARK,
1861
1862 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1863 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
1864 AVB_COL_MARK,
1865};
1866static const unsigned int avb_gmii_pins[] = {
1867 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1868 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1869 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1870
1871 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1872 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1873 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1874
1875 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1876 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1877 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1878 RCAR_GP_PIN(3, 12),
1879};
1880static const unsigned int avb_gmii_mux[] = {
1881 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1882 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1883 AVB_TXD6_MARK, AVB_TXD7_MARK,
1884
1885 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1886 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1887 AVB_RXD6_MARK, AVB_RXD7_MARK,
1888
1889 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1890 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1891 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1892 AVB_COL_MARK,
1893};
62783b71
LP		 1894/* - DU RGB ----------------------------------------------------------------- */
1895static const unsigned int du_rgb666_pins[] = {
1896 /* R[7:2], G[7:2], B[7:2] */
1897 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1898 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1899 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1900 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1901 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1902 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1903};
1904static const unsigned int du_rgb666_mux[] = {
1905 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1906 DU2_DR3_MARK, DU2_DR2_MARK,
1907 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1908 DU2_DG3_MARK, DU2_DG2_MARK,
1909 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1910 DU2_DB3_MARK, DU2_DB2_MARK,
1911};
1912static const unsigned int du_rgb888_pins[] = {
1913 /* R[7:0], G[7:0], B[7:0] */
1914 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1915 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1916 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1917 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1918 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1919 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1920 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1921 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1922};
1923static const unsigned int du_rgb888_mux[] = {
1924 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1925 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1926 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1927 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1928 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1929 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1930};
1931static const unsigned int du_clk_out_0_pins[] = {
1932 /* CLKOUT */
1933 RCAR_GP_PIN(5, 2),
1934};
1935static const unsigned int du_clk_out_0_mux[] = {
1936 DU0_DOTCLKOUT_MARK
1937};
1938static const unsigned int du_clk_out_1_pins[] = {
1939 /* CLKOUT */
1940 RCAR_GP_PIN(5, 3),
1941};
1942static const unsigned int du_clk_out_1_mux[] = {
1943 DU1_DOTCLKOUT_MARK
1944};
1945static const unsigned int du_sync_0_pins[] = {
1946 /* VSYNC, HSYNC, DISP */
1947 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1948};
1949static const unsigned int du_sync_0_mux[] = {
1950 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1951 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1952};
1953static const unsigned int du_sync_1_pins[] = {
1954 /* VSYNC, HSYNC, DISP */
1955 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1956};
1957static const unsigned int du_sync_1_mux[] = {
1958 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1959 DU2_DISP_MARK
1960};
1961static const unsigned int du_cde_pins[] = {
1962 /* CDE */
1963 RCAR_GP_PIN(5, 17),
1964};
1965static const unsigned int du_cde_mux[] = {
1966 DU2_CDE_MARK,
1967};
1968/* - DU0 -------------------------------------------------------------------- */
1969static const unsigned int du0_clk_in_pins[] = {
1970 /* CLKIN */
1971 RCAR_GP_PIN(5, 26),
1972};
1973static const unsigned int du0_clk_in_mux[] = {
1974 DU_DOTCLKIN0_MARK
1975};
1976/* - DU1 -------------------------------------------------------------------- */
1977static const unsigned int du1_clk_in_pins[] = {
1978 /* CLKIN */
1979 RCAR_GP_PIN(5, 27),
1980};
1981static const unsigned int du1_clk_in_mux[] = {
1982 DU_DOTCLKIN1_MARK,
1983};
1984/* - DU2 -------------------------------------------------------------------- */
1985static const unsigned int du2_clk_in_pins[] = {
1986 /* CLKIN */
1987 RCAR_GP_PIN(5, 28),
1988};
1989static const unsigned int du2_clk_in_mux[] = {
1990 DU_DOTCLKIN2_MARK,
1991};
1627769b
LP		 1992/* - ETH -------------------------------------------------------------------- */
1993static const unsigned int eth_link_pins[] = {
1994 /* LINK */
1995 RCAR_GP_PIN(2, 22),
1996};
1997static const unsigned int eth_link_mux[] = {
1998 ETH_LINK_MARK,
1999};
2000static const unsigned int eth_magic_pins[] = {
2001 /* MAGIC */
2002 RCAR_GP_PIN(2, 27),
2003};
2004static const unsigned int eth_magic_mux[] = {
2005 ETH_MAGIC_MARK,
2006};
2007static const unsigned int eth_mdio_pins[] = {
2008 /* MDC, MDIO */
2009 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2010};
2011static const unsigned int eth_mdio_mux[] = {
2012 ETH_MDC_MARK, ETH_MDIO_MARK,
2013};
2014static const unsigned int eth_rmii_pins[] = {
2015 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2016 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2017 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2018 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2019};
2020static const unsigned int eth_rmii_mux[] = {
2021 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2022 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2023};
fbd0ca3d
UH		 2024/* - HSCIF0 ----------------------------------------------------------------- */
2025static const unsigned int hscif0_data_pins[] = {
2026 /* RX, TX */
2027 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2028};
2029static const unsigned int hscif0_data_mux[] = {
2030 HRX0_MARK, HTX0_MARK,
2031};
2032static const unsigned int hscif0_clk_pins[] = {
2033 /* SCK */
2034 RCAR_GP_PIN(5, 7),
2035};
2036static const unsigned int hscif0_clk_mux[] = {
2037 HSCK0_MARK,
2038};
2039static const unsigned int hscif0_ctrl_pins[] = {
2040 /* RTS, CTS */
2041 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2042};
2043static const unsigned int hscif0_ctrl_mux[] = {
2044 HRTS0_N_MARK, HCTS0_N_MARK,
2045};
2046static const unsigned int hscif0_data_b_pins[] = {
2047 /* RX, TX */
2048 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2049};
2050static const unsigned int hscif0_data_b_mux[] = {
2051 HRX0_B_MARK, HTX0_B_MARK,
2052};
2053static const unsigned int hscif0_ctrl_b_pins[] = {
2054 /* RTS, CTS */
2055 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2056};
2057static const unsigned int hscif0_ctrl_b_mux[] = {
2058 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2059};
2060static const unsigned int hscif0_data_c_pins[] = {
2061 /* RX, TX */
2062 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2063};
2064static const unsigned int hscif0_data_c_mux[] = {
2065 HRX0_C_MARK, HTX0_C_MARK,
2066};
2067static const unsigned int hscif0_ctrl_c_pins[] = {
2068 /* RTS, CTS */
2069 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2070};
2071static const unsigned int hscif0_ctrl_c_mux[] = {
2072 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2073};
2074static const unsigned int hscif0_data_d_pins[] = {
2075 /* RX, TX */
2076 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2077};
2078static const unsigned int hscif0_data_d_mux[] = {
2079 HRX0_D_MARK, HTX0_D_MARK,
2080};
2081static const unsigned int hscif0_ctrl_d_pins[] = {
2082 /* RTS, CTS */
2083 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2084};
2085static const unsigned int hscif0_ctrl_d_mux[] = {
2086 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2087};
2088static const unsigned int hscif0_data_e_pins[] = {
2089 /* RX, TX */
2090 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2091};
2092static const unsigned int hscif0_data_e_mux[] = {
2093 HRX0_E_MARK, HTX0_E_MARK,
2094};
2095static const unsigned int hscif0_ctrl_e_pins[] = {
2096 /* RTS, CTS */
2097 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2098};
2099static const unsigned int hscif0_ctrl_e_mux[] = {
2100 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2101};
2102static const unsigned int hscif0_data_f_pins[] = {
2103 /* RX, TX */
2104 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2105};
2106static const unsigned int hscif0_data_f_mux[] = {
2107 HRX0_F_MARK, HTX0_F_MARK,
2108};
2109static const unsigned int hscif0_ctrl_f_pins[] = {
2110 /* RTS, CTS */
2111 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2112};
2113static const unsigned int hscif0_ctrl_f_mux[] = {
2114 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2115};
2116/* - HSCIF1 ----------------------------------------------------------------- */
2117static const unsigned int hscif1_data_pins[] = {
2118 /* RX, TX */
2119 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2120};
2121static const unsigned int hscif1_data_mux[] = {
2122 HRX1_MARK, HTX1_MARK,
2123};
2124static const unsigned int hscif1_clk_pins[] = {
2125 /* SCK */
2126 RCAR_GP_PIN(4, 27),
2127};
2128static const unsigned int hscif1_clk_mux[] = {
2129 HSCK1_MARK,
2130};
2131static const unsigned int hscif1_ctrl_pins[] = {
2132 /* RTS, CTS */
2133 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2134};
2135static const unsigned int hscif1_ctrl_mux[] = {
2136 HRTS1_N_MARK, HCTS1_N_MARK,
2137};
2138static const unsigned int hscif1_data_b_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2141};
2142static const unsigned int hscif1_data_b_mux[] = {
2143 HRX1_B_MARK, HTX1_B_MARK,
2144};
2145static const unsigned int hscif1_clk_b_pins[] = {
2146 /* SCK */
2147 RCAR_GP_PIN(1, 28),
2148};
2149static const unsigned int hscif1_clk_b_mux[] = {
2150 HSCK1_B_MARK,
2151};
2152static const unsigned int hscif1_ctrl_b_pins[] = {
2153 /* RTS, CTS */
2154 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2155};
2156static const unsigned int hscif1_ctrl_b_mux[] = {
2157 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2158};
35a493de
WS		 2159/* - I2C0 ------------------------------------------------------------------- */
2160static const unsigned int i2c0_pins[] = {
2161 /* SCL, SDA */
2162 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2163};
2164static const unsigned int i2c0_mux[] = {
2165 I2C0_SCL_MARK, I2C0_SDA_MARK,
2166};
70702bfc
UH		 2167/* - I2C1 ------------------------------------------------------------------- */
2168static const unsigned int i2c1_pins[] = {
2169 /* SCL, SDA */
2170 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2171};
2172static const unsigned int i2c1_mux[] = {
2173 I2C1_SCL_MARK, I2C1_SDA_MARK,
2174};
2175static const unsigned int i2c1_b_pins[] = {
2176 /* SCL, SDA */
2177 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2178};
2179static const unsigned int i2c1_b_mux[] = {
2180 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2181};
2182static const unsigned int i2c1_c_pins[] = {
2183 /* SCL, SDA */
2184 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2185};
2186static const unsigned int i2c1_c_mux[] = {
2187 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2188};
2189/* - I2C2 ------------------------------------------------------------------- */
2190static const unsigned int i2c2_pins[] = {
2191 /* SCL, SDA */
2192 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2193};
2194static const unsigned int i2c2_mux[] = {
2195 I2C2_SCL_MARK, I2C2_SDA_MARK,
2196};
2197static const unsigned int i2c2_b_pins[] = {
2198 /* SCL, SDA */
2199 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2200};
2201static const unsigned int i2c2_b_mux[] = {
2202 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2203};
2204static const unsigned int i2c2_c_pins[] = {
2205 /* SCL, SDA */
2206 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2207};
2208static const unsigned int i2c2_c_mux[] = {
2209 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2210};
2211static const unsigned int i2c2_d_pins[] = {
2212 /* SCL, SDA */
2213 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2214};
2215static const unsigned int i2c2_d_mux[] = {
2216 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2217};
2218static const unsigned int i2c2_e_pins[] = {
2219 /* SCL, SDA */
2220 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2221};
2222static const unsigned int i2c2_e_mux[] = {
2223 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2224};
f6aaaac9
GL		 2225/* - I2C3 ------------------------------------------------------------------- */
2226static const unsigned int i2c3_pins[] = {
2227 /* SCL, SDA */
2228 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2229};
2230static const unsigned int i2c3_mux[] = {
2231 I2C3_SCL_MARK, I2C3_SDA_MARK,
2232};
a16b81dc
WS		 2233/* - IIC0 (I2C4) ------------------------------------------------------------ */
2234static const unsigned int iic0_pins[] = {
2235 /* SCL, SDA */
2236 PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2237};
2238static const unsigned int iic0_mux[] = {
2239 IIC0_SCL_MARK, IIC0_SDA_MARK,
2240};
2241/* - IIC1 (I2C5) ------------------------------------------------------------ */
2242static const unsigned int iic1_pins[] = {
2243 /* SCL, SDA */
2244 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2245};
2246static const unsigned int iic1_mux[] = {
2247 IIC1_SCL_MARK, IIC1_SDA_MARK,
2248};
2249static const unsigned int iic1_b_pins[] = {
2250 /* SCL, SDA */
2251 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2252};
2253static const unsigned int iic1_b_mux[] = {
2254 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2255};
2256static const unsigned int iic1_c_pins[] = {
2257 /* SCL, SDA */
2258 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2259};
2260static const unsigned int iic1_c_mux[] = {
2261 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2262};
2263/* - IIC2 (I2C6) ------------------------------------------------------------ */
2264static const unsigned int iic2_pins[] = {
2265 /* SCL, SDA */
2266 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2267};
2268static const unsigned int iic2_mux[] = {
2269 IIC2_SCL_MARK, IIC2_SDA_MARK,
2270};
2271static const unsigned int iic2_b_pins[] = {
2272 /* SCL, SDA */
2273 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2274};
2275static const unsigned int iic2_b_mux[] = {
2276 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2277};
2278static const unsigned int iic2_c_pins[] = {
2279 /* SCL, SDA */
2280 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2281};
2282static const unsigned int iic2_c_mux[] = {
2283 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2284};
2285static const unsigned int iic2_d_pins[] = {
2286 /* SCL, SDA */
2287 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2288};
2289static const unsigned int iic2_d_mux[] = {
2290 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2291};
2292static const unsigned int iic2_e_pins[] = {
2293 /* SCL, SDA */
2294 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2295};
2296static const unsigned int iic2_e_mux[] = {
2297 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2298};
2299/* - IIC3 (I2C7) ------------------------------------------------------------ */
2300static const unsigned int iic3_pins[] = {
2301/* SCL, SDA */
2302 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2303};
2304static const unsigned int iic3_mux[] = {
2305 IIC3_SCL_MARK, IIC3_SDA_MARK,
2306};
457c11d3
LP		 2307/* - INTC ------------------------------------------------------------------- */
2308static const unsigned int intc_irq0_pins[] = {
2309 /* IRQ */
2310 RCAR_GP_PIN(1, 25),
2311};
2312static const unsigned int intc_irq0_mux[] = {
2313 IRQ0_MARK,
2314};
2315static const unsigned int intc_irq1_pins[] = {
2316 /* IRQ */
2317 RCAR_GP_PIN(1, 27),
2318};
2319static const unsigned int intc_irq1_mux[] = {
2320 IRQ1_MARK,
2321};
2322static const unsigned int intc_irq2_pins[] = {
2323 /* IRQ */
2324 RCAR_GP_PIN(1, 29),
2325};
2326static const unsigned int intc_irq2_mux[] = {
2327 IRQ2_MARK,
2328};
2329static const unsigned int intc_irq3_pins[] = {
2330 /* IRQ */
2331 RCAR_GP_PIN(1, 23),
2332};
2333static const unsigned int intc_irq3_mux[] = {
2334 IRQ3_MARK,
2335};
e29a4c3a
SS		 2336/* - MLB+ ------------------------------------------------------------------- */
2337static const unsigned int mlb_3pin_pins[] = {
2338 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2339};
2340static const unsigned int mlb_3pin_mux[] = {
2341 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2342};
457c11d3
LP		 2343/* - MMCIF0 ----------------------------------------------------------------- */
2344static const unsigned int mmc0_data1_pins[] = {
2345 /* D[0] */
2346 RCAR_GP_PIN(3, 18),
2347};
2348static const unsigned int mmc0_data1_mux[] = {
2349 MMC0_D0_MARK,
2350};
2351static const unsigned int mmc0_data4_pins[] = {
2352 /* D[0:3] */
2353 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2354 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2355};
2356static const unsigned int mmc0_data4_mux[] = {
2357 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2358};
2359static const unsigned int mmc0_data8_pins[] = {
2360 /* D[0:7] */
2361 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2362 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2363 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2364 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2365};
2366static const unsigned int mmc0_data8_mux[] = {
2367 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2368 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2369};
2370static const unsigned int mmc0_ctrl_pins[] = {
2371 /* CLK, CMD */
2372 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2373};
2374static const unsigned int mmc0_ctrl_mux[] = {
2375 MMC0_CLK_MARK, MMC0_CMD_MARK,
2376};
2377/* - MMCIF1 ----------------------------------------------------------------- */
2378static const unsigned int mmc1_data1_pins[] = {
2379 /* D[0] */
2380 RCAR_GP_PIN(3, 26),
2381};
2382static const unsigned int mmc1_data1_mux[] = {
2383 MMC1_D0_MARK,
2384};
2385static const unsigned int mmc1_data4_pins[] = {
2386 /* D[0:3] */
2387 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2388 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2389};
2390static const unsigned int mmc1_data4_mux[] = {
2391 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2392};
2393static const unsigned int mmc1_data8_pins[] = {
2394 /* D[0:7] */
2395 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2396 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2397 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2398 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2399};
2400static const unsigned int mmc1_data8_mux[] = {
2401 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2402 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2403};
2404static const unsigned int mmc1_ctrl_pins[] = {
2405 /* CLK, CMD */
2406 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2407};
2408static const unsigned int mmc1_ctrl_mux[] = {
2409 MMC1_CLK_MARK, MMC1_CMD_MARK,
2410};
4f47cc5e
KH		 2411/* - MSIOF0 ----------------------------------------------------------------- */
2412static const unsigned int msiof0_clk_pins[] = {
2413 /* SCK */
2414 RCAR_GP_PIN(5, 12),
2415};
2416static const unsigned int msiof0_clk_mux[] = {
2417 MSIOF0_SCK_MARK,
2418};
2419static const unsigned int msiof0_sync_pins[] = {
2420 /* SYNC */
2421 RCAR_GP_PIN(5, 13),
2422};
2423static const unsigned int msiof0_sync_mux[] = {
2424 MSIOF0_SYNC_MARK,
2425};
2426static const unsigned int msiof0_ss1_pins[] = {
2427 /* SS1 */
2428 RCAR_GP_PIN(5, 14),
2429};
2430static const unsigned int msiof0_ss1_mux[] = {
2431 MSIOF0_SS1_MARK,
2432};
2433static const unsigned int msiof0_ss2_pins[] = {
2434 /* SS2 */
2435 RCAR_GP_PIN(5, 16),
2436};
2437static const unsigned int msiof0_ss2_mux[] = {
2438 MSIOF0_SS2_MARK,
2439};
2440static const unsigned int msiof0_rx_pins[] = {
2441 /* RXD */
2442 RCAR_GP_PIN(5, 17),
2443};
2444static const unsigned int msiof0_rx_mux[] = {
2445 MSIOF0_RXD_MARK,
2446};
2447static const unsigned int msiof0_tx_pins[] = {
2448 /* TXD */
2449 RCAR_GP_PIN(5, 15),
2450};
2451static const unsigned int msiof0_tx_mux[] = {
2452 MSIOF0_TXD_MARK,
2453};
7033168d
GU		 2454
2455static const unsigned int msiof0_clk_b_pins[] = {
2456 /* SCK */
2457 RCAR_GP_PIN(1, 23),
2458};
2459static const unsigned int msiof0_clk_b_mux[] = {
2460 MSIOF0_SCK_B_MARK,
2461};
2462static const unsigned int msiof0_ss1_b_pins[] = {
2463 /* SS1 */
2464 RCAR_GP_PIN(1, 12),
2465};
2466static const unsigned int msiof0_ss1_b_mux[] = {
2467 MSIOF0_SS1_B_MARK,
2468};
2469static const unsigned int msiof0_ss2_b_pins[] = {
2470 /* SS2 */
2471 RCAR_GP_PIN(1, 10),
2472};
2473static const unsigned int msiof0_ss2_b_mux[] = {
2474 MSIOF0_SS2_B_MARK,
2475};
2476static const unsigned int msiof0_rx_b_pins[] = {
2477 /* RXD */
2478 RCAR_GP_PIN(1, 29),
2479};
2480static const unsigned int msiof0_rx_b_mux[] = {
2481 MSIOF0_RXD_B_MARK,
2482};
2483static const unsigned int msiof0_tx_b_pins[] = {
2484 /* TXD */
2485 RCAR_GP_PIN(1, 28),
2486};
2487static const unsigned int msiof0_tx_b_mux[] = {
2488 MSIOF0_TXD_B_MARK,
2489};
4f47cc5e
KH		 2490/* - MSIOF1 ----------------------------------------------------------------- */
2491static const unsigned int msiof1_clk_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(4, 8),
2494};
2495static const unsigned int msiof1_clk_mux[] = {
2496 MSIOF1_SCK_MARK,
2497};
2498static const unsigned int msiof1_sync_pins[] = {
2499 /* SYNC */
2500 RCAR_GP_PIN(4, 9),
2501};
2502static const unsigned int msiof1_sync_mux[] = {
2503 MSIOF1_SYNC_MARK,
2504};
2505static const unsigned int msiof1_ss1_pins[] = {
2506 /* SS1 */
2507 RCAR_GP_PIN(4, 10),
2508};
2509static const unsigned int msiof1_ss1_mux[] = {
2510 MSIOF1_SS1_MARK,
2511};
2512static const unsigned int msiof1_ss2_pins[] = {
2513 /* SS2 */
2514 RCAR_GP_PIN(4, 11),
2515};
2516static const unsigned int msiof1_ss2_mux[] = {
2517 MSIOF1_SS2_MARK,
2518};
2519static const unsigned int msiof1_rx_pins[] = {
2520 /* RXD */
2521 RCAR_GP_PIN(4, 13),
2522};
2523static const unsigned int msiof1_rx_mux[] = {
2524 MSIOF1_RXD_MARK,
2525};
2526static const unsigned int msiof1_tx_pins[] = {
2527 /* TXD */
2528 RCAR_GP_PIN(4, 12),
2529};
2530static const unsigned int msiof1_tx_mux[] = {
2531 MSIOF1_TXD_MARK,
2532};
7033168d
GU		 2533
2534static const unsigned int msiof1_clk_b_pins[] = {
2535 /* SCK */
2536 RCAR_GP_PIN(1, 16),
2537};
2538static const unsigned int msiof1_clk_b_mux[] = {
2539 MSIOF1_SCK_B_MARK,
2540};
2541static const unsigned int msiof1_ss1_b_pins[] = {
2542 /* SS1 */
2543 RCAR_GP_PIN(0, 18),
2544};
2545static const unsigned int msiof1_ss1_b_mux[] = {
2546 MSIOF1_SS1_B_MARK,
2547};
2548static const unsigned int msiof1_ss2_b_pins[] = {
2549 /* SS2 */
2550 RCAR_GP_PIN(0, 19),
2551};
2552static const unsigned int msiof1_ss2_b_mux[] = {
2553 MSIOF1_SS2_B_MARK,
2554};
2555static const unsigned int msiof1_rx_b_pins[] = {
2556 /* RXD */
2557 RCAR_GP_PIN(1, 17),
2558};
2559static const unsigned int msiof1_rx_b_mux[] = {
2560 MSIOF1_RXD_B_MARK,
2561};
2562static const unsigned int msiof1_tx_b_pins[] = {
2563 /* TXD */
2564 RCAR_GP_PIN(0, 20),
2565};
2566static const unsigned int msiof1_tx_b_mux[] = {
2567 MSIOF1_TXD_B_MARK,
2568};
4f47cc5e
KH		 2569/* - MSIOF2 ----------------------------------------------------------------- */
2570static const unsigned int msiof2_clk_pins[] = {
2571 /* SCK */
2572 RCAR_GP_PIN(0, 27),
2573};
2574static const unsigned int msiof2_clk_mux[] = {
2575 MSIOF2_SCK_MARK,
2576};
2577static const unsigned int msiof2_sync_pins[] = {
2578 /* SYNC */
2579 RCAR_GP_PIN(0, 26),
2580};
2581static const unsigned int msiof2_sync_mux[] = {
2582 MSIOF2_SYNC_MARK,
2583};
2584static const unsigned int msiof2_ss1_pins[] = {
2585 /* SS1 */
2586 RCAR_GP_PIN(0, 30),
2587};
2588static const unsigned int msiof2_ss1_mux[] = {
2589 MSIOF2_SS1_MARK,
2590};
2591static const unsigned int msiof2_ss2_pins[] = {
2592 /* SS2 */
2593 RCAR_GP_PIN(0, 31),
2594};
2595static const unsigned int msiof2_ss2_mux[] = {
2596 MSIOF2_SS2_MARK,
2597};
2598static const unsigned int msiof2_rx_pins[] = {
2599 /* RXD */
2600 RCAR_GP_PIN(0, 29),
2601};
2602static const unsigned int msiof2_rx_mux[] = {
2603 MSIOF2_RXD_MARK,
2604};
2605static const unsigned int msiof2_tx_pins[] = {
2606 /* TXD */
2607 RCAR_GP_PIN(0, 28),
2608};
2609static const unsigned int msiof2_tx_mux[] = {
2610 MSIOF2_TXD_MARK,
2611};
2612/* - MSIOF3 ----------------------------------------------------------------- */
2613static const unsigned int msiof3_clk_pins[] = {
2614 /* SCK */
2615 RCAR_GP_PIN(5, 4),
2616};
2617static const unsigned int msiof3_clk_mux[] = {
2618 MSIOF3_SCK_MARK,
2619};
2620static const unsigned int msiof3_sync_pins[] = {
2621 /* SYNC */
2622 RCAR_GP_PIN(4, 30),
2623};
2624static const unsigned int msiof3_sync_mux[] = {
2625 MSIOF3_SYNC_MARK,
2626};
2627static const unsigned int msiof3_ss1_pins[] = {
2628 /* SS1 */
2629 RCAR_GP_PIN(4, 31),
2630};
2631static const unsigned int msiof3_ss1_mux[] = {
2632 MSIOF3_SS1_MARK,
2633};
2634static const unsigned int msiof3_ss2_pins[] = {
2635 /* SS2 */
2636 RCAR_GP_PIN(4, 27),
2637};
2638static const unsigned int msiof3_ss2_mux[] = {
2639 MSIOF3_SS2_MARK,
2640};
2641static const unsigned int msiof3_rx_pins[] = {
2642 /* RXD */
2643 RCAR_GP_PIN(5, 2),
2644};
2645static const unsigned int msiof3_rx_mux[] = {
2646 MSIOF3_RXD_MARK,
2647};
2648static const unsigned int msiof3_tx_pins[] = {
2649 /* TXD */
2650 RCAR_GP_PIN(5, 3),
2651};
2652static const unsigned int msiof3_tx_mux[] = {
2653 MSIOF3_TXD_MARK,
2654};
7033168d
GU		 2655
2656static const unsigned int msiof3_clk_b_pins[] = {
2657 /* SCK */
2658 RCAR_GP_PIN(0, 0),
2659};
2660static const unsigned int msiof3_clk_b_mux[] = {
2661 MSIOF3_SCK_B_MARK,
2662};
2663static const unsigned int msiof3_sync_b_pins[] = {
2664 /* SYNC */
2665 RCAR_GP_PIN(0, 1),
2666};
2667static const unsigned int msiof3_sync_b_mux[] = {
2668 MSIOF3_SYNC_B_MARK,
2669};
2670static const unsigned int msiof3_rx_b_pins[] = {
2671 /* RXD */
2672 RCAR_GP_PIN(0, 2),
2673};
2674static const unsigned int msiof3_rx_b_mux[] = {
2675 MSIOF3_RXD_B_MARK,
2676};
2677static const unsigned int msiof3_tx_b_pins[] = {
2678 /* TXD */
2679 RCAR_GP_PIN(0, 3),
2680};
2681static const unsigned int msiof3_tx_b_mux[] = {
2682 MSIOF3_TXD_B_MARK,
2683};
5c89c15b
YS		 2684/* - PWM -------------------------------------------------------------------- */
2685static const unsigned int pwm0_pins[] = {
2686 RCAR_GP_PIN(5, 29),
2687};
2688static const unsigned int pwm0_mux[] = {
2689 PWM0_MARK,
2690};
2691static const unsigned int pwm0_b_pins[] = {
2692 RCAR_GP_PIN(4, 30),
2693};
2694static const unsigned int pwm0_b_mux[] = {
2695 PWM0_B_MARK,
2696};
2697static const unsigned int pwm1_pins[] = {
2698 RCAR_GP_PIN(5, 30),
2699};
2700static const unsigned int pwm1_mux[] = {
2701 PWM1_MARK,
2702};
2703static const unsigned int pwm1_b_pins[] = {
2704 RCAR_GP_PIN(4, 31),
2705};
2706static const unsigned int pwm1_b_mux[] = {
2707 PWM1_B_MARK,
2708};
2709static const unsigned int pwm2_pins[] = {
2710 RCAR_GP_PIN(5, 31),
2711};
2712static const unsigned int pwm2_mux[] = {
2713 PWM2_MARK,
2714};
2715static const unsigned int pwm3_pins[] = {
2716 RCAR_GP_PIN(0, 16),
2717};
2718static const unsigned int pwm3_mux[] = {
2719 PWM3_MARK,
2720};
2721static const unsigned int pwm4_pins[] = {
2722 RCAR_GP_PIN(0, 17),
2723};
2724static const unsigned int pwm4_mux[] = {
2725 PWM4_MARK,
2726};
2727static const unsigned int pwm5_pins[] = {
2728 RCAR_GP_PIN(0, 18),
2729};
2730static const unsigned int pwm5_mux[] = {
2731 PWM5_MARK,
2732};
2733static const unsigned int pwm6_pins[] = {
2734 RCAR_GP_PIN(0, 19),
2735};
2736static const unsigned int pwm6_mux[] = {
2737 PWM6_MARK,
2738};
202909cd
GU		 2739/* - QSPI ------------------------------------------------------------------- */
2740static const unsigned int qspi_ctrl_pins[] = {
2741 /* SPCLK, SSL */
2742 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2743};
2744static const unsigned int qspi_ctrl_mux[] = {
2745 SPCLK_MARK, SSL_MARK,
2746};
2747static const unsigned int qspi_data2_pins[] = {
2748 /* MOSI_IO0, MISO_IO1 */
2749 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2750};
2751static const unsigned int qspi_data2_mux[] = {
2752 MOSI_IO0_MARK, MISO_IO1_MARK,
2753};
2754static const unsigned int qspi_data4_pins[] = {
2755 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2756 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2757 RCAR_GP_PIN(1, 8),
2758};
2759static const unsigned int qspi_data4_mux[] = {
2760 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2761};
457c11d3
LP		 2762/* - SCIF0 ------------------------------------------------------------------ */
2763static const unsigned int scif0_data_pins[] = {
2764 /* RX, TX */
2765 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2766};
2767static const unsigned int scif0_data_mux[] = {
2768 RX0_MARK, TX0_MARK,
2769};
2770static const unsigned int scif0_clk_pins[] = {
2771 /* SCK */
2772 RCAR_GP_PIN(4, 27),
2773};
2774static const unsigned int scif0_clk_mux[] = {
2775 SCK0_MARK,
2776};
2777static const unsigned int scif0_ctrl_pins[] = {
2778 /* RTS, CTS */
2779 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2780};
2781static const unsigned int scif0_ctrl_mux[] = {
2782 RTS0_N_MARK, CTS0_N_MARK,
2783};
2784static const unsigned int scif0_data_b_pins[] = {
2785 /* RX, TX */
2786 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2787};
2788static const unsigned int scif0_data_b_mux[] = {
2789 RX0_B_MARK, TX0_B_MARK,
2790};
2791/* - SCIF1 ------------------------------------------------------------------ */
2792static const unsigned int scif1_data_pins[] = {
2793 /* RX, TX */
2794 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2795};
2796static const unsigned int scif1_data_mux[] = {
2797 RX1_MARK, TX1_MARK,
2798};
2799static const unsigned int scif1_clk_pins[] = {
2800 /* SCK */
2801 RCAR_GP_PIN(4, 20),
2802};
2803static const unsigned int scif1_clk_mux[] = {
2804 SCK1_MARK,
2805};
2806static const unsigned int scif1_ctrl_pins[] = {
2807 /* RTS, CTS */
2808 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2809};
2810static const unsigned int scif1_ctrl_mux[] = {
2811 RTS1_N_MARK, CTS1_N_MARK,
2812};
2813static const unsigned int scif1_data_b_pins[] = {
2814 /* RX, TX */
2815 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2816};
2817static const unsigned int scif1_data_b_mux[] = {
2818 RX1_B_MARK, TX1_B_MARK,
2819};
2820static const unsigned int scif1_data_c_pins[] = {
2821 /* RX, TX */
2822 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2823};
2824static const unsigned int scif1_data_c_mux[] = {
2825 RX1_C_MARK, TX1_C_MARK,
fbd0ca3d 2826};
457c11d3 2827static const unsigned int scif1_data_d_pins[] = {
fbd0ca3d 2828 /* RX, TX */
457c11d3 2829 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
fbd0ca3d 2830};
457c11d3
LP		 2831static const unsigned int scif1_data_d_mux[] = {
2832 RX1_D_MARK, TX1_D_MARK,
fbd0ca3d 2833};
457c11d3 2834static const unsigned int scif1_clk_d_pins[] = {
fbd0ca3d 2835 /* SCK */
457c11d3 2836 RCAR_GP_PIN(3, 17),
fbd0ca3d 2837};
457c11d3
LP		 2838static const unsigned int scif1_clk_d_mux[] = {
2839 SCK1_D_MARK,
fbd0ca3d 2840};
457c11d3
LP		 2841static const unsigned int scif1_data_e_pins[] = {
2842 /* RX, TX */
2843 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
fbd0ca3d 2844};
457c11d3
LP		 2845static const unsigned int scif1_data_e_mux[] = {
2846 RX1_E_MARK, TX1_E_MARK,
2847};
2848static const unsigned int scif1_clk_e_pins[] = {
2849 /* SCK */
2850 RCAR_GP_PIN(2, 20),
2851};
2852static const unsigned int scif1_clk_e_mux[] = {
2853 SCK1_E_MARK,
fbd0ca3d 2854};
2dbe7f2c
LP		 2855/* - SCIF2 ------------------------------------------------------------------ */
2856static const unsigned int scif2_data_pins[] = {
2857 /* RX, TX */
2858 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2859};
2860static const unsigned int scif2_data_mux[] = {
2861 RX2_MARK, TX2_MARK,
2862};
2863static const unsigned int scif2_clk_pins[] = {
2864 /* SCK */
2865 RCAR_GP_PIN(5, 4),
2866};
2867static const unsigned int scif2_clk_mux[] = {
2868 SCK2_MARK,
2869};
2870static const unsigned int scif2_data_b_pins[] = {
2871 /* RX, TX */
2872 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2873};
2874static const unsigned int scif2_data_b_mux[] = {
2875 RX2_B_MARK, TX2_B_MARK,
2876};
45c6c85d
LP		 2877/* - SCIFA0 ----------------------------------------------------------------- */
2878static const unsigned int scifa0_data_pins[] = {
2879 /* RXD, TXD */
2880 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2881};
2882static const unsigned int scifa0_data_mux[] = {
2883 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2884};
2885static const unsigned int scifa0_clk_pins[] = {
2886 /* SCK */
2887 RCAR_GP_PIN(4, 27),
2888};
2889static const unsigned int scifa0_clk_mux[] = {
2890 SCIFA0_SCK_MARK,
2891};
2892static const unsigned int scifa0_ctrl_pins[] = {
2893 /* RTS, CTS */
2894 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2895};
2896static const unsigned int scifa0_ctrl_mux[] = {
2897 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2898};
2899static const unsigned int scifa0_data_b_pins[] = {
2900 /* RXD, TXD */
2901 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2902};
2903static const unsigned int scifa0_data_b_mux[] = {
2904 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2905};
2906static const unsigned int scifa0_clk_b_pins[] = {
2907 /* SCK */
2908 RCAR_GP_PIN(1, 19),
2909};
2910static const unsigned int scifa0_clk_b_mux[] = {
2911 SCIFA0_SCK_B_MARK,
2912};
2913static const unsigned int scifa0_ctrl_b_pins[] = {
2914 /* RTS, CTS */
2915 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2916};
2917static const unsigned int scifa0_ctrl_b_mux[] = {
2918 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2919};
2920/* - SCIFA1 ----------------------------------------------------------------- */
2921static const unsigned int scifa1_data_pins[] = {
2922 /* RXD, TXD */
2923 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2924};
2925static const unsigned int scifa1_data_mux[] = {
2926 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2927};
2928static const unsigned int scifa1_clk_pins[] = {
2929 /* SCK */
2930 RCAR_GP_PIN(4, 20),
2931};
2932static const unsigned int scifa1_clk_mux[] = {
2933 SCIFA1_SCK_MARK,
2934};
2935static const unsigned int scifa1_ctrl_pins[] = {
2936 /* RTS, CTS */
2937 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2938};
2939static const unsigned int scifa1_ctrl_mux[] = {
2940 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2941};
2942static const unsigned int scifa1_data_b_pins[] = {
2943 /* RXD, TXD */
2944 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2945};
2946static const unsigned int scifa1_data_b_mux[] = {
2947 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2948};
2949static const unsigned int scifa1_clk_b_pins[] = {
2950 /* SCK */
2951 RCAR_GP_PIN(0, 23),
2952};
2953static const unsigned int scifa1_clk_b_mux[] = {
2954 SCIFA1_SCK_B_MARK,
2955};
2956static const unsigned int scifa1_ctrl_b_pins[] = {
2957 /* RTS, CTS */
2958 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2959};
2960static const unsigned int scifa1_ctrl_b_mux[] = {
2961 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2962};
2963static const unsigned int scifa1_data_c_pins[] = {
2964 /* RXD, TXD */
2965 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2966};
2967static const unsigned int scifa1_data_c_mux[] = {
2968 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2969};
2970static const unsigned int scifa1_clk_c_pins[] = {
2971 /* SCK */
2972 RCAR_GP_PIN(0, 8),
2973};
2974static const unsigned int scifa1_clk_c_mux[] = {
2975 SCIFA1_SCK_C_MARK,
2976};
2977static const unsigned int scifa1_ctrl_c_pins[] = {
2978 /* RTS, CTS */
2979 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2980};
2981static const unsigned int scifa1_ctrl_c_mux[] = {
2982 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2983};
2984static const unsigned int scifa1_data_d_pins[] = {
2985 /* RXD, TXD */
2986 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2987};
2988static const unsigned int scifa1_data_d_mux[] = {
2989 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2990};
2991static const unsigned int scifa1_clk_d_pins[] = {
2992 /* SCK */
2993 RCAR_GP_PIN(2, 10),
2994};
2995static const unsigned int scifa1_clk_d_mux[] = {
2996 SCIFA1_SCK_D_MARK,
2997};
2998static const unsigned int scifa1_ctrl_d_pins[] = {
2999 /* RTS, CTS */
3000 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3001};
3002static const unsigned int scifa1_ctrl_d_mux[] = {
3003 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
3004};
3005/* - SCIFA2 ----------------------------------------------------------------- */
3006static const unsigned int scifa2_data_pins[] = {
3007 /* RXD, TXD */
3008 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3009};
3010static const unsigned int scifa2_data_mux[] = {
3011 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3012};
3013static const unsigned int scifa2_clk_pins[] = {
3014 /* SCK */
3015 RCAR_GP_PIN(5, 4),
3016};
3017static const unsigned int scifa2_clk_mux[] = {
3018 SCIFA2_SCK_MARK,
3019};
3020static const unsigned int scifa2_ctrl_pins[] = {
3021 /* RTS, CTS */
3022 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3023};
3024static const unsigned int scifa2_ctrl_mux[] = {
3025 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3026};
3027static const unsigned int scifa2_data_b_pins[] = {
3028 /* RXD, TXD */
3029 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3030};
3031static const unsigned int scifa2_data_b_mux[] = {
3032 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3033};
3034static const unsigned int scifa2_data_c_pins[] = {
3035 /* RXD, TXD */
3036 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3037};
3038static const unsigned int scifa2_data_c_mux[] = {
3039 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3040};
3041static const unsigned int scifa2_clk_c_pins[] = {
3042 /* SCK */
3043 RCAR_GP_PIN(5, 29),
3044};
3045static const unsigned int scifa2_clk_c_mux[] = {
3046 SCIFA2_SCK_C_MARK,
3047};
3048/* - SCIFB0 ----------------------------------------------------------------- */
3049static const unsigned int scifb0_data_pins[] = {
3050 /* RXD, TXD */
3051 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3052};
3053static const unsigned int scifb0_data_mux[] = {
3054 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3055};
3056static const unsigned int scifb0_clk_pins[] = {
3057 /* SCK */
3058 RCAR_GP_PIN(4, 8),
3059};
3060static const unsigned int scifb0_clk_mux[] = {
3061 SCIFB0_SCK_MARK,
3062};
3063static const unsigned int scifb0_ctrl_pins[] = {
3064 /* RTS, CTS */
3065 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3066};
3067static const unsigned int scifb0_ctrl_mux[] = {
3068 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3069};
3070static const unsigned int scifb0_data_b_pins[] = {
3071 /* RXD, TXD */
3072 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3073};
3074static const unsigned int scifb0_data_b_mux[] = {
3075 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3076};
3077static const unsigned int scifb0_clk_b_pins[] = {
3078 /* SCK */
3079 RCAR_GP_PIN(3, 9),
3080};
3081static const unsigned int scifb0_clk_b_mux[] = {
3082 SCIFB0_SCK_B_MARK,
3083};
3084static const unsigned int scifb0_ctrl_b_pins[] = {
3085 /* RTS, CTS */
3086 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3087};
3088static const unsigned int scifb0_ctrl_b_mux[] = {
3089 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3090};
3091static const unsigned int scifb0_data_c_pins[] = {
3092 /* RXD, TXD */
3093 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3094};
3095static const unsigned int scifb0_data_c_mux[] = {
3096 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3097};
3098/* - SCIFB1 ----------------------------------------------------------------- */
3099static const unsigned int scifb1_data_pins[] = {
3100 /* RXD, TXD */
3101 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3102};
3103static const unsigned int scifb1_data_mux[] = {
3104 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3105};
3106static const unsigned int scifb1_clk_pins[] = {
3107 /* SCK */
3108 RCAR_GP_PIN(4, 14),
3109};
3110static const unsigned int scifb1_clk_mux[] = {
3111 SCIFB1_SCK_MARK,
3112};
3113static const unsigned int scifb1_ctrl_pins[] = {
3114 /* RTS, CTS */
3115 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3116};
3117static const unsigned int scifb1_ctrl_mux[] = {
3118 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3119};
3120static const unsigned int scifb1_data_b_pins[] = {
3121 /* RXD, TXD */
3122 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3123};
3124static const unsigned int scifb1_data_b_mux[] = {
3125 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3126};
3127static const unsigned int scifb1_clk_b_pins[] = {
3128 /* SCK */
3129 RCAR_GP_PIN(3, 1),
3130};
3131static const unsigned int scifb1_clk_b_mux[] = {
3132 SCIFB1_SCK_B_MARK,
3133};
3134static const unsigned int scifb1_ctrl_b_pins[] = {
3135 /* RTS, CTS */
3136 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3137};
3138static const unsigned int scifb1_ctrl_b_mux[] = {
3139 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3140};
3141static const unsigned int scifb1_data_c_pins[] = {
3142 /* RXD, TXD */
3143 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3144};
3145static const unsigned int scifb1_data_c_mux[] = {
3146 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3147};
3148static const unsigned int scifb1_data_d_pins[] = {
3149 /* RXD, TXD */
3150 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3151};
3152static const unsigned int scifb1_data_d_mux[] = {
3153 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3154};
3155static const unsigned int scifb1_data_e_pins[] = {
3156 /* RXD, TXD */
3157 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3158};
3159static const unsigned int scifb1_data_e_mux[] = {
3160 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3161};
3162static const unsigned int scifb1_clk_e_pins[] = {
3163 /* SCK */
3164 RCAR_GP_PIN(3, 17),
3165};
3166static const unsigned int scifb1_clk_e_mux[] = {
3167 SCIFB1_SCK_E_MARK,
3168};
3169static const unsigned int scifb1_data_f_pins[] = {
3170 /* RXD, TXD */
3171 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3172};
3173static const unsigned int scifb1_data_f_mux[] = {
3174 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3175};
3176static const unsigned int scifb1_data_g_pins[] = {
3177 /* RXD, TXD */
3178 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3179};
3180static const unsigned int scifb1_data_g_mux[] = {
3181 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3182};
3183static const unsigned int scifb1_clk_g_pins[] = {
3184 /* SCK */
3185 RCAR_GP_PIN(2, 20),
3186};
3187static const unsigned int scifb1_clk_g_mux[] = {
3188 SCIFB1_SCK_G_MARK,
066f0d6e 3189};
45c6c85d
LP		 3190/* - SCIFB2 ----------------------------------------------------------------- */
3191static const unsigned int scifb2_data_pins[] = {
3192 /* RXD, TXD */
3193 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
066f0d6e 3194};
45c6c85d
LP		 3195static const unsigned int scifb2_data_mux[] = {
3196 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
066f0d6e 3197};
45c6c85d
LP		 3198static const unsigned int scifb2_clk_pins[] = {
3199 /* SCK */
3200 RCAR_GP_PIN(4, 21),
066f0d6e 3201};
45c6c85d
LP		 3202static const unsigned int scifb2_clk_mux[] = {
3203 SCIFB2_SCK_MARK,
066f0d6e 3204};
45c6c85d
LP		 3205static const unsigned int scifb2_ctrl_pins[] = {
3206 /* RTS, CTS */
3207 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
066f0d6e 3208};
45c6c85d
LP		 3209static const unsigned int scifb2_ctrl_mux[] = {
3210 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
066f0d6e 3211};
45c6c85d
LP		 3212static const unsigned int scifb2_data_b_pins[] = {
3213 /* RXD, TXD */
3214 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
066f0d6e 3215};
45c6c85d
LP		 3216static const unsigned int scifb2_data_b_mux[] = {
3217 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
066f0d6e 3218};
45c6c85d
LP		 3219static const unsigned int scifb2_clk_b_pins[] = {
3220 /* SCK */
3221 RCAR_GP_PIN(0, 31),
066f0d6e 3222};
45c6c85d
LP		 3223static const unsigned int scifb2_clk_b_mux[] = {
3224 SCIFB2_SCK_B_MARK,
066f0d6e 3225};
45c6c85d
LP		 3226static const unsigned int scifb2_ctrl_b_pins[] = {
3227 /* RTS, CTS */
3228 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
066f0d6e 3229};
45c6c85d
LP		 3230static const unsigned int scifb2_ctrl_b_mux[] = {
3231 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
066f0d6e 3232};
45c6c85d
LP		 3233static const unsigned int scifb2_data_c_pins[] = {
3234 /* RXD, TXD */
3235 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3236};
3237static const unsigned int scifb2_data_c_mux[] = {
3238 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
066f0d6e 3239};
0a6ea54f 3240/* - SDHI0 ------------------------------------------------------------------ */
066f0d6e
GL		 3241static const unsigned int sdhi0_data1_pins[] = {
3242 /* D0 */
3243 RCAR_GP_PIN(3, 2),
3244};
3245static const unsigned int sdhi0_data1_mux[] = {
3246 SD0_DAT0_MARK,
3247};
3248static const unsigned int sdhi0_data4_pins[] = {
3249 /* D[0:3] */
3250 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3251};
3252static const unsigned int sdhi0_data4_mux[] = {
3253 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3254};
3255static const unsigned int sdhi0_ctrl_pins[] = {
3256 /* CLK, CMD */
3257 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3258};
3259static const unsigned int sdhi0_ctrl_mux[] = {
3260 SD0_CLK_MARK, SD0_CMD_MARK,
3261};
3262static const unsigned int sdhi0_cd_pins[] = {
3263 /* CD */
3264 RCAR_GP_PIN(3, 6),
3265};
3266static const unsigned int sdhi0_cd_mux[] = {
3267 SD0_CD_MARK,
3268};
3269static const unsigned int sdhi0_wp_pins[] = {
3270 /* WP */
3271 RCAR_GP_PIN(3, 7),
3272};
3273static const unsigned int sdhi0_wp_mux[] = {
3274 SD0_WP_MARK,
3275};
0a6ea54f 3276/* - SDHI1 ------------------------------------------------------------------ */
066f0d6e
GL		 3277static const unsigned int sdhi1_data1_pins[] = {
3278 /* D0 */
3279 RCAR_GP_PIN(3, 10),
3280};
3281static const unsigned int sdhi1_data1_mux[] = {
3282 SD1_DAT0_MARK,
3283};
3284static const unsigned int sdhi1_data4_pins[] = {
3285 /* D[0:3] */
3286 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3287};
3288static const unsigned int sdhi1_data4_mux[] = {
3289 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3290};
3291static const unsigned int sdhi1_ctrl_pins[] = {
3292 /* CLK, CMD */
3293 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3294};
3295static const unsigned int sdhi1_ctrl_mux[] = {
3296 SD1_CLK_MARK, SD1_CMD_MARK,
3297};
3298static const unsigned int sdhi1_cd_pins[] = {
3299 /* CD */
3300 RCAR_GP_PIN(3, 14),
3301};
3302static const unsigned int sdhi1_cd_mux[] = {
3303 SD1_CD_MARK,
3304};
3305static const unsigned int sdhi1_wp_pins[] = {
3306 /* WP */
3307 RCAR_GP_PIN(3, 15),
3308};
3309static const unsigned int sdhi1_wp_mux[] = {
3310 SD1_WP_MARK,
3311};
0a6ea54f 3312/* - SDHI2 ------------------------------------------------------------------ */
066f0d6e
GL		 3313static const unsigned int sdhi2_data1_pins[] = {
3314 /* D0 */
3315 RCAR_GP_PIN(3, 18),
3316};
3317static const unsigned int sdhi2_data1_mux[] = {
3318 SD2_DAT0_MARK,
3319};
3320static const unsigned int sdhi2_data4_pins[] = {
3321 /* D[0:3] */
3322 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3323};
3324static const unsigned int sdhi2_data4_mux[] = {
3325 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3326};
3327static const unsigned int sdhi2_ctrl_pins[] = {
3328 /* CLK, CMD */
3329 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3330};
3331static const unsigned int sdhi2_ctrl_mux[] = {
3332 SD2_CLK_MARK, SD2_CMD_MARK,
3333};
3334static const unsigned int sdhi2_cd_pins[] = {
3335 /* CD */
3336 RCAR_GP_PIN(3, 22),
3337};
3338static const unsigned int sdhi2_cd_mux[] = {
3339 SD2_CD_MARK,
3340};
3341static const unsigned int sdhi2_wp_pins[] = {
3342 /* WP */
3343 RCAR_GP_PIN(3, 23),
3344};
3345static const unsigned int sdhi2_wp_mux[] = {
3346 SD2_WP_MARK,
3347};
0a6ea54f 3348/* - SDHI3 ------------------------------------------------------------------ */
066f0d6e
GL		 3349static const unsigned int sdhi3_data1_pins[] = {
3350 /* D0 */
3351 RCAR_GP_PIN(3, 26),
3352};
3353static const unsigned int sdhi3_data1_mux[] = {
3354 SD3_DAT0_MARK,
3355};
3356static const unsigned int sdhi3_data4_pins[] = {
3357 /* D[0:3] */
3358 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3359};
3360static const unsigned int sdhi3_data4_mux[] = {
3361 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3362};
3363static const unsigned int sdhi3_ctrl_pins[] = {
3364 /* CLK, CMD */
3365 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3366};
3367static const unsigned int sdhi3_ctrl_mux[] = {
3368 SD3_CLK_MARK, SD3_CMD_MARK,
3369};
3370static const unsigned int sdhi3_cd_pins[] = {
3371 /* CD */
3372 RCAR_GP_PIN(3, 30),
3373};
3374static const unsigned int sdhi3_cd_mux[] = {
3375 SD3_CD_MARK,
3376};
3377static const unsigned int sdhi3_wp_pins[] = {
3378 /* WP */
3379 RCAR_GP_PIN(3, 31),
3380};
3381static const unsigned int sdhi3_wp_mux[] = {
3382 SD3_WP_MARK,
3383};
1d7b59a0
KM		 3384/* - SSI -------------------------------------------------------------------- */
3385static const unsigned int ssi0_data_pins[] = {
3386 /* SDATA0 */
3387 RCAR_GP_PIN(4, 5),
3388};
3389static const unsigned int ssi0_data_mux[] = {
3390 SSI_SDATA0_MARK,
3391};
3392static const unsigned int ssi0129_ctrl_pins[] = {
3393 /* SCK, WS */
3394 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3395};
3396static const unsigned int ssi0129_ctrl_mux[] = {
3397 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3398};
3399static const unsigned int ssi1_data_pins[] = {
3400 /* SDATA1 */
3401 RCAR_GP_PIN(4, 6),
3402};
3403static const unsigned int ssi1_data_mux[] = {
3404 SSI_SDATA1_MARK,
3405};
3406static const unsigned int ssi1_ctrl_pins[] = {
3407 /* SCK, WS */
3408 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3409};
3410static const unsigned int ssi1_ctrl_mux[] = {
3411 SSI_SCK1_MARK, SSI_WS1_MARK,
3412};
3413static const unsigned int ssi2_data_pins[] = {
3414 /* SDATA2 */
3415 RCAR_GP_PIN(4, 7),
3416};
3417static const unsigned int ssi2_data_mux[] = {
3418 SSI_SDATA2_MARK,
3419};
3420static const unsigned int ssi2_ctrl_pins[] = {
3421 /* SCK, WS */
3422 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3423};
3424static const unsigned int ssi2_ctrl_mux[] = {
3425 SSI_SCK2_MARK, SSI_WS2_MARK,
3426};
3427static const unsigned int ssi3_data_pins[] = {
3428 /* SDATA3 */
3429 RCAR_GP_PIN(4, 10),
3430};
3431static const unsigned int ssi3_data_mux[] = {
3432 SSI_SDATA3_MARK
3433};
3434static const unsigned int ssi34_ctrl_pins[] = {
3435 /* SCK, WS */
3436 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3437};
3438static const unsigned int ssi34_ctrl_mux[] = {
3439 SSI_SCK34_MARK, SSI_WS34_MARK,
3440};
3441static const unsigned int ssi4_data_pins[] = {
3442 /* SDATA4 */
3443 RCAR_GP_PIN(4, 13),
3444};
3445static const unsigned int ssi4_data_mux[] = {
3446 SSI_SDATA4_MARK,
3447};
3448static const unsigned int ssi4_ctrl_pins[] = {
3449 /* SCK, WS */
3450 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3451};
3452static const unsigned int ssi4_ctrl_mux[] = {
3453 SSI_SCK4_MARK, SSI_WS4_MARK,
3454};
3455static const unsigned int ssi5_pins[] = {
3456 /* SDATA5, SCK, WS */
3457 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3458};
3459static const unsigned int ssi5_mux[] = {
3460 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3461};
3462static const unsigned int ssi5_b_pins[] = {
3463 /* SDATA5, SCK, WS */
3464 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3465};
3466static const unsigned int ssi5_b_mux[] = {
3467 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3468};
3469static const unsigned int ssi5_c_pins[] = {
3470 /* SDATA5, SCK, WS */
3471 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3472};
3473static const unsigned int ssi5_c_mux[] = {
3474 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3475};
3476static const unsigned int ssi6_pins[] = {
3477 /* SDATA6, SCK, WS */
3478 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3479};
3480static const unsigned int ssi6_mux[] = {
3481 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3482};
3483static const unsigned int ssi6_b_pins[] = {
3484 /* SDATA6, SCK, WS */
3485 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3486};
3487static const unsigned int ssi6_b_mux[] = {
3488 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3489};
3490static const unsigned int ssi7_data_pins[] = {
3491 /* SDATA7 */
3492 RCAR_GP_PIN(4, 22),
3493};
3494static const unsigned int ssi7_data_mux[] = {
3495 SSI_SDATA7_MARK,
3496};
3497static const unsigned int ssi7_b_data_pins[] = {
3498 /* SDATA7 */
3499 RCAR_GP_PIN(4, 22),
3500};
3501static const unsigned int ssi7_b_data_mux[] = {
3502 SSI_SDATA7_B_MARK,
3503};
3504static const unsigned int ssi7_c_data_pins[] = {
3505 /* SDATA7 */
3506 RCAR_GP_PIN(1, 26),
3507};
3508static const unsigned int ssi7_c_data_mux[] = {
3509 SSI_SDATA7_C_MARK,
3510};
3511static const unsigned int ssi78_ctrl_pins[] = {
3512 /* SCK, WS */
3513 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3514};
3515static const unsigned int ssi78_ctrl_mux[] = {
3516 SSI_SCK78_MARK, SSI_WS78_MARK,
3517};
3518static const unsigned int ssi78_b_ctrl_pins[] = {
3519 /* SCK, WS */
3520 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3521};
3522static const unsigned int ssi78_b_ctrl_mux[] = {
3523 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3524};
3525static const unsigned int ssi78_c_ctrl_pins[] = {
3526 /* SCK, WS */
3527 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3528};
3529static const unsigned int ssi78_c_ctrl_mux[] = {
3530 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3531};
3532static const unsigned int ssi8_data_pins[] = {
3533 /* SDATA8 */
3534 RCAR_GP_PIN(4, 23),
3535};
3536static const unsigned int ssi8_data_mux[] = {
3537 SSI_SDATA8_MARK,
3538};
3539static const unsigned int ssi8_b_data_pins[] = {
3540 /* SDATA8 */
3541 RCAR_GP_PIN(4, 23),
3542};
3543static const unsigned int ssi8_b_data_mux[] = {
3544 SSI_SDATA8_B_MARK,
3545};
3546static const unsigned int ssi8_c_data_pins[] = {
3547 /* SDATA8 */
3548 RCAR_GP_PIN(1, 27),
3549};
3550static const unsigned int ssi8_c_data_mux[] = {
3551 SSI_SDATA8_C_MARK,
3552};
3553static const unsigned int ssi9_data_pins[] = {
3554 /* SDATA9 */
3555 RCAR_GP_PIN(4, 24),
3556};
3557static const unsigned int ssi9_data_mux[] = {
3558 SSI_SDATA9_MARK,
3559};
3560static const unsigned int ssi9_ctrl_pins[] = {
3561 /* SCK, WS */
3562 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3563};
3564static const unsigned int ssi9_ctrl_mux[] = {
3565 SSI_SCK9_MARK, SSI_WS9_MARK,
3566};
457c11d3
LP		 3567/* - TPU0 ------------------------------------------------------------------- */
3568static const unsigned int tpu0_to0_pins[] = {
3569 /* TO */
3570 RCAR_GP_PIN(0, 20),
3571};
3572static const unsigned int tpu0_to0_mux[] = {
3573 TPU0TO0_MARK,
3574};
3575static const unsigned int tpu0_to1_pins[] = {
3576 /* TO */
3577 RCAR_GP_PIN(0, 21),
3578};
3579static const unsigned int tpu0_to1_mux[] = {
3580 TPU0TO1_MARK,
3581};
3582static const unsigned int tpu0_to2_pins[] = {
3583 /* TO */
3584 RCAR_GP_PIN(0, 22),
3585};
3586static const unsigned int tpu0_to2_mux[] = {
3587 TPU0TO2_MARK,
3588};
3589static const unsigned int tpu0_to3_pins[] = {
3590 /* TO */
3591 RCAR_GP_PIN(0, 23),
3592};
3593static const unsigned int tpu0_to3_mux[] = {
3594 TPU0TO3_MARK,
3595};
dac896e2
SU		 3596/* - USB0 ------------------------------------------------------------------- */
3597static const unsigned int usb0_pins[] = {
3598 /* PWEN, OVC/VBUS */
3599 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3600};
3601static const unsigned int usb0_mux[] = {
3602 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3603};
97e00faa
MD		 3604static const unsigned int usb0_ovc_vbus_pins[] = {
3605 /* OVC/VBUS */
3606 RCAR_GP_PIN(5, 19),
3607};
3608static const unsigned int usb0_ovc_vbus_mux[] = {
3609 USB0_OVC_VBUS_MARK,
3610};
dac896e2
SU		 3611/* - USB1 ------------------------------------------------------------------- */
3612static const unsigned int usb1_pins[] = {
3613 /* PWEN, OVC */
3614 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3615};
3616static const unsigned int usb1_mux[] = {
3617 USB1_PWEN_MARK, USB1_OVC_MARK,
3618};
3619/* - USB2 ------------------------------------------------------------------- */
3620static const unsigned int usb2_pins[] = {
3621 /* PWEN, OVC */
3622 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3623};
3624static const unsigned int usb2_mux[] = {
3625 USB2_PWEN_MARK, USB2_OVC_MARK,
3626};
64fe8abc
VB		 3627
3628union vin_data {
3629 unsigned int data24[24];
3630 unsigned int data20[20];
3631 unsigned int data16[16];
3632 unsigned int data12[12];
3633 unsigned int data10[10];
3634 unsigned int data8[8];
3635 unsigned int data4[4];
3636};
3637
3638#define VIN_DATA_PIN_GROUP(n, s) \
3639 { \
3640 .name = #n#s, \
3641 .pins = n##_pins.data##s, \
3642 .mux = n##_mux.data##s, \
3643 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3644 }
3645
e120cacf 3646/* - VIN0 ------------------------------------------------------------------- */
64fe8abc
VB		 3647static const union vin_data vin0_data_pins = {
3648 .data24 = {
3649 /* B */
3650 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3651 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3652 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3653 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3654 /* G */
3655 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3656 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3657 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3658 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3659 /* R */
3660 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3661 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3662 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3663 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3664 },
3665};
3666static const union vin_data vin0_data_mux = {
3667 .data24 = {
3668 /* B */
3669 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3670 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3671 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3672 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3673 /* G */
3674 VI0_G0_MARK, VI0_G1_MARK,
3675 VI0_G2_MARK, VI0_G3_MARK,
3676 VI0_G4_MARK, VI0_G5_MARK,
3677 VI0_G6_MARK, VI0_G7_MARK,
3678 /* R */
3679 VI0_R0_MARK, VI0_R1_MARK,
3680 VI0_R2_MARK, VI0_R3_MARK,
3681 VI0_R4_MARK, VI0_R5_MARK,
3682 VI0_R6_MARK, VI0_R7_MARK,
3683 },
3684};
3685static const unsigned int vin0_data18_pins[] = {
3686 /* B */
3687 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3688 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3689 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3690 /* G */
3691 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3692 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
e120cacf 3693 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
64fe8abc
VB		 3694 /* R */
3695 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3696 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
e120cacf
SU		 3697 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3698};
64fe8abc
VB		 3699static const unsigned int vin0_data18_mux[] = {
3700 /* B */
3701 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3702 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
e120cacf 3703 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
64fe8abc
VB		 3704 /* G */
3705 VI0_G2_MARK, VI0_G3_MARK,
3706 VI0_G4_MARK, VI0_G5_MARK,
3707 VI0_G6_MARK, VI0_G7_MARK,
3708 /* R */
3709 VI0_R2_MARK, VI0_R3_MARK,
3710 VI0_R4_MARK, VI0_R5_MARK,
3711 VI0_R6_MARK, VI0_R7_MARK,
e120cacf 3712};
a9e4c7bb
VB		 3713static const unsigned int vin0_sync_pins[] = {
3714 RCAR_GP_PIN(0, 12), /* HSYNC */
3715 RCAR_GP_PIN(0, 13), /* VSYNC */
e120cacf 3716};
a9e4c7bb 3717static const unsigned int vin0_sync_mux[] = {
e120cacf 3718 VI0_HSYNC_N_MARK,
e120cacf
SU		 3719 VI0_VSYNC_N_MARK,
3720};
7a57be87 3721static const unsigned int vin0_field_pins[] = {
e120cacf
SU		 3722 RCAR_GP_PIN(0, 15),
3723};
7a57be87 3724static const unsigned int vin0_field_mux[] = {
e120cacf
SU		 3725 VI0_FIELD_MARK,
3726};
7a57be87 3727static const unsigned int vin0_clkenb_pins[] = {
e120cacf
SU		 3728 RCAR_GP_PIN(0, 14),
3729};
7a57be87 3730static const unsigned int vin0_clkenb_mux[] = {
e120cacf
SU		 3731 VI0_CLKENB_MARK,
3732};
3733static const unsigned int vin0_clk_pins[] = {
3734 RCAR_GP_PIN(2, 0),
3735};
3736static const unsigned int vin0_clk_mux[] = {
3737 VI0_CLK_MARK,
3738};
3739/* - VIN1 ------------------------------------------------------------------- */
317a03a9
VB		 3740static const union vin_data vin1_data_pins = {
3741 .data24 = {
3742 /* B */
3743 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3744 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3745 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3746 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3747 /* G */
3748 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3749 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3750 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3751 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3752 /* R */
3753 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3754 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3755 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3756 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3757 },
3758};
3759static const union vin_data vin1_data_mux = {
3760 .data24 = {
3761 /* B */
3762 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3763 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3764 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3765 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3766 /* G */
3767 VI1_G0_MARK, VI1_G1_MARK,
3768 VI1_G2_MARK, VI1_G3_MARK,
3769 VI1_G4_MARK, VI1_G5_MARK,
3770 VI1_G6_MARK, VI1_G7_MARK,
3771 /* R */
3772 VI1_R0_MARK, VI1_R1_MARK,
3773 VI1_R2_MARK, VI1_R3_MARK,
3774 VI1_R4_MARK, VI1_R5_MARK,
3775 VI1_R6_MARK, VI1_R7_MARK,
3776 },
3777};
3778static const unsigned int vin1_data18_pins[] = {
3779 /* B */
3780 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3781 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
e120cacf 3782 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
317a03a9
VB		 3783 /* G */
3784 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3785 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3786 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3787 /* R */
3788 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3789 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3790 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
e120cacf 3791};
317a03a9
VB		 3792static const unsigned int vin1_data18_mux[] = {
3793 /* B */
3794 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3795 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
e120cacf 3796 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
317a03a9
VB		 3797 /* G */
3798 VI1_G2_MARK, VI1_G3_MARK,
3799 VI1_G4_MARK, VI1_G5_MARK,
3800 VI1_G6_MARK, VI1_G7_MARK,
3801 /* R */
3802 VI1_R2_MARK, VI1_R3_MARK,
3803 VI1_R4_MARK, VI1_R5_MARK,
3804 VI1_R6_MARK, VI1_R7_MARK,
3805};
3806static const unsigned int vin1_sync_pins[] = {
3807 RCAR_GP_PIN(1, 24), /* HSYNC */
3808 RCAR_GP_PIN(1, 25), /* VSYNC */
3809};
3810static const unsigned int vin1_sync_mux[] = {
3811 VI1_HSYNC_N_MARK,
3812 VI1_VSYNC_N_MARK,
3813};
3814static const unsigned int vin1_field_pins[] = {
3815 RCAR_GP_PIN(1, 13),
3816};
3817static const unsigned int vin1_field_mux[] = {
3818 VI1_FIELD_MARK,
3819};
3820static const unsigned int vin1_clkenb_pins[] = {
3821 RCAR_GP_PIN(1, 26),
3822};
3823static const unsigned int vin1_clkenb_mux[] = {
3824 VI1_CLKENB_MARK,
e120cacf
SU		 3825};
3826static const unsigned int vin1_clk_pins[] = {
3827 RCAR_GP_PIN(2, 9),
3828};
3829static const unsigned int vin1_clk_mux[] = {
3830 VI1_CLK_MARK,
3831};
054d4259
VB		 3832/* - VIN2 ----------------------------------------------------------------- */
3833static const union vin_data vin2_data_pins = {
3834 .data24 = {
3835 /* B */
3836 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3837 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3838 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3839 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3840 /* G */
3841 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3842 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3843 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3844 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3845 /* R */
3846 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3847 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3848 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3849 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3850 },
3851};
3852static const union vin_data vin2_data_mux = {
3853 .data24 = {
3854 /* B */
3855 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3856 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3857 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3858 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3859 /* G */
3860 VI2_G0_MARK, VI2_G1_MARK,
3861 VI2_G2_MARK, VI2_G3_MARK,
3862 VI2_G4_MARK, VI2_G5_MARK,
3863 VI2_G6_MARK, VI2_G7_MARK,
3864 /* R */
3865 VI2_R0_MARK, VI2_R1_MARK,
3866 VI2_R2_MARK, VI2_R3_MARK,
3867 VI2_R4_MARK, VI2_R5_MARK,
3868 VI2_R6_MARK, VI2_R7_MARK,
3869 },
3870};
3871static const unsigned int vin2_data18_pins[] = {
3872 /* B */
3873 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3874 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3875 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3876 /* G */
3877 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3878 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3879 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3880 /* R */
3881 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3882 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3883 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3884};
3885static const unsigned int vin2_data18_mux[] = {
3886 /* B */
3887 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3888 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3889 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3890 /* G */
3891 VI2_G2_MARK, VI2_G3_MARK,
3892 VI2_G4_MARK, VI2_G5_MARK,
3893 VI2_G6_MARK, VI2_G7_MARK,
3894 /* R */
3895 VI2_R2_MARK, VI2_R3_MARK,
3896 VI2_R4_MARK, VI2_R5_MARK,
3897 VI2_R6_MARK, VI2_R7_MARK,
3898};
3899static const unsigned int vin2_sync_pins[] = {
3900 RCAR_GP_PIN(1, 16), /* HSYNC */
3901 RCAR_GP_PIN(1, 21), /* VSYNC */
3902};
3903static const unsigned int vin2_sync_mux[] = {
3904 VI2_HSYNC_N_MARK,
3905 VI2_VSYNC_N_MARK,
3906};
3907static const unsigned int vin2_field_pins[] = {
3908 RCAR_GP_PIN(1, 9),
3909};
3910static const unsigned int vin2_field_mux[] = {
3911 VI2_FIELD_MARK,
3912};
3913static const unsigned int vin2_clkenb_pins[] = {
3914 RCAR_GP_PIN(1, 8),
3915};
3916static const unsigned int vin2_clkenb_mux[] = {
3917 VI2_CLKENB_MARK,
3918};
3919static const unsigned int vin2_clk_pins[] = {
3920 RCAR_GP_PIN(1, 11),
3921};
3922static const unsigned int vin2_clk_mux[] = {
3923 VI2_CLK_MARK,
3924};
3925/* - VIN3 ----------------------------------------------------------------- */
3926static const unsigned int vin3_data8_pins[] = {
3927 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3928 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3929 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3930 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3931};
3932static const unsigned int vin3_data8_mux[] = {
3933 VI3_DATA0_MARK, VI3_DATA1_MARK,
3934 VI3_DATA2_MARK, VI3_DATA3_MARK,
3935 VI3_DATA4_MARK, VI3_DATA5_MARK,
3936 VI3_DATA6_MARK, VI3_DATA7_MARK,
3937};
3938static const unsigned int vin3_sync_pins[] = {
3939 RCAR_GP_PIN(1, 16), /* HSYNC */
3940 RCAR_GP_PIN(1, 17), /* VSYNC */
3941};
3942static const unsigned int vin3_sync_mux[] = {
3943 VI3_HSYNC_N_MARK,
646ae3ef 3944 VI3_VSYNC_N_MARK,
054d4259
VB		 3945};
3946static const unsigned int vin3_field_pins[] = {
3947 RCAR_GP_PIN(1, 15),
3948};
3949static const unsigned int vin3_field_mux[] = {
3950 VI3_FIELD_MARK,
3951};
3952static const unsigned int vin3_clkenb_pins[] = {
3953 RCAR_GP_PIN(1, 14),
3954};
3955static const unsigned int vin3_clkenb_mux[] = {
3956 VI3_CLKENB_MARK,
3957};
3958static const unsigned int vin3_clk_pins[] = {
3959 RCAR_GP_PIN(1, 23),
3960};
3961static const unsigned int vin3_clk_mux[] = {
3962 VI3_CLK_MARK,
3963};
066f0d6e 3964
1627769b 3965static const struct sh_pfc_pin_group pinmux_groups[] = {
fcec5b22
KM		 3966 SH_PFC_PIN_GROUP(audio_clk_a),
3967 SH_PFC_PIN_GROUP(audio_clk_b),
3968 SH_PFC_PIN_GROUP(audio_clk_c),
3969 SH_PFC_PIN_GROUP(audio_clkout),
3970 SH_PFC_PIN_GROUP(audio_clkout_b),
3971 SH_PFC_PIN_GROUP(audio_clkout_c),
3972 SH_PFC_PIN_GROUP(audio_clkout_d),
19ef697d
SS		 3973 SH_PFC_PIN_GROUP(avb_link),
3974 SH_PFC_PIN_GROUP(avb_magic),
3975 SH_PFC_PIN_GROUP(avb_phy_int),
3976 SH_PFC_PIN_GROUP(avb_mdio),
3977 SH_PFC_PIN_GROUP(avb_mii),
3978 SH_PFC_PIN_GROUP(avb_gmii),
62783b71
LP		 3979 SH_PFC_PIN_GROUP(du_rgb666),
3980 SH_PFC_PIN_GROUP(du_rgb888),
3981 SH_PFC_PIN_GROUP(du_clk_out_0),
3982 SH_PFC_PIN_GROUP(du_clk_out_1),
3983 SH_PFC_PIN_GROUP(du_sync_0),
3984 SH_PFC_PIN_GROUP(du_sync_1),
3985 SH_PFC_PIN_GROUP(du_cde),
3986 SH_PFC_PIN_GROUP(du0_clk_in),
3987 SH_PFC_PIN_GROUP(du1_clk_in),
3988 SH_PFC_PIN_GROUP(du2_clk_in),
1627769b
LP		 3989 SH_PFC_PIN_GROUP(eth_link),
3990 SH_PFC_PIN_GROUP(eth_magic),
3991 SH_PFC_PIN_GROUP(eth_mdio),
3992 SH_PFC_PIN_GROUP(eth_rmii),
fbd0ca3d
UH		 3993 SH_PFC_PIN_GROUP(hscif0_data),
3994 SH_PFC_PIN_GROUP(hscif0_clk),
3995 SH_PFC_PIN_GROUP(hscif0_ctrl),
3996 SH_PFC_PIN_GROUP(hscif0_data_b),
3997 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3998 SH_PFC_PIN_GROUP(hscif0_data_c),
3999 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
4000 SH_PFC_PIN_GROUP(hscif0_data_d),
4001 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
4002 SH_PFC_PIN_GROUP(hscif0_data_e),
4003 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
4004 SH_PFC_PIN_GROUP(hscif0_data_f),
4005 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
4006 SH_PFC_PIN_GROUP(hscif1_data),
4007 SH_PFC_PIN_GROUP(hscif1_clk),
4008 SH_PFC_PIN_GROUP(hscif1_ctrl),
4009 SH_PFC_PIN_GROUP(hscif1_data_b),
4010 SH_PFC_PIN_GROUP(hscif1_clk_b),
4011 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
35a493de 4012 SH_PFC_PIN_GROUP(i2c0),
70702bfc
UH		 4013 SH_PFC_PIN_GROUP(i2c1),
4014 SH_PFC_PIN_GROUP(i2c1_b),
4015 SH_PFC_PIN_GROUP(i2c1_c),
4016 SH_PFC_PIN_GROUP(i2c2),
4017 SH_PFC_PIN_GROUP(i2c2_b),
4018 SH_PFC_PIN_GROUP(i2c2_c),
4019 SH_PFC_PIN_GROUP(i2c2_d),
4020 SH_PFC_PIN_GROUP(i2c2_e),
f6aaaac9 4021 SH_PFC_PIN_GROUP(i2c3),
a16b81dc
WS		 4022 SH_PFC_PIN_GROUP(iic0),
4023 SH_PFC_PIN_GROUP(iic1),
4024 SH_PFC_PIN_GROUP(iic1_b),
4025 SH_PFC_PIN_GROUP(iic1_c),
4026 SH_PFC_PIN_GROUP(iic2),
4027 SH_PFC_PIN_GROUP(iic2_b),
4028 SH_PFC_PIN_GROUP(iic2_c),
4029 SH_PFC_PIN_GROUP(iic2_d),
4030 SH_PFC_PIN_GROUP(iic2_e),
4031 SH_PFC_PIN_GROUP(iic3),
04e7ce78
LP		 4032 SH_PFC_PIN_GROUP(intc_irq0),
4033 SH_PFC_PIN_GROUP(intc_irq1),
4034 SH_PFC_PIN_GROUP(intc_irq2),
4035 SH_PFC_PIN_GROUP(intc_irq3),
e29a4c3a 4036 SH_PFC_PIN_GROUP(mlb_3pin),
fbd0ca3d
UH		 4037 SH_PFC_PIN_GROUP(mmc0_data1),
4038 SH_PFC_PIN_GROUP(mmc0_data4),
4039 SH_PFC_PIN_GROUP(mmc0_data8),
4040 SH_PFC_PIN_GROUP(mmc0_ctrl),
4041 SH_PFC_PIN_GROUP(mmc1_data1),
4042 SH_PFC_PIN_GROUP(mmc1_data4),
4043 SH_PFC_PIN_GROUP(mmc1_data8),
4044 SH_PFC_PIN_GROUP(mmc1_ctrl),
4f47cc5e
KH		 4045 SH_PFC_PIN_GROUP(msiof0_clk),
4046 SH_PFC_PIN_GROUP(msiof0_sync),
4047 SH_PFC_PIN_GROUP(msiof0_ss1),
4048 SH_PFC_PIN_GROUP(msiof0_ss2),
4049 SH_PFC_PIN_GROUP(msiof0_rx),
4050 SH_PFC_PIN_GROUP(msiof0_tx),
7033168d
GU		 4051 SH_PFC_PIN_GROUP(msiof0_clk_b),
4052 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4053 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4054 SH_PFC_PIN_GROUP(msiof0_rx_b),
4055 SH_PFC_PIN_GROUP(msiof0_tx_b),
4f47cc5e
KH		 4056 SH_PFC_PIN_GROUP(msiof1_clk),
4057 SH_PFC_PIN_GROUP(msiof1_sync),
4058 SH_PFC_PIN_GROUP(msiof1_ss1),
4059 SH_PFC_PIN_GROUP(msiof1_ss2),
4060 SH_PFC_PIN_GROUP(msiof1_rx),
4061 SH_PFC_PIN_GROUP(msiof1_tx),
7033168d
GU		 4062 SH_PFC_PIN_GROUP(msiof1_clk_b),
4063 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4064 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4065 SH_PFC_PIN_GROUP(msiof1_rx_b),
4066 SH_PFC_PIN_GROUP(msiof1_tx_b),
4f47cc5e
KH		 4067 SH_PFC_PIN_GROUP(msiof2_clk),
4068 SH_PFC_PIN_GROUP(msiof2_sync),
4069 SH_PFC_PIN_GROUP(msiof2_ss1),
4070 SH_PFC_PIN_GROUP(msiof2_ss2),
4071 SH_PFC_PIN_GROUP(msiof2_rx),
4072 SH_PFC_PIN_GROUP(msiof2_tx),
4073 SH_PFC_PIN_GROUP(msiof3_clk),
4074 SH_PFC_PIN_GROUP(msiof3_sync),
4075 SH_PFC_PIN_GROUP(msiof3_ss1),
4076 SH_PFC_PIN_GROUP(msiof3_ss2),
4077 SH_PFC_PIN_GROUP(msiof3_rx),
4078 SH_PFC_PIN_GROUP(msiof3_tx),
7033168d
GU		 4079 SH_PFC_PIN_GROUP(msiof3_clk_b),
4080 SH_PFC_PIN_GROUP(msiof3_sync_b),
4081 SH_PFC_PIN_GROUP(msiof3_rx_b),
4082 SH_PFC_PIN_GROUP(msiof3_tx_b),
5c89c15b
YS		 4083 SH_PFC_PIN_GROUP(pwm0),
4084 SH_PFC_PIN_GROUP(pwm0_b),
4085 SH_PFC_PIN_GROUP(pwm1),
4086 SH_PFC_PIN_GROUP(pwm1_b),
4087 SH_PFC_PIN_GROUP(pwm2),
4088 SH_PFC_PIN_GROUP(pwm3),
4089 SH_PFC_PIN_GROUP(pwm4),
4090 SH_PFC_PIN_GROUP(pwm5),
4091 SH_PFC_PIN_GROUP(pwm6),
202909cd
GU		 4092 SH_PFC_PIN_GROUP(qspi_ctrl),
4093 SH_PFC_PIN_GROUP(qspi_data2),
4094 SH_PFC_PIN_GROUP(qspi_data4),
45c6c85d
LP		 4095 SH_PFC_PIN_GROUP(scif0_data),
4096 SH_PFC_PIN_GROUP(scif0_clk),
4097 SH_PFC_PIN_GROUP(scif0_ctrl),
4098 SH_PFC_PIN_GROUP(scif0_data_b),
4099 SH_PFC_PIN_GROUP(scif1_data),
4100 SH_PFC_PIN_GROUP(scif1_clk),
4101 SH_PFC_PIN_GROUP(scif1_ctrl),
4102 SH_PFC_PIN_GROUP(scif1_data_b),
4103 SH_PFC_PIN_GROUP(scif1_data_c),
4104 SH_PFC_PIN_GROUP(scif1_data_d),
4105 SH_PFC_PIN_GROUP(scif1_clk_d),
4106 SH_PFC_PIN_GROUP(scif1_data_e),
4107 SH_PFC_PIN_GROUP(scif1_clk_e),
2dbe7f2c
LP		 4108 SH_PFC_PIN_GROUP(scif2_data),
4109 SH_PFC_PIN_GROUP(scif2_clk),
4110 SH_PFC_PIN_GROUP(scif2_data_b),
45c6c85d
LP		 4111 SH_PFC_PIN_GROUP(scifa0_data),
4112 SH_PFC_PIN_GROUP(scifa0_clk),
4113 SH_PFC_PIN_GROUP(scifa0_ctrl),
4114 SH_PFC_PIN_GROUP(scifa0_data_b),
4115 SH_PFC_PIN_GROUP(scifa0_clk_b),
4116 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4117 SH_PFC_PIN_GROUP(scifa1_data),
4118 SH_PFC_PIN_GROUP(scifa1_clk),
4119 SH_PFC_PIN_GROUP(scifa1_ctrl),
4120 SH_PFC_PIN_GROUP(scifa1_data_b),
4121 SH_PFC_PIN_GROUP(scifa1_clk_b),
4122 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4123 SH_PFC_PIN_GROUP(scifa1_data_c),
4124 SH_PFC_PIN_GROUP(scifa1_clk_c),
4125 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4126 SH_PFC_PIN_GROUP(scifa1_data_d),
4127 SH_PFC_PIN_GROUP(scifa1_clk_d),
4128 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4129 SH_PFC_PIN_GROUP(scifa2_data),
4130 SH_PFC_PIN_GROUP(scifa2_clk),
4131 SH_PFC_PIN_GROUP(scifa2_ctrl),
4132 SH_PFC_PIN_GROUP(scifa2_data_b),
4133 SH_PFC_PIN_GROUP(scifa2_data_c),
4134 SH_PFC_PIN_GROUP(scifa2_clk_c),
4135 SH_PFC_PIN_GROUP(scifb0_data),
4136 SH_PFC_PIN_GROUP(scifb0_clk),
4137 SH_PFC_PIN_GROUP(scifb0_ctrl),
4138 SH_PFC_PIN_GROUP(scifb0_data_b),
4139 SH_PFC_PIN_GROUP(scifb0_clk_b),
4140 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4141 SH_PFC_PIN_GROUP(scifb0_data_c),
4142 SH_PFC_PIN_GROUP(scifb1_data),
4143 SH_PFC_PIN_GROUP(scifb1_clk),
4144 SH_PFC_PIN_GROUP(scifb1_ctrl),
4145 SH_PFC_PIN_GROUP(scifb1_data_b),
4146 SH_PFC_PIN_GROUP(scifb1_clk_b),
4147 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4148 SH_PFC_PIN_GROUP(scifb1_data_c),
4149 SH_PFC_PIN_GROUP(scifb1_data_d),
4150 SH_PFC_PIN_GROUP(scifb1_data_e),
4151 SH_PFC_PIN_GROUP(scifb1_clk_e),
4152 SH_PFC_PIN_GROUP(scifb1_data_f),
4153 SH_PFC_PIN_GROUP(scifb1_data_g),
4154 SH_PFC_PIN_GROUP(scifb1_clk_g),
4155 SH_PFC_PIN_GROUP(scifb2_data),
4156 SH_PFC_PIN_GROUP(scifb2_clk),
4157 SH_PFC_PIN_GROUP(scifb2_ctrl),
4158 SH_PFC_PIN_GROUP(scifb2_data_b),
4159 SH_PFC_PIN_GROUP(scifb2_clk_b),
4160 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4161 SH_PFC_PIN_GROUP(scifb2_data_c),
066f0d6e
GL		 4162 SH_PFC_PIN_GROUP(sdhi0_data1),
4163 SH_PFC_PIN_GROUP(sdhi0_data4),
4164 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4165 SH_PFC_PIN_GROUP(sdhi0_cd),
4166 SH_PFC_PIN_GROUP(sdhi0_wp),
4167 SH_PFC_PIN_GROUP(sdhi1_data1),
4168 SH_PFC_PIN_GROUP(sdhi1_data4),
4169 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4170 SH_PFC_PIN_GROUP(sdhi1_cd),
4171 SH_PFC_PIN_GROUP(sdhi1_wp),
4172 SH_PFC_PIN_GROUP(sdhi2_data1),
4173 SH_PFC_PIN_GROUP(sdhi2_data4),
4174 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4175 SH_PFC_PIN_GROUP(sdhi2_cd),
4176 SH_PFC_PIN_GROUP(sdhi2_wp),
4177 SH_PFC_PIN_GROUP(sdhi3_data1),
4178 SH_PFC_PIN_GROUP(sdhi3_data4),
4179 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4180 SH_PFC_PIN_GROUP(sdhi3_cd),
4181 SH_PFC_PIN_GROUP(sdhi3_wp),
1d7b59a0
KM		 4182 SH_PFC_PIN_GROUP(ssi0_data),
4183 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4184 SH_PFC_PIN_GROUP(ssi1_data),
4185 SH_PFC_PIN_GROUP(ssi1_ctrl),
4186 SH_PFC_PIN_GROUP(ssi2_data),
4187 SH_PFC_PIN_GROUP(ssi2_ctrl),
4188 SH_PFC_PIN_GROUP(ssi3_data),
4189 SH_PFC_PIN_GROUP(ssi34_ctrl),
4190 SH_PFC_PIN_GROUP(ssi4_data),
4191 SH_PFC_PIN_GROUP(ssi4_ctrl),
4192 SH_PFC_PIN_GROUP(ssi5),
4193 SH_PFC_PIN_GROUP(ssi5_b),
4194 SH_PFC_PIN_GROUP(ssi5_c),
4195 SH_PFC_PIN_GROUP(ssi6),
4196 SH_PFC_PIN_GROUP(ssi6_b),
4197 SH_PFC_PIN_GROUP(ssi7_data),
4198 SH_PFC_PIN_GROUP(ssi7_b_data),
4199 SH_PFC_PIN_GROUP(ssi7_c_data),
4200 SH_PFC_PIN_GROUP(ssi78_ctrl),
4201 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4202 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4203 SH_PFC_PIN_GROUP(ssi8_data),
4204 SH_PFC_PIN_GROUP(ssi8_b_data),
4205 SH_PFC_PIN_GROUP(ssi8_c_data),
4206 SH_PFC_PIN_GROUP(ssi9_data),
4207 SH_PFC_PIN_GROUP(ssi9_ctrl),
fbd0ca3d
UH		 4208 SH_PFC_PIN_GROUP(tpu0_to0),
4209 SH_PFC_PIN_GROUP(tpu0_to1),
4210 SH_PFC_PIN_GROUP(tpu0_to2),
4211 SH_PFC_PIN_GROUP(tpu0_to3),
dac896e2 4212 SH_PFC_PIN_GROUP(usb0),
97e00faa 4213 SH_PFC_PIN_GROUP(usb0_ovc_vbus),
dac896e2
SU		 4214 SH_PFC_PIN_GROUP(usb1),
4215 SH_PFC_PIN_GROUP(usb2),
64fe8abc
VB		 4216 VIN_DATA_PIN_GROUP(vin0_data, 24),
4217 VIN_DATA_PIN_GROUP(vin0_data, 20),
4218 SH_PFC_PIN_GROUP(vin0_data18),
4219 VIN_DATA_PIN_GROUP(vin0_data, 16),
4220 VIN_DATA_PIN_GROUP(vin0_data, 12),
4221 VIN_DATA_PIN_GROUP(vin0_data, 10),
4222 VIN_DATA_PIN_GROUP(vin0_data, 8),
4223 VIN_DATA_PIN_GROUP(vin0_data, 4),
a9e4c7bb 4224 SH_PFC_PIN_GROUP(vin0_sync),
7a57be87
VB		 4225 SH_PFC_PIN_GROUP(vin0_field),
4226 SH_PFC_PIN_GROUP(vin0_clkenb),
e120cacf 4227 SH_PFC_PIN_GROUP(vin0_clk),
317a03a9
VB		 4228 VIN_DATA_PIN_GROUP(vin1_data, 24),
4229 VIN_DATA_PIN_GROUP(vin1_data, 20),
4230 SH_PFC_PIN_GROUP(vin1_data18),
4231 VIN_DATA_PIN_GROUP(vin1_data, 16),
4232 VIN_DATA_PIN_GROUP(vin1_data, 12),
4233 VIN_DATA_PIN_GROUP(vin1_data, 10),
4234 VIN_DATA_PIN_GROUP(vin1_data, 8),
4235 VIN_DATA_PIN_GROUP(vin1_data, 4),
4236 SH_PFC_PIN_GROUP(vin1_sync),
4237 SH_PFC_PIN_GROUP(vin1_field),
4238 SH_PFC_PIN_GROUP(vin1_clkenb),
e120cacf 4239 SH_PFC_PIN_GROUP(vin1_clk),
054d4259
VB		 4240 VIN_DATA_PIN_GROUP(vin2_data, 24),
4241 SH_PFC_PIN_GROUP(vin2_data18),
4242 VIN_DATA_PIN_GROUP(vin2_data, 16),
4243 VIN_DATA_PIN_GROUP(vin2_data, 8),
4244 VIN_DATA_PIN_GROUP(vin2_data, 4),
4245 SH_PFC_PIN_GROUP(vin2_sync),
4246 SH_PFC_PIN_GROUP(vin2_field),
4247 SH_PFC_PIN_GROUP(vin2_clkenb),
4248 SH_PFC_PIN_GROUP(vin2_clk),
4249 SH_PFC_PIN_GROUP(vin3_data8),
4250 SH_PFC_PIN_GROUP(vin3_sync),
4251 SH_PFC_PIN_GROUP(vin3_field),
4252 SH_PFC_PIN_GROUP(vin3_clkenb),
4253 SH_PFC_PIN_GROUP(vin3_clk),
1627769b
LP		 4254};
4255
fcec5b22
KM		 4256static const char * const audio_clk_groups[] = {
4257 "audio_clk_a",
4258 "audio_clk_b",
4259 "audio_clk_c",
4260 "audio_clkout",
4261 "audio_clkout_b",
4262 "audio_clkout_c",
4263 "audio_clkout_d",
4264};
4265
19ef697d
SS		 4266static const char * const avb_groups[] = {
4267 "avb_link",
4268 "avb_magic",
4269 "avb_phy_int",
4270 "avb_mdio",
4271 "avb_mii",
4272 "avb_gmii",
4273};
4274
62783b71
LP		 4275static const char * const du_groups[] = {
4276 "du_rgb666",
4277 "du_rgb888",
4278 "du_clk_out_0",
4279 "du_clk_out_1",
4280 "du_sync_0",
4281 "du_sync_1",
4282 "du_cde",
4283};
4284
4285static const char * const du0_groups[] = {
4286 "du0_clk_in",
4287};
4288
4289static const char * const du1_groups[] = {
4290 "du1_clk_in",
4291};
4292
4293static const char * const du2_groups[] = {
4294 "du2_clk_in",
4295};
4296
1627769b
LP		 4297static const char * const eth_groups[] = {
4298 "eth_link",
4299 "eth_magic",
4300 "eth_mdio",
4301 "eth_rmii",
4302};
4303
457c11d3
LP		 4304static const char * const hscif0_groups[] = {
4305 "hscif0_data",
4306 "hscif0_clk",
4307 "hscif0_ctrl",
4308 "hscif0_data_b",
4309 "hscif0_ctrl_b",
4310 "hscif0_data_c",
4311 "hscif0_ctrl_c",
4312 "hscif0_data_d",
4313 "hscif0_ctrl_d",
4314 "hscif0_data_e",
4315 "hscif0_ctrl_e",
4316 "hscif0_data_f",
4317 "hscif0_ctrl_f",
4318};
4319
4320static const char * const hscif1_groups[] = {
4321 "hscif1_data",
4322 "hscif1_clk",
4323 "hscif1_ctrl",
4324 "hscif1_data_b",
4325 "hscif1_clk_b",
4326 "hscif1_ctrl_b",
4327};
4328
35a493de
WS		 4329static const char * const i2c0_groups[] = {
4330 "i2c0",
4331};
4332
70702bfc
UH		 4333static const char * const i2c1_groups[] = {
4334 "i2c1",
4335 "i2c1_b",
4336 "i2c1_c",
4337};
4338
4339static const char * const i2c2_groups[] = {
4340 "i2c2",
4341 "i2c2_b",
4342 "i2c2_c",
4343 "i2c2_d",
4344 "i2c2_e",
4345};
4346
f6aaaac9
GL		 4347static const char * const i2c3_groups[] = {
4348 "i2c3",
4349};
4350
a16b81dc
WS		 4351static const char * const iic0_groups[] = {
4352 "iic0",
4353};
4354
4355static const char * const iic1_groups[] = {
4356 "iic1",
4357 "iic1_b",
4358 "iic1_c",
4359};
4360
4361static const char * const iic2_groups[] = {
4362 "iic2",
4363 "iic2_b",
4364 "iic2_c",
4365 "iic2_d",
4366 "iic2_e",
4367};
4368
4369static const char * const iic3_groups[] = {
4370 "iic3",
4371};
4372
04e7ce78
LP		 4373static const char * const intc_groups[] = {
4374 "intc_irq0",
4375 "intc_irq1",
4376 "intc_irq2",
4377 "intc_irq3",
4378};
45c6c85d 4379
e29a4c3a
SS		 4380static const char * const mlb_groups[] = {
4381 "mlb_3pin",
4382};
4383
457c11d3
LP		 4384static const char * const mmc0_groups[] = {
4385 "mmc0_data1",
4386 "mmc0_data4",
4387 "mmc0_data8",
4388 "mmc0_ctrl",
4389};
4390
4391static const char * const mmc1_groups[] = {
4392 "mmc1_data1",
4393 "mmc1_data4",
4394 "mmc1_data8",
4395 "mmc1_ctrl",
4396};
4397
4f47cc5e
KH		 4398static const char * const msiof0_groups[] = {
4399 "msiof0_clk",
4400 "msiof0_sync",
4401 "msiof0_ss1",
4402 "msiof0_ss2",
4403 "msiof0_rx",
4404 "msiof0_tx",
7033168d
GU		 4405 "msiof0_clk_b",
4406 "msiof0_ss1_b",
4407 "msiof0_ss2_b",
4408 "msiof0_rx_b",
4409 "msiof0_tx_b",
4f47cc5e
KH		 4410};
4411
4412static const char * const msiof1_groups[] = {
4413 "msiof1_clk",
4414 "msiof1_sync",
4415 "msiof1_ss1",
4416 "msiof1_ss2",
4417 "msiof1_rx",
4418 "msiof1_tx",
7033168d
GU		 4419 "msiof1_clk_b",
4420 "msiof1_ss1_b",
4421 "msiof1_ss2_b",
4422 "msiof1_rx_b",
4423 "msiof1_tx_b",
4f47cc5e
KH		 4424};
4425
4426static const char * const msiof2_groups[] = {
4427 "msiof2_clk",
4428 "msiof2_sync",
4429 "msiof2_ss1",
4430 "msiof2_ss2",
4431 "msiof2_rx",
4432 "msiof2_tx",
4433};
4434
4435static const char * const msiof3_groups[] = {
4436 "msiof3_clk",
4437 "msiof3_sync",
4438 "msiof3_ss1",
4439 "msiof3_ss2",
4440 "msiof3_rx",
4441 "msiof3_tx",
7033168d
GU		 4442 "msiof3_clk_b",
4443 "msiof3_sync_b",
4444 "msiof3_rx_b",
4445 "msiof3_tx_b",
4f47cc5e
KH		 4446};
4447
5c89c15b
YS		 4448static const char * const pwm0_groups[] = {
4449 "pwm0",
4450 "pwm0_b",
4451};
4452
4453static const char * const pwm1_groups[] = {
4454 "pwm1",
4455 "pwm1_b",
4456};
4457
4458static const char * const pwm2_groups[] = {
4459 "pwm2",
4460};
4461
4462static const char * const pwm3_groups[] = {
4463 "pwm3",
4464};
4465
4466static const char * const pwm4_groups[] = {
4467 "pwm4",
4468};
4469
4470static const char * const pwm5_groups[] = {
4471 "pwm5",
4472};
4473
4474static const char * const pwm6_groups[] = {
4475 "pwm6",
4476};
4477
202909cd
GU		 4478static const char * const qspi_groups[] = {
4479 "qspi_ctrl",
4480 "qspi_data2",
4481 "qspi_data4",
4482};
4483
45c6c85d
LP		 4484static const char * const scif0_groups[] = {
4485 "scif0_data",
4486 "scif0_clk",
4487 "scif0_ctrl",
4488 "scif0_data_b",
4489};
4490
4491static const char * const scif1_groups[] = {
4492 "scif1_data",
4493 "scif1_clk",
4494 "scif1_ctrl",
4495 "scif1_data_b",
4496 "scif1_data_c",
4497 "scif1_data_d",
4498 "scif1_clk_d",
4499 "scif1_data_e",
4500 "scif1_clk_e",
4501};
4502
2dbe7f2c
LP		 4503static const char * const scif2_groups[] = {
4504 "scif2_data",
4505 "scif2_clk",
4506 "scif2_data_b",
fbd0ca3d
UH		 4507};
4508
45c6c85d
LP		 4509static const char * const scifa0_groups[] = {
4510 "scifa0_data",
4511 "scifa0_clk",
4512 "scifa0_ctrl",
4513 "scifa0_data_b",
4514 "scifa0_clk_b",
4515 "scifa0_ctrl_b",
4516};
4517
4518static const char * const scifa1_groups[] = {
4519 "scifa1_data",
4520 "scifa1_clk",
4521 "scifa1_ctrl",
4522 "scifa1_data_b",
4523 "scifa1_clk_b",
4524 "scifa1_ctrl_b",
4525 "scifa1_data_c",
4526 "scifa1_clk_c",
4527 "scifa1_ctrl_c",
4528 "scifa1_data_d",
4529 "scifa1_clk_d",
4530 "scifa1_ctrl_d",
4531};
4532
4533static const char * const scifa2_groups[] = {
4534 "scifa2_data",
4535 "scifa2_clk",
4536 "scifa2_ctrl",
4537 "scifa2_data_b",
4538 "scifa2_data_c",
4539 "scifa2_clk_c",
4540};
4541
4542static const char * const scifb0_groups[] = {
4543 "scifb0_data",
4544 "scifb0_clk",
4545 "scifb0_ctrl",
4546 "scifb0_data_b",
4547 "scifb0_clk_b",
4548 "scifb0_ctrl_b",
4549 "scifb0_data_c",
4550};
4551
4552static const char * const scifb1_groups[] = {
4553 "scifb1_data",
4554 "scifb1_clk",
4555 "scifb1_ctrl",
4556 "scifb1_data_b",
4557 "scifb1_clk_b",
4558 "scifb1_ctrl_b",
4559 "scifb1_data_c",
4560 "scifb1_data_d",
4561 "scifb1_data_e",
4562 "scifb1_clk_e",
4563 "scifb1_data_f",
4564 "scifb1_data_g",
4565 "scifb1_clk_g",
4566};
4567
4568static const char * const scifb2_groups[] = {
4569 "scifb2_data",
4570 "scifb2_clk",
4571 "scifb2_ctrl",
4572 "scifb2_data_b",
4573 "scifb2_clk_b",
4574 "scifb2_ctrl_b",
4575 "scifb2_data_c",
4576};
4577
066f0d6e
GL		 4578static const char * const sdhi0_groups[] = {
4579 "sdhi0_data1",
4580 "sdhi0_data4",
4581 "sdhi0_ctrl",
4582 "sdhi0_cd",
4583 "sdhi0_wp",
4584};
4585
4586static const char * const sdhi1_groups[] = {
4587 "sdhi1_data1",
4588 "sdhi1_data4",
4589 "sdhi1_ctrl",
4590 "sdhi1_cd",
4591 "sdhi1_wp",
4592};
4593
4594static const char * const sdhi2_groups[] = {
4595 "sdhi2_data1",
4596 "sdhi2_data4",
4597 "sdhi2_ctrl",
4598 "sdhi2_cd",
4599 "sdhi2_wp",
4600};
4601
4602static const char * const sdhi3_groups[] = {
4603 "sdhi3_data1",
4604 "sdhi3_data4",
4605 "sdhi3_ctrl",
4606 "sdhi3_cd",
4607 "sdhi3_wp",
4608};
4609
1d7b59a0
KM		 4610static const char * const ssi_groups[] = {
4611 "ssi0_data",
4612 "ssi0129_ctrl",
4613 "ssi1_data",
4614 "ssi1_ctrl",
4615 "ssi2_data",
4616 "ssi2_ctrl",
4617 "ssi3_data",
4618 "ssi34_ctrl",
4619 "ssi4_data",
4620 "ssi4_ctrl",
4621 "ssi5",
4622 "ssi5_b",
4623 "ssi5_c",
4624 "ssi6",
4625 "ssi6_b",
4626 "ssi7_data",
4627 "ssi7_b_data",
4628 "ssi7_c_data",
4629 "ssi78_ctrl",
4630 "ssi78_b_ctrl",
4631 "ssi78_c_ctrl",
4632 "ssi8_data",
4633 "ssi8_b_data",
4634 "ssi8_c_data",
4635 "ssi9_data",
4636 "ssi9_ctrl",
4637};
4638
457c11d3
LP		 4639static const char * const tpu0_groups[] = {
4640 "tpu0_to0",
4641 "tpu0_to1",
4642 "tpu0_to2",
4643 "tpu0_to3",
4644};
4645
dac896e2
SU		 4646static const char * const usb0_groups[] = {
4647 "usb0",
97e00faa 4648 "usb0_ovc_vbus",
dac896e2
SU		 4649};
4650
4651static const char * const usb1_groups[] = {
4652 "usb1",
4653};
4654
4655static const char * const usb2_groups[] = {
4656 "usb2",
4657};
4658
e120cacf 4659static const char * const vin0_groups[] = {
64fe8abc
VB		 4660 "vin0_data24",
4661 "vin0_data20",
4662 "vin0_data18",
4663 "vin0_data16",
4664 "vin0_data12",
4665 "vin0_data10",
4666 "vin0_data8",
4667 "vin0_data4",
a9e4c7bb 4668 "vin0_sync",
7a57be87
VB		 4669 "vin0_field",
4670 "vin0_clkenb",
e120cacf
SU		 4671 "vin0_clk",
4672};
4673
4674static const char * const vin1_groups[] = {
317a03a9
VB		 4675 "vin1_data24",
4676 "vin1_data20",
4677 "vin1_data18",
4678 "vin1_data16",
4679 "vin1_data12",
4680 "vin1_data10",
4681 "vin1_data8",
4682 "vin1_data4",
4683 "vin1_sync",
4684 "vin1_field",
4685 "vin1_clkenb",
e120cacf
SU		 4686 "vin1_clk",
4687};
4688
054d4259
VB		 4689static const char * const vin2_groups[] = {
4690 "vin2_data24",
4691 "vin2_data18",
4692 "vin2_data16",
4693 "vin2_data8",
4694 "vin2_data4",
4695 "vin2_sync",
4696 "vin2_field",
4697 "vin2_clkenb",
4698 "vin2_clk",
4699};
4700
4701static const char * const vin3_groups[] = {
4702 "vin3_data8",
4703 "vin3_sync",
4704 "vin3_field",
4705 "vin3_clkenb",
4706 "vin3_clk",
4707};
4708
1627769b 4709static const struct sh_pfc_function pinmux_functions[] = {
fcec5b22 4710 SH_PFC_FUNCTION(audio_clk),
19ef697d 4711 SH_PFC_FUNCTION(avb),
62783b71
LP		 4712 SH_PFC_FUNCTION(du),
4713 SH_PFC_FUNCTION(du0),
4714 SH_PFC_FUNCTION(du1),
4715 SH_PFC_FUNCTION(du2),
1627769b 4716 SH_PFC_FUNCTION(eth),
fbd0ca3d
UH		 4717 SH_PFC_FUNCTION(hscif0),
4718 SH_PFC_FUNCTION(hscif1),
35a493de 4719 SH_PFC_FUNCTION(i2c0),
70702bfc
UH		 4720 SH_PFC_FUNCTION(i2c1),
4721 SH_PFC_FUNCTION(i2c2),
f6aaaac9 4722 SH_PFC_FUNCTION(i2c3),
a16b81dc
WS		 4723 SH_PFC_FUNCTION(iic0),
4724 SH_PFC_FUNCTION(iic1),
4725 SH_PFC_FUNCTION(iic2),
4726 SH_PFC_FUNCTION(iic3),
04e7ce78 4727 SH_PFC_FUNCTION(intc),
e29a4c3a 4728 SH_PFC_FUNCTION(mlb),
fbd0ca3d
UH		 4729 SH_PFC_FUNCTION(mmc0),
4730 SH_PFC_FUNCTION(mmc1),
4f47cc5e
KH		 4731 SH_PFC_FUNCTION(msiof0),
4732 SH_PFC_FUNCTION(msiof1),
4733 SH_PFC_FUNCTION(msiof2),
4734 SH_PFC_FUNCTION(msiof3),
5c89c15b
YS		 4735 SH_PFC_FUNCTION(pwm0),
4736 SH_PFC_FUNCTION(pwm1),
4737 SH_PFC_FUNCTION(pwm2),
4738 SH_PFC_FUNCTION(pwm3),
4739 SH_PFC_FUNCTION(pwm4),
4740 SH_PFC_FUNCTION(pwm5),
4741 SH_PFC_FUNCTION(pwm6),
202909cd 4742 SH_PFC_FUNCTION(qspi),
45c6c85d
LP		 4743 SH_PFC_FUNCTION(scif0),
4744 SH_PFC_FUNCTION(scif1),
2dbe7f2c 4745 SH_PFC_FUNCTION(scif2),
45c6c85d
LP		 4746 SH_PFC_FUNCTION(scifa0),
4747 SH_PFC_FUNCTION(scifa1),
4748 SH_PFC_FUNCTION(scifa2),
4749 SH_PFC_FUNCTION(scifb0),
4750 SH_PFC_FUNCTION(scifb1),
4751 SH_PFC_FUNCTION(scifb2),
066f0d6e
GL		 4752 SH_PFC_FUNCTION(sdhi0),
4753 SH_PFC_FUNCTION(sdhi1),
4754 SH_PFC_FUNCTION(sdhi2),
4755 SH_PFC_FUNCTION(sdhi3),
1d7b59a0 4756 SH_PFC_FUNCTION(ssi),
fbd0ca3d 4757 SH_PFC_FUNCTION(tpu0),
dac896e2
SU		 4758 SH_PFC_FUNCTION(usb0),
4759 SH_PFC_FUNCTION(usb1),
4760 SH_PFC_FUNCTION(usb2),
e120cacf
SU		 4761 SH_PFC_FUNCTION(vin0),
4762 SH_PFC_FUNCTION(vin1),
054d4259
VB		 4763 SH_PFC_FUNCTION(vin2),
4764 SH_PFC_FUNCTION(vin3),
1627769b
LP		 4765};
4766
44a45b55 4767static const struct pinmux_cfg_reg pinmux_config_regs[] = {
58c229e1
KM		 4768 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4769 GP_0_31_FN, FN_IP3_17_15,
4770 GP_0_30_FN, FN_IP3_14_12,
4771 GP_0_29_FN, FN_IP3_11_8,
4772 GP_0_28_FN, FN_IP3_7_4,
4773 GP_0_27_FN, FN_IP3_3_0,
4774 GP_0_26_FN, FN_IP2_28_26,
4775 GP_0_25_FN, FN_IP2_25_22,
4776 GP_0_24_FN, FN_IP2_21_18,
4777 GP_0_23_FN, FN_IP2_17_15,
4778 GP_0_22_FN, FN_IP2_14_12,
4779 GP_0_21_FN, FN_IP2_11_9,
4780 GP_0_20_FN, FN_IP2_8_6,
4781 GP_0_19_FN, FN_IP2_5_3,
4782 GP_0_18_FN, FN_IP2_2_0,
4783 GP_0_17_FN, FN_IP1_29_28,
4784 GP_0_16_FN, FN_IP1_27_26,
4785 GP_0_15_FN, FN_IP1_25_22,
4786 GP_0_14_FN, FN_IP1_21_18,
4787 GP_0_13_FN, FN_IP1_17_15,
4788 GP_0_12_FN, FN_IP1_14_12,
4789 GP_0_11_FN, FN_IP1_11_8,
4790 GP_0_10_FN, FN_IP1_7_4,
4791 GP_0_9_FN, FN_IP1_3_0,
4792 GP_0_8_FN, FN_IP0_30_27,
4793 GP_0_7_FN, FN_IP0_26_23,
4794 GP_0_6_FN, FN_IP0_22_20,
4795 GP_0_5_FN, FN_IP0_19_16,
4796 GP_0_4_FN, FN_IP0_15_12,
4797 GP_0_3_FN, FN_IP0_11_9,
4798 GP_0_2_FN, FN_IP0_8_6,
4799 GP_0_1_FN, FN_IP0_5_3,
4800 GP_0_0_FN, FN_IP0_2_0 }
4801 },
4802 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4803 0, 0,
4804 0, 0,
4805 GP_1_29_FN, FN_IP6_13_11,
4806 GP_1_28_FN, FN_IP6_10_9,
4807 GP_1_27_FN, FN_IP6_8_6,
4808 GP_1_26_FN, FN_IP6_5_3,
4809 GP_1_25_FN, FN_IP6_2_0,
4810 GP_1_24_FN, FN_IP5_29_27,
4811 GP_1_23_FN, FN_IP5_26_24,
4812 GP_1_22_FN, FN_IP5_23_21,
4813 GP_1_21_FN, FN_IP5_20_18,
4814 GP_1_20_FN, FN_IP5_17_15,
4815 GP_1_19_FN, FN_IP5_14_13,
4816 GP_1_18_FN, FN_IP5_12_10,
4817 GP_1_17_FN, FN_IP5_9_6,
4818 GP_1_16_FN, FN_IP5_5_3,
4819 GP_1_15_FN, FN_IP5_2_0,
4820 GP_1_14_FN, FN_IP4_29_27,
4821 GP_1_13_FN, FN_IP4_26_24,
4822 GP_1_12_FN, FN_IP4_23_21,
4823 GP_1_11_FN, FN_IP4_20_18,
4824 GP_1_10_FN, FN_IP4_17_15,
4825 GP_1_9_FN, FN_IP4_14_12,
4826 GP_1_8_FN, FN_IP4_11_9,
4827 GP_1_7_FN, FN_IP4_8_6,
4828 GP_1_6_FN, FN_IP4_5_3,
4829 GP_1_5_FN, FN_IP4_2_0,
4830 GP_1_4_FN, FN_IP3_31_29,
4831 GP_1_3_FN, FN_IP3_28_26,
4832 GP_1_2_FN, FN_IP3_25_23,
4833 GP_1_1_FN, FN_IP3_22_20,
4834 GP_1_0_FN, FN_IP3_19_18, }
4835 },
4836 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4837 0, 0,
4838 0, 0,
4839 GP_2_29_FN, FN_IP7_15_13,
4840 GP_2_28_FN, FN_IP7_12_10,
4841 GP_2_27_FN, FN_IP7_9_8,
4842 GP_2_26_FN, FN_IP7_7_6,
4843 GP_2_25_FN, FN_IP7_5_3,
4844 GP_2_24_FN, FN_IP7_2_0,
4845 GP_2_23_FN, FN_IP6_31_29,
4846 GP_2_22_FN, FN_IP6_28_26,
4847 GP_2_21_FN, FN_IP6_25_23,
4848 GP_2_20_FN, FN_IP6_22_20,
4849 GP_2_19_FN, FN_IP6_19_17,
4850 GP_2_18_FN, FN_IP6_16_14,
4851 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4852 GP_2_16_FN, FN_IP8_27,
4853 GP_2_15_FN, FN_IP8_26,
4854 GP_2_14_FN, FN_IP8_25_24,
4855 GP_2_13_FN, FN_IP8_23_22,
4856 GP_2_12_FN, FN_IP8_21_20,
4857 GP_2_11_FN, FN_IP8_19_18,
4858 GP_2_10_FN, FN_IP8_17_16,
4859 GP_2_9_FN, FN_IP8_15_14,
4860 GP_2_8_FN, FN_IP8_13_12,
4861 GP_2_7_FN, FN_IP8_11_10,
4862 GP_2_6_FN, FN_IP8_9_8,
4863 GP_2_5_FN, FN_IP8_7_6,
4864 GP_2_4_FN, FN_IP8_5_4,
4865 GP_2_3_FN, FN_IP8_3_2,
4866 GP_2_2_FN, FN_IP8_1_0,
4867 GP_2_1_FN, FN_IP7_30_29,
4868 GP_2_0_FN, FN_IP7_28_27 }
4869 },
4870 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4871 GP_3_31_FN, FN_IP11_21_18,
4872 GP_3_30_FN, FN_IP11_17_15,
4873 GP_3_29_FN, FN_IP11_14_13,
4874 GP_3_28_FN, FN_IP11_12_11,
4875 GP_3_27_FN, FN_IP11_10_9,
4876 GP_3_26_FN, FN_IP11_8_7,
4877 GP_3_25_FN, FN_IP11_6_5,
4878 GP_3_24_FN, FN_IP11_4,
4879 GP_3_23_FN, FN_IP11_3_0,
4880 GP_3_22_FN, FN_IP10_29_26,
4881 GP_3_21_FN, FN_IP10_25_23,
4882 GP_3_20_FN, FN_IP10_22_19,
4883 GP_3_19_FN, FN_IP10_18_15,
4884 GP_3_18_FN, FN_IP10_14_11,
4885 GP_3_17_FN, FN_IP10_10_7,
4886 GP_3_16_FN, FN_IP10_6_4,
4887 GP_3_15_FN, FN_IP10_3_0,
4888 GP_3_14_FN, FN_IP9_31_28,
4889 GP_3_13_FN, FN_IP9_27_26,
4890 GP_3_12_FN, FN_IP9_25_24,
4891 GP_3_11_FN, FN_IP9_23_22,
4892 GP_3_10_FN, FN_IP9_21_20,
4893 GP_3_9_FN, FN_IP9_19_18,
4894 GP_3_8_FN, FN_IP9_17_16,
4895 GP_3_7_FN, FN_IP9_15_12,
4896 GP_3_6_FN, FN_IP9_11_8,
4897 GP_3_5_FN, FN_IP9_7_6,
4898 GP_3_4_FN, FN_IP9_5_4,
4899 GP_3_3_FN, FN_IP9_3_2,
4900 GP_3_2_FN, FN_IP9_1_0,
4901 GP_3_1_FN, FN_IP8_30_29,
4902 GP_3_0_FN, FN_IP8_28 }
4903 },
4904 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4905 GP_4_31_FN, FN_IP14_18_16,
4906 GP_4_30_FN, FN_IP14_15_12,
4907 GP_4_29_FN, FN_IP14_11_9,
4908 GP_4_28_FN, FN_IP14_8_6,
4909 GP_4_27_FN, FN_IP14_5_3,
4910 GP_4_26_FN, FN_IP14_2_0,
4911 GP_4_25_FN, FN_IP13_30_29,
4912 GP_4_24_FN, FN_IP13_28_26,
4913 GP_4_23_FN, FN_IP13_25_23,
4914 GP_4_22_FN, FN_IP13_22_19,
4915 GP_4_21_FN, FN_IP13_18_16,
4916 GP_4_20_FN, FN_IP13_15_13,
4917 GP_4_19_FN, FN_IP13_12_10,
4918 GP_4_18_FN, FN_IP13_9_7,
4919 GP_4_17_FN, FN_IP13_6_3,
4920 GP_4_16_FN, FN_IP13_2_0,
4921 GP_4_15_FN, FN_IP12_30_28,
4922 GP_4_14_FN, FN_IP12_27_25,
4923 GP_4_13_FN, FN_IP12_24_23,
4924 GP_4_12_FN, FN_IP12_22_20,
4925 GP_4_11_FN, FN_IP12_19_17,
4926 GP_4_10_FN, FN_IP12_16_14,
4927 GP_4_9_FN, FN_IP12_13_11,
4928 GP_4_8_FN, FN_IP12_10_8,
4929 GP_4_7_FN, FN_IP12_7_6,
4930 GP_4_6_FN, FN_IP12_5_4,
4931 GP_4_5_FN, FN_IP12_3_2,
4932 GP_4_4_FN, FN_IP12_1_0,
4933 GP_4_3_FN, FN_IP11_31_30,
4934 GP_4_2_FN, FN_IP11_29_27,
4935 GP_4_1_FN, FN_IP11_26_24,
4936 GP_4_0_FN, FN_IP11_23_22 }
4937 },
4938 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4939 GP_5_31_FN, FN_IP7_24_22,
4940 GP_5_30_FN, FN_IP7_21_19,
4941 GP_5_29_FN, FN_IP7_18_16,
4942 GP_5_28_FN, FN_DU_DOTCLKIN2,
4943 GP_5_27_FN, FN_IP7_26_25,
4944 GP_5_26_FN, FN_DU_DOTCLKIN0,
4945 GP_5_25_FN, FN_AVS2,
4946 GP_5_24_FN, FN_AVS1,
4947 GP_5_23_FN, FN_USB2_OVC,
4948 GP_5_22_FN, FN_USB2_PWEN,
4949 GP_5_21_FN, FN_IP16_7,
4950 GP_5_20_FN, FN_IP16_6,
4951 GP_5_19_FN, FN_USB0_OVC_VBUS,
4952 GP_5_18_FN, FN_USB0_PWEN,
4953 GP_5_17_FN, FN_IP16_5_3,
4954 GP_5_16_FN, FN_IP16_2_0,
4955 GP_5_15_FN, FN_IP15_29_28,
4956 GP_5_14_FN, FN_IP15_27_26,
4957 GP_5_13_FN, FN_IP15_25_23,
4958 GP_5_12_FN, FN_IP15_22_20,
4959 GP_5_11_FN, FN_IP15_19_18,
4960 GP_5_10_FN, FN_IP15_17_16,
4961 GP_5_9_FN, FN_IP15_15_14,
4962 GP_5_8_FN, FN_IP15_13_12,
4963 GP_5_7_FN, FN_IP15_11_9,
4964 GP_5_6_FN, FN_IP15_8_6,
4965 GP_5_5_FN, FN_IP15_5_3,
4966 GP_5_4_FN, FN_IP15_2_0,
4967 GP_5_3_FN, FN_IP14_30_28,
4968 GP_5_2_FN, FN_IP14_27_25,
4969 GP_5_1_FN, FN_IP14_24_22,
4970 GP_5_0_FN, FN_IP14_21_19 }
4971 },
4972 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4973 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4974 /* IP0_31 [1] */
4975 0, 0,
4976 /* IP0_30_27 [4] */
9f2edd41 4977 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
58c229e1
KM		 4978 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4979 0, 0, 0, 0, 0, 0, 0, 0, 0,
4980 /* IP0_26_23 [4] */
c4721249
SK		 4981 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4982 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
05bcb07b 4983 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1 4984 /* IP0_22_20 [3] */
c4721249
SK		 4985 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4986 FN_I2C2_SCL_C, 0, 0,
58c229e1
KM		 4987 /* IP0_19_16 [4] */
4988 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4989 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4990 0, 0, 0, 0, 0, 0, 0, 0, 0,
4991 /* IP0_15_12 [4] */
4992 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4993 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4994 0, 0, 0, 0, 0, 0, 0, 0, 0,
4995 /* IP0_11_9 [3] */
4996 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4997 0, 0, 0,
4998 /* IP0_8_6 [3] */
4999 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
5000 0, 0, 0,
5001 /* IP0_5_3 [3] */
5002 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5003 0, 0, 0,
5004 /* IP0_2_0 [3] */
5005 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5006 0, 0, 0, }
5007 },
5008 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5009 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
5010 /* IP1_31_30 [2] */
5011 0, 0, 0, 0,
5012 /* IP1_29_28 [2] */
5013 FN_A1, FN_PWM4, 0, 0,
5014 /* IP1_27_26 [2] */
5015 FN_A0, FN_PWM3, 0, 0,
5016 /* IP1_25_22 [4] */
5017 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5018 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5019 0, 0, 0, 0, 0, 0, 0, 0, 0,
5020 /* IP1_21_18 [4] */
5021 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5022 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5023 0, 0, 0, 0, 0, 0, 0, 0, 0,
5024 /* IP1_17_15 [3] */
5025 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5026 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5027 0, 0, 0,
5028 /* IP1_14_12 [3] */
5029 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5030 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5031 0, 0,
5032 /* IP1_11_8 [4] */
9f2edd41 5033 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
58c229e1
KM		 5034 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5035 0, 0, 0, 0, 0, 0, 0, 0, 0,
5036 /* IP1_7_4 [4] */
9f2edd41 5037 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
58c229e1
KM		 5038 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5039 0, 0, 0, 0, 0, 0, 0, 0, 0,
5040 /* IP1_3_0 [4] */
9f2edd41 5041 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
58c229e1
KM		 5042 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5043 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5044 },
5045 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5046 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5047 /* IP2_31_29 [3] */
5048 0, 0, 0, 0, 0, 0, 0, 0,
5049 /* IP2_28_26 [3] */
5050 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5051 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5052 /* IP2_25_22 [4] */
5053 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
1ddb66cd 5054 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
58c229e1
KM		 5055 0, 0, 0, 0, 0, 0, 0, 0,
5056 /* IP2_21_18 [4] */
5057 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
1ddb66cd 5058 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
58c229e1
KM		 5059 0, 0, 0, 0, 0, 0, 0, 0,
5060 /* IP2_17_15 [3] */
5061 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5062 0, 0, 0, 0,
5063 /* IP2_14_12 [3] */
5064 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5065 /* IP2_11_9 [3] */
5066 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5067 /* IP2_8_6 [3] */
5068 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5069 /* IP2_5_3 [3] */
5070 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5071 /* IP2_2_0 [3] */
5072 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
5073 },
5074 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5075 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5076 /* IP3_31_29 [3] */
5077 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5078 0, 0, 0,
5079 /* IP3_28_26 [3] */
5080 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5081 0, 0, 0, 0,
5082 /* IP3_25_23 [3] */
5083 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5084 /* IP3_22_20 [3] */
5085 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5086 /* IP3_19_18 [2] */
5087 FN_A16, FN_ATAWR1_N, 0, 0,
5088 /* IP3_17_15 [3] */
5089 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5090 0, 0, 0, 0,
5091 /* IP3_14_12 [3] */
5092 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5093 0, 0, 0, 0,
5094 /* IP3_11_8 [4] */
5095 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5096 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5097 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5098 /* IP3_7_4 [4] */
5099 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5100 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5101 0, 0, 0, 0, 0, 0, 0, 0, 0,
5102 /* IP3_3_0 [4] */
5103 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5104 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5105 0, 0, 0, 0, 0, 0, 0, 0, }
5106 },
5107 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5108 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5109 /* IP4_31_30 [2] */
5110 0, 0, 0, 0,
5111 /* IP4_29_27 [3] */
5112 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5113 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5114 /* IP4_26_24 [3] */
5115 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5116 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5117 /* IP4_23_21 [3] */
5118 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5119 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5120 /* IP4_20_18 [3] */
5121 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5122 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5123 /* IP4_17_15 [3] */
5124 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5125 0, 0, 0,
5126 /* IP4_14_12 [3] */
5127 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5128 FN_VI2_FIELD_B, 0, 0,
5129 /* IP4_11_9 [3] */
5130 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5131 FN_VI2_CLKENB_B, 0, 0,
5132 /* IP4_8_6 [3] */
5133 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5134 /* IP4_5_3 [3] */
5135 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5136 /* IP4_2_0 [3] */
5137 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5138 }
5139 },
5140 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5141 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5142 /* IP5_31_30 [2] */
5143 0, 0, 0, 0,
5144 /* IP5_29_27 [3] */
5145 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5146 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5147 /* IP5_26_24 [3] */
5148 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5149 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5150 FN_MSIOF0_SCK_B, 0,
5151 /* IP5_23_21 [3] */
5152 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
34ce57e9 5153 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
58c229e1
KM		 5154 /* IP5_20_18 [3] */
5155 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5156 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5157 /* IP5_17_15 [3] */
5158 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5159 FN_INTC_IRQ4_N, 0, 0,
5160 /* IP5_14_13 [2] */
5161 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5162 /* IP5_12_10 [3] */
5163 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5164 0, 0,
5165 /* IP5_9_6 [4] */
5166 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
c4721249
SK		 5167 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5168 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5169 /* IP5_5_3 [3] */
5170 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
c4721249
SK		 5171 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5172 FN_INTC_EN0_N, FN_I2C1_SCL,
58c229e1
KM		 5173 /* IP5_2_0 [3] */
5174 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5175 FN_VI2_R3, 0, 0, }
5176 },
5177 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5178 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5179 /* IP6_31_29 [3] */
9f2edd41 5180 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
58c229e1
KM		 5181 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5182 /* IP6_28_26 [3] */
9f2edd41 5183 FN_ETH_LINK, 0, FN_HTX0_E,
58c229e1
KM		 5184 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5185 /* IP6_25_23 [3] */
9f2edd41 5186 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
58c229e1
KM		 5187 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5188 /* IP6_22_20 [3] */
9f2edd41 5189 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
58c229e1
KM		 5190 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5191 /* IP6_19_17 [3] */
9f2edd41 5192 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
c4721249 5193 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
58c229e1 5194 /* IP6_16_14 [3] */
9f2edd41 5195 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
c4721249
SK		 5196 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5197 FN_I2C2_SCL_E, 0,
58c229e1
KM		 5198 /* IP6_13_11 [3] */
5199 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5200 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5201 /* IP6_10_9 [2] */
5202 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5203 /* IP6_8_6 [3] */
5204 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5205 FN_SSI_SDATA8_C, 0, 0, 0,
5206 /* IP6_5_3 [3] */
5207 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5208 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5209 /* IP6_2_0 [3] */
5210 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5211 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
5212 },
5213 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5214 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5215 /* IP7_31 [1] */
5216 0, 0,
5217 /* IP7_30_29 [2] */
9f2edd41 5218 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
58c229e1 5219 /* IP7_28_27 [2] */
9f2edd41 5220 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
58c229e1 5221 /* IP7_26_25 [2] */
f0681209 5222 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
58c229e1
KM		 5223 /* IP7_24_22 [3] */
5224 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5225 0, 0, 0,
5226 /* IP7_21_19 [3] */
5227 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5228 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5229 /* IP7_18_16 [3] */
5230 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5231 FN_GLO_SS_C, 0, 0, 0,
5232 /* IP7_15_13 [3] */
9f2edd41 5233 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
58c229e1
KM		 5234 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5235 /* IP7_12_10 [3] */
9f2edd41 5236 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
58c229e1
KM		 5237 FN_GLO_SCLK_C, 0, 0, 0,
5238 /* IP7_9_8 [2] */
9f2edd41 5239 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
58c229e1 5240 /* IP7_7_6 [2] */
9f2edd41 5241 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
58c229e1 5242 /* IP7_5_3 [3] */
14da999b 5243 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
58c229e1 5244 /* IP7_2_0 [3] */
9f2edd41 5245 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
58c229e1
KM		 5246 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5247 },
5248 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5249 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5250 2, 2, 2, 2, 2, 2, 2) {
5251 /* IP8_31 [1] */
5252 0, 0,
5253 /* IP8_30_29 [2] */
5254 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5255 /* IP8_28 [1] */
5256 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5257 /* IP8_27 [1] */
5258 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5259 /* IP8_26 [1] */
5260 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5261 /* IP8_25_24 [2] */
5262 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
9f2edd41 5263 FN_AVB_MAGIC, 0,
58c229e1
KM		 5264 /* IP8_23_22 [2] */
5265 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5266 /* IP8_21_20 [2] */
9f2edd41 5267 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
58c229e1 5268 /* IP8_19_18 [2] */
9f2edd41 5269 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
58c229e1 5270 /* IP8_17_16 [2] */
9f2edd41 5271 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
58c229e1 5272 /* IP8_15_14 [2] */
9f2edd41 5273 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
58c229e1 5274 /* IP8_13_12 [2] */
9f2edd41 5275 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
58c229e1 5276 /* IP8_11_10 [2] */
9f2edd41 5277 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
58c229e1
KM		 5278 /* IP8_9_8 [2] */
5279 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5280 /* IP8_7_6 [2] */
5281 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5282 /* IP8_5_4 [2] */
5283 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5284 /* IP8_3_2 [2] */
5285 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5286 /* IP8_1_0 [2] */
9f2edd41 5287 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
58c229e1
KM		 5288 },
5289 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5290 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5291 /* IP9_31_28 [4] */
5292 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
c4721249 5293 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
58c229e1
KM		 5294 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5295 /* IP9_27_26 [2] */
9f2edd41 5296 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
58c229e1 5297 /* IP9_25_24 [2] */
9f2edd41 5298 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
58c229e1 5299 /* IP9_23_22 [2] */
9f2edd41 5300 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
58c229e1 5301 /* IP9_21_20 [2] */
9f2edd41 5302 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
58c229e1 5303 /* IP9_19_18 [2] */
9f2edd41 5304 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
58c229e1 5305 /* IP9_17_16 [2] */
9f2edd41 5306 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
58c229e1
KM		 5307 /* IP9_15_12 [4] */
5308 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
c4721249
SK		 5309 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5310 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5311 /* IP9_11_8 [4] */
5312 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
c4721249
SK		 5313 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5314 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5315 /* IP9_7_6 [2] */
5316 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5317 /* IP9_5_4 [2] */
5318 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5319 /* IP9_3_2 [2] */
5320 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5321 /* IP9_1_0 [2] */
5322 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5323 },
5324 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5325 2, 4, 3, 4, 4, 4, 4, 3, 4) {
5326 /* IP10_31_30 [2] */
5327 0, 0, 0, 0,
5328 /* IP10_29_26 [4] */
5329 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5330 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5331 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5332 /* IP10_25_23 [3] */
5333 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5334 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5335 /* IP10_22_19 [4] */
14da999b 5336 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
58c229e1
KM		 5337 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5338 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5339 /* IP10_18_15 [4] */
14da999b 5340 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
58c229e1
KM		 5341 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5342 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5343 0, 0, 0, 0, 0, 0,
5344 /* IP10_14_11 [4] */
5345 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5346 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5347 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5348 0, 0, 0, 0, 0, 0, 0,
5349 /* IP10_10_7 [4] */
5350 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5351 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5352 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5353 0, 0, 0, 0, 0, 0, 0,
5354 /* IP10_6_4 [3] */
5355 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5356 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5357 FN_VI3_DATA0_B, 0,
5358 /* IP10_3_0 [4] */
5359 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
c4721249 5360 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
58c229e1
KM		 5361 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5362 },
5363 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
17babad6 5364 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
58c229e1
KM		 5365 /* IP11_31_30 [2] */
5366 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5367 /* IP11_29_27 [3] */
7d2b2854 5368 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
14da999b 5369 0, 0, 0,
58c229e1 5370 /* IP11_26_24 [3] */
c4721249 5371 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
58c229e1
KM		 5372 0, 0, 0,
5373 /* IP11_23_22 [2] */
c4721249 5374 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
58c229e1
KM		 5375 /* IP11_21_18 [4] */
5376 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
14da999b 5377 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5378 /* IP11_17_15 [3] */
5379 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5380 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5381 /* IP11_14_13 [2] */
5382 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5383 /* IP11_12_11 [2] */
5384 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5385 /* IP11_10_9 [2] */
5386 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5387 /* IP11_8_7 [2] */
5388 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5389 /* IP11_6_5 [2] */
5390 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5391 /* IP11_4 [1] */
5392 FN_SD3_CLK, FN_MMC1_CLK,
5393 /* IP11_3_0 [4] */
5394 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5395 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5396 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5397 },
5398 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5399 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5400 /* IP12_31 [1] */
5401 0, 0,
5402 /* IP12_30_28 [3] */
5403 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5404 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5405 FN_CAN_DEBUGOUT4, 0, 0,
5406 /* IP12_27_25 [3] */
5407 FN_SSI_SCK5, FN_SCIFB1_SCK,
5408 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5409 FN_CAN_DEBUGOUT3, 0, 0,
5410 /* IP12_24_23 [2] */
5411 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5412 FN_CAN_DEBUGOUT2,
5413 /* IP12_22_20 [3] */
5414 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5415 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5416 /* IP12_19_17 [3] */
5417 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5418 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5419 /* IP12_16_14 [3] */
5420 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5421 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5422 /* IP12_13_11 [3] */
5423 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5424 FN_CAN_STEP0, 0, 0, 0,
5425 /* IP12_10_8 [3] */
5426 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5427 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5428 /* IP12_7_6 [2] */
5429 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5430 /* IP12_5_4 [2] */
5431 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5432 /* IP12_3_2 [2] */
5433 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5434 /* IP12_1_0 [2] */
5435 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5436 },
5437 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5438 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5439 /* IP13_31 [1] */
5440 0, 0,
5441 /* IP13_30_29 [2] */
5442 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5443 /* IP13_28_26 [3] */
5444 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5445 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5446 /* IP13_25_23 [3] */
5447 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5448 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5449 /* IP13_22_19 [4] */
5450 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5451 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
14da999b 5452 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
58c229e1
KM		 5453 /* IP13_18_16 [3] */
5454 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5455 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5456 /* IP13_15_13 [3] */
5457 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5458 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5459 /* IP13_12_10 [3] */
14da999b 5460 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
58c229e1
KM		 5461 FN_CAN_DEBUGOUT8, 0, 0,
5462 /* IP13_9_7 [3] */
5463 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5464 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5465 /* IP13_6_3 [4] */
14da999b 5466 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
58c229e1 5467 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
14da999b 5468 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5469 /* IP13_2_0 [3] */
5470 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5471 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5472 },
5473 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5474 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5475 /* IP14_30 [1] */
5476 0, 0,
5477 /* IP14_30_28 [3] */
bcec7475 5478 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
58c229e1
KM		 5479 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5480 FN_HRTS0_N_C, 0,
5481 /* IP14_27_25 [3] */
5482 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5483 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5484 /* IP14_24_22 [3] */
5485 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5486 FN_LCDOUT9, 0, 0, 0,
5487 /* IP14_21_19 [3] */
5488 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5489 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5490 /* IP14_18_16 [3] */
bcec7475 5491 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
58c229e1
KM		 5492 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5493 /* IP14_15_12 [4] */
5494 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
c4721249 5495 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
58c229e1
KM		 5496 0, 0, 0, 0, 0, 0, 0,
5497 /* IP14_11_9 [3] */
5498 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5499 0, 0, 0,
5500 /* IP14_8_6 [3] */
5501 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5502 0, 0, 0,
5503 /* IP14_5_3 [3] */
5504 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
c4721249 5505 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
58c229e1
KM		 5506 /* IP14_2_0 [3] */
5507 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5508 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5509 FN_REMOCON, 0, }
5510 },
5511 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5512 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5513 /* IP15_31_30 [2] */
5514 0, 0, 0, 0,
5515 /* IP15_29_28 [2] */
5516 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5517 /* IP15_27_26 [2] */
5518 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5519 /* IP15_25_23 [3] */
5520 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5de880dd 5521 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
58c229e1
KM		 5522 /* IP15_22_20 [3] */
5523 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5524 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5525 /* IP15_19_18 [2] */
5526 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5527 /* IP15_17_16 [2] */
5528 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5529 /* IP15_15_14 [2] */
5530 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5531 /* IP15_13_12 [2] */
5532 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5533 /* IP15_11_9 [3] */
5534 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5535 0, 0, 0,
5536 /* IP15_8_6 [3] */
1ddb66cd 5537 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
c4721249 5538 FN_IIC2_SDA, FN_I2C2_SDA, 0,
58c229e1 5539 /* IP15_5_3 [3] */
1ddb66cd 5540 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
c4721249 5541 FN_IIC2_SCL, FN_I2C2_SCL, 0,
58c229e1 5542 /* IP15_2_0 [3] */
1ddb66cd 5543 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
58c229e1
KM		 5544 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5545 },
5546 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5547 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5548 /* IP16_31_28 [4] */
5549 0, 0, 0, 0, 0, 0, 0, 0,
5550 0, 0, 0, 0, 0, 0, 0, 0,
5551 /* IP16_27_24 [4] */
5552 0, 0, 0, 0, 0, 0, 0, 0,
5553 0, 0, 0, 0, 0, 0, 0, 0,
5554 /* IP16_23_20 [4] */
5555 0, 0, 0, 0, 0, 0, 0, 0,
5556 0, 0, 0, 0, 0, 0, 0, 0,
5557 /* IP16_19_16 [4] */
5558 0, 0, 0, 0, 0, 0, 0, 0,
5559 0, 0, 0, 0, 0, 0, 0, 0,
5560 /* IP16_15_12 [4] */
5561 0, 0, 0, 0, 0, 0, 0, 0,
5562 0, 0, 0, 0, 0, 0, 0, 0,
5563 /* IP16_11_8 [4] */
5564 0, 0, 0, 0, 0, 0, 0, 0,
5565 0, 0, 0, 0, 0, 0, 0, 0,
5566 /* IP16_7 [1] */
5567 FN_USB1_OVC, FN_TCLK1_B,
5568 /* IP16_6 [1] */
5569 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5570 /* IP16_5_3 [3] */
5571 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5de880dd 5572 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
58c229e1
KM		 5573 /* IP16_2_0 [3] */
5574 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5575 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5576 },
5577 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5578 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5579 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5580 /* SEL_SCIF1 [3] */
5581 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5582 FN_SEL_SCIF1_4, 0, 0, 0,
5583 /* SEL_SCIFB [2] */
5584 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5585 /* SEL_SCIFB2 [2] */
5586 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5587 /* SEL_SCIFB1 [3] */
5588 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5589 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5590 FN_SEL_SCIFB1_6, 0,
5591 /* SEL_SCIFA1 [2] */
5592 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5593 FN_SEL_SCIFA1_3,
5594 /* SEL_SCIF0 [1] */
5595 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5596 /* SEL_SCIFA [1] */
5597 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5598 /* SEL_SOF1 [1] */
5599 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5600 /* SEL_SSI7 [2] */
5601 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5602 /* SEL_SSI6 [1] */
5603 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5604 /* SEL_SSI5 [2] */
5605 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5606 /* SEL_VI3 [1] */
5607 FN_SEL_VI3_0, FN_SEL_VI3_1,
5608 /* SEL_VI2 [1] */
5609 FN_SEL_VI2_0, FN_SEL_VI2_1,
5610 /* SEL_VI1 [1] */
5611 FN_SEL_VI1_0, FN_SEL_VI1_1,
5612 /* SEL_VI0 [1] */
5613 FN_SEL_VI0_0, FN_SEL_VI0_1,
5614 /* SEL_TSIF1 [2] */
5615 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5616 /* RESERVED [1] */
5617 0, 0,
5618 /* SEL_LBS [1] */
5619 FN_SEL_LBS_0, FN_SEL_LBS_1,
5620 /* SEL_TSIF0 [2] */
5621 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5622 /* SEL_SOF3 [1] */
5623 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5624 /* SEL_SOF0 [1] */
5625 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5626 },
5627 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
17babad6
GL		 5628 3, 1, 1, 1, 2, 1, 2, 1, 2,
5629 1, 1, 1, 3, 3, 2, 3, 2, 2) {
7f35184b 5630 /* RESERVED [3] */
58c229e1 5631 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5632 /* SEL_TMU1 [1] */
5633 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5634 /* SEL_HSCIF1 [1] */
5635 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5636 /* SEL_SCIFCLK [1] */
5637 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5638 /* SEL_CAN0 [2] */
5639 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5640 /* SEL_CANCLK [1] */
5641 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5642 /* SEL_SCIFA2 [2] */
5643 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5644 /* SEL_CAN1 [1] */
5645 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
7f35184b 5646 /* RESERVED [2] */
17babad6 5647 0, 0, 0, 0,
1ddb66cd
SK		 5648 /* SEL_SCIF2 [1] */
5649 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
58c229e1
KM		 5650 /* SEL_ADI [1] */
5651 FN_SEL_ADI_0, FN_SEL_ADI_1,
5652 /* SEL_SSP [1] */
5653 FN_SEL_SSP_0, FN_SEL_SSP_1,
5654 /* SEL_FM [3] */
5655 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5656 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5657 /* SEL_HSCIF0 [3] */
5658 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5659 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5660 /* SEL_GPS [2] */
5661 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
14da999b
SK		 5662 /* RESERVED [3] */
5663 0, 0, 0, 0, 0, 0, 0, 0,
58c229e1
KM		 5664 /* SEL_SIM [2] */
5665 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5666 /* SEL_SSI8 [2] */
5667 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5668 },
5669 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5670 1, 1, 2, 4, 4, 2, 2,
5671 4, 2, 3, 2, 3, 2) {
5672 /* SEL_IICDVFS [1] */
5673 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5674 /* SEL_IIC0 [1] */
5675 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
7f35184b 5676 /* RESERVED [2] */
58c229e1 5677 0, 0, 0, 0,
7f35184b 5678 /* RESERVED [4] */
58c229e1
KM		 5679 0, 0, 0, 0, 0, 0, 0, 0,
5680 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5681 /* RESERVED [4] */
58c229e1
KM		 5682 0, 0, 0, 0, 0, 0, 0, 0,
5683 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5684 /* RESERVED [2] */
58c229e1
KM		 5685 0, 0, 0, 0,
5686 /* SEL_IEB [2] */
5687 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
7f35184b 5688 /* RESERVED [4] */
58c229e1
KM		 5689 0, 0, 0, 0, 0, 0, 0, 0,
5690 0, 0, 0, 0, 0, 0, 0, 0,
7f35184b 5691 /* RESERVED [2] */
58c229e1
KM		 5692 0, 0, 0, 0,
5693 /* SEL_IIC2 [3] */
5694 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5695 FN_SEL_IIC2_4, 0, 0, 0,
5696 /* SEL_IIC1 [2] */
5697 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5698 /* SEL_I2C2 [3] */
5699 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5700 FN_SEL_I2C2_4, 0, 0, 0,
5701 /* SEL_I2C1 [2] */
5702 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5703 },
58c229e1
KM		 5704 { },
5705};
5706
5707const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5708 .name = "r8a77900_pfc",
5709 .unlock_reg = 0xe6060000, /* PMMR */
5710
58c229e1
KM		 5711 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5712
5713 .pins = pinmux_pins,
5714 .nr_pins = ARRAY_SIZE(pinmux_pins),
1627769b
LP		 5715 .groups = pinmux_groups,
5716 .nr_groups = ARRAY_SIZE(pinmux_groups),
5717 .functions = pinmux_functions,
5718 .nr_functions = ARRAY_SIZE(pinmux_functions),
58c229e1 5719
58c229e1 5720 .cfg_regs = pinmux_config_regs,
58c229e1
KM		 5721
5722 .gpio_data = pinmux_data,
5723 .gpio_data_size = ARRAY_SIZE(pinmux_data),
5724};
Linux kernel - Deliverables
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