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Merge branch 'for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / drivers / pinctrl / sirf / pinctrl-atlas6.c
CommitLineData
3370dc91
BS		 1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVI
3 *
019c12f4
BS		 4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
3370dc91
BS		 6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/pinctrl/pinctrl.h>
11#include <linux/bitops.h>
12
13#include "pinctrl-sirf.h"
14
15/*
16 * pad list for the pinmux subsystem
17 * refer to atlasVI_io_table_v0.93.xls
18 */
19static const struct pinctrl_pin_desc sirfsoc_pads[] = {
20 PINCTRL_PIN(0, "gpio0-0"),
21 PINCTRL_PIN(1, "gpio0-1"),
22 PINCTRL_PIN(2, "gpio0-2"),
23 PINCTRL_PIN(3, "gpio0-3"),
24 PINCTRL_PIN(4, "pwm0"),
25 PINCTRL_PIN(5, "pwm1"),
26 PINCTRL_PIN(6, "pwm2"),
27 PINCTRL_PIN(7, "pwm3"),
28 PINCTRL_PIN(8, "warm_rst_b"),
29 PINCTRL_PIN(9, "odo_0"),
30 PINCTRL_PIN(10, "odo_1"),
31 PINCTRL_PIN(11, "dr_dir"),
32 PINCTRL_PIN(12, "rts_0"),
33 PINCTRL_PIN(13, "scl_1"),
34 PINCTRL_PIN(14, "ntrst"),
35 PINCTRL_PIN(15, "sda_1"),
36 PINCTRL_PIN(16, "x_ldd[16]"),
37 PINCTRL_PIN(17, "x_ldd[17]"),
38 PINCTRL_PIN(18, "x_ldd[18]"),
39 PINCTRL_PIN(19, "x_ldd[19]"),
40 PINCTRL_PIN(20, "x_ldd[20]"),
41 PINCTRL_PIN(21, "x_ldd[21]"),
42 PINCTRL_PIN(22, "x_ldd[22]"),
43 PINCTRL_PIN(23, "x_ldd[23]"),
44 PINCTRL_PIN(24, "gps_sgn"),
45 PINCTRL_PIN(25, "gps_mag"),
46 PINCTRL_PIN(26, "gps_clk"),
47 PINCTRL_PIN(27, "sd_cd_b_2"),
48 PINCTRL_PIN(28, "sd_vcc_on_2"),
49 PINCTRL_PIN(29, "sd_wp_b_2"),
50 PINCTRL_PIN(30, "sd_clk_3"),
51 PINCTRL_PIN(31, "sd_cmd_3"),
52
53 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
54 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
55 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
56 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
57 PINCTRL_PIN(36, "usb_clk"),
58 PINCTRL_PIN(37, "usb_dir"),
59 PINCTRL_PIN(38, "usb_nxt"),
60 PINCTRL_PIN(39, "usb_stp"),
61 PINCTRL_PIN(40, "usb_dat[7]"),
62 PINCTRL_PIN(41, "usb_dat[6]"),
63 PINCTRL_PIN(42, "x_cko_1"),
64 PINCTRL_PIN(43, "spi_clk_1"),
65 PINCTRL_PIN(44, "spi_dout_1"),
66 PINCTRL_PIN(45, "spi_din_1"),
67 PINCTRL_PIN(46, "spi_en_1"),
68 PINCTRL_PIN(47, "x_txd_1"),
69 PINCTRL_PIN(48, "x_txd_2"),
70 PINCTRL_PIN(49, "x_rxd_1"),
71 PINCTRL_PIN(50, "x_rxd_2"),
72 PINCTRL_PIN(51, "x_usclk_0"),
73 PINCTRL_PIN(52, "x_utxd_0"),
74 PINCTRL_PIN(53, "x_urxd_0"),
75 PINCTRL_PIN(54, "x_utfs_0"),
76 PINCTRL_PIN(55, "x_urfs_0"),
77 PINCTRL_PIN(56, "usb_dat5"),
78 PINCTRL_PIN(57, "usb_dat4"),
79 PINCTRL_PIN(58, "usb_dat3"),
80 PINCTRL_PIN(59, "usb_dat2"),
81 PINCTRL_PIN(60, "usb_dat1"),
82 PINCTRL_PIN(61, "usb_dat0"),
83 PINCTRL_PIN(62, "x_ldd[14]"),
84 PINCTRL_PIN(63, "x_ldd[15]"),
85
86 PINCTRL_PIN(64, "x_gps_gpio"),
87 PINCTRL_PIN(65, "x_ldd[13]"),
88 PINCTRL_PIN(66, "x_df_we_b"),
89 PINCTRL_PIN(67, "x_df_re_b"),
90 PINCTRL_PIN(68, "x_txd_0"),
91 PINCTRL_PIN(69, "x_rxd_0"),
92 PINCTRL_PIN(70, "x_l_lck"),
93 PINCTRL_PIN(71, "x_l_fck"),
94 PINCTRL_PIN(72, "x_l_de"),
95 PINCTRL_PIN(73, "x_ldd[0]"),
96 PINCTRL_PIN(74, "x_ldd[1]"),
97 PINCTRL_PIN(75, "x_ldd[2]"),
98 PINCTRL_PIN(76, "x_ldd[3]"),
99 PINCTRL_PIN(77, "x_ldd[4]"),
100 PINCTRL_PIN(78, "x_cko_0"),
101 PINCTRL_PIN(79, "x_ldd[5]"),
102 PINCTRL_PIN(80, "x_ldd[6]"),
103 PINCTRL_PIN(81, "x_ldd[7]"),
104 PINCTRL_PIN(82, "x_ldd[8]"),
105 PINCTRL_PIN(83, "x_ldd[9]"),
106 PINCTRL_PIN(84, "x_ldd[10]"),
107 PINCTRL_PIN(85, "x_ldd[11]"),
108 PINCTRL_PIN(86, "x_ldd[12]"),
109 PINCTRL_PIN(87, "x_vip_vsync"),
110 PINCTRL_PIN(88, "x_vip_hsync"),
111 PINCTRL_PIN(89, "x_vip_pxclk"),
112 PINCTRL_PIN(90, "x_sda_0"),
113 PINCTRL_PIN(91, "x_scl_0"),
114 PINCTRL_PIN(92, "x_df_ry_by"),
115 PINCTRL_PIN(93, "x_df_cs_b[1]"),
116 PINCTRL_PIN(94, "x_df_cs_b[0]"),
117 PINCTRL_PIN(95, "x_l_pclk"),
118
119 PINCTRL_PIN(96, "x_df_dqs"),
120 PINCTRL_PIN(97, "x_df_wp_b"),
121 PINCTRL_PIN(98, "ac97_sync"),
122 PINCTRL_PIN(99, "ac97_bit_clk "),
123 PINCTRL_PIN(100, "ac97_dout"),
124 PINCTRL_PIN(101, "ac97_din"),
125 PINCTRL_PIN(102, "x_rtc_io"),
6a08a92e
RW		 126
127 PINCTRL_PIN(103, "x_usb1_dp"),
128 PINCTRL_PIN(104, "x_usb1_dn"),
3370dc91
BS		 129};
130
131static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
132 {
133 .group = 1,
134 .mask = BIT(30) | BIT(31),
135 }, {
136 .group = 2,
c09f80db
BS		 137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
138 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
139 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
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BS		 140 BIT(20) | BIT(21) | BIT(22) | BIT(31),
141 },
142};
143
144static const struct sirfsoc_padmux lcd_16bits_padmux = {
145 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
146 .muxmask = lcd_16bits_sirfsoc_muxmask,
6a08a92e 147 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 148 .funcmask = BIT(4),
149 .funcval = 0,
150};
151
c09f80db
BS		 152static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
153 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
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BS		 154
155static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
156 {
157 .group = 2,
c09f80db
BS		 158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
159 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
160 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
3370dc91
BS		 161 BIT(20) | BIT(21) | BIT(22) | BIT(31),
162 }, {
163 .group = 1,
164 .mask = BIT(30) | BIT(31),
165 }, {
166 .group = 0,
167 .mask = BIT(16) | BIT(17),
168 },
169};
170
171static const struct sirfsoc_padmux lcd_18bits_padmux = {
172 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
173 .muxmask = lcd_18bits_muxmask,
6a08a92e 174 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 175 .funcmask = BIT(4) | BIT(15),
176 .funcval = 0,
177};
178
c09f80db
BS		 179static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
180 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
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BS		 181
182static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
183 {
184 .group = 2,
c09f80db
BS		 185 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
186 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
187 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
3370dc91
BS		 188 BIT(20) | BIT(21) | BIT(22) | BIT(31),
189 }, {
190 .group = 1,
191 .mask = BIT(30) | BIT(31),
192 }, {
193 .group = 0,
c09f80db
BS		 194 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
195 BIT(21) | BIT(22) | BIT(23),
3370dc91
BS		 196 },
197};
198
199static const struct sirfsoc_padmux lcd_24bits_padmux = {
200 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
201 .muxmask = lcd_24bits_muxmask,
6a08a92e 202 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 203 .funcmask = BIT(4) | BIT(15),
204 .funcval = 0,
205};
206
c09f80db
BS		 207static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
208 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
209 85, 86, 95};
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BS		 210
211static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
212 {
213 .group = 2,
c09f80db
BS		 214 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
215 BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
216 BIT(17) | BIT(18) | BIT(19) |
3370dc91
BS		 217 BIT(20) | BIT(21) | BIT(22) | BIT(31),
218 }, {
219 .group = 1,
220 .mask = BIT(30) | BIT(31),
221 }, {
222 .group = 0,
223 .mask = BIT(8),
224 },
225};
226
227static const struct sirfsoc_padmux lcdrom_padmux = {
228 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
229 .muxmask = lcdrom_muxmask,
6a08a92e 230 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 231 .funcmask = BIT(4),
232 .funcval = BIT(4),
233};
234
c09f80db
BS		 235static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
236 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
3370dc91
BS		 237
238static const struct sirfsoc_muxmask uart0_muxmask[] = {
239 {
240 .group = 0,
241 .mask = BIT(12),
242 }, {
243 .group = 1,
244 .mask = BIT(23),
245 }, {
246 .group = 2,
247 .mask = BIT(4) | BIT(5),
248 },
249};
250
251static const struct sirfsoc_padmux uart0_padmux = {
252 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
253 .muxmask = uart0_muxmask,
6a08a92e 254 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 255 .funcmask = BIT(9),
256 .funcval = BIT(9),
257};
258
259static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
260
261static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
262 {
263 .group = 2,
264 .mask = BIT(4) | BIT(5),
265 },
266};
267
268static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
269 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
270 .muxmask = uart0_nostreamctrl_muxmask,
271};
272
273static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
274
275static const struct sirfsoc_muxmask uart1_muxmask[] = {
276 {
277 .group = 1,
278 .mask = BIT(15) | BIT(17),
279 },
280};
281
282static const struct sirfsoc_padmux uart1_padmux = {
283 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
284 .muxmask = uart1_muxmask,
285};
286
287static const unsigned uart1_pins[] = { 47, 49 };
288
289static const struct sirfsoc_muxmask uart2_muxmask[] = {
290 {
291 .group = 0,
292 .mask = BIT(10) | BIT(14),
293 }, {
294 .group = 1,
295 .mask = BIT(16) | BIT(18),
296 },
297};
298
299static const struct sirfsoc_padmux uart2_padmux = {
300 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
301 .muxmask = uart2_muxmask,
6a08a92e 302 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 303 .funcmask = BIT(10),
304 .funcval = BIT(10),
305};
306
307static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
308
309static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
310 {
311 .group = 1,
312 .mask = BIT(16) | BIT(18),
313 },
314};
315
316static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
317 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
318 .muxmask = uart2_nostreamctrl_muxmask,
319};
320
321static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
322
323static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
324 {
325 .group = 0,
326 .mask = BIT(30) | BIT(31),
327 }, {
328 .group = 1,
329 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
330 },
331};
332
333static const struct sirfsoc_padmux sdmmc3_padmux = {
334 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
335 .muxmask = sdmmc3_muxmask,
6a08a92e 336 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 337 .funcmask = BIT(7),
338 .funcval = 0,
339};
340
341static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
342
343static const struct sirfsoc_muxmask spi0_muxmask[] = {
344 {
345 .group = 0,
346 .mask = BIT(30),
347 }, {
348 .group = 1,
349 .mask = BIT(0) | BIT(2) | BIT(3),
350 },
351};
352
353static const struct sirfsoc_padmux spi0_padmux = {
354 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
355 .muxmask = spi0_muxmask,
6a08a92e 356 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 357 .funcmask = BIT(7),
358 .funcval = BIT(7),
359};
360
361static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
362
363static const struct sirfsoc_muxmask cko1_muxmask[] = {
364 {
365 .group = 1,
366 .mask = BIT(10),
367 },
368};
369
370static const struct sirfsoc_padmux cko1_padmux = {
371 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
372 .muxmask = cko1_muxmask,
6a08a92e 373 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 374 .funcmask = BIT(3),
375 .funcval = 0,
376};
377
378static const unsigned cko1_pins[] = { 42 };
379
ed36c1a0 380static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
3370dc91
BS		 381 {
382 .group = 1,
383 .mask = BIT(10),
ed36c1a0
RY		 384 },
385};
386
387static const struct sirfsoc_padmux i2s_mclk_padmux = {
388 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
389 .muxmask = i2s_mclk_muxmask,
390 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
391 .funcmask = BIT(3),
392 .funcval = BIT(3),
393};
394
395static const unsigned i2s_mclk_pins[] = { 42 };
396
086b8904
RY		 397static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
398 {
399 .group = 1,
400 .mask = BIT(19),
401 },
402};
403
404static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
405 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
406 .muxmask = i2s_ext_clk_input_muxmask,
407 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
408 .funcmask = BIT(2),
409 .funcval = BIT(2),
410};
411
412static const unsigned i2s_ext_clk_input_pins[] = { 51 };
413
ed36c1a0
RY		 414static const struct sirfsoc_muxmask i2s_muxmask[] = {
415 {
3370dc91
BS		 416 .group = 3,
417 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
418 },
419};
420
421static const struct sirfsoc_padmux i2s_padmux = {
422 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
423 .muxmask = i2s_muxmask,
6a08a92e 424 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 425};
426
ed36c1a0 427static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
3370dc91
BS		 428
429static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
430 {
3370dc91
BS		 431 .group = 3,
432 .mask = BIT(2) | BIT(3) | BIT(4),
433 },
434};
435
436static const struct sirfsoc_padmux i2s_no_din_padmux = {
437 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
438 .muxmask = i2s_no_din_muxmask,
6a08a92e 439 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 440};
441
ed36c1a0 442static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
3370dc91
BS		 443
444static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
445 {
3370dc91
BS		 446 .group = 3,
447 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
448 },
449};
450
451static const struct sirfsoc_padmux i2s_6chn_padmux = {
452 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
453 .muxmask = i2s_6chn_muxmask,
6a08a92e 454 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
ed36c1a0
RY		 455 .funcmask = BIT(1) | BIT(9),
456 .funcval = BIT(1) | BIT(9),
3370dc91
BS		 457};
458
ed36c1a0 459static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
3370dc91
BS		 460
461static const struct sirfsoc_muxmask ac97_muxmask[] = {
462 {
463 .group = 3,
464 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
465 },
466};
467
468static const struct sirfsoc_padmux ac97_padmux = {
469 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
470 .muxmask = ac97_muxmask,
471};
472
473static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
474
475static const struct sirfsoc_muxmask spi1_muxmask[] = {
476 {
477 .group = 1,
478 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
479 },
480};
481
482static const struct sirfsoc_padmux spi1_padmux = {
483 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
484 .muxmask = spi1_muxmask,
6a08a92e 485 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 486 .funcmask = BIT(16),
487 .funcval = 0,
488};
489
490static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
491
492static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
493 {
494 .group = 2,
495 .mask = BIT(2) | BIT(3),
496 },
497};
498
499static const struct sirfsoc_padmux sdmmc1_padmux = {
500 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
501 .muxmask = sdmmc1_muxmask,
6a08a92e 502 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 503 .funcmask = BIT(5),
504 .funcval = BIT(5),
505};
506
507static const unsigned sdmmc1_pins[] = { 66, 67 };
508
509static const struct sirfsoc_muxmask gps_muxmask[] = {
510 {
511 .group = 0,
512 .mask = BIT(24) | BIT(25) | BIT(26),
513 },
514};
515
516static const struct sirfsoc_padmux gps_padmux = {
517 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
518 .muxmask = gps_muxmask,
6a08a92e 519 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
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BS		 520 .funcmask = BIT(13),
521 .funcval = 0,
522};
523
524static const unsigned gps_pins[] = { 24, 25, 26 };
525
526static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
527 {
528 .group = 0,
529 .mask = BIT(24) | BIT(25) | BIT(26),
530 },
531};
532
533static const struct sirfsoc_padmux sdmmc5_padmux = {
534 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
535 .muxmask = sdmmc5_muxmask,
6a08a92e 536 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
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BS		 537 .funcmask = BIT(13),
538 .funcval = BIT(13),
539};
540
541static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
542
543static const struct sirfsoc_muxmask usp0_muxmask[] = {
544 {
545 .group = 1,
42a708c9 546 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
3370dc91
BS		 547 },
548};
549
550static const struct sirfsoc_padmux usp0_padmux = {
551 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
552 .muxmask = usp0_muxmask,
6a08a92e 553 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 554 .funcmask = BIT(1) | BIT(2) | BIT(9),
555 .funcval = 0,
556};
557
42a708c9 558static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
3370dc91 559
58ffe7a0
RY		 560static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
561 {
562 .group = 1,
563 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
564 },
565};
566
567static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
568 .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
569 .muxmask = usp0_only_utfs_muxmask,
570 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
571 .funcmask = BIT(1) | BIT(2) | BIT(6),
572 .funcval = 0,
573};
574
575static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
576
577static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
578 {
579 .group = 1,
580 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
581 },
582};
583
584static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
585 .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
586 .muxmask = usp0_only_urfs_muxmask,
587 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
588 .funcmask = BIT(1) | BIT(2) | BIT(9),
589 .funcval = 0,
590};
591
592static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
593
d58e9a02
QL		 594static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
595 {
596 .group = 1,
597 .mask = BIT(20) | BIT(21),
598 },
599};
600
601static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
602 .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
603 .muxmask = usp0_uart_nostreamctrl_muxmask,
604};
605
606static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
3370dc91
BS		 607static const struct sirfsoc_muxmask usp1_muxmask[] = {
608 {
609 .group = 0,
610 .mask = BIT(15),
611 }, {
612 .group = 1,
613 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
614 },
615};
616
617static const struct sirfsoc_padmux usp1_padmux = {
618 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
619 .muxmask = usp1_muxmask,
6a08a92e 620 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 621 .funcmask = BIT(16),
622 .funcval = BIT(16),
623};
624
625static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
626
6225633d
QL		 627static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
628 {
629 .group = 1,
630 .mask = BIT(12) | BIT(13),
631 },
632};
633
634static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
635 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
636 .muxmask = usp1_uart_nostreamctrl_muxmask,
637 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
638 .funcmask = BIT(16),
639 .funcval = BIT(16),
640};
641
642static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
643
3370dc91
BS		 644static const struct sirfsoc_muxmask nand_muxmask[] = {
645 {
646 .group = 2,
647 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
648 }, {
649 .group = 3,
650 .mask = BIT(0) | BIT(1),
651 },
652};
653
654static const struct sirfsoc_padmux nand_padmux = {
655 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
656 .muxmask = nand_muxmask,
6a08a92e 657 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 658 .funcmask = BIT(5) | BIT(19),
659 .funcval = 0,
660};
661
662static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
663
664static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
665 {
666 .group = 3,
667 .mask = BIT(1),
668 },
669};
670
671static const struct sirfsoc_padmux sdmmc0_padmux = {
672 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
673 .muxmask = sdmmc0_muxmask,
6a08a92e 674 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 675 .funcmask = BIT(5) | BIT(19),
676 .funcval = BIT(19),
677};
678
679static const unsigned sdmmc0_pins[] = { 97 };
680
681static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
682 {
683 .group = 0,
684 .mask = BIT(27) | BIT(28) | BIT(29),
685 },
686};
687
688static const struct sirfsoc_padmux sdmmc2_padmux = {
689 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
690 .muxmask = sdmmc2_muxmask,
6a08a92e 691 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 692 .funcmask = BIT(11),
693 .funcval = 0,
694};
695
696static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
697
698static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
699 {
700 .group = 0,
701 .mask = BIT(27) | BIT(28),
702 },
703};
704
705static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
706 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
707 .muxmask = sdmmc2_nowp_muxmask,
6a08a92e 708 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 709 .funcmask = BIT(11),
710 .funcval = 0,
711};
712
713static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
714
715static const struct sirfsoc_muxmask cko0_muxmask[] = {
716 {
717 .group = 2,
718 .mask = BIT(14),
719 },
720};
721
722static const struct sirfsoc_padmux cko0_padmux = {
723 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
724 .muxmask = cko0_muxmask,
725};
726
727static const unsigned cko0_pins[] = { 78 };
728
729static const struct sirfsoc_muxmask vip_muxmask[] = {
730 {
731 .group = 1,
732 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
733 | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
734 BIT(29),
735 },
736};
737
738static const struct sirfsoc_padmux vip_padmux = {
739 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
740 .muxmask = vip_muxmask,
6a08a92e 741 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 742 .funcmask = BIT(18),
743 .funcval = BIT(18),
744};
745
c09f80db
BS		 746static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
747 60, 61 };
3370dc91
BS		 748
749static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
750 {
751 .group = 0,
752 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
753 | BIT(21) | BIT(22) | BIT(23),
754 }, {
755 .group = 2,
756 .mask = BIT(23) | BIT(24) | BIT(25),
757 },
758};
759
760static const struct sirfsoc_padmux vip_noupli_padmux = {
761 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
762 .muxmask = vip_noupli_muxmask,
6a08a92e 763 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 764 .funcmask = BIT(15),
765 .funcval = BIT(15),
766};
767
c09f80db
BS		 768static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
769 87, 88, 89 };
3370dc91
BS		 770
771static const struct sirfsoc_muxmask i2c0_muxmask[] = {
772 {
773 .group = 2,
774 .mask = BIT(26) | BIT(27),
775 },
776};
777
778static const struct sirfsoc_padmux i2c0_padmux = {
779 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
780 .muxmask = i2c0_muxmask,
781};
782
783static const unsigned i2c0_pins[] = { 90, 91 };
784
785static const struct sirfsoc_muxmask i2c1_muxmask[] = {
786 {
787 .group = 0,
788 .mask = BIT(13) | BIT(15),
789 },
790};
791
792static const struct sirfsoc_padmux i2c1_padmux = {
793 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
794 .muxmask = i2c1_muxmask,
6a08a92e 795 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 796 .funcmask = BIT(16),
797 .funcval = 0,
798};
799
800static const unsigned i2c1_pins[] = { 13, 15 };
801
802static const struct sirfsoc_muxmask pwm0_muxmask[] = {
803 {
804 .group = 0,
805 .mask = BIT(4),
806 },
807};
808
809static const struct sirfsoc_padmux pwm0_padmux = {
810 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
811 .muxmask = pwm0_muxmask,
6a08a92e 812 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 813 .funcmask = BIT(12),
814 .funcval = 0,
815};
816
817static const unsigned pwm0_pins[] = { 4 };
818
819static const struct sirfsoc_muxmask pwm1_muxmask[] = {
820 {
821 .group = 0,
822 .mask = BIT(5),
823 },
824};
825
826static const struct sirfsoc_padmux pwm1_padmux = {
827 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
828 .muxmask = pwm1_muxmask,
829};
830
831static const unsigned pwm1_pins[] = { 5 };
832
833static const struct sirfsoc_muxmask pwm2_muxmask[] = {
834 {
835 .group = 0,
836 .mask = BIT(6),
837 },
838};
839
840static const struct sirfsoc_padmux pwm2_padmux = {
841 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
842 .muxmask = pwm2_muxmask,
843};
844
845static const unsigned pwm2_pins[] = { 6 };
846
847static const struct sirfsoc_muxmask pwm3_muxmask[] = {
848 {
849 .group = 0,
850 .mask = BIT(7),
851 },
852};
853
854static const struct sirfsoc_padmux pwm3_padmux = {
855 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
856 .muxmask = pwm3_muxmask,
857};
858
859static const unsigned pwm3_pins[] = { 7 };
860
861static const struct sirfsoc_muxmask pwm4_muxmask[] = {
862 {
863 .group = 2,
864 .mask = BIT(14),
865 },
866};
867
868static const struct sirfsoc_padmux pwm4_padmux = {
869 .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
870 .muxmask = pwm4_muxmask,
871};
872
873static const unsigned pwm4_pins[] = { 78 };
874
875static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
876 {
877 .group = 0,
878 .mask = BIT(8),
879 },
880};
881
882static const struct sirfsoc_padmux warm_rst_padmux = {
883 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
884 .muxmask = warm_rst_muxmask,
6a08a92e 885 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 886 .funcmask = BIT(4),
887 .funcval = 0,
888};
889
890static const unsigned warm_rst_pins[] = { 8 };
891
892static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
893 {
894 .group = 1,
895 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
896 | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
897 BIT(27) | BIT(28) | BIT(29),
898 },
899};
900static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
901 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
902 .muxmask = usb0_upli_drvbus_muxmask,
6a08a92e 903 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 904 .funcmask = BIT(18),
905 .funcval = 0,
906};
907
c09f80db
BS		 908static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
909 41, 56, 57, 58, 59, 60, 61 };
3370dc91
BS		 910
911static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
912 {
913 .group = 0,
914 .mask = BIT(28),
915 },
916};
917
918static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
919 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
920 .muxmask = usb1_utmi_drvbus_muxmask,
6a08a92e 921 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
3370dc91
BS		 922 .funcmask = BIT(11),
923 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
924};
925
926static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
927
6a08a92e
RW		 928static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
929 .muxmask_counts = 0,
930 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
931 .funcmask = BIT(2),
932 .funcval = BIT(2),
933};
934
935static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
936
937static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
938 .muxmask_counts = 0,
939 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
940 .funcmask = BIT(2),
941 .funcval = 0,
942};
943
944static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
945
3370dc91
BS		 946static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
947 {
948 .group = 0,
949 .mask = BIT(9) | BIT(10) | BIT(11),
950 },
951};
952
953static const struct sirfsoc_padmux pulse_count_padmux = {
954 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
955 .muxmask = pulse_count_muxmask,
956};
957
958static const unsigned pulse_count_pins[] = { 9, 10, 11 };
959
960static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
961 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
962 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
963 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
964 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
965 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
031b8ce0 966 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
3370dc91
BS		 967 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
968 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
969 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
970 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
d58e9a02
QL		 971 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
972 usp0_uart_nostreamctrl_pins),
58ffe7a0
RY		 973 SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
974 SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
3370dc91 975 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
6225633d
QL		 976 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
977 usp1_uart_nostreamctrl_pins),
3370dc91
BS		 978 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
979 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
980 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
981 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
982 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
983 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
984 SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
985 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
986 SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
987 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
988 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
989 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
990 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
991 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
992 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
993 SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
994 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
995 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
996 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
997 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
6a08a92e
RW		 998 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
999 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
3370dc91 1000 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
ed36c1a0 1001 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
086b8904 1002 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
3370dc91
BS		 1003 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
1004 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
1005 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
1006 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
1007 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
1008 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
1009 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
1010 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
1011};
1012
1013static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
1014static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1015static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1016static const char * const lcdromgrp[] = { "lcdromgrp" };
1017static const char * const uart0grp[] = { "uart0grp" };
031b8ce0 1018static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
3370dc91
BS		 1019static const char * const uart1grp[] = { "uart1grp" };
1020static const char * const uart2grp[] = { "uart2grp" };
1021static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
d58e9a02
QL		 1022static const char * const usp0_uart_nostreamctrl_grp[] = {
1023 "usp0_uart_nostreamctrl_grp" };
3370dc91 1024static const char * const usp0grp[] = { "usp0grp" };
58ffe7a0
RY		 1025static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
1026static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
1027
3370dc91 1028static const char * const usp1grp[] = { "usp1grp" };
6225633d
QL		 1029static const char * const usp1_uart_nostreamctrl_grp[] = {
1030 "usp1_uart_nostreamctrl_grp" };
3370dc91
BS		 1031static const char * const i2c0grp[] = { "i2c0grp" };
1032static const char * const i2c1grp[] = { "i2c1grp" };
1033static const char * const pwm0grp[] = { "pwm0grp" };
1034static const char * const pwm1grp[] = { "pwm1grp" };
1035static const char * const pwm2grp[] = { "pwm2grp" };
1036static const char * const pwm3grp[] = { "pwm3grp" };
1037static const char * const pwm4grp[] = { "pwm4grp" };
1038static const char * const vipgrp[] = { "vipgrp" };
1039static const char * const vip_noupligrp[] = { "vip_noupligrp" };
1040static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1041static const char * const cko0grp[] = { "cko0grp" };
1042static const char * const cko1grp[] = { "cko1grp" };
1043static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1044static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1045static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1046static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1047static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1048static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
1049static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
1050static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
6a08a92e 1051static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
c09f80db
BS		 1052static const char * const
1053 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
3370dc91 1054static const char * const pulse_countgrp[] = { "pulse_countgrp" };
ed36c1a0 1055static const char * const i2smclkgrp[] = { "i2smclkgrp" };
086b8904 1056static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
3370dc91
BS		 1057static const char * const i2sgrp[] = { "i2sgrp" };
1058static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1059static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
1060static const char * const ac97grp[] = { "ac97grp" };
1061static const char * const nandgrp[] = { "nandgrp" };
1062static const char * const spi0grp[] = { "spi0grp" };
1063static const char * const spi1grp[] = { "spi1grp" };
1064static const char * const gpsgrp[] = { "gpsgrp" };
1065
1066static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1067 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1068 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1069 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1070 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1071 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
031b8ce0
QL		 1072 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp,
1073 uart0_nostreamctrl_padmux),
3370dc91
BS		 1074 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1075 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
c09f80db
BS		 1076 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1077 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
3370dc91 1078 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
d58e9a02
QL		 1079 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1080 usp0_uart_nostreamctrl_grp,
1081 usp0_uart_nostreamctrl_padmux),
58ffe7a0
RY		 1082 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp,
1083 usp0_only_utfs_padmux),
1084 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp,
1085 usp0_only_urfs_padmux),
3370dc91 1086 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
6225633d
QL		 1087 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1088 usp1_uart_nostreamctrl_grp,
1089 usp1_uart_nostreamctrl_padmux),
3370dc91
BS		 1090 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1091 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1092 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1093 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1094 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1095 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1096 SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
1097 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1098 SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
1099 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1100 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1101 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1102 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1103 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1104 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1105 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1106 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
c09f80db
BS		 1107 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
1108 sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1109 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
1110 usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1111 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1112 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
6a08a92e 1113 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
c09f80db
BS		 1114 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1115 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
3370dc91 1116 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
ed36c1a0 1117 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
086b8904
RY		 1118 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1119 i2s_ext_clk_input_padmux),
3370dc91
BS		 1120 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1121 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1122 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1123 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1124 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1125 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1126 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1127 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1128};
1129
1130struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
1131 (struct pinctrl_pin_desc *)sirfsoc_pads,
1132 ARRAY_SIZE(sirfsoc_pads),
1133 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1134 ARRAY_SIZE(sirfsoc_pin_groups),
1135 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1136 ARRAY_SIZE(sirfsoc_pmx_functions),
1137};
1138
Linux kernel - Deliverables
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