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pinctrl: Remove .owner field
[deliverable/linux.git] / drivers / pinctrl / sirf / pinctrl-atlas7.c
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f9367793
WC		 1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVII
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/io.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/of_platform.h>
21#include <linux/of_irq.h>
22#include <linux/of_gpio.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/pinctrl/pinconf-generic.h>
29#include <linux/gpio.h>
30
31/* Definition of Pad&Mux Properties */
32#define N 0
33
34/* The Bank contains input-disable regisgers */
35#define BANK_DS 0
36
37/* Clear Register offset */
38#define CLR_REG(r) ((r) + 0x04)
39
40/* Definition of multiple function select register */
41#define FUNC_CLEAR_MASK 0x7
42#define FUNC_GPIO 0
43#define FUNC_ANALOGUE 0x8
44#define ANA_CLEAR_MASK 0x1
45
46/* The Atlas7's Pad Type List */
47enum altas7_pad_type {
48 PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
49 PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
50 PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
51 PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
52 PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
53 PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
54 PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
55 PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
56};
57
58/* Raw value of Driver-Strength Bits */
59#define DS3 BIT(3)
60#define DS2 BIT(2)
61#define DS1 BIT(1)
62#define DS0 BIT(0)
63#define DSZ 0
64
65/* Drive-Strength Intermediate Values */
66#define DS_NULL -1
67#define DS_1BIT_IM_VAL DS0
68#define DS_1BIT_MASK 0x1
69#define DS_2BIT_IM_VAL (DS1 | DS0)
70#define DS_2BIT_MASK 0x3
71#define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
72#define DS_4BIT_MASK 0xf
73
74/* The Drive-Strength of 4WE Pad DS1 0 CO */
75#define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
76#define DS_4WE_2 (DS1) /* 1 0 2 */
77#define DS_4WE_1 (DS0) /* 0 1 1 */
78#define DS_4WE_0 (DSZ) /* 0 0 0 */
79
80/* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
81#define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
82#define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
83#define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
84#define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
85#define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
86#define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
87#define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
88#define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
89#define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
90#define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
91#define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
92#define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
93#define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
94#define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
95#define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
96#define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
97
98/* The Drive-Strength of M31 Pad DS0 CO */
99#define DS_M31_0 (DSZ) /* 0 0 */
100#define DS_M31_1 (DS0) /* 1 1 */
101
102/* Raw values of Pull Option Bits */
103#define PUN BIT(1)
104#define PD BIT(0)
105#define PE BIT(0)
106#define PZ 0
107
108/* Definition of Pull Types */
109#define PULL_UP 0
110#define HIGH_HYSTERESIS 1
111#define HIGH_Z 2
112#define PULL_DOWN 3
113#define PULL_DISABLE 4
114#define PULL_ENABLE 5
115#define PULL_UNKNOWN -1
116
117/* Pull Options for 4WE Pad PUN PD CO */
118#define P4WE_PULL_MASK 0x3
119#define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
120#define P4WE_HIGH_Z (PUN) /* 1 0 2 */
121#define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122#define P4WE_PULL_UP (PZ) /* 0 0 0 */
123
124/* Pull Options for 16ST Pad PUN PD CO */
125#define P16ST_PULL_MASK 0x3
126#define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
127#define P16ST_HIGH_Z (PUN) /* 1 0 2 */
128#define P16ST_PULL_UP (PZ) /* 0 0 0 */
129
130/* Pull Options for M31 Pad PE */
131#define PM31_PULL_MASK 0x1
132#define PM31_PULL_ENABLED (PE) /* 1 */
133#define PM31_PULL_DISABLED (PZ) /* 0 */
134
135/* Pull Options for A/D Pad PUN PD CO */
136#define PANGD_PULL_MASK 0x3
137#define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
138#define PANGD_HIGH_Z (PUN) /* 1 0 2 */
139#define PANGD_PULL_UP (PZ) /* 0 0 0 */
140
141/* Definition of Input Disable */
142#define DI_MASK 0x1
143#define DI_DISABLE 0x1
144#define DI_ENABLE 0x0
145
146/* Definition of Input Disable Value */
147#define DIV_MASK 0x1
148#define DIV_DISABLE 0x1
149#define DIV_ENABLE 0x0
150
151struct dt_params {
152 const char *property;
153 int value;
154};
155
156/**
157 * struct atlas7_pad_conf - Atlas7 Pad Configuration
158 * @id The ID of this Pad.
159 * @type: The type of this Pad.
160 * @mux_reg: The mux register offset.
161 * This register contains the mux.
162 * @pupd_reg: The pull-up/down register offset.
163 * @drvstr_reg: The drive-strength register offset.
164 * @ad_ctrl_reg: The Analogue/Digital Control register.
165 *
166 * @mux_bit: The start bit of mux register.
167 * @pupd_bit: The start bit of pull-up/down register.
168 * @drvstr_bit: The start bit of drive-strength register.
169 * @ad_ctrl_bit: The start bit of analogue/digital register.
170 */
171struct atlas7_pad_config {
172 const u32 id;
173 u32 type;
174 u32 mux_reg;
175 u32 pupd_reg;
176 u32 drvstr_reg;
177 u32 ad_ctrl_reg;
178 /* bits in register */
179 u8 mux_bit;
180 u8 pupd_bit;
181 u8 drvstr_bit;
182 u8 ad_ctrl_bit;
183};
184
185#define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
186 { \
187 .id = pad, \
188 .type = t, \
189 .mux_reg = mr, \
190 .pupd_reg = pr, \
191 .drvstr_reg = dsr, \
192 .ad_ctrl_reg = adr, \
193 .mux_bit = mb, \
194 .pupd_bit = pb, \
195 .drvstr_bit = dsb, \
196 .ad_ctrl_bit = adb, \
197 }
198
199/**
200 * struct atlas7_pad_mux - Atlas7 mux
201 * @bank: The bank of this pad's registers on.
202 * @pin : The ID of this Pad.
203 * @func: The mux func on this Pad.
204 * @dinput_reg: The Input-Disable register offset.
205 * @dinput_bit: The start bit of Input-Disable register.
206 * @dinput_val_reg: The Input-Disable-value register offset.
207 * This register is used to set the value of this pad
208 * if this pad was disabled.
209 * @dinput_val_bit: The start bit of Input-Disable Value register.
210 */
211struct atlas7_pad_mux {
212 u32 bank;
213 u32 pin;
214 u32 func;
215 u32 dinput_reg;
216 u32 dinput_bit;
217 u32 dinput_val_reg;
218 u32 dinput_val_bit;
219};
220
221#define MUX(b, pad, f, dr, db, dvr, dvb) \
222 { \
223 .bank = b, \
224 .pin = pad, \
225 .func = f, \
226 .dinput_reg = dr, \
227 .dinput_bit = db, \
228 .dinput_val_reg = dvr, \
229 .dinput_val_bit = dvb, \
230 }
231
232struct atlas7_grp_mux {
233 unsigned int group;
234 unsigned int pad_mux_count;
235 const struct atlas7_pad_mux *pad_mux_list;
236};
237
238 /**
239 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
240 * @name: the name of this specific pin group
241 * @pins: an array of discrete physical pins used in this group, taken
242 * from the driver-local pin enumeration space
243 * @num_pins: the number of pins in this group array, i.e. the number of
244 * elements in .pins so we can iterate over that array
245 */
246struct atlas7_pin_group {
247 const char *name;
248 const unsigned int *pins;
249 const unsigned num_pins;
250};
251
252#define GROUP(n, p) \
253 { \
254 .name = n, \
255 .pins = p, \
256 .num_pins = ARRAY_SIZE(p), \
257 }
258
259struct atlas7_pmx_func {
260 const char *name;
261 const char * const *groups;
262 const unsigned num_groups;
263 const struct atlas7_grp_mux *grpmux;
264};
265
266#define FUNCTION(n, g, m) \
267 { \
268 .name = n, \
269 .groups = g, \
270 .num_groups = ARRAY_SIZE(g), \
271 .grpmux = m, \
272 }
273
274struct atlas7_pinctrl_data {
275 struct pinctrl_pin_desc *pads;
276 int pads_cnt;
277 struct atlas7_pin_group *grps;
278 int grps_cnt;
279 struct atlas7_pmx_func *funcs;
280 int funcs_cnt;
281 struct atlas7_pad_config *confs;
282 int confs_cnt;
283};
284
285/* Platform info of atlas7 pinctrl */
286#define ATLAS7_PINCTRL_REG_BANKS 2
287#define ATLAS7_PINCTRL_BANK_0_PINS 18
288
289/**
290 * Atlas7 GPIO Chip
291 */
292
293#define NGPIO_OF_BANK 32
294#define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
295
296/* Registers of GPIO Controllers */
297#define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
298#define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
299#define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
300
301/* Definition bits of GPIO Control Registers */
302#define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
303#define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
304#define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
305#define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
306#define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
307#define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
308#define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
309#define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
310
311struct atlas7_gpio_bank {
312 struct pinctrl_dev *pctldev;
313 int id;
314 int irq;
315 void __iomem *base;
316 unsigned int gpio_offset;
317 unsigned int ngpio;
318 const unsigned int *gpio_pins;
319};
320
321struct atlas7_gpio_chip {
322 const char *name;
323 void __iomem *reg;
324 struct clk *clk;
325 int nbank;
326 spinlock_t lock;
327 struct gpio_chip chip;
328 struct atlas7_gpio_bank banks[0];
329};
330
331static inline struct atlas7_gpio_chip *to_atlas7_gpio(struct gpio_chip *gc)
332{
333 return container_of(gc, struct atlas7_gpio_chip, chip);
334}
335
336/**
337 * @dev: a pointer back to containing device
338 * @virtbase: the offset to the controller in virtual memory
339 */
340struct atlas7_pmx {
341 struct device *dev;
342 struct pinctrl_dev *pctl;
343 struct pinctrl_desc pctl_desc;
344 struct atlas7_pinctrl_data *pctl_data;
345 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
346};
347
348/*
349 * Pad list for the pinmux subsystem
350 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
351 */
352
353/*Pads in IOC RTC & TOP */
354static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
355 /* RTC PADs */
356 PINCTRL_PIN(0, "rtc_gpio_0"),
357 PINCTRL_PIN(1, "rtc_gpio_1"),
358 PINCTRL_PIN(2, "rtc_gpio_2"),
359 PINCTRL_PIN(3, "rtc_gpio_3"),
360 PINCTRL_PIN(4, "low_bat_ind_b"),
361 PINCTRL_PIN(5, "on_key_b"),
362 PINCTRL_PIN(6, "ext_on"),
363 PINCTRL_PIN(7, "mem_on"),
364 PINCTRL_PIN(8, "core_on"),
365 PINCTRL_PIN(9, "io_on"),
366 PINCTRL_PIN(10, "can0_tx"),
367 PINCTRL_PIN(11, "can0_rx"),
368 PINCTRL_PIN(12, "spi0_clk"),
369 PINCTRL_PIN(13, "spi0_cs_b"),
370 PINCTRL_PIN(14, "spi0_io_0"),
371 PINCTRL_PIN(15, "spi0_io_1"),
372 PINCTRL_PIN(16, "spi0_io_2"),
373 PINCTRL_PIN(17, "spi0_io_3"),
374
375 /* TOP PADs */
376 PINCTRL_PIN(18, "spi1_en"),
377 PINCTRL_PIN(19, "spi1_clk"),
378 PINCTRL_PIN(20, "spi1_din"),
379 PINCTRL_PIN(21, "spi1_dout"),
380 PINCTRL_PIN(22, "trg_spi_clk"),
381 PINCTRL_PIN(23, "trg_spi_di"),
382 PINCTRL_PIN(24, "trg_spi_do"),
383 PINCTRL_PIN(25, "trg_spi_cs_b"),
384 PINCTRL_PIN(26, "trg_acq_d1"),
385 PINCTRL_PIN(27, "trg_irq_b"),
386 PINCTRL_PIN(28, "trg_acq_d0"),
387 PINCTRL_PIN(29, "trg_acq_clk"),
388 PINCTRL_PIN(30, "trg_shutdown_b_out"),
389 PINCTRL_PIN(31, "sdio2_clk"),
390 PINCTRL_PIN(32, "sdio2_cmd"),
391 PINCTRL_PIN(33, "sdio2_dat_0"),
392 PINCTRL_PIN(34, "sdio2_dat_1"),
393 PINCTRL_PIN(35, "sdio2_dat_2"),
394 PINCTRL_PIN(36, "sdio2_dat_3"),
395 PINCTRL_PIN(37, "df_ad_7"),
396 PINCTRL_PIN(38, "df_ad_6"),
397 PINCTRL_PIN(39, "df_ad_5"),
398 PINCTRL_PIN(40, "df_ad_4"),
399 PINCTRL_PIN(41, "df_ad_3"),
400 PINCTRL_PIN(42, "df_ad_2"),
401 PINCTRL_PIN(43, "df_ad_1"),
402 PINCTRL_PIN(44, "df_ad_0"),
403 PINCTRL_PIN(45, "df_dqs"),
404 PINCTRL_PIN(46, "df_cle"),
405 PINCTRL_PIN(47, "df_ale"),
406 PINCTRL_PIN(48, "df_we_b"),
407 PINCTRL_PIN(49, "df_re_b"),
408 PINCTRL_PIN(50, "df_ry_by"),
409 PINCTRL_PIN(51, "df_cs_b_1"),
410 PINCTRL_PIN(52, "df_cs_b_0"),
411 PINCTRL_PIN(53, "l_pclk"),
412 PINCTRL_PIN(54, "l_lck"),
413 PINCTRL_PIN(55, "l_fck"),
414 PINCTRL_PIN(56, "l_de"),
415 PINCTRL_PIN(57, "ldd_0"),
416 PINCTRL_PIN(58, "ldd_1"),
417 PINCTRL_PIN(59, "ldd_2"),
418 PINCTRL_PIN(60, "ldd_3"),
419 PINCTRL_PIN(61, "ldd_4"),
420 PINCTRL_PIN(62, "ldd_5"),
421 PINCTRL_PIN(63, "ldd_6"),
422 PINCTRL_PIN(64, "ldd_7"),
423 PINCTRL_PIN(65, "ldd_8"),
424 PINCTRL_PIN(66, "ldd_9"),
425 PINCTRL_PIN(67, "ldd_10"),
426 PINCTRL_PIN(68, "ldd_11"),
427 PINCTRL_PIN(69, "ldd_12"),
428 PINCTRL_PIN(70, "ldd_13"),
429 PINCTRL_PIN(71, "ldd_14"),
430 PINCTRL_PIN(72, "ldd_15"),
431 PINCTRL_PIN(73, "lcd_gpio_20"),
432 PINCTRL_PIN(74, "vip_0"),
433 PINCTRL_PIN(75, "vip_1"),
434 PINCTRL_PIN(76, "vip_2"),
435 PINCTRL_PIN(77, "vip_3"),
436 PINCTRL_PIN(78, "vip_4"),
437 PINCTRL_PIN(79, "vip_5"),
438 PINCTRL_PIN(80, "vip_6"),
439 PINCTRL_PIN(81, "vip_7"),
440 PINCTRL_PIN(82, "vip_pxclk"),
441 PINCTRL_PIN(83, "vip_hsync"),
442 PINCTRL_PIN(84, "vip_vsync"),
443 PINCTRL_PIN(85, "sdio3_clk"),
444 PINCTRL_PIN(86, "sdio3_cmd"),
445 PINCTRL_PIN(87, "sdio3_dat_0"),
446 PINCTRL_PIN(88, "sdio3_dat_1"),
447 PINCTRL_PIN(89, "sdio3_dat_2"),
448 PINCTRL_PIN(90, "sdio3_dat_3"),
449 PINCTRL_PIN(91, "sdio5_clk"),
450 PINCTRL_PIN(92, "sdio5_cmd"),
451 PINCTRL_PIN(93, "sdio5_dat_0"),
452 PINCTRL_PIN(94, "sdio5_dat_1"),
453 PINCTRL_PIN(95, "sdio5_dat_2"),
454 PINCTRL_PIN(96, "sdio5_dat_3"),
455 PINCTRL_PIN(97, "rgmii_txd_0"),
456 PINCTRL_PIN(98, "rgmii_txd_1"),
457 PINCTRL_PIN(99, "rgmii_txd_2"),
458 PINCTRL_PIN(100, "rgmii_txd_3"),
459 PINCTRL_PIN(101, "rgmii_txclk"),
460 PINCTRL_PIN(102, "rgmii_tx_ctl"),
461 PINCTRL_PIN(103, "rgmii_rxd_0"),
462 PINCTRL_PIN(104, "rgmii_rxd_1"),
463 PINCTRL_PIN(105, "rgmii_rxd_2"),
464 PINCTRL_PIN(106, "rgmii_rxd_3"),
465 PINCTRL_PIN(107, "rgmii_rx_clk"),
466 PINCTRL_PIN(108, "rgmii_rxc_ctl"),
467 PINCTRL_PIN(109, "rgmii_mdio"),
468 PINCTRL_PIN(110, "rgmii_mdc"),
469 PINCTRL_PIN(111, "rgmii_intr_n"),
470 PINCTRL_PIN(112, "i2s_mclk"),
471 PINCTRL_PIN(113, "i2s_bclk"),
472 PINCTRL_PIN(114, "i2s_ws"),
473 PINCTRL_PIN(115, "i2s_dout0"),
474 PINCTRL_PIN(116, "i2s_dout1"),
475 PINCTRL_PIN(117, "i2s_dout2"),
476 PINCTRL_PIN(118, "i2s_din"),
477 PINCTRL_PIN(119, "gpio_0"),
478 PINCTRL_PIN(120, "gpio_1"),
479 PINCTRL_PIN(121, "gpio_2"),
480 PINCTRL_PIN(122, "gpio_3"),
481 PINCTRL_PIN(123, "gpio_4"),
482 PINCTRL_PIN(124, "gpio_5"),
483 PINCTRL_PIN(125, "gpio_6"),
484 PINCTRL_PIN(126, "gpio_7"),
485 PINCTRL_PIN(127, "sda_0"),
486 PINCTRL_PIN(128, "scl_0"),
487 PINCTRL_PIN(129, "coex_pio_0"),
488 PINCTRL_PIN(130, "coex_pio_1"),
489 PINCTRL_PIN(131, "coex_pio_2"),
490 PINCTRL_PIN(132, "coex_pio_3"),
491 PINCTRL_PIN(133, "uart0_tx"),
492 PINCTRL_PIN(134, "uart0_rx"),
493 PINCTRL_PIN(135, "uart1_tx"),
494 PINCTRL_PIN(136, "uart1_rx"),
495 PINCTRL_PIN(137, "uart3_tx"),
496 PINCTRL_PIN(138, "uart3_rx"),
497 PINCTRL_PIN(139, "uart4_tx"),
498 PINCTRL_PIN(140, "uart4_rx"),
499 PINCTRL_PIN(141, "usp0_clk"),
500 PINCTRL_PIN(142, "usp0_tx"),
501 PINCTRL_PIN(143, "usp0_rx"),
502 PINCTRL_PIN(144, "usp0_fs"),
503 PINCTRL_PIN(145, "usp1_clk"),
504 PINCTRL_PIN(146, "usp1_tx"),
505 PINCTRL_PIN(147, "usp1_rx"),
506 PINCTRL_PIN(148, "usp1_fs"),
507 PINCTRL_PIN(149, "lvds_tx0d4p"),
508 PINCTRL_PIN(150, "lvds_tx0d4n"),
509 PINCTRL_PIN(151, "lvds_tx0d3p"),
510 PINCTRL_PIN(152, "lvds_tx0d3n"),
511 PINCTRL_PIN(153, "lvds_tx0d2p"),
512 PINCTRL_PIN(154, "lvds_tx0d2n"),
513 PINCTRL_PIN(155, "lvds_tx0d1p"),
514 PINCTRL_PIN(156, "lvds_tx0d1n"),
515 PINCTRL_PIN(157, "lvds_tx0d0p"),
516 PINCTRL_PIN(158, "lvds_tx0d0n"),
517};
518
519struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
520 /* The Configuration of IOC_RTC Pads */
521 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
522 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
523 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
524 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
525 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
526 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
527 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
528 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
529 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
530 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
531 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
532 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
533 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
534 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
535 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
536 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
537 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
538 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
539 /* The Configuration of IOC_TOP Pads */
540 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
541 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
542 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
543 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
544 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
545 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
546 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
547 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
548 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
549 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
550 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
551 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
552 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
553 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
554 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
555 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
556 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
557 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
558 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
559 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
560 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
561 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
562 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
563 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
564 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
565 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
566 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
567 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
568 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
569 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
570 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
571 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
572 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
573 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
574 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
575 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
576 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
577 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
578 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
579 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
580 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
581 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
582 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
583 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
584 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
585 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
586 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
587 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
588 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
589 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
590 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
591 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
592 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
593 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
594 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
595 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
596 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
597 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
598 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
599 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
600 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
601 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
602 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
603 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
604 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
605 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
606 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
607 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
608 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
609 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
610 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
611 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
612 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
613 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
614 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
615 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
616 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
617 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
618 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
619 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
620 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
621 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
622 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
623 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
624 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
625 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
626 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
627 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
628 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
629 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
630 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
631 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
632 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
633 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
634 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
635 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
636 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
637 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
638 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
639 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
640 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
641 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
642 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
643 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
644 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
645 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
646 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
647 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
648 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
649 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
650 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
651 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
652 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
653 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
654 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
655 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
656 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
657 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
658 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
659 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
660 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
661 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
662 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
663 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
664 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
665 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
666 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
667 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
668 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
669 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
670 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
671 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
672 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
673 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
674 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
675 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
676 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
677 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
678 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
679 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
680 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
681};
682
683/* pin list of each pin group */
684static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
685 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
686static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
687 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
688 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
689static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
690 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
691 95, 96, 112, 113, 114, 115, 116, 117, 118, };
692static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
693 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
694 141, 142, 143, 144, 145, 146, 147, 148, };
695static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
696 151, 152, 149, 150, };
697static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39,
698 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136,
699 137, 138, 139, 140, };
700static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
701 14, 15, 16, 17, };
702static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
703static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
704 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
705 115, 49, 50, 142, 143, 80, };
706static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
707 114, };
708static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
709static const unsigned int audio_i2s_extclk_pins[] = { 112, };
710static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, };
711static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, };
712static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, };
713static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, };
714static const unsigned int c_can_trnsvr_pins[] = { 1, };
715static const unsigned int c0_can_pins0[] = { 11, 10, };
716static const unsigned int c0_can_pins1[] = { 2, 3, };
717static const unsigned int c1_can_pins0[] = { 138, 137, };
718static const unsigned int c1_can_pins1[] = { 147, 146, };
719static const unsigned int c1_can_pins2[] = { 2, 3, };
720static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
721 69, 70, 71, };
722static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
723static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
724static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
725static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
726static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
727 49, 50, 54, 55, 56, };
728static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
729static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
730static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
731 76, 77, };
732static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
733static const unsigned int clkc_pins0[] = { 30, 47, };
734static const unsigned int clkc_pins1[] = { 78, 54, };
735static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
736static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
737static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
738static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
739static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
740static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
741 79, 80, 81, 83, 84, 73, 55, 56, };
742static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
743static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
744static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
745static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
746static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
747static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
748static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
749static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
750static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
751static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
752static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
753static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
754static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
755static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
756static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
757static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
758static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
759 120, };
760static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
761 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
762static const unsigned int gn_gnss_eclk_pins[] = { 113, };
763static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
764static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
765static const unsigned int gn_gnss_tm_pins[] = { 115, };
766static const unsigned int gn_gnss_tsync_pins[] = { 114, };
767static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
768 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
769static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
770static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
771static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
772static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
773static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
774static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
775static const unsigned int i2c0_pins[] = { 128, 127, };
776static const unsigned int i2c1_pins[] = { 126, 125, };
777static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, };
778static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
779static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
780 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
781 81, 56, 53, };
782static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
783 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
784static const unsigned int ld_ldd_fck_pins[] = { 55, };
785static const unsigned int ld_ldd_lck_pins[] = { 54, };
786static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
787 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
788static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
789 155, 156, 157, 158, };
790static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37,
791 47, 46, 52, 51, 45, 49, 50, 48, 124, };
792static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38,
793 37, 47, 46, 52, 51, 45, 49, 50, 48, };
794static const unsigned int ps_pins[] = { 120, 119, };
795static const unsigned int pwc_core_on_pins[] = { 8, };
796static const unsigned int pwc_ext_on_pins[] = { 6, };
797static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
798static const unsigned int pwc_io_on_pins[] = { 9, };
799static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
800static const unsigned int pwc_mem_on_pins[] = { 7, };
801static const unsigned int pwc_on_key_b_pins0[] = { 5, };
802static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
803static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
804static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
805static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
806static const unsigned int pw_cko0_pins0[] = { 123, };
807static const unsigned int pw_cko0_pins1[] = { 101, };
808static const unsigned int pw_cko0_pins2[] = { 82, };
809static const unsigned int pw_cko1_pins0[] = { 124, };
810static const unsigned int pw_cko1_pins1[] = { 110, };
811static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
812static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
813static const unsigned int pw_pwm0_pins[] = { 119, };
814static const unsigned int pw_pwm1_pins[] = { 120, };
815static const unsigned int pw_pwm2_pins0[] = { 121, };
816static const unsigned int pw_pwm2_pins1[] = { 98, };
817static const unsigned int pw_pwm3_pins0[] = { 122, };
818static const unsigned int pw_pwm3_pins1[] = { 73, };
819static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
820static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
821static const unsigned int pw_backlight_pins0[] = { 122, };
822static const unsigned int pw_backlight_pins1[] = { 73, };
823static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
824 102, 97, 98, 99, 100, 101, };
825static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
826static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
827static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
828static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
829static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
830 37, };
831static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
832static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
833 37, };
834static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
835static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
836static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, };
837static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, };
838static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, };
839static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
840static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
841static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
842static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
843static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
844static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
845static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
846 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
847static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
848static const unsigned int uart0_nopause_pins[] = { 134, 133, };
849static const unsigned int uart1_pins[] = { 136, 135, };
850static const unsigned int uart2_pins[] = { 11, 10, };
851static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, };
852static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, };
853static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, };
854static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, };
855static const unsigned int uart3_nopause_pins0[] = { 138, 137, };
856static const unsigned int uart3_nopause_pins1[] = { 84, 83, };
857static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, };
858static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, };
859static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, };
860static const unsigned int uart4_nopause_pins[] = { 140, 139, };
861static const unsigned int usb0_drvvbus_pins[] = { 51, };
862static const unsigned int usb1_drvvbus_pins[] = { 134, };
863static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
864 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
865 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
866static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
867 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
868static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
869 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
870 99, 100, };
871static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
872 80, 81, };
873static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 108, 103,
874 104, 105, 106, };
875
876/* definition of pin group table */
877struct atlas7_pin_group altas7_pin_groups[] = {
878 GROUP("gnss_gpio_grp", gnss_gpio_pins),
879 GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
880 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
881 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
882 GROUP("lvds_gpio_grp", lvds_gpio_pins),
883 GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins),
884 GROUP("rtc_gpio_grp", rtc_gpio_pins),
885 GROUP("audio_ac97_grp", audio_ac97_pins),
886 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
887 GROUP("audio_i2s_grp", audio_i2s_pins),
888 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
889 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
890 GROUP("audio_uart0_grp", audio_uart0_pins),
891 GROUP("audio_uart1_grp", audio_uart1_pins),
892 GROUP("audio_uart2_grp0", audio_uart2_pins0),
893 GROUP("audio_uart2_grp1", audio_uart2_pins1),
894 GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins),
895 GROUP("c0_can_grp0", c0_can_pins0),
896 GROUP("c0_can_grp1", c0_can_pins1),
897 GROUP("c1_can_grp0", c1_can_pins0),
898 GROUP("c1_can_grp1", c1_can_pins1),
899 GROUP("c1_can_grp2", c1_can_pins2),
900 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
901 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
902 GROUP("ca_coex_grp", ca_coex_pins),
903 GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
904 GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
905 GROUP("ca_pio_grp", ca_pio_pins),
906 GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
907 GROUP("ca_spi_grp", ca_spi_pins),
908 GROUP("ca_trb_grp", ca_trb_pins),
909 GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
910 GROUP("clkc_grp0", clkc_pins0),
911 GROUP("clkc_grp1", clkc_pins1),
912 GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
913 GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
914 GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
915 GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
916 GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
917 GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
918 GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
919 GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
920 GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
921 GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
922 GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
923 GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
924 GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
925 GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
926 GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
927 GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
928 GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
929 GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
930 GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
931 GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
932 GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
933 GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
934 GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
935 GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
936 GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
937 GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
938 GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
939 GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
940 GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
941 GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
942 GROUP("gn_trg_grp0", gn_trg_pins0),
943 GROUP("gn_trg_grp1", gn_trg_pins1),
944 GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
945 GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
946 GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
947 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
948 GROUP("i2c0_grp", i2c0_pins),
949 GROUP("i2c1_grp", i2c1_pins),
950 GROUP("jtag_grp0", jtag_pins0),
951 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
952 GROUP("ld_ldd_grp", ld_ldd_pins),
953 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
954 GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
955 GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
956 GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
957 GROUP("lvds_analog_grp", lvds_analog_pins),
958 GROUP("nd_df_grp", nd_df_pins),
959 GROUP("nd_df_nowp_grp", nd_df_nowp_pins),
960 GROUP("ps_grp", ps_pins),
961 GROUP("pwc_core_on_grp", pwc_core_on_pins),
962 GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
963 GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
964 GROUP("pwc_io_on_grp", pwc_io_on_pins),
965 GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
966 GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
967 GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
968 GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
969 GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
970 GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
971 GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
972 GROUP("pw_cko0_grp0", pw_cko0_pins0),
973 GROUP("pw_cko0_grp1", pw_cko0_pins1),
974 GROUP("pw_cko0_grp2", pw_cko0_pins2),
975 GROUP("pw_cko1_grp0", pw_cko1_pins0),
976 GROUP("pw_cko1_grp1", pw_cko1_pins1),
977 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
978 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
979 GROUP("pw_pwm0_grp", pw_pwm0_pins),
980 GROUP("pw_pwm1_grp", pw_pwm1_pins),
981 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
982 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
983 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
984 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
985 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
986 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
987 GROUP("pw_backlight_grp0", pw_backlight_pins0),
988 GROUP("pw_backlight_grp1", pw_backlight_pins1),
989 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
990 GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
991 GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
992 GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
993 GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
994 GROUP("sd0_grp", sd0_pins),
995 GROUP("sd0_4bit_grp", sd0_4bit_pins),
996 GROUP("sd1_grp", sd1_pins),
997 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
998 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
999 GROUP("sd2_grp0", sd2_pins0),
1000 GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0),
1001 GROUP("sd3_grp", sd3_pins),
1002 GROUP("sd5_grp", sd5_pins),
1003 GROUP("sd6_grp0", sd6_pins0),
1004 GROUP("sd6_grp1", sd6_pins1),
1005 GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
1006 GROUP("sp0_qspi_grp", sp0_qspi_pins),
1007 GROUP("sp1_spi_grp", sp1_spi_pins),
1008 GROUP("tpiu_trace_grp", tpiu_trace_pins),
1009 GROUP("uart0_grp", uart0_pins),
1010 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1011 GROUP("uart1_grp", uart1_pins),
1012 GROUP("uart2_grp", uart2_pins),
1013 GROUP("uart3_grp0", uart3_pins0),
1014 GROUP("uart3_grp1", uart3_pins1),
1015 GROUP("uart3_grp2", uart3_pins2),
1016 GROUP("uart3_grp3", uart3_pins3),
1017 GROUP("uart3_nopause_grp0", uart3_nopause_pins0),
1018 GROUP("uart3_nopause_grp1", uart3_nopause_pins1),
1019 GROUP("uart4_grp0", uart4_pins0),
1020 GROUP("uart4_grp1", uart4_pins1),
1021 GROUP("uart4_grp2", uart4_pins2),
1022 GROUP("uart4_nopause_grp", uart4_nopause_pins),
1023 GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins),
1024 GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins),
1025 GROUP("visbus_dout_grp", visbus_dout_pins),
1026 GROUP("vi_vip1_grp", vi_vip1_pins),
1027 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
1028 GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
1029 GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
1030};
1031
1032/* How many groups that a function can use */
1033static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
1034static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1035static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1036static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1037static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1038static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", };
1039static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1040static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1041static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1042static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1043static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1044static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1045static const char * const audio_uart0_grp[] = { "audio_uart0_grp", };
1046static const char * const audio_uart1_grp[] = { "audio_uart1_grp", };
1047static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", };
1048static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", };
1049static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", };
1050static const char * const c0_can_grp0[] = { "c0_can_grp0", };
1051static const char * const c0_can_grp1[] = { "c0_can_grp1", };
1052static const char * const c1_can_grp0[] = { "c1_can_grp0", };
1053static const char * const c1_can_grp1[] = { "c1_can_grp1", };
1054static const char * const c1_can_grp2[] = { "c1_can_grp2", };
1055static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1056static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1057static const char * const ca_coex_grp[] = { "ca_coex_grp", };
1058static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
1059static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
1060static const char * const ca_pio_grp[] = { "ca_pio_grp", };
1061static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
1062static const char * const ca_spi_grp[] = { "ca_spi_grp", };
1063static const char * const ca_trb_grp[] = { "ca_trb_grp", };
1064static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
1065static const char * const clkc_grp0[] = { "clkc_grp0", };
1066static const char * const clkc_grp1[] = { "clkc_grp1", };
1067static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
1068static const char * const gn_gnss_uart_nopause_grp[] = {
1069 "gn_gnss_uart_nopause_grp", };
1070static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
1071static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
1072static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
1073static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
1074static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
1075static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
1076static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
1077static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
1078static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
1079static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
1080static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
1081static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
1082static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
1083static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
1084static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
1085static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
1086static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
1087static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
1088static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
1089static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
1090static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
1091static const char * const gn_gnss_sw_status_grp[] = {
1092 "gn_gnss_sw_status_grp", };
1093static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
1094static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
1095static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
1096static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
1097static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
1098static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
1099 "gn_io_gnsssys_sw_cfg_grp", };
1100static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
1101static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
1102static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
1103static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
1104static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1105static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1106static const char * const i2c0_grp[] = { "i2c0_grp", };
1107static const char * const i2c1_grp[] = { "i2c1_grp", };
1108static const char * const jtag_grp0[] = { "jtag_grp0", };
1109static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1110static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1111static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
1112static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
1113static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
1114static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
1115static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
1116static const char * const nd_df_grp[] = { "nd_df_grp", };
1117static const char * const nd_df_nowp_grp[] = { "nd_df_nowp_grp", };
1118static const char * const ps_grp[] = { "ps_grp", };
1119static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
1120static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
1121static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
1122static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
1123static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
1124static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
1125static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
1126static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
1127static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
1128static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
1129static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1130static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1131static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1132static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1133static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1134static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1135static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1136static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1137static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", };
1138static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", };
1139static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1140static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1141static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1142static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1143static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1144static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1145static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1146static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1147static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
1148static const char * const rg_gmac_phy_intr_n_grp[] = {
1149 "rg_gmac_phy_intr_n_grp", };
1150static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
1151static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
1152 "rg_rgmii_phy_ref_clk_grp0", };
1153static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
1154 "rg_rgmii_phy_ref_clk_grp1", };
1155static const char * const sd0_grp[] = { "sd0_grp", };
1156static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1157static const char * const sd1_grp[] = { "sd1_grp", };
1158static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1159static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1160static const char * const sd2_grp0[] = { "sd2_grp0", };
1161static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", };
1162static const char * const sd3_grp[] = { "sd3_grp", };
1163static const char * const sd5_grp[] = { "sd5_grp", };
1164static const char * const sd6_grp0[] = { "sd6_grp0", };
1165static const char * const sd6_grp1[] = { "sd6_grp1", };
1166static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
1167static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
1168static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
1169static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1170static const char * const uart0_grp[] = { "uart0_grp", };
1171static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1172static const char * const uart1_grp[] = { "uart1_grp", };
1173static const char * const uart2_grp[] = { "uart2_grp", };
1174static const char * const uart3_grp0[] = { "uart3_grp0", };
1175static const char * const uart3_grp1[] = { "uart3_grp1", };
1176static const char * const uart3_grp2[] = { "uart3_grp2", };
1177static const char * const uart3_grp3[] = { "uart3_grp3", };
1178static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", };
1179static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", };
1180static const char * const uart4_grp0[] = { "uart4_grp0", };
1181static const char * const uart4_grp1[] = { "uart4_grp1", };
1182static const char * const uart4_grp2[] = { "uart4_grp2", };
1183static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", };
1184static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", };
1185static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", };
1186static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1187static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1188static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
1189static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
1190static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
1191
1192static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
1193 MUX(1, 119, 0, N, N, N, N),
1194 MUX(1, 120, 0, N, N, N, N),
1195 MUX(1, 121, 0, N, N, N, N),
1196 MUX(1, 122, 0, N, N, N, N),
1197 MUX(1, 123, 0, N, N, N, N),
1198 MUX(1, 124, 0, N, N, N, N),
1199 MUX(1, 125, 0, N, N, N, N),
1200 MUX(1, 126, 0, N, N, N, N),
1201 MUX(1, 127, 0, N, N, N, N),
1202 MUX(1, 128, 0, N, N, N, N),
1203 MUX(1, 22, 0, N, N, N, N),
1204 MUX(1, 23, 0, N, N, N, N),
1205 MUX(1, 24, 0, N, N, N, N),
1206 MUX(1, 25, 0, N, N, N, N),
1207 MUX(1, 26, 0, N, N, N, N),
1208 MUX(1, 27, 0, N, N, N, N),
1209 MUX(1, 28, 0, N, N, N, N),
1210 MUX(1, 29, 0, N, N, N, N),
1211 MUX(1, 30, 0, N, N, N, N),
1212};
1213
1214static struct atlas7_grp_mux gnss_gpio_grp_mux = {
1215 .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
1216 .pad_mux_list = gnss_gpio_grp_pad_mux,
1217};
1218
1219static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
1220 MUX(1, 74, 0, N, N, N, N),
1221 MUX(1, 75, 0, N, N, N, N),
1222 MUX(1, 76, 0, N, N, N, N),
1223 MUX(1, 77, 0, N, N, N, N),
1224 MUX(1, 78, 0, N, N, N, N),
1225 MUX(1, 79, 0, N, N, N, N),
1226 MUX(1, 80, 0, N, N, N, N),
1227 MUX(1, 81, 0, N, N, N, N),
1228 MUX(1, 82, 0, N, N, N, N),
1229 MUX(1, 83, 0, N, N, N, N),
1230 MUX(1, 84, 0, N, N, N, N),
1231 MUX(1, 53, 0, N, N, N, N),
1232 MUX(1, 54, 0, N, N, N, N),
1233 MUX(1, 55, 0, N, N, N, N),
1234 MUX(1, 56, 0, N, N, N, N),
1235 MUX(1, 57, 0, N, N, N, N),
1236 MUX(1, 58, 0, N, N, N, N),
1237 MUX(1, 59, 0, N, N, N, N),
1238 MUX(1, 60, 0, N, N, N, N),
1239 MUX(1, 61, 0, N, N, N, N),
1240 MUX(1, 62, 0, N, N, N, N),
1241 MUX(1, 63, 0, N, N, N, N),
1242 MUX(1, 64, 0, N, N, N, N),
1243 MUX(1, 65, 0, N, N, N, N),
1244 MUX(1, 66, 0, N, N, N, N),
1245 MUX(1, 67, 0, N, N, N, N),
1246 MUX(1, 68, 0, N, N, N, N),
1247 MUX(1, 69, 0, N, N, N, N),
1248 MUX(1, 70, 0, N, N, N, N),
1249 MUX(1, 71, 0, N, N, N, N),
1250 MUX(1, 72, 0, N, N, N, N),
1251 MUX(1, 73, 0, N, N, N, N),
1252};
1253
1254static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
1255 .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
1256 .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
1257};
1258
1259static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
1260 MUX(1, 31, 0, N, N, N, N),
1261 MUX(1, 32, 0, N, N, N, N),
1262 MUX(1, 33, 0, N, N, N, N),
1263 MUX(1, 34, 0, N, N, N, N),
1264 MUX(1, 35, 0, N, N, N, N),
1265 MUX(1, 36, 0, N, N, N, N),
1266 MUX(1, 85, 0, N, N, N, N),
1267 MUX(1, 86, 0, N, N, N, N),
1268 MUX(1, 87, 0, N, N, N, N),
1269 MUX(1, 88, 0, N, N, N, N),
1270 MUX(1, 89, 0, N, N, N, N),
1271 MUX(1, 90, 0, N, N, N, N),
1272 MUX(1, 129, 0, N, N, N, N),
1273 MUX(1, 130, 0, N, N, N, N),
1274 MUX(1, 131, 0, N, N, N, N),
1275 MUX(1, 132, 0, N, N, N, N),
1276 MUX(1, 91, 0, N, N, N, N),
1277 MUX(1, 92, 0, N, N, N, N),
1278 MUX(1, 93, 0, N, N, N, N),
1279 MUX(1, 94, 0, N, N, N, N),
1280 MUX(1, 95, 0, N, N, N, N),
1281 MUX(1, 96, 0, N, N, N, N),
1282 MUX(1, 112, 0, N, N, N, N),
1283 MUX(1, 113, 0, N, N, N, N),
1284 MUX(1, 114, 0, N, N, N, N),
1285 MUX(1, 115, 0, N, N, N, N),
1286 MUX(1, 116, 0, N, N, N, N),
1287 MUX(1, 117, 0, N, N, N, N),
1288 MUX(1, 118, 0, N, N, N, N),
1289};
1290
1291static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
1292 .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
1293 .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
1294};
1295
1296static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
1297 MUX(1, 97, 0, N, N, N, N),
1298 MUX(1, 98, 0, N, N, N, N),
1299 MUX(1, 99, 0, N, N, N, N),
1300 MUX(1, 100, 0, N, N, N, N),
1301 MUX(1, 101, 0, N, N, N, N),
1302 MUX(1, 102, 0, N, N, N, N),
1303 MUX(1, 103, 0, N, N, N, N),
1304 MUX(1, 104, 0, N, N, N, N),
1305 MUX(1, 105, 0, N, N, N, N),
1306 MUX(1, 106, 0, N, N, N, N),
1307 MUX(1, 107, 0, N, N, N, N),
1308 MUX(1, 108, 0, N, N, N, N),
1309 MUX(1, 109, 0, N, N, N, N),
1310 MUX(1, 110, 0, N, N, N, N),
1311 MUX(1, 111, 0, N, N, N, N),
1312 MUX(1, 18, 0, N, N, N, N),
1313 MUX(1, 19, 0, N, N, N, N),
1314 MUX(1, 20, 0, N, N, N, N),
1315 MUX(1, 21, 0, N, N, N, N),
1316 MUX(1, 141, 0, N, N, N, N),
1317 MUX(1, 142, 0, N, N, N, N),
1318 MUX(1, 143, 0, N, N, N, N),
1319 MUX(1, 144, 0, N, N, N, N),
1320 MUX(1, 145, 0, N, N, N, N),
1321 MUX(1, 146, 0, N, N, N, N),
1322 MUX(1, 147, 0, N, N, N, N),
1323 MUX(1, 148, 0, N, N, N, N),
1324};
1325
1326static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
1327 .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
1328 .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
1329};
1330
1331static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
1332 MUX(1, 157, 0, N, N, N, N),
1333 MUX(1, 158, 0, N, N, N, N),
1334 MUX(1, 155, 0, N, N, N, N),
1335 MUX(1, 156, 0, N, N, N, N),
1336 MUX(1, 153, 0, N, N, N, N),
1337 MUX(1, 154, 0, N, N, N, N),
1338 MUX(1, 151, 0, N, N, N, N),
1339 MUX(1, 152, 0, N, N, N, N),
1340 MUX(1, 149, 0, N, N, N, N),
1341 MUX(1, 150, 0, N, N, N, N),
1342};
1343
1344static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1345 .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
1346 .pad_mux_list = lvds_gpio_grp_pad_mux,
1347};
1348
1349static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = {
1350 MUX(1, 44, 0, N, N, N, N),
1351 MUX(1, 43, 0, N, N, N, N),
1352 MUX(1, 42, 0, N, N, N, N),
1353 MUX(1, 41, 0, N, N, N, N),
1354 MUX(1, 40, 0, N, N, N, N),
1355 MUX(1, 39, 0, N, N, N, N),
1356 MUX(1, 38, 0, N, N, N, N),
1357 MUX(1, 37, 0, N, N, N, N),
1358 MUX(1, 46, 0, N, N, N, N),
1359 MUX(1, 47, 0, N, N, N, N),
1360 MUX(1, 48, 0, N, N, N, N),
1361 MUX(1, 49, 0, N, N, N, N),
1362 MUX(1, 50, 0, N, N, N, N),
1363 MUX(1, 52, 0, N, N, N, N),
1364 MUX(1, 51, 0, N, N, N, N),
1365 MUX(1, 45, 0, N, N, N, N),
1366 MUX(1, 133, 0, N, N, N, N),
1367 MUX(1, 134, 0, N, N, N, N),
1368 MUX(1, 135, 0, N, N, N, N),
1369 MUX(1, 136, 0, N, N, N, N),
1370 MUX(1, 137, 0, N, N, N, N),
1371 MUX(1, 138, 0, N, N, N, N),
1372 MUX(1, 139, 0, N, N, N, N),
1373 MUX(1, 140, 0, N, N, N, N),
1374};
1375
1376static struct atlas7_grp_mux uart_nand_gpio_grp_mux = {
1377 .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux),
1378 .pad_mux_list = uart_nand_gpio_grp_pad_mux,
1379};
1380
1381static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1382 MUX(0, 0, 0, N, N, N, N),
1383 MUX(0, 1, 0, N, N, N, N),
1384 MUX(0, 2, 0, N, N, N, N),
1385 MUX(0, 3, 0, N, N, N, N),
1386 MUX(0, 4, 0, N, N, N, N),
1387 MUX(0, 10, 0, N, N, N, N),
1388 MUX(0, 11, 0, N, N, N, N),
1389 MUX(0, 12, 0, N, N, N, N),
1390 MUX(0, 13, 0, N, N, N, N),
1391 MUX(0, 14, 0, N, N, N, N),
1392 MUX(0, 15, 0, N, N, N, N),
1393 MUX(0, 16, 0, N, N, N, N),
1394 MUX(0, 17, 0, N, N, N, N),
1395};
1396
1397static struct atlas7_grp_mux rtc_gpio_grp_mux = {
1398 .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
1399 .pad_mux_list = rtc_gpio_grp_pad_mux,
1400};
1401
1402static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
1403 MUX(1, 113, 2, N, N, N, N),
1404 MUX(1, 118, 2, N, N, N, N),
1405 MUX(1, 115, 2, N, N, N, N),
1406 MUX(1, 114, 2, N, N, N, N),
1407};
1408
1409static struct atlas7_grp_mux audio_ac97_grp_mux = {
1410 .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
1411 .pad_mux_list = audio_ac97_grp_pad_mux,
1412};
1413
1414static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1415 MUX(1, 141, 4, N, N, N, N),
1416 MUX(1, 144, 4, N, N, N, N),
1417 MUX(1, 44, 6, N, N, N, N),
1418 MUX(1, 43, 6, N, N, N, N),
1419 MUX(1, 42, 6, N, N, N, N),
1420 MUX(1, 41, 6, N, N, N, N),
1421 MUX(1, 40, 6, N, N, N, N),
1422 MUX(1, 39, 6, N, N, N, N),
1423 MUX(1, 38, 6, N, N, N, N),
1424 MUX(1, 37, 6, N, N, N, N),
1425 MUX(1, 74, 6, N, N, N, N),
1426 MUX(1, 75, 6, N, N, N, N),
1427 MUX(1, 76, 6, N, N, N, N),
1428 MUX(1, 77, 6, N, N, N, N),
1429 MUX(1, 78, 6, N, N, N, N),
1430 MUX(1, 79, 6, N, N, N, N),
1431 MUX(1, 81, 6, N, N, N, N),
1432 MUX(1, 113, 6, N, N, N, N),
1433 MUX(1, 114, 6, N, N, N, N),
1434 MUX(1, 118, 6, N, N, N, N),
1435 MUX(1, 115, 6, N, N, N, N),
1436 MUX(1, 49, 6, N, N, N, N),
1437 MUX(1, 50, 6, N, N, N, N),
1438 MUX(1, 142, 4, N, N, N, N),
1439 MUX(1, 143, 4, N, N, N, N),
1440 MUX(1, 80, 6, N, N, N, N),
1441};
1442
1443static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
1444 .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
1445 .pad_mux_list = audio_func_dbg_grp_pad_mux,
1446};
1447
1448static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
1449 MUX(1, 118, 1, N, N, N, N),
1450 MUX(1, 115, 1, N, N, N, N),
1451 MUX(1, 116, 1, N, N, N, N),
1452 MUX(1, 117, 1, N, N, N, N),
1453 MUX(1, 112, 1, N, N, N, N),
1454 MUX(1, 113, 1, N, N, N, N),
1455 MUX(1, 114, 1, N, N, N, N),
1456};
1457
1458static struct atlas7_grp_mux audio_i2s_grp_mux = {
1459 .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
1460 .pad_mux_list = audio_i2s_grp_pad_mux,
1461};
1462
1463static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
1464 MUX(1, 118, 1, N, N, N, N),
1465 MUX(1, 115, 1, N, N, N, N),
1466 MUX(1, 112, 1, N, N, N, N),
1467 MUX(1, 113, 1, N, N, N, N),
1468 MUX(1, 114, 1, N, N, N, N),
1469};
1470
1471static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
1472 .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
1473 .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
1474};
1475
1476static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
1477 MUX(1, 112, 2, N, N, N, N),
1478};
1479
1480static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1481 .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
1482 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1483};
1484
1485static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = {
1486 MUX(1, 143, 1, N, N, N, N),
1487 MUX(1, 142, 1, N, N, N, N),
1488 MUX(1, 141, 1, N, N, N, N),
1489 MUX(1, 144, 1, N, N, N, N),
1490};
1491
1492static struct atlas7_grp_mux audio_uart0_grp_mux = {
1493 .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux),
1494 .pad_mux_list = audio_uart0_grp_pad_mux,
1495};
1496
1497static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = {
1498 MUX(1, 147, 1, N, N, N, N),
1499 MUX(1, 146, 1, N, N, N, N),
1500 MUX(1, 145, 1, N, N, N, N),
1501 MUX(1, 148, 1, N, N, N, N),
1502};
1503
1504static struct atlas7_grp_mux audio_uart1_grp_mux = {
1505 .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux),
1506 .pad_mux_list = audio_uart1_grp_pad_mux,
1507};
1508
1509static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = {
1510 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
1511 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
1512 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
1513 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
1514};
1515
1516static struct atlas7_grp_mux audio_uart2_grp0_mux = {
1517 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux),
1518 .pad_mux_list = audio_uart2_grp0_pad_mux,
1519};
1520
1521static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = {
1522 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
1523 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
1524 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
1525 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
1526};
1527
1528static struct atlas7_grp_mux audio_uart2_grp1_mux = {
1529 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux),
1530 .pad_mux_list = audio_uart2_grp1_pad_mux,
1531};
1532
1533static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = {
1534 MUX(0, 1, 2, N, N, N, N),
1535};
1536
1537static struct atlas7_grp_mux c_can_trnsvr_grp_mux = {
1538 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux),
1539 .pad_mux_list = c_can_trnsvr_grp_pad_mux,
1540};
1541
1542static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = {
1543 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
1544 MUX(0, 10, 1, N, N, N, N),
1545};
1546
1547static struct atlas7_grp_mux c0_can_grp0_mux = {
1548 .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux),
1549 .pad_mux_list = c0_can_grp0_pad_mux,
1550};
1551
1552static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = {
1553 MUX(0, 2, 5, 0xa08, 9, 0xa88, 9),
1554 MUX(0, 3, 5, N, N, N, N),
1555};
1556
1557static struct atlas7_grp_mux c0_can_grp1_mux = {
1558 .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux),
1559 .pad_mux_list = c0_can_grp1_pad_mux,
1560};
1561
1562static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = {
1563 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
1564 MUX(1, 137, 2, N, N, N, N),
1565};
1566
1567static struct atlas7_grp_mux c1_can_grp0_mux = {
1568 .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux),
1569 .pad_mux_list = c1_can_grp0_pad_mux,
1570};
1571
1572static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = {
1573 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
1574 MUX(1, 146, 2, N, N, N, N),
1575};
1576
1577static struct atlas7_grp_mux c1_can_grp1_mux = {
1578 .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux),
1579 .pad_mux_list = c1_can_grp1_pad_mux,
1580};
1581
1582static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = {
1583 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
1584 MUX(0, 3, 2, N, N, N, N),
1585};
1586
1587static struct atlas7_grp_mux c1_can_grp2_mux = {
1588 .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux),
1589 .pad_mux_list = c1_can_grp2_pad_mux,
1590};
1591
1592static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
1593 MUX(1, 62, 4, N, N, N, N),
1594 MUX(1, 63, 4, N, N, N, N),
1595 MUX(1, 64, 4, N, N, N, N),
1596 MUX(1, 65, 4, N, N, N, N),
1597 MUX(1, 66, 4, N, N, N, N),
1598 MUX(1, 67, 4, N, N, N, N),
1599 MUX(1, 68, 4, N, N, N, N),
1600 MUX(1, 69, 4, N, N, N, N),
1601 MUX(1, 70, 4, N, N, N, N),
1602 MUX(1, 71, 4, N, N, N, N),
1603};
1604
1605static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
1606 .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
1607 .pad_mux_list = ca_audio_lpc_grp_pad_mux,
1608};
1609
1610static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
1611 MUX(1, 85, 5, N, N, N, N),
1612 MUX(1, 86, 5, N, N, N, N),
1613 MUX(1, 87, 5, N, N, N, N),
1614 MUX(1, 88, 5, N, N, N, N),
1615 MUX(1, 89, 5, N, N, N, N),
1616 MUX(1, 90, 5, N, N, N, N),
1617};
1618
1619static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
1620 .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
1621 .pad_mux_list = ca_bt_lpc_grp_pad_mux,
1622};
1623
1624static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
1625 MUX(1, 129, 1, N, N, N, N),
1626 MUX(1, 130, 1, N, N, N, N),
1627 MUX(1, 131, 1, N, N, N, N),
1628 MUX(1, 132, 1, N, N, N, N),
1629};
1630
1631static struct atlas7_grp_mux ca_coex_grp_mux = {
1632 .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
1633 .pad_mux_list = ca_coex_grp_pad_mux,
1634};
1635
1636static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
1637 MUX(1, 57, 4, N, N, N, N),
1638 MUX(1, 58, 4, N, N, N, N),
1639 MUX(1, 59, 4, N, N, N, N),
1640 MUX(1, 60, 4, N, N, N, N),
1641};
1642
1643static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
1644 .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
1645 .pad_mux_list = ca_curator_lpc_grp_pad_mux,
1646};
1647
1648static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
1649 MUX(1, 91, 5, N, N, N, N),
1650 MUX(1, 93, 5, N, N, N, N),
1651 MUX(1, 94, 5, N, N, N, N),
1652 MUX(1, 92, 5, N, N, N, N),
1653};
1654
1655static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
1656 .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
1657 .pad_mux_list = ca_pcm_debug_grp_pad_mux,
1658};
1659
1660static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
1661 MUX(1, 121, 2, N, N, N, N),
1662 MUX(1, 122, 2, N, N, N, N),
1663 MUX(1, 125, 6, N, N, N, N),
1664 MUX(1, 126, 6, N, N, N, N),
1665 MUX(1, 38, 5, N, N, N, N),
1666 MUX(1, 37, 5, N, N, N, N),
1667 MUX(1, 47, 5, N, N, N, N),
1668 MUX(1, 49, 5, N, N, N, N),
1669 MUX(1, 50, 5, N, N, N, N),
1670 MUX(1, 54, 4, N, N, N, N),
1671 MUX(1, 55, 4, N, N, N, N),
1672 MUX(1, 56, 4, N, N, N, N),
1673};
1674
1675static struct atlas7_grp_mux ca_pio_grp_mux = {
1676 .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
1677 .pad_mux_list = ca_pio_grp_pad_mux,
1678};
1679
1680static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
1681 MUX(1, 40, 5, N, N, N, N),
1682 MUX(1, 39, 5, N, N, N, N),
1683 MUX(1, 44, 5, N, N, N, N),
1684 MUX(1, 43, 5, N, N, N, N),
1685 MUX(1, 42, 5, N, N, N, N),
1686 MUX(1, 41, 5, N, N, N, N),
1687};
1688
1689static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
1690 .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
1691 .pad_mux_list = ca_sdio_debug_grp_pad_mux,
1692};
1693
1694static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
1695 MUX(1, 82, 5, N, N, N, N),
1696 MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
1697 MUX(1, 80, 5, N, N, N, N),
1698 MUX(1, 81, 5, N, N, N, N),
1699};
1700
1701static struct atlas7_grp_mux ca_spi_grp_mux = {
1702 .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
1703 .pad_mux_list = ca_spi_grp_pad_mux,
1704};
1705
1706static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
1707 MUX(1, 91, 4, N, N, N, N),
1708 MUX(1, 93, 4, N, N, N, N),
1709 MUX(1, 94, 4, N, N, N, N),
1710 MUX(1, 95, 4, N, N, N, N),
1711 MUX(1, 96, 4, N, N, N, N),
1712 MUX(1, 78, 5, N, N, N, N),
1713 MUX(1, 74, 5, N, N, N, N),
1714 MUX(1, 75, 5, N, N, N, N),
1715 MUX(1, 76, 5, N, N, N, N),
1716 MUX(1, 77, 5, N, N, N, N),
1717};
1718
1719static struct atlas7_grp_mux ca_trb_grp_mux = {
1720 .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
1721 .pad_mux_list = ca_trb_grp_pad_mux,
1722};
1723
1724static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
1725 MUX(1, 136, 3, N, N, N, N),
1726 MUX(1, 135, 3, N, N, N, N),
1727 MUX(1, 134, 3, N, N, N, N),
1728 MUX(1, 133, 3, N, N, N, N),
1729};
1730
1731static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
1732 .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
1733 .pad_mux_list = ca_uart_debug_grp_pad_mux,
1734};
1735
1736static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
1737 MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
1738 MUX(1, 47, 6, N, N, N, N),
1739};
1740
1741static struct atlas7_grp_mux clkc_grp0_mux = {
1742 .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
1743 .pad_mux_list = clkc_grp0_pad_mux,
1744};
1745
1746static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
1747 MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
1748 MUX(1, 54, 5, N, N, N, N),
1749};
1750
1751static struct atlas7_grp_mux clkc_grp1_mux = {
1752 .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
1753 .pad_mux_list = clkc_grp1_pad_mux,
1754};
1755
1756static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
1757 MUX(1, 128, 2, N, N, N, N),
1758 MUX(1, 127, 2, N, N, N, N),
1759};
1760
1761static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
1762 .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
1763 .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
1764};
1765
1766static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
1767 MUX(1, 134, 4, N, N, N, N),
1768 MUX(1, 133, 4, N, N, N, N),
1769};
1770
1771static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
1772 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
1773 .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
1774};
1775
1776static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
1777 MUX(1, 134, 4, N, N, N, N),
1778 MUX(1, 133, 4, N, N, N, N),
1779 MUX(1, 136, 4, N, N, N, N),
1780 MUX(1, 135, 4, N, N, N, N),
1781};
1782
1783static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
1784 .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
1785 .pad_mux_list = gn_gnss_uart_grp_pad_mux,
1786};
1787
1788static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
1789 MUX(1, 22, 1, N, N, N, N),
1790 MUX(1, 25, 1, N, N, N, N),
1791 MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
1792 MUX(1, 24, 1, N, N, N, N),
1793};
1794
1795static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
1796 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
1797 .pad_mux_list = gn_trg_spi_grp0_pad_mux,
1798};
1799
1800static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
1801 MUX(1, 82, 3, N, N, N, N),
1802 MUX(1, 79, 3, N, N, N, N),
1803 MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
1804 MUX(1, 81, 3, N, N, N, N),
1805};
1806
1807static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
1808 .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
1809 .pad_mux_list = gn_trg_spi_grp1_pad_mux,
1810};
1811
1812static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
1813 MUX(1, 54, 3, N, N, N, N),
1814 MUX(1, 53, 3, N, N, N, N),
1815 MUX(1, 82, 7, N, N, N, N),
1816 MUX(1, 74, 7, N, N, N, N),
1817 MUX(1, 75, 7, N, N, N, N),
1818 MUX(1, 76, 7, N, N, N, N),
1819 MUX(1, 77, 7, N, N, N, N),
1820 MUX(1, 78, 7, N, N, N, N),
1821 MUX(1, 79, 7, N, N, N, N),
1822 MUX(1, 80, 7, N, N, N, N),
1823 MUX(1, 81, 7, N, N, N, N),
1824 MUX(1, 83, 7, N, N, N, N),
1825 MUX(1, 84, 7, N, N, N, N),
1826 MUX(1, 73, 3, N, N, N, N),
1827 MUX(1, 55, 3, N, N, N, N),
1828 MUX(1, 56, 3, N, N, N, N),
1829};
1830
1831static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
1832 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
1833 .pad_mux_list = cvbs_dbg_grp_pad_mux,
1834};
1835
1836static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
1837 MUX(1, 57, 3, N, N, N, N),
1838};
1839
1840static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
1841 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
1842 .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
1843};
1844
1845static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
1846 MUX(1, 58, 3, N, N, N, N),
1847};
1848
1849static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
1850 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
1851 .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
1852};
1853
1854static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
1855 MUX(1, 59, 3, N, N, N, N),
1856};
1857
1858static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
1859 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
1860 .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
1861};
1862
1863static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
1864 MUX(1, 60, 3, N, N, N, N),
1865};
1866
1867static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
1868 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
1869 .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
1870};
1871
1872static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
1873 MUX(1, 61, 3, N, N, N, N),
1874};
1875
1876static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
1877 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
1878 .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
1879};
1880
1881static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
1882 MUX(1, 62, 3, N, N, N, N),
1883};
1884
1885static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
1886 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
1887 .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
1888};
1889
1890static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
1891 MUX(1, 63, 3, N, N, N, N),
1892};
1893
1894static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
1895 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
1896 .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
1897};
1898
1899static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
1900 MUX(1, 64, 3, N, N, N, N),
1901};
1902
1903static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
1904 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
1905 .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
1906};
1907
1908static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
1909 MUX(1, 65, 3, N, N, N, N),
1910};
1911
1912static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
1913 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
1914 .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
1915};
1916
1917static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
1918 MUX(1, 66, 3, N, N, N, N),
1919};
1920
1921static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
1922 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
1923 .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
1924};
1925
1926static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
1927 MUX(1, 67, 3, N, N, N, N),
1928};
1929
1930static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
1931 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
1932 .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
1933};
1934
1935static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
1936 MUX(1, 68, 3, N, N, N, N),
1937};
1938
1939static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
1940 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
1941 .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
1942};
1943
1944static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
1945 MUX(1, 69, 3, N, N, N, N),
1946};
1947
1948static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
1949 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
1950 .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
1951};
1952
1953static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
1954 MUX(1, 70, 3, N, N, N, N),
1955};
1956
1957static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
1958 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
1959 .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
1960};
1961
1962static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
1963 MUX(1, 71, 3, N, N, N, N),
1964};
1965
1966static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
1967 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
1968 .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
1969};
1970
1971static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
1972 MUX(1, 72, 3, N, N, N, N),
1973};
1974
1975static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
1976 .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
1977 .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
1978};
1979
1980static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
1981 MUX(1, 123, 7, N, N, N, N),
1982 MUX(1, 124, 7, N, N, N, N),
1983 MUX(1, 121, 7, N, N, N, N),
1984 MUX(1, 122, 7, N, N, N, N),
1985 MUX(1, 125, 7, N, N, N, N),
1986 MUX(1, 120, 7, N, N, N, N),
1987};
1988
1989static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
1990 .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
1991 .pad_mux_list = gn_gnss_power_grp_pad_mux,
1992};
1993
1994static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
1995 MUX(1, 57, 7, N, N, N, N),
1996 MUX(1, 58, 7, N, N, N, N),
1997 MUX(1, 59, 7, N, N, N, N),
1998 MUX(1, 60, 7, N, N, N, N),
1999 MUX(1, 61, 7, N, N, N, N),
2000 MUX(1, 62, 7, N, N, N, N),
2001 MUX(1, 63, 7, N, N, N, N),
2002 MUX(1, 64, 7, N, N, N, N),
2003 MUX(1, 65, 7, N, N, N, N),
2004 MUX(1, 66, 7, N, N, N, N),
2005 MUX(1, 67, 7, N, N, N, N),
2006 MUX(1, 68, 7, N, N, N, N),
2007 MUX(1, 69, 7, N, N, N, N),
2008 MUX(1, 70, 7, N, N, N, N),
2009 MUX(1, 71, 7, N, N, N, N),
2010 MUX(1, 72, 7, N, N, N, N),
2011 MUX(1, 53, 7, N, N, N, N),
2012 MUX(1, 55, 7, N, N, N, N),
2013 MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
2014 MUX(1, 54, 7, N, N, N, N),
2015};
2016
2017static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
2018 .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
2019 .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
2020};
2021
2022static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
2023 MUX(1, 113, 4, N, N, N, N),
2024};
2025
2026static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
2027 .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
2028 .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
2029};
2030
2031static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
2032 MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
2033};
2034
2035static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
2036 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
2037 .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
2038};
2039
2040static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
2041 MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
2042};
2043
2044static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
2045 .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
2046 .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
2047};
2048
2049static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
2050 MUX(1, 115, 4, N, N, N, N),
2051};
2052
2053static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
2054 .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
2055 .pad_mux_list = gn_gnss_tm_grp_pad_mux,
2056};
2057
2058static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
2059 MUX(1, 114, 4, N, N, N, N),
2060};
2061
2062static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
2063 .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
2064 .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
2065};
2066
2067static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
2068 MUX(1, 44, 7, N, N, N, N),
2069 MUX(1, 43, 7, N, N, N, N),
2070 MUX(1, 42, 7, N, N, N, N),
2071 MUX(1, 41, 7, N, N, N, N),
2072 MUX(1, 40, 7, N, N, N, N),
2073 MUX(1, 39, 7, N, N, N, N),
2074 MUX(1, 38, 7, N, N, N, N),
2075 MUX(1, 37, 7, N, N, N, N),
2076 MUX(1, 49, 7, N, N, N, N),
2077 MUX(1, 50, 7, N, N, N, N),
2078 MUX(1, 91, 7, N, N, N, N),
2079 MUX(1, 92, 7, N, N, N, N),
2080 MUX(1, 93, 7, N, N, N, N),
2081 MUX(1, 94, 7, N, N, N, N),
2082 MUX(1, 95, 7, N, N, N, N),
2083 MUX(1, 96, 7, N, N, N, N),
2084};
2085
2086static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
2087 .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
2088 .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
2089};
2090
2091static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
2092 MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
2093 MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
2094 MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
2095 MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
2096};
2097
2098static struct atlas7_grp_mux gn_trg_grp0_mux = {
2099 .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
2100 .pad_mux_list = gn_trg_grp0_pad_mux,
2101};
2102
2103static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
2104 MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
2105 MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
2106 MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
2107 MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
2108};
2109
2110static struct atlas7_grp_mux gn_trg_grp1_mux = {
2111 .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
2112 .pad_mux_list = gn_trg_grp1_pad_mux,
2113};
2114
2115static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
2116 MUX(1, 30, 1, N, N, N, N),
2117};
2118
2119static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
2120 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
2121 .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
2122};
2123
2124static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
2125 MUX(1, 83, 3, N, N, N, N),
2126};
2127
2128static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
2129 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
2130 .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
2131};
2132
2133static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
2134 MUX(1, 117, 4, N, N, N, N),
2135};
2136
2137static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
2138 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
2139 .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
2140};
2141
2142static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
2143 MUX(1, 123, 5, N, N, N, N),
2144};
2145
2146static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
2147 .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
2148 .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
2149};
2150
2151static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
2152 MUX(1, 128, 1, N, N, N, N),
2153 MUX(1, 127, 1, N, N, N, N),
2154};
2155
2156static struct atlas7_grp_mux i2c0_grp_mux = {
2157 .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
2158 .pad_mux_list = i2c0_grp_pad_mux,
2159};
2160
2161static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
2162 MUX(1, 126, 4, N, N, N, N),
2163 MUX(1, 125, 4, N, N, N, N),
2164};
2165
2166static struct atlas7_grp_mux i2c1_grp_mux = {
2167 .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
2168 .pad_mux_list = i2c1_grp_pad_mux,
2169};
2170
2171static struct atlas7_pad_mux jtag_grp0_pad_mux[] = {
2172 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2173 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2174 MUX(0, 2, 3, N, N, N, N),
2175 MUX(0, 0, 3, N, N, N, N),
2176 MUX(0, 1, 3, N, N, N, N),
2177 MUX(0, 3, 3, N, N, N, N),
2178};
2179
2180static struct atlas7_grp_mux jtag_grp0_mux = {
2181 .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux),
2182 .pad_mux_list = jtag_grp0_pad_mux,
2183};
2184
2185static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
2186 MUX(1, 141, 2, N, N, N, N),
2187 MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
2188 MUX(1, 143, 2, N, N, N, N),
2189 MUX(1, 142, 2, N, N, N, N),
2190};
2191
2192static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
2193 .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
2194 .pad_mux_list = ks_kas_spi_grp0_pad_mux,
2195};
2196
2197static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
2198 MUX(1, 57, 1, N, N, N, N),
2199 MUX(1, 58, 1, N, N, N, N),
2200 MUX(1, 59, 1, N, N, N, N),
2201 MUX(1, 60, 1, N, N, N, N),
2202 MUX(1, 61, 1, N, N, N, N),
2203 MUX(1, 62, 1, N, N, N, N),
2204 MUX(1, 63, 1, N, N, N, N),
2205 MUX(1, 64, 1, N, N, N, N),
2206 MUX(1, 65, 1, N, N, N, N),
2207 MUX(1, 66, 1, N, N, N, N),
2208 MUX(1, 67, 1, N, N, N, N),
2209 MUX(1, 68, 1, N, N, N, N),
2210 MUX(1, 69, 1, N, N, N, N),
2211 MUX(1, 70, 1, N, N, N, N),
2212 MUX(1, 71, 1, N, N, N, N),
2213 MUX(1, 72, 1, N, N, N, N),
2214 MUX(1, 74, 2, N, N, N, N),
2215 MUX(1, 75, 2, N, N, N, N),
2216 MUX(1, 76, 2, N, N, N, N),
2217 MUX(1, 77, 2, N, N, N, N),
2218 MUX(1, 78, 2, N, N, N, N),
2219 MUX(1, 79, 2, N, N, N, N),
2220 MUX(1, 80, 2, N, N, N, N),
2221 MUX(1, 81, 2, N, N, N, N),
2222 MUX(1, 56, 1, N, N, N, N),
2223 MUX(1, 53, 1, N, N, N, N),
2224};
2225
2226static struct atlas7_grp_mux ld_ldd_grp_mux = {
2227 .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
2228 .pad_mux_list = ld_ldd_grp_pad_mux,
2229};
2230
2231static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
2232 MUX(1, 57, 1, N, N, N, N),
2233 MUX(1, 58, 1, N, N, N, N),
2234 MUX(1, 59, 1, N, N, N, N),
2235 MUX(1, 60, 1, N, N, N, N),
2236 MUX(1, 61, 1, N, N, N, N),
2237 MUX(1, 62, 1, N, N, N, N),
2238 MUX(1, 63, 1, N, N, N, N),
2239 MUX(1, 64, 1, N, N, N, N),
2240 MUX(1, 65, 1, N, N, N, N),
2241 MUX(1, 66, 1, N, N, N, N),
2242 MUX(1, 67, 1, N, N, N, N),
2243 MUX(1, 68, 1, N, N, N, N),
2244 MUX(1, 69, 1, N, N, N, N),
2245 MUX(1, 70, 1, N, N, N, N),
2246 MUX(1, 71, 1, N, N, N, N),
2247 MUX(1, 72, 1, N, N, N, N),
2248 MUX(1, 56, 1, N, N, N, N),
2249 MUX(1, 53, 1, N, N, N, N),
2250};
2251
2252static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
2253 .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
2254 .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
2255};
2256
2257static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
2258 MUX(1, 55, 1, N, N, N, N),
2259};
2260
2261static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
2262 .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
2263 .pad_mux_list = ld_ldd_fck_grp_pad_mux,
2264};
2265
2266static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
2267 MUX(1, 54, 1, N, N, N, N),
2268};
2269
2270static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
2271 .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
2272 .pad_mux_list = ld_ldd_lck_grp_pad_mux,
2273};
2274
2275static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
2276 MUX(1, 73, 2, N, N, N, N),
2277 MUX(1, 54, 2, N, N, N, N),
2278 MUX(1, 57, 2, N, N, N, N),
2279 MUX(1, 58, 2, N, N, N, N),
2280 MUX(1, 59, 2, N, N, N, N),
2281 MUX(1, 60, 2, N, N, N, N),
2282 MUX(1, 61, 2, N, N, N, N),
2283 MUX(1, 62, 2, N, N, N, N),
2284 MUX(1, 63, 2, N, N, N, N),
2285 MUX(1, 64, 2, N, N, N, N),
2286 MUX(1, 65, 2, N, N, N, N),
2287 MUX(1, 66, 2, N, N, N, N),
2288 MUX(1, 67, 2, N, N, N, N),
2289 MUX(1, 68, 2, N, N, N, N),
2290 MUX(1, 69, 2, N, N, N, N),
2291 MUX(1, 70, 2, N, N, N, N),
2292 MUX(1, 71, 2, N, N, N, N),
2293 MUX(1, 72, 2, N, N, N, N),
2294 MUX(1, 56, 2, N, N, N, N),
2295 MUX(1, 53, 2, N, N, N, N),
2296 MUX(1, 55, 2, N, N, N, N),
2297};
2298
2299static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
2300 .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
2301 .pad_mux_list = lr_lcdrom_grp_pad_mux,
2302};
2303
2304static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
2305 MUX(1, 149, 8, N, N, N, N),
2306 MUX(1, 150, 8, N, N, N, N),
2307 MUX(1, 151, 8, N, N, N, N),
2308 MUX(1, 152, 8, N, N, N, N),
2309 MUX(1, 153, 8, N, N, N, N),
2310 MUX(1, 154, 8, N, N, N, N),
2311 MUX(1, 155, 8, N, N, N, N),
2312 MUX(1, 156, 8, N, N, N, N),
2313 MUX(1, 157, 8, N, N, N, N),
2314 MUX(1, 158, 8, N, N, N, N),
2315};
2316
2317static struct atlas7_grp_mux lvds_analog_grp_mux = {
2318 .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
2319 .pad_mux_list = lvds_analog_grp_pad_mux,
2320};
2321
2322static struct atlas7_pad_mux nd_df_grp_pad_mux[] = {
2323 MUX(1, 44, 1, N, N, N, N),
2324 MUX(1, 43, 1, N, N, N, N),
2325 MUX(1, 42, 1, N, N, N, N),
2326 MUX(1, 41, 1, N, N, N, N),
2327 MUX(1, 40, 1, N, N, N, N),
2328 MUX(1, 39, 1, N, N, N, N),
2329 MUX(1, 38, 1, N, N, N, N),
2330 MUX(1, 37, 1, N, N, N, N),
2331 MUX(1, 47, 1, N, N, N, N),
2332 MUX(1, 46, 1, N, N, N, N),
2333 MUX(1, 52, 1, N, N, N, N),
2334 MUX(1, 51, 1, N, N, N, N),
2335 MUX(1, 45, 1, N, N, N, N),
2336 MUX(1, 49, 1, N, N, N, N),
2337 MUX(1, 50, 1, N, N, N, N),
2338 MUX(1, 48, 1, N, N, N, N),
2339 MUX(1, 124, 4, N, N, N, N),
2340};
2341
2342static struct atlas7_grp_mux nd_df_grp_mux = {
2343 .pad_mux_count = ARRAY_SIZE(nd_df_grp_pad_mux),
2344 .pad_mux_list = nd_df_grp_pad_mux,
2345};
2346
2347static struct atlas7_pad_mux nd_df_nowp_grp_pad_mux[] = {
2348 MUX(1, 44, 1, N, N, N, N),
2349 MUX(1, 43, 1, N, N, N, N),
2350 MUX(1, 42, 1, N, N, N, N),
2351 MUX(1, 41, 1, N, N, N, N),
2352 MUX(1, 40, 1, N, N, N, N),
2353 MUX(1, 39, 1, N, N, N, N),
2354 MUX(1, 38, 1, N, N, N, N),
2355 MUX(1, 37, 1, N, N, N, N),
2356 MUX(1, 47, 1, N, N, N, N),
2357 MUX(1, 46, 1, N, N, N, N),
2358 MUX(1, 52, 1, N, N, N, N),
2359 MUX(1, 51, 1, N, N, N, N),
2360 MUX(1, 45, 1, N, N, N, N),
2361 MUX(1, 49, 1, N, N, N, N),
2362 MUX(1, 50, 1, N, N, N, N),
2363 MUX(1, 48, 1, N, N, N, N),
2364};
2365
2366static struct atlas7_grp_mux nd_df_nowp_grp_mux = {
2367 .pad_mux_count = ARRAY_SIZE(nd_df_nowp_grp_pad_mux),
2368 .pad_mux_list = nd_df_nowp_grp_pad_mux,
2369};
2370
2371static struct atlas7_pad_mux ps_grp_pad_mux[] = {
2372 MUX(1, 120, 2, N, N, N, N),
2373 MUX(1, 119, 2, N, N, N, N),
2374};
2375
2376static struct atlas7_grp_mux ps_grp_mux = {
2377 .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
2378 .pad_mux_list = ps_grp_pad_mux,
2379};
2380
2381static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
2382 MUX(0, 8, 1, N, N, N, N),
2383};
2384
2385static struct atlas7_grp_mux pwc_core_on_grp_mux = {
2386 .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
2387 .pad_mux_list = pwc_core_on_grp_pad_mux,
2388};
2389
2390static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
2391 MUX(0, 6, 1, N, N, N, N),
2392};
2393
2394static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
2395 .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
2396 .pad_mux_list = pwc_ext_on_grp_pad_mux,
2397};
2398
2399static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
2400 MUX(0, 3, 4, N, N, N, N),
2401};
2402
2403static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
2404 .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
2405 .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
2406};
2407
2408static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
2409 MUX(0, 9, 1, N, N, N, N),
2410};
2411
2412static struct atlas7_grp_mux pwc_io_on_grp_mux = {
2413 .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
2414 .pad_mux_list = pwc_io_on_grp_pad_mux,
2415};
2416
2417static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
2418 MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
2419};
2420
2421static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
2422 .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
2423 .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
2424};
2425
2426static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
2427 MUX(0, 7, 1, N, N, N, N),
2428};
2429
2430static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
2431 .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
2432 .pad_mux_list = pwc_mem_on_grp_pad_mux,
2433};
2434
2435static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
2436 MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
2437};
2438
2439static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
2440 .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
2441 .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
2442};
2443
2444static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
2445 MUX(0, 0, 1, N, N, N, N),
2446};
2447
2448static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
2449 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
2450 .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
2451};
2452
2453static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
2454 MUX(0, 1, 1, N, N, N, N),
2455};
2456
2457static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
2458 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
2459 .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
2460};
2461
2462static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
2463 MUX(0, 2, 1, N, N, N, N),
2464};
2465
2466static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
2467 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
2468 .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
2469};
2470
2471static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
2472 MUX(0, 3, 1, N, N, N, N),
2473};
2474
2475static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
2476 .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
2477 .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
2478};
2479
2480static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
2481 MUX(1, 123, 3, N, N, N, N),
2482};
2483
2484static struct atlas7_grp_mux pw_cko0_grp0_mux = {
2485 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
2486 .pad_mux_list = pw_cko0_grp0_pad_mux,
2487};
2488
2489static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
2490 MUX(1, 101, 4, N, N, N, N),
2491};
2492
2493static struct atlas7_grp_mux pw_cko0_grp1_mux = {
2494 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
2495 .pad_mux_list = pw_cko0_grp1_pad_mux,
2496};
2497
2498static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
2499 MUX(1, 82, 2, N, N, N, N),
2500};
2501
2502static struct atlas7_grp_mux pw_cko0_grp2_mux = {
2503 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
2504 .pad_mux_list = pw_cko0_grp2_pad_mux,
2505};
2506
2507static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
2508 MUX(1, 124, 3, N, N, N, N),
2509};
2510
2511static struct atlas7_grp_mux pw_cko1_grp0_mux = {
2512 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
2513 .pad_mux_list = pw_cko1_grp0_pad_mux,
2514};
2515
2516static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
2517 MUX(1, 110, 4, N, N, N, N),
2518};
2519
2520static struct atlas7_grp_mux pw_cko1_grp1_mux = {
2521 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
2522 .pad_mux_list = pw_cko1_grp1_pad_mux,
2523};
2524
2525static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
2526 MUX(1, 125, 3, N, N, N, N),
2527};
2528
2529static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
2530 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
2531 .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
2532};
2533
2534static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
2535 MUX(1, 117, 3, N, N, N, N),
2536};
2537
2538static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
2539 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
2540 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
2541};
2542
2543static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = {
2544 MUX(1, 119, 3, N, N, N, N),
2545};
2546
2547static struct atlas7_grp_mux pw_pwm0_grp_mux = {
2548 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux),
2549 .pad_mux_list = pw_pwm0_grp_pad_mux,
2550};
2551
2552static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = {
2553 MUX(1, 120, 3, N, N, N, N),
2554};
2555
2556static struct atlas7_grp_mux pw_pwm1_grp_mux = {
2557 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux),
2558 .pad_mux_list = pw_pwm1_grp_pad_mux,
2559};
2560
2561static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
2562 MUX(1, 121, 3, N, N, N, N),
2563};
2564
2565static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
2566 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
2567 .pad_mux_list = pw_pwm2_grp0_pad_mux,
2568};
2569
2570static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
2571 MUX(1, 98, 3, N, N, N, N),
2572};
2573
2574static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
2575 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
2576 .pad_mux_list = pw_pwm2_grp1_pad_mux,
2577};
2578
2579static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
2580 MUX(1, 122, 3, N, N, N, N),
2581};
2582
2583static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
2584 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
2585 .pad_mux_list = pw_pwm3_grp0_pad_mux,
2586};
2587
2588static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
2589 MUX(1, 73, 4, N, N, N, N),
2590};
2591
2592static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
2593 .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
2594 .pad_mux_list = pw_pwm3_grp1_pad_mux,
2595};
2596
2597static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
2598 MUX(1, 121, 3, N, N, N, N),
2599};
2600
2601static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
2602 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
2603 .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
2604};
2605
2606static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
2607 MUX(1, 98, 3, N, N, N, N),
2608};
2609
2610static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
2611 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
2612 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
2613};
2614
2615static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
2616 MUX(1, 122, 3, N, N, N, N),
2617};
2618
2619static struct atlas7_grp_mux pw_backlight_grp0_mux = {
2620 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
2621 .pad_mux_list = pw_backlight_grp0_pad_mux,
2622};
2623
2624static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
2625 MUX(1, 73, 4, N, N, N, N),
2626};
2627
2628static struct atlas7_grp_mux pw_backlight_grp1_mux = {
2629 .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
2630 .pad_mux_list = pw_backlight_grp1_pad_mux,
2631};
2632
2633static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
2634 MUX(1, 108, 1, N, N, N, N),
2635 MUX(1, 103, 1, N, N, N, N),
2636 MUX(1, 104, 1, N, N, N, N),
2637 MUX(1, 105, 1, N, N, N, N),
2638 MUX(1, 106, 1, N, N, N, N),
2639 MUX(1, 107, 1, N, N, N, N),
2640 MUX(1, 102, 1, N, N, N, N),
2641 MUX(1, 97, 1, N, N, N, N),
2642 MUX(1, 98, 1, N, N, N, N),
2643 MUX(1, 99, 1, N, N, N, N),
2644 MUX(1, 100, 1, N, N, N, N),
2645 MUX(1, 101, 1, N, N, N, N),
2646};
2647
2648static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
2649 .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
2650 .pad_mux_list = rg_eth_mac_grp_pad_mux,
2651};
2652
2653static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
2654 MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
2655};
2656
2657static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
2658 .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
2659 .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
2660};
2661
2662static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
2663 MUX(1, 109, 1, N, N, N, N),
2664 MUX(1, 110, 1, N, N, N, N),
2665};
2666
2667static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
2668 .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
2669 .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
2670};
2671
2672static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
2673 MUX(1, 111, 5, N, N, N, N),
2674};
2675
2676static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
2677 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
2678 .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
2679};
2680
2681static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
2682 MUX(1, 53, 4, N, N, N, N),
2683};
2684
2685static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
2686 .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
2687 .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
2688};
2689
2690static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
2691 MUX(1, 46, 2, N, N, N, N),
2692 MUX(1, 47, 2, N, N, N, N),
2693 MUX(1, 44, 2, N, N, N, N),
2694 MUX(1, 43, 2, N, N, N, N),
2695 MUX(1, 42, 2, N, N, N, N),
2696 MUX(1, 41, 2, N, N, N, N),
2697 MUX(1, 40, 2, N, N, N, N),
2698 MUX(1, 39, 2, N, N, N, N),
2699 MUX(1, 38, 2, N, N, N, N),
2700 MUX(1, 37, 2, N, N, N, N),
2701};
2702
2703static struct atlas7_grp_mux sd0_grp_mux = {
2704 .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
2705 .pad_mux_list = sd0_grp_pad_mux,
2706};
2707
2708static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
2709 MUX(1, 46, 2, N, N, N, N),
2710 MUX(1, 47, 2, N, N, N, N),
2711 MUX(1, 44, 2, N, N, N, N),
2712 MUX(1, 43, 2, N, N, N, N),
2713 MUX(1, 42, 2, N, N, N, N),
2714 MUX(1, 41, 2, N, N, N, N),
2715};
2716
2717static struct atlas7_grp_mux sd0_4bit_grp_mux = {
2718 .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
2719 .pad_mux_list = sd0_4bit_grp_pad_mux,
2720};
2721
2722static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
2723 MUX(1, 48, 3, N, N, N, N),
2724 MUX(1, 49, 3, N, N, N, N),
2725 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
2726 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
2727 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
2728 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
2729 MUX(1, 40, 3, N, N, N, N),
2730 MUX(1, 39, 3, N, N, N, N),
2731 MUX(1, 38, 3, N, N, N, N),
2732 MUX(1, 37, 3, N, N, N, N),
2733};
2734
2735static struct atlas7_grp_mux sd1_grp_mux = {
2736 .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
2737 .pad_mux_list = sd1_grp_pad_mux,
2738};
2739
2740static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
2741 MUX(1, 48, 3, N, N, N, N),
2742 MUX(1, 49, 3, N, N, N, N),
2743 MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
2744 MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
2745 MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
2746 MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
2747};
2748
2749static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
2750 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
2751 .pad_mux_list = sd1_4bit_grp0_pad_mux,
2752};
2753
2754static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
2755 MUX(1, 48, 3, N, N, N, N),
2756 MUX(1, 49, 3, N, N, N, N),
2757 MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
2758 MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
2759 MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
2760 MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
2761};
2762
2763static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
2764 .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
2765 .pad_mux_list = sd1_4bit_grp1_pad_mux,
2766};
2767
2768static struct atlas7_pad_mux sd2_grp0_pad_mux[] = {
2769 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
2770 MUX(1, 31, 1, N, N, N, N),
2771 MUX(1, 32, 1, N, N, N, N),
2772 MUX(1, 33, 1, N, N, N, N),
2773 MUX(1, 34, 1, N, N, N, N),
2774 MUX(1, 35, 1, N, N, N, N),
2775 MUX(1, 36, 1, N, N, N, N),
2776 MUX(1, 123, 2, N, N, N, N),
2777};
2778
2779static struct atlas7_grp_mux sd2_grp0_mux = {
2780 .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux),
2781 .pad_mux_list = sd2_grp0_pad_mux,
2782};
2783
2784static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = {
2785 MUX(1, 31, 1, N, N, N, N),
2786 MUX(1, 32, 1, N, N, N, N),
2787 MUX(1, 33, 1, N, N, N, N),
2788 MUX(1, 34, 1, N, N, N, N),
2789 MUX(1, 35, 1, N, N, N, N),
2790 MUX(1, 36, 1, N, N, N, N),
2791 MUX(1, 123, 2, N, N, N, N),
2792};
2793
2794static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = {
2795 .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux),
2796 .pad_mux_list = sd2_no_cdb_grp0_pad_mux,
2797};
2798
2799static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
2800 MUX(1, 85, 1, N, N, N, N),
2801 MUX(1, 86, 1, N, N, N, N),
2802 MUX(1, 87, 1, N, N, N, N),
2803 MUX(1, 88, 1, N, N, N, N),
2804 MUX(1, 89, 1, N, N, N, N),
2805 MUX(1, 90, 1, N, N, N, N),
2806};
2807
2808static struct atlas7_grp_mux sd3_grp_mux = {
2809 .pad_mux_count = ARRAY_SIZE(sd3_grp_pad_mux),
2810 .pad_mux_list = sd3_grp_pad_mux,
2811};
2812
2813static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
2814 MUX(1, 91, 1, N, N, N, N),
2815 MUX(1, 92, 1, N, N, N, N),
2816 MUX(1, 93, 1, N, N, N, N),
2817 MUX(1, 94, 1, N, N, N, N),
2818 MUX(1, 95, 1, N, N, N, N),
2819 MUX(1, 96, 1, N, N, N, N),
2820};
2821
2822static struct atlas7_grp_mux sd5_grp_mux = {
2823 .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
2824 .pad_mux_list = sd5_grp_pad_mux,
2825};
2826
2827static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
2828 MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
2829 MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
2830 MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
2831 MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
2832 MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
2833 MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
2834};
2835
2836static struct atlas7_grp_mux sd6_grp0_mux = {
2837 .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
2838 .pad_mux_list = sd6_grp0_pad_mux,
2839};
2840
2841static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
2842 MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
2843 MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
2844 MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
2845 MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
2846 MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
2847 MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
2848};
2849
2850static struct atlas7_grp_mux sd6_grp1_mux = {
2851 .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
2852 .pad_mux_list = sd6_grp1_pad_mux,
2853};
2854
2855static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
2856 MUX(0, 4, 2, N, N, N, N),
2857};
2858
2859static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
2860 .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
2861 .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
2862};
2863
2864static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
2865 MUX(0, 12, 1, N, N, N, N),
2866 MUX(0, 13, 1, N, N, N, N),
2867 MUX(0, 14, 1, N, N, N, N),
2868 MUX(0, 15, 1, N, N, N, N),
2869 MUX(0, 16, 1, N, N, N, N),
2870 MUX(0, 17, 1, N, N, N, N),
2871};
2872
2873static struct atlas7_grp_mux sp0_qspi_grp_mux = {
2874 .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
2875 .pad_mux_list = sp0_qspi_grp_pad_mux,
2876};
2877
2878static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
2879 MUX(1, 19, 1, N, N, N, N),
2880 MUX(1, 20, 1, N, N, N, N),
2881 MUX(1, 21, 1, N, N, N, N),
2882 MUX(1, 18, 1, N, N, N, N),
2883};
2884
2885static struct atlas7_grp_mux sp1_spi_grp_mux = {
2886 .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
2887 .pad_mux_list = sp1_spi_grp_pad_mux,
2888};
2889
2890static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
2891 MUX(1, 53, 5, N, N, N, N),
2892 MUX(1, 56, 5, N, N, N, N),
2893 MUX(1, 57, 5, N, N, N, N),
2894 MUX(1, 58, 5, N, N, N, N),
2895 MUX(1, 59, 5, N, N, N, N),
2896 MUX(1, 60, 5, N, N, N, N),
2897 MUX(1, 61, 5, N, N, N, N),
2898 MUX(1, 62, 5, N, N, N, N),
2899 MUX(1, 63, 5, N, N, N, N),
2900 MUX(1, 64, 5, N, N, N, N),
2901 MUX(1, 65, 5, N, N, N, N),
2902 MUX(1, 66, 5, N, N, N, N),
2903 MUX(1, 67, 5, N, N, N, N),
2904 MUX(1, 68, 5, N, N, N, N),
2905 MUX(1, 69, 5, N, N, N, N),
2906 MUX(1, 70, 5, N, N, N, N),
2907 MUX(1, 71, 5, N, N, N, N),
2908 MUX(1, 72, 5, N, N, N, N),
2909};
2910
2911static struct atlas7_grp_mux tpiu_trace_grp_mux = {
2912 .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
2913 .pad_mux_list = tpiu_trace_grp_pad_mux,
2914};
2915
2916static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
2917 MUX(1, 121, 4, N, N, N, N),
2918 MUX(1, 120, 4, N, N, N, N),
2919 MUX(1, 134, 1, N, N, N, N),
2920 MUX(1, 133, 1, N, N, N, N),
2921};
2922
2923static struct atlas7_grp_mux uart0_grp_mux = {
2924 .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
2925 .pad_mux_list = uart0_grp_pad_mux,
2926};
2927
2928static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
2929 MUX(1, 134, 1, N, N, N, N),
2930 MUX(1, 133, 1, N, N, N, N),
2931};
2932
2933static struct atlas7_grp_mux uart0_nopause_grp_mux = {
2934 .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
2935 .pad_mux_list = uart0_nopause_grp_pad_mux,
2936};
2937
2938static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
2939 MUX(1, 136, 1, N, N, N, N),
2940 MUX(1, 135, 1, N, N, N, N),
2941};
2942
2943static struct atlas7_grp_mux uart1_grp_mux = {
2944 .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
2945 .pad_mux_list = uart1_grp_pad_mux,
2946};
2947
2948static struct atlas7_pad_mux uart2_grp_pad_mux[] = {
2949 MUX(0, 11, 2, N, N, N, N),
2950 MUX(0, 10, 2, N, N, N, N),
2951};
2952
2953static struct atlas7_grp_mux uart2_grp_mux = {
2954 .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux),
2955 .pad_mux_list = uart2_grp_pad_mux,
2956};
2957
2958static struct atlas7_pad_mux uart3_grp0_pad_mux[] = {
2959 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
2960 MUX(1, 126, 2, N, N, N, N),
2961 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
2962 MUX(1, 137, 1, N, N, N, N),
2963};
2964
2965static struct atlas7_grp_mux uart3_grp0_mux = {
2966 .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux),
2967 .pad_mux_list = uart3_grp0_pad_mux,
2968};
2969
2970static struct atlas7_pad_mux uart3_grp1_pad_mux[] = {
2971 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
2972 MUX(1, 109, 4, N, N, N, N),
2973 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
2974 MUX(1, 83, 2, N, N, N, N),
2975};
2976
2977static struct atlas7_grp_mux uart3_grp1_mux = {
2978 .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux),
2979 .pad_mux_list = uart3_grp1_pad_mux,
2980};
2981
2982static struct atlas7_pad_mux uart3_grp2_pad_mux[] = {
2983 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
2984 MUX(1, 139, 2, N, N, N, N),
2985 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
2986 MUX(1, 137, 1, N, N, N, N),
2987};
2988
2989static struct atlas7_grp_mux uart3_grp2_mux = {
2990 .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux),
2991 .pad_mux_list = uart3_grp2_pad_mux,
2992};
2993
2994static struct atlas7_pad_mux uart3_grp3_pad_mux[] = {
2995 MUX(1, 139, 2, N, N, N, N),
2996 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
2997 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
2998 MUX(1, 83, 2, N, N, N, N),
2999};
3000
3001static struct atlas7_grp_mux uart3_grp3_mux = {
3002 .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux),
3003 .pad_mux_list = uart3_grp3_pad_mux,
3004};
3005
3006static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = {
3007 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
3008 MUX(1, 137, 1, N, N, N, N),
3009};
3010
3011static struct atlas7_grp_mux uart3_nopause_grp0_mux = {
3012 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux),
3013 .pad_mux_list = uart3_nopause_grp0_pad_mux,
3014};
3015
3016static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = {
3017 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3018 MUX(1, 83, 2, N, N, N, N),
3019};
3020
3021static struct atlas7_grp_mux uart3_nopause_grp1_mux = {
3022 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux),
3023 .pad_mux_list = uart3_nopause_grp1_pad_mux,
3024};
3025
3026static struct atlas7_pad_mux uart4_grp0_pad_mux[] = {
3027 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
3028 MUX(1, 123, 4, N, N, N, N),
3029 MUX(1, 140, 1, N, N, N, N),
3030 MUX(1, 139, 1, N, N, N, N),
3031};
3032
3033static struct atlas7_grp_mux uart4_grp0_mux = {
3034 .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux),
3035 .pad_mux_list = uart4_grp0_pad_mux,
3036};
3037
3038static struct atlas7_pad_mux uart4_grp1_pad_mux[] = {
3039 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
3040 MUX(1, 99, 4, N, N, N, N),
3041 MUX(1, 140, 1, N, N, N, N),
3042 MUX(1, 139, 1, N, N, N, N),
3043};
3044
3045static struct atlas7_grp_mux uart4_grp1_mux = {
3046 .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux),
3047 .pad_mux_list = uart4_grp1_pad_mux,
3048};
3049
3050static struct atlas7_pad_mux uart4_grp2_pad_mux[] = {
3051 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
3052 MUX(1, 116, 2, N, N, N, N),
3053 MUX(1, 140, 1, N, N, N, N),
3054 MUX(1, 139, 1, N, N, N, N),
3055};
3056
3057static struct atlas7_grp_mux uart4_grp2_mux = {
3058 .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux),
3059 .pad_mux_list = uart4_grp2_pad_mux,
3060};
3061
3062static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = {
3063 MUX(1, 140, 1, N, N, N, N),
3064 MUX(1, 139, 1, N, N, N, N),
3065};
3066
3067static struct atlas7_grp_mux uart4_nopause_grp_mux = {
3068 .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux),
3069 .pad_mux_list = uart4_nopause_grp_pad_mux,
3070};
3071
3072static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = {
3073 MUX(1, 51, 2, N, N, N, N),
3074};
3075
3076static struct atlas7_grp_mux usb0_drvvbus_grp_mux = {
3077 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux),
3078 .pad_mux_list = usb0_drvvbus_grp_pad_mux,
3079};
3080
3081static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = {
3082 MUX(1, 134, 2, N, N, N, N),
3083};
3084
3085static struct atlas7_grp_mux usb1_drvvbus_grp_mux = {
3086 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux),
3087 .pad_mux_list = usb1_drvvbus_grp_pad_mux,
3088};
3089
3090static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
3091 MUX(1, 57, 6, N, N, N, N),
3092 MUX(1, 58, 6, N, N, N, N),
3093 MUX(1, 59, 6, N, N, N, N),
3094 MUX(1, 60, 6, N, N, N, N),
3095 MUX(1, 61, 6, N, N, N, N),
3096 MUX(1, 62, 6, N, N, N, N),
3097 MUX(1, 63, 6, N, N, N, N),
3098 MUX(1, 64, 6, N, N, N, N),
3099 MUX(1, 65, 6, N, N, N, N),
3100 MUX(1, 66, 6, N, N, N, N),
3101 MUX(1, 67, 6, N, N, N, N),
3102 MUX(1, 68, 6, N, N, N, N),
3103 MUX(1, 69, 6, N, N, N, N),
3104 MUX(1, 70, 6, N, N, N, N),
3105 MUX(1, 71, 6, N, N, N, N),
3106 MUX(1, 72, 6, N, N, N, N),
3107 MUX(1, 53, 6, N, N, N, N),
3108 MUX(1, 54, 6, N, N, N, N),
3109 MUX(1, 55, 6, N, N, N, N),
3110 MUX(1, 56, 6, N, N, N, N),
3111 MUX(1, 85, 6, N, N, N, N),
3112 MUX(1, 86, 6, N, N, N, N),
3113 MUX(1, 87, 6, N, N, N, N),
3114 MUX(1, 88, 6, N, N, N, N),
3115 MUX(1, 89, 6, N, N, N, N),
3116 MUX(1, 90, 6, N, N, N, N),
3117 MUX(1, 91, 6, N, N, N, N),
3118 MUX(1, 92, 6, N, N, N, N),
3119 MUX(1, 93, 6, N, N, N, N),
3120 MUX(1, 94, 6, N, N, N, N),
3121 MUX(1, 95, 6, N, N, N, N),
3122 MUX(1, 96, 6, N, N, N, N),
3123};
3124
3125static struct atlas7_grp_mux visbus_dout_grp_mux = {
3126 .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
3127 .pad_mux_list = visbus_dout_grp_pad_mux,
3128};
3129
3130static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
3131 MUX(1, 74, 1, N, N, N, N),
3132 MUX(1, 75, 1, N, N, N, N),
3133 MUX(1, 76, 1, N, N, N, N),
3134 MUX(1, 77, 1, N, N, N, N),
3135 MUX(1, 78, 1, N, N, N, N),
3136 MUX(1, 79, 1, N, N, N, N),
3137 MUX(1, 80, 1, N, N, N, N),
3138 MUX(1, 81, 1, N, N, N, N),
3139 MUX(1, 82, 1, N, N, N, N),
3140 MUX(1, 83, 1, N, N, N, N),
3141 MUX(1, 84, 1, N, N, N, N),
3142 MUX(1, 103, 2, N, N, N, N),
3143 MUX(1, 104, 2, N, N, N, N),
3144 MUX(1, 105, 2, N, N, N, N),
3145 MUX(1, 106, 2, N, N, N, N),
3146 MUX(1, 107, 2, N, N, N, N),
3147 MUX(1, 102, 2, N, N, N, N),
3148 MUX(1, 97, 2, N, N, N, N),
3149 MUX(1, 98, 2, N, N, N, N),
3150};
3151
3152static struct atlas7_grp_mux vi_vip1_grp_mux = {
3153 .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
3154 .pad_mux_list = vi_vip1_grp_pad_mux,
3155};
3156
3157static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
3158 MUX(1, 74, 1, N, N, N, N),
3159 MUX(1, 75, 1, N, N, N, N),
3160 MUX(1, 76, 1, N, N, N, N),
3161 MUX(1, 77, 1, N, N, N, N),
3162 MUX(1, 78, 1, N, N, N, N),
3163 MUX(1, 79, 1, N, N, N, N),
3164 MUX(1, 80, 1, N, N, N, N),
3165 MUX(1, 81, 1, N, N, N, N),
3166 MUX(1, 82, 1, N, N, N, N),
3167 MUX(1, 83, 1, N, N, N, N),
3168 MUX(1, 84, 1, N, N, N, N),
3169 MUX(1, 108, 2, N, N, N, N),
3170 MUX(1, 103, 2, N, N, N, N),
3171 MUX(1, 104, 2, N, N, N, N),
3172 MUX(1, 105, 2, N, N, N, N),
3173 MUX(1, 106, 2, N, N, N, N),
3174 MUX(1, 107, 2, N, N, N, N),
3175 MUX(1, 102, 2, N, N, N, N),
3176 MUX(1, 97, 2, N, N, N, N),
3177 MUX(1, 98, 2, N, N, N, N),
3178 MUX(1, 99, 2, N, N, N, N),
3179 MUX(1, 100, 2, N, N, N, N),
3180};
3181
3182static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
3183 .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
3184 .pad_mux_list = vi_vip1_ext_grp_pad_mux,
3185};
3186
3187static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
3188 MUX(1, 74, 1, N, N, N, N),
3189 MUX(1, 75, 1, N, N, N, N),
3190 MUX(1, 76, 1, N, N, N, N),
3191 MUX(1, 77, 1, N, N, N, N),
3192 MUX(1, 78, 1, N, N, N, N),
3193 MUX(1, 79, 1, N, N, N, N),
3194 MUX(1, 80, 1, N, N, N, N),
3195 MUX(1, 81, 1, N, N, N, N),
3196};
3197
3198static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
3199 .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
3200 .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
3201};
3202
3203static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
3204 MUX(1, 82, 1, N, N, N, N),
3205 MUX(1, 83, 1, N, N, N, N),
3206 MUX(1, 84, 1, N, N, N, N),
3207 MUX(1, 108, 2, N, N, N, N),
3208 MUX(1, 103, 2, N, N, N, N),
3209 MUX(1, 104, 2, N, N, N, N),
3210 MUX(1, 105, 2, N, N, N, N),
3211 MUX(1, 106, 2, N, N, N, N),
3212};
3213
3214static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
3215 .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
3216 .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
3217};
3218
3219static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3220 FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
3221 FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
3222 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
3223 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
3224 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
3225 FUNCTION("uart_nand_gpio",
3226 uart_nand_gpio_grp,
3227 &uart_nand_gpio_grp_mux),
3228 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
3229 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
3230 FUNCTION("audio_func_dbg",
3231 audio_func_dbg_grp,
3232 &audio_func_dbg_grp_mux),
3233 FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
3234 FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
3235 FUNCTION("audio_i2s_extclk",
3236 audio_i2s_extclk_grp,
3237 &audio_i2s_extclk_grp_mux),
3238 FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux),
3239 FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux),
3240 FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux),
3241 FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux),
3242 FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux),
3243 FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux),
3244 FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux),
3245 FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux),
3246 FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux),
3247 FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux),
3248 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
3249 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
3250 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
3251 FUNCTION("ca_curator_lpc",
3252 ca_curator_lpc_grp,
3253 &ca_curator_lpc_grp_mux),
3254 FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
3255 FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
3256 FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
3257 FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
3258 FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
3259 FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
3260 FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
3261 FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
3262 FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
3263 FUNCTION("gn_gnss_uart_nopause",
3264 gn_gnss_uart_nopause_grp,
3265 &gn_gnss_uart_nopause_grp_mux),
3266 FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
3267 FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
3268 FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
3269 FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
3270 FUNCTION("cvbs_dbg_test_m0",
3271 cvbs_dbg_test_grp0,
3272 &cvbs_dbg_test_grp0_mux),
3273 FUNCTION("cvbs_dbg_test_m1",
3274 cvbs_dbg_test_grp1,
3275 &cvbs_dbg_test_grp1_mux),
3276 FUNCTION("cvbs_dbg_test_m2",
3277 cvbs_dbg_test_grp2,
3278 &cvbs_dbg_test_grp2_mux),
3279 FUNCTION("cvbs_dbg_test_m3",
3280 cvbs_dbg_test_grp3,
3281 &cvbs_dbg_test_grp3_mux),
3282 FUNCTION("cvbs_dbg_test_m4",
3283 cvbs_dbg_test_grp4,
3284 &cvbs_dbg_test_grp4_mux),
3285 FUNCTION("cvbs_dbg_test_m5",
3286 cvbs_dbg_test_grp5,
3287 &cvbs_dbg_test_grp5_mux),
3288 FUNCTION("cvbs_dbg_test_m6",
3289 cvbs_dbg_test_grp6,
3290 &cvbs_dbg_test_grp6_mux),
3291 FUNCTION("cvbs_dbg_test_m7",
3292 cvbs_dbg_test_grp7,
3293 &cvbs_dbg_test_grp7_mux),
3294 FUNCTION("cvbs_dbg_test_m8",
3295 cvbs_dbg_test_grp8,
3296 &cvbs_dbg_test_grp8_mux),
3297 FUNCTION("cvbs_dbg_test_m9",
3298 cvbs_dbg_test_grp9,
3299 &cvbs_dbg_test_grp9_mux),
3300 FUNCTION("cvbs_dbg_test_m10",
3301 cvbs_dbg_test_grp10,
3302 &cvbs_dbg_test_grp10_mux),
3303 FUNCTION("cvbs_dbg_test_m11",
3304 cvbs_dbg_test_grp11,
3305 &cvbs_dbg_test_grp11_mux),
3306 FUNCTION("cvbs_dbg_test_m12",
3307 cvbs_dbg_test_grp12,
3308 &cvbs_dbg_test_grp12_mux),
3309 FUNCTION("cvbs_dbg_test_m13",
3310 cvbs_dbg_test_grp13,
3311 &cvbs_dbg_test_grp13_mux),
3312 FUNCTION("cvbs_dbg_test_m14",
3313 cvbs_dbg_test_grp14,
3314 &cvbs_dbg_test_grp14_mux),
3315 FUNCTION("cvbs_dbg_test_m15",
3316 cvbs_dbg_test_grp15,
3317 &cvbs_dbg_test_grp15_mux),
3318 FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
3319 FUNCTION("gn_gnss_sw_status",
3320 gn_gnss_sw_status_grp,
3321 &gn_gnss_sw_status_grp_mux),
3322 FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
3323 FUNCTION("gn_gnss_irq1_m0",
3324 gn_gnss_irq1_grp0,
3325 &gn_gnss_irq1_grp0_mux),
3326 FUNCTION("gn_gnss_irq2_m0",
3327 gn_gnss_irq2_grp0,
3328 &gn_gnss_irq2_grp0_mux),
3329 FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
3330 FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
3331 FUNCTION("gn_io_gnsssys_sw_cfg",
3332 gn_io_gnsssys_sw_cfg_grp,
3333 &gn_io_gnsssys_sw_cfg_grp_mux),
3334 FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
3335 FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
3336 FUNCTION("gn_trg_shutdown_m0",
3337 gn_trg_shutdown_grp0,
3338 &gn_trg_shutdown_grp0_mux),
3339 FUNCTION("gn_trg_shutdown_m1",
3340 gn_trg_shutdown_grp1,
3341 &gn_trg_shutdown_grp1_mux),
3342 FUNCTION("gn_trg_shutdown_m2",
3343 gn_trg_shutdown_grp2,
3344 &gn_trg_shutdown_grp2_mux),
3345 FUNCTION("gn_trg_shutdown_m3",
3346 gn_trg_shutdown_grp3,
3347 &gn_trg_shutdown_grp3_mux),
3348 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
3349 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
3350 FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux),
3351 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
3352 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
3353 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
3354 FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
3355 FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
3356 FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
3357 FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
3358 FUNCTION("nd_df", nd_df_grp, &nd_df_grp_mux),
3359 FUNCTION("nd_df_nowp", nd_df_nowp_grp, &nd_df_nowp_grp_mux),
3360 FUNCTION("ps", ps_grp, &ps_grp_mux),
3361 FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
3362 FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
3363 FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
3364 FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
3365 FUNCTION("pwc_lowbatt_b_m0",
3366 pwc_lowbatt_b_grp0,
3367 &pwc_lowbatt_b_grp0_mux),
3368 FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
3369 FUNCTION("pwc_on_key_b_m0",
3370 pwc_on_key_b_grp0,
3371 &pwc_on_key_b_grp0_mux),
3372 FUNCTION("pwc_wakeup_src0",
3373 pwc_wakeup_src0_grp,
3374 &pwc_wakeup_src0_grp_mux),
3375 FUNCTION("pwc_wakeup_src1",
3376 pwc_wakeup_src1_grp,
3377 &pwc_wakeup_src1_grp_mux),
3378 FUNCTION("pwc_wakeup_src2",
3379 pwc_wakeup_src2_grp,
3380 &pwc_wakeup_src2_grp_mux),
3381 FUNCTION("pwc_wakeup_src3",
3382 pwc_wakeup_src3_grp,
3383 &pwc_wakeup_src3_grp_mux),
3384 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
3385 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
3386 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
3387 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
3388 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
3389 FUNCTION("pw_i2s01_clk_m0",
3390 pw_i2s01_clk_grp0,
3391 &pw_i2s01_clk_grp0_mux),
3392 FUNCTION("pw_i2s01_clk_m1",
3393 pw_i2s01_clk_grp1,
3394 &pw_i2s01_clk_grp1_mux),
3395 FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux),
3396 FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux),
3397 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
3398 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
3399 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
3400 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
3401 FUNCTION("pw_pwm_cpu_vol_m0",
3402 pw_pwm_cpu_vol_grp0,
3403 &pw_pwm_cpu_vol_grp0_mux),
3404 FUNCTION("pw_pwm_cpu_vol_m1",
3405 pw_pwm_cpu_vol_grp1,
3406 &pw_pwm_cpu_vol_grp1_mux),
3407 FUNCTION("pw_backlight_m0",
3408 pw_backlight_grp0,
3409 &pw_backlight_grp0_mux),
3410 FUNCTION("pw_backlight_m1",
3411 pw_backlight_grp1,
3412 &pw_backlight_grp1_mux),
3413 FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
3414 FUNCTION("rg_gmac_phy_intr_n",
3415 rg_gmac_phy_intr_n_grp,
3416 &rg_gmac_phy_intr_n_grp_mux),
3417 FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
3418 FUNCTION("rg_rgmii_phy_ref_clk_m0",
3419 rg_rgmii_phy_ref_clk_grp0,
3420 &rg_rgmii_phy_ref_clk_grp0_mux),
3421 FUNCTION("rg_rgmii_phy_ref_clk_m1",
3422 rg_rgmii_phy_ref_clk_grp1,
3423 &rg_rgmii_phy_ref_clk_grp1_mux),
3424 FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
3425 FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
3426 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
3427 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
3428 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
3429 FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux),
3430 FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux),
3431 FUNCTION("sd3", sd3_grp, &sd3_grp_mux),
3432 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
3433 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
3434 FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
3435 FUNCTION("sp0_ext_ldo_on",
3436 sp0_ext_ldo_on_grp,
3437 &sp0_ext_ldo_on_grp_mux),
3438 FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
3439 FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
3440 FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
3441 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
3442 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
3443 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
3444 FUNCTION("uart2", uart2_grp, &uart2_grp_mux),
3445 FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux),
3446 FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux),
3447 FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux),
3448 FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux),
3449 FUNCTION("uart3_nopause_m0",
3450 uart3_nopause_grp0,
3451 &uart3_nopause_grp0_mux),
3452 FUNCTION("uart3_nopause_m1",
3453 uart3_nopause_grp1,
3454 &uart3_nopause_grp1_mux),
3455 FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux),
3456 FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux),
3457 FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux),
3458 FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux),
3459 FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux),
3460 FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux),
3461 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
3462 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
3463 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
3464 FUNCTION("vi_vip1_low8bit",
3465 vi_vip1_low8bit_grp,
3466 &vi_vip1_low8bit_grp_mux),
3467 FUNCTION("vi_vip1_high8bit",
3468 vi_vip1_high8bit_grp,
3469 &vi_vip1_high8bit_grp_mux),
3470};
3471
3472struct atlas7_pinctrl_data atlas7_ioc_data = {
3473 .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
3474 .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
3475 .grps = (struct atlas7_pin_group *)altas7_pin_groups,
3476 .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
3477 .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
3478 .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
3479 .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
3480 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
3481};
3482
3483static inline u32 atlas7_pin_to_bank(u32 pin)
3484{
3485 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
3486}
3487
3488static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3489{
3490 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3491
3492 return pmx->pctl_data->funcs_cnt;
3493}
3494
3495static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
3496 u32 selector)
3497{
3498 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3499
3500 return pmx->pctl_data->funcs[selector].name;
3501}
3502
3503static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
3504 u32 selector, const char * const **groups,
3505 u32 * const num_groups)
3506{
3507 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3508
3509 *groups = pmx->pctl_data->funcs[selector].groups;
3510 *num_groups = pmx->pctl_data->funcs[selector].num_groups;
3511
3512 return 0;
3513}
3514
3515static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
3516 const struct atlas7_pad_mux *mux)
3517{
3518 /* Set Input Disable to avoid input glitches
3519 *
3520 * All Input-Disable Control registers are located on IOCRTC.
3521 * So the regs bank is always 0.
3522 *
3523 */
3524 if (mux->dinput_reg && mux->dinput_val_reg) {
3525 writel(DI_MASK << mux->dinput_bit,
3526 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
3527 writel(DI_DISABLE << mux->dinput_bit,
3528 pmx->regs[BANK_DS] + mux->dinput_reg);
3529
3530
3531 writel(DIV_MASK << mux->dinput_val_bit,
3532 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
3533 writel(DIV_DISABLE << mux->dinput_val_bit,
3534 pmx->regs[BANK_DS] + mux->dinput_val_reg);
3535 }
3536}
3537
3538static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
3539 const struct atlas7_pad_mux *mux)
3540{
3541 /* Clear Input Disable to avoid input glitches */
3542 if (mux->dinput_reg && mux->dinput_val_reg) {
3543 writel(DI_MASK << mux->dinput_bit,
3544 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
3545 writel(DI_ENABLE << mux->dinput_bit,
3546 pmx->regs[BANK_DS] + mux->dinput_reg);
3547
3548 writel(DIV_MASK << mux->dinput_val_bit,
3549 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
3550 writel(DIV_ENABLE << mux->dinput_val_bit,
3551 pmx->regs[BANK_DS] + mux->dinput_val_reg);
3552 }
3553}
3554
3555static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
3556 struct atlas7_pad_config *conf,
3557 u32 bank, u32 ad_sel)
3558{
3559 unsigned long regv;
3560
3561 /* Write to clear register to clear A/D selector */
3562 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
3563 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
3564
3565 /* Set target pad A/D selector */
3566 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
3567 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
3568 writel(regv | (ad_sel << conf->ad_ctrl_bit),
3569 pmx->regs[bank] + conf->ad_ctrl_reg);
3570
3571 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
3572 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
3573 bank, conf->ad_ctrl_reg, regv);
3574 return 0;
3575}
3576
3577static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
3578 struct atlas7_pad_config *conf, u32 bank)
3579{
3580 /* Only PAD_T_AD pins can change between Analogue&Digital */
3581 if (conf->type != PAD_T_AD)
3582 return -EINVAL;
3583
3584 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
3585}
3586
3587static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
3588 struct atlas7_pad_config *conf, u32 bank)
3589{
3590 /* Other type pads are always digital */
3591 if (conf->type != PAD_T_AD)
3592 return 0;
3593
3594 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
3595}
3596
3597static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
3598 u32 pin, u32 func)
3599{
3600 struct atlas7_pad_config *conf;
3601 u32 bank;
3602 int ret;
3603 unsigned long regv;
3604
3605 pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
3606 pin, func);
3607
3608 /* Get this Pad's descriptor from PINCTRL */
3609 conf = &pmx->pctl_data->confs[pin];
3610 bank = atlas7_pin_to_bank(pin);
3611
3612 /* Just enable the analog function of this pad */
3613 if (FUNC_ANALOGUE == func) {
3614 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
3615 if (ret)
3616 dev_err(pmx->dev,
3617 "Convert pad#%d to analog failed, ret=%d\n",
3618 pin, ret);
3619 return ret;
3620 }
3621
3622 /* Set Pads from analog to digital */
3623 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
3624 if (ret) {
3625 dev_err(pmx->dev,
3626 "Convert pad#%d to digital failed, ret=%d\n",
3627 pin, ret);
3628 return ret;
3629 }
3630
3631 /* Write to clear register to clear current function */
3632 writel(FUNC_CLEAR_MASK << conf->mux_bit,
3633 pmx->regs[bank] + CLR_REG(conf->mux_reg));
3634
3635 /* Set target pad mux function */
3636 regv = readl(pmx->regs[bank] + conf->mux_reg);
3637 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
3638 writel(regv | (func << conf->mux_bit),
3639 pmx->regs[bank] + conf->mux_reg);
3640
3641 regv = readl(pmx->regs[bank] + conf->mux_reg);
3642 pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
3643 bank, conf->mux_reg, regv);
3644
3645 return 0;
3646}
3647
3648static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
3649 u32 func_selector, u32 group_selector)
3650{
3651 int idx, ret;
3652 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3653 struct atlas7_pmx_func *pmx_func;
3654 struct atlas7_pin_group *pin_grp;
3655 const struct atlas7_grp_mux *grp_mux;
3656 const struct atlas7_pad_mux *mux;
3657
3658 pmx_func = &pmx->pctl_data->funcs[func_selector];
3659 pin_grp = &pmx->pctl_data->grps[group_selector];
3660
3661 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
3662 pmx_func->name, pin_grp->name);
3663
3664 grp_mux = pmx_func->grpmux;
3665
3666 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
3667 mux = &grp_mux->pad_mux_list[idx];
3668 __atlas7_pmx_pin_input_disable_set(pmx, mux);
3669 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
3670 if (ret) {
3671 dev_err(pmx->dev,
3672 "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
3673 pmx_func->name, pin_grp->name,
3674 mux->pin, mux->func, ret);
3675 BUG_ON(1);
3676 }
3677 __atlas7_pmx_pin_input_disable_clr(pmx, mux);
3678 }
3679 pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
3680 pmx_func->name, pin_grp->name);
3681
3682 return 0;
3683}
3684
3685struct atlas7_ds_info {
3686 u32 ma;
3687 u32 ds_16st;
3688 u32 ds_4we;
3689 u32 ds_0204m31;
3690 u32 ds_0610m31;
3691};
3692
3693const struct atlas7_ds_info atlas7_ds_map[] = {
3694 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL},
3695 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL},
3696 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0},
3697 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL},
3698 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1},
3699 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL},
3700 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL},
3701 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL},
3702 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL},
3703 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL},
3704 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL},
3705 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL},
3706 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL},
3707 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL},
3708 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL},
3709 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL},
3710};
3711
3712static u32 convert_current_to_drive_strength(u32 type, u32 ma)
3713{
3714 int idx;
3715
3716 for (idx = 0; idx < ARRAY_SIZE(atlas7_ds_map); idx++) {
3717 if (atlas7_ds_map[idx].ma != ma)
3718 continue;
3719
3720 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
3721 return atlas7_ds_map[idx].ds_4we;
3722 else if (type == PAD_T_16ST)
3723 return atlas7_ds_map[idx].ds_16st;
3724 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
3725 return atlas7_ds_map[idx].ds_0204m31;
3726 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
3727 return atlas7_ds_map[idx].ds_0610m31;
3728 }
3729
3730 return DS_NULL;
3731}
3732
3733static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
3734 u32 pin, u32 sel)
3735{
3736 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3737 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3738 u32 type = conf->type;
3739 u32 shift = conf->pupd_bit;
3740 u32 bank = atlas7_pin_to_bank(pin);
3741 void __iomem *pull_sel_reg, *pull_clr_reg;
3742
3743 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
3744 pull_clr_reg = CLR_REG(pull_sel_reg);
3745
3746 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) {
3747 writel(P4WE_PULL_MASK << shift, pull_clr_reg);
3748
3749 if (sel == PULL_UP)
3750 writel(P4WE_PULL_UP << shift, pull_sel_reg);
3751 else if (sel == HIGH_HYSTERESIS)
3752 writel(P4WE_HIGH_HYSTERESIS << shift, pull_sel_reg);
3753 else if (sel == HIGH_Z)
3754 writel(P4WE_HIGH_Z << shift, pull_sel_reg);
3755 else if (sel == PULL_DOWN)
3756 writel(P4WE_PULL_DOWN << shift, pull_sel_reg);
3757 else {
3758 pr_err("Unknown Pull select type for 4WEPAD#%d\n",
3759 pin);
3760 return -ENOTSUPP;
3761 }
3762 } else if (type == PAD_T_16ST) {
3763 writel(P16ST_PULL_MASK << shift, pull_clr_reg);
3764
3765 if (sel == PULL_UP)
3766 writel(P16ST_PULL_UP << shift, pull_sel_reg);
3767 else if (sel == HIGH_Z)
3768 writel(P16ST_HIGH_Z << shift, pull_sel_reg);
3769 else if (sel == PULL_DOWN)
3770 writel(P16ST_PULL_DOWN << shift, pull_sel_reg);
3771 else {
3772 pr_err("Unknown Pull select type for 16STPAD#%d\n",
3773 pin);
3774 return -ENOTSUPP;
3775 }
3776 } else if (type == PAD_T_M31_0204_PD ||
3777 type == PAD_T_M31_0204_PU ||
3778 type == PAD_T_M31_0610_PD ||
3779 type == PAD_T_M31_0610_PU) {
3780 writel(PM31_PULL_MASK << shift, pull_clr_reg);
3781
3782 if (sel == PULL_UP)
3783 writel(PM31_PULL_ENABLED << shift, pull_sel_reg);
3784 else if (sel == PULL_DOWN)
3785 writel(PM31_PULL_DISABLED << shift, pull_sel_reg);
3786 else {
3787 pr_err("Unknown Pull select type for M31PAD#%d\n",
3788 pin);
3789 return -ENOTSUPP;
3790 }
3791 } else if (type == PAD_T_AD) {
3792 writel(PANGD_PULL_MASK << shift, pull_clr_reg);
3793
3794 if (sel == PULL_UP)
3795 writel(PANGD_PULL_UP << shift, pull_sel_reg);
3796 else if (sel == HIGH_Z)
3797 writel(PANGD_HIGH_Z << shift, pull_sel_reg);
3798 else if (sel == PULL_DOWN)
3799 writel(PANGD_PULL_DOWN << shift, pull_sel_reg);
3800 else {
3801 pr_err("Unknown Pull select type for A/D PAD#%d\n",
3802 pin);
3803 return -ENOTSUPP;
3804 }
3805 } else {
3806 pr_err("Unknown Pad type[%d] for pull select PAD#%d\n",
3807 type, pin);
3808 return -ENOTSUPP;
3809 }
3810
3811 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
3812 pin, sel);
3813 return 0;
3814}
3815
3816static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
3817 u32 pin, u32 sel)
3818{
3819 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3820 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3821 u32 type = conf->type;
3822 u32 shift = conf->drvstr_bit;
3823 u32 bank = atlas7_pin_to_bank(pin);
3824 void __iomem *ds_sel_reg, *ds_clr_reg;
3825
3826 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
3827 ds_clr_reg = CLR_REG(ds_sel_reg);
3828 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) {
3829 if (sel & (~DS_2BIT_MASK))
3830 goto unsupport;
3831
3832 writel(DS_2BIT_IM_VAL << shift, ds_clr_reg);
3833 writel(sel << shift, ds_sel_reg);
3834
3835 return 0;
3836 } else if (type == PAD_T_16ST) {
3837 if (sel & (~DS_4BIT_MASK))
3838 goto unsupport;
3839
3840 writel(DS_4BIT_IM_VAL << shift, ds_clr_reg);
3841 writel(sel << shift, ds_sel_reg);
3842
3843 return 0;
3844 } else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU ||
3845 type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) {
3846 if (sel & (~DS_1BIT_MASK))
3847 goto unsupport;
3848
3849 writel(DS_1BIT_IM_VAL << shift, ds_clr_reg);
3850 writel(sel << shift, ds_sel_reg);
3851
3852 return 0;
3853 }
3854
3855unsupport:
3856 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
3857 pin, type, sel);
3858 return -ENOTSUPP;
3859}
3860
3861static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
3862 u32 pin, u32 ma)
3863{
3864 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3865 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3866 u32 type = conf->type;
3867 u32 sel;
3868 int ret;
3869
3870 sel = convert_current_to_drive_strength(conf->type, ma);
3871 if (DS_NULL == sel) {
3872 pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
3873 pin, type, ma);
3874 return -ENOTSUPP;
3875 }
3876
3877 ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
3878 pin, sel);
3879 pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
3880 pin, sel, ma, ret?"FAILED":"OK");
3881 return ret;
3882}
3883
3884static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
3885 struct pinctrl_gpio_range *range, u32 pin)
3886{
3887 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3888 u32 idx;
3889
3890 dev_dbg(pmx->dev,
3891 "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
3892 for (idx = 0; idx < range->npins; idx++) {
3893 if (pin == range->pins[idx])
3894 break;
3895 }
3896
3897 if (idx >= range->npins) {
3898 dev_err(pmx->dev,
3899 "The pin#%d could not be requested as GPIO!!\n",
3900 pin);
3901 return -EPERM;
3902 }
3903
3904 __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
3905
3906 return 0;
3907}
3908
3909static struct pinmux_ops atlas7_pinmux_ops = {
3910 .get_functions_count = atlas7_pmx_get_funcs_count,
3911 .get_function_name = atlas7_pmx_get_func_name,
3912 .get_function_groups = atlas7_pmx_get_func_groups,
3913 .set_mux = atlas7_pmx_set_mux,
3914 .gpio_request_enable = atlas7_pmx_gpio_request_enable,
3915};
3916
3917static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
3918{
3919 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3920
3921 return pmx->pctl_data->grps_cnt;
3922}
3923
3924static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
3925 u32 group)
3926{
3927 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3928
3929 return pmx->pctl_data->grps[group].name;
3930}
3931
3932static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
3933 u32 group, const u32 **pins, u32 *num_pins)
3934{
3935 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3936
3937 *num_pins = pmx->pctl_data->grps[group].num_pins;
3938 *pins = pmx->pctl_data->grps[group].pins;
3939
3940 return 0;
3941}
3942
3943static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
3944 struct device_node *np_config,
3945 struct pinctrl_map **map,
3946 u32 *num_maps)
3947{
3948 return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
3949 num_maps, PIN_MAP_TYPE_INVALID);
3950}
3951
3952static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
3953 struct pinctrl_map *map, u32 num_maps)
3954{
3955 kfree(map);
3956}
3957
3958static const struct pinctrl_ops atlas7_pinctrl_ops = {
3959 .get_groups_count = atlas7_pinctrl_get_groups_count,
3960 .get_group_name = atlas7_pinctrl_get_group_name,
3961 .get_group_pins = atlas7_pinctrl_get_group_pins,
3962 .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
3963 .dt_free_map = atlas7_pinctrl_dt_free_map,
3964};
3965
3966static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
3967 unsigned pin, unsigned long *configs,
3968 unsigned num_configs)
3969{
3970 u16 param, arg;
3971 int idx, err;
3972
3973 for (idx = 0; idx < num_configs; idx++) {
3974 param = pinconf_to_config_param(configs[idx]);
3975 arg = pinconf_to_config_argument(configs[idx]);
3976
3977 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
3978 pin, atlas7_ioc_pads[pin].name, param, arg);
3979 switch (param) {
3980 case PIN_CONFIG_BIAS_PULL_UP:
3981 err = altas7_pinctrl_set_pull_sel(pctldev,
3982 pin, PULL_UP);
3983 if (err)
3984 return err;
3985 break;
3986
3987 case PIN_CONFIG_BIAS_PULL_DOWN:
3988 err = altas7_pinctrl_set_pull_sel(pctldev,
3989 pin, PULL_DOWN);
3990 if (err)
3991 return err;
3992 break;
3993
3994 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3995 err = altas7_pinctrl_set_pull_sel(pctldev,
3996 pin, HIGH_HYSTERESIS);
3997 if (err)
3998 return err;
3999 break;
4000 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
4001 err = altas7_pinctrl_set_pull_sel(pctldev,
4002 pin, HIGH_Z);
4003 if (err)
4004 return err;
4005 break;
4006
4007 case PIN_CONFIG_DRIVE_STRENGTH:
4008 err = altas7_pinctrl_set_drive_strength_sel(pctldev,
4009 pin, arg);
4010 if (err)
4011 return err;
4012 break;
4013 default:
4014 return -ENOTSUPP;
4015 }
4016 pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
4017 pin, atlas7_ioc_pads[pin].name, param, arg);
4018 }
4019
4020 return 0;
4021}
4022
4023static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
4024 unsigned group, unsigned long *configs,
4025 unsigned num_configs)
4026{
4027 const unsigned *pins;
4028 unsigned npins;
4029 int i, ret;
4030
4031 ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
4032 if (ret)
4033 return ret;
4034 for (i = 0; i < npins; i++) {
4035 if (atlas7_pin_config_set(pctldev, pins[i],
4036 configs, num_configs))
4037 return -ENOTSUPP;
4038 }
4039 return 0;
4040}
4041
4042static const struct pinconf_ops atlas7_pinconf_ops = {
4043 .pin_config_set = atlas7_pin_config_set,
4044 .pin_config_group_set = atlas7_pin_config_group_set,
4045 .is_generic = true,
4046};
4047
4048static int atlas7_pinmux_probe(struct platform_device *pdev)
4049{
4050 int ret, idx;
4051 struct atlas7_pmx *pmx;
4052 struct device_node *np = pdev->dev.of_node;
4053 u32 banks = ATLAS7_PINCTRL_REG_BANKS;
4054
4055 /* Create state holders etc for this driver */
4056 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
4057 if (!pmx)
4058 return -ENOMEM;
4059
4060 pmx->dev = &pdev->dev;
4061
4062 pmx->pctl_data = &atlas7_ioc_data;
4063 pmx->pctl_desc.name = "pinctrl-atlas7";
4064 pmx->pctl_desc.pins = pmx->pctl_data->pads;
4065 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
4066 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
4067 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
4068 pmx->pctl_desc.confops = &atlas7_pinconf_ops;
f9367793
WC		 4069
4070 for (idx = 0; idx < banks; idx++) {
4071 pmx->regs[idx] = of_iomap(np, idx);
4072 if (!pmx->regs[idx]) {
4073 dev_err(&pdev->dev,
4074 "can't map ioc bank#%d registers\n", idx);
4075 ret = -ENOMEM;
4076 goto unmap_io;
4077 }
4078 }
4079
4080 /* Now register the pin controller and all pins it handles */
4081 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
4082 if (!pmx->pctl) {
4083 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
4084 ret = -EINVAL;
4085 goto unmap_io;
4086 }
4087
4088 platform_set_drvdata(pdev, pmx);
4089
4090 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
4091
4092 return 0;
4093
4094unmap_io:
4095 for (idx = 0; idx < banks; idx++) {
4096 if (!pmx->regs[idx])
4097 break;
4098 iounmap(pmx->regs[idx]);
4099 }
4100
4101 return ret;
4102}
4103
4104static const struct of_device_id atlas7_pinmux_ids[] = {
4105 { .compatible = "sirf,atlas7-ioc",},
4106};
4107
4108static struct platform_driver atlas7_pinmux_driver = {
4109 .driver = {
4110 .name = "atlas7-ioc",
f9367793
WC		 4111 .of_match_table = atlas7_pinmux_ids,
4112 },
4113 .probe = atlas7_pinmux_probe,
4114};
4115
4116static int __init atlas7_pinmux_init(void)
4117{
4118 return platform_driver_register(&atlas7_pinmux_driver);
4119}
4120arch_initcall(atlas7_pinmux_init);
4121
4122
4123/**
4124 * The Following is GPIO Code
4125 */
4126static inline struct
4127atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
4128{
4129 return &a7gc->banks[GPIO_TO_BANK(gpio)];
4130}
4131
4132static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
4133{
4134 struct atlas7_gpio_bank *bank;
4135 u32 ofs;
4136
4137 bank = atlas7_gpio_to_bank(a7gc, gpio);
4138 ofs = gpio - bank->gpio_offset;
4139 if (ofs >= bank->ngpio)
4140 return -ENODEV;
4141
4142 return bank->gpio_pins[ofs];
4143}
4144
4145static void atlas7_gpio_irq_ack(struct irq_data *d)
4146{
4147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4148 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4149 struct atlas7_gpio_bank *bank;
4150 void __iomem *ctrl_reg;
4151 u32 val, pin_in_bank;
4152 unsigned long flags;
4153
4154 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4155 pin_in_bank = d->hwirq - bank->gpio_offset;
4156 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4157
4158 spin_lock_irqsave(&a7gc->lock, flags);
4159
4160 val = readl(ctrl_reg);
4161 /* clear interrupt status */
4162 writel(val, ctrl_reg);
4163
4164 spin_unlock_irqrestore(&a7gc->lock, flags);
4165}
4166
4167static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
4168{
4169 struct atlas7_gpio_bank *bank;
4170 void __iomem *ctrl_reg;
4171 u32 val, pin_in_bank;
4172
4173 bank = atlas7_gpio_to_bank(a7gc, idx);
4174 pin_in_bank = idx - bank->gpio_offset;
4175 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4176
4177 val = readl(ctrl_reg);
4178 val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
4179 ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
4180 writel(val, ctrl_reg);
4181}
4182
4183static void atlas7_gpio_irq_mask(struct irq_data *d)
4184{
4185 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4186 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4187 unsigned long flags;
4188
4189 spin_lock_irqsave(&a7gc->lock, flags);
4190
4191 __atlas7_gpio_irq_mask(a7gc, d->hwirq);
4192
4193 spin_unlock_irqrestore(&a7gc->lock, flags);
4194}
4195
4196static void atlas7_gpio_irq_unmask(struct irq_data *d)
4197{
4198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4199 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4200 struct atlas7_gpio_bank *bank;
4201 void __iomem *ctrl_reg;
4202 u32 val, pin_in_bank;
4203 unsigned long flags;
4204
4205 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4206 pin_in_bank = d->hwirq - bank->gpio_offset;
4207 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4208
4209 spin_lock_irqsave(&a7gc->lock, flags);
4210
4211 val = readl(ctrl_reg);
4212 val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
4213 val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
4214 writel(val, ctrl_reg);
4215
4216 spin_unlock_irqrestore(&a7gc->lock, flags);
4217}
4218
4219static int atlas7_gpio_irq_type(struct irq_data *d,
4220 unsigned int type)
4221{
4222 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
4223 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4224 struct atlas7_gpio_bank *bank;
4225 void __iomem *ctrl_reg;
4226 u32 val, pin_in_bank;
4227 unsigned long flags;
4228
4229 bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
4230 pin_in_bank = d->hwirq - bank->gpio_offset;
4231 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4232
4233 spin_lock_irqsave(&a7gc->lock, flags);
4234
4235 val = readl(ctrl_reg);
4236 val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
4237 ATLAS7_GPIO_CTL_INTR_EN_MASK);
4238
4239 switch (type) {
4240 case IRQ_TYPE_NONE:
4241 break;
4242
4243 case IRQ_TYPE_EDGE_RISING:
4244 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4245 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4246 val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
4247 break;
4248
4249 case IRQ_TYPE_EDGE_FALLING:
4250 val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
4251 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4252 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4253 break;
4254
4255 case IRQ_TYPE_EDGE_BOTH:
4256 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4257 ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4258 ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
4259 break;
4260
4261 case IRQ_TYPE_LEVEL_LOW:
4262 val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
4263 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
4264 val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
4265 break;
4266
4267 case IRQ_TYPE_LEVEL_HIGH:
4268 val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
4269 val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
4270 ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
4271 break;
4272 }
4273
4274 writel(val, ctrl_reg);
4275
4276 spin_unlock_irqrestore(&a7gc->lock, flags);
4277
4278 return 0;
4279}
4280
4281static struct irq_chip atlas7_gpio_irq_chip = {
4282 .name = "atlas7-gpio-irq",
4283 .irq_ack = atlas7_gpio_irq_ack,
4284 .irq_mask = atlas7_gpio_irq_mask,
4285 .irq_unmask = atlas7_gpio_irq_unmask,
4286 .irq_set_type = atlas7_gpio_irq_type,
4287};
4288
4289static void atlas7_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
4290{
4291 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
4292 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4293 struct atlas7_gpio_bank *bank = NULL;
4294 u32 status, ctrl;
4295 int pin_in_bank = 0, idx;
4296 struct irq_chip *chip = irq_get_chip(irq);
4297
4298 for (idx = 0; idx < a7gc->nbank; idx++) {
4299 bank = &a7gc->banks[idx];
4300 if (bank->irq == irq)
4301 break;
4302 }
4303 BUG_ON(idx == a7gc->nbank);
4304
4305 chained_irq_enter(chip, desc);
4306
4307 status = readl(ATLAS7_GPIO_INT_STATUS(bank));
4308 if (!status) {
4309 pr_warn("%s: gpio [%s] status %#x no interrupt is flaged\n",
4310 __func__, gc->label, status);
4311 handle_bad_irq(irq, desc);
4312 return;
4313 }
4314
4315 while (status) {
4316 ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
4317
4318 /*
4319 * Here we must check whether the corresponding GPIO's
4320 * interrupt has been enabled, otherwise just skip it
4321 */
4322 if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
4323 pr_debug("%s: chip[%s] gpio:%d happens\n",
4324 __func__, gc->label,
4325 bank->gpio_offset + pin_in_bank);
4326 generic_handle_irq(
4327 irq_find_mapping(gc->irqdomain,
4328 bank->gpio_offset + pin_in_bank));
4329 }
4330
4331 if (++pin_in_bank >= bank->ngpio)
4332 break;
4333
4334 status = status >> 1;
4335 }
4336
4337 chained_irq_exit(chip, desc);
4338}
4339
4340static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
4341 unsigned int gpio)
4342{
4343 struct atlas7_gpio_bank *bank;
4344 void __iomem *ctrl_reg;
4345 u32 val, pin_in_bank;
4346
4347 bank = atlas7_gpio_to_bank(a7gc, gpio);
4348 pin_in_bank = gpio - bank->gpio_offset;
4349 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4350
4351 val = readl(ctrl_reg);
4352 val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
4353 writel(val, ctrl_reg);
4354}
4355
4356static int atlas7_gpio_request(struct gpio_chip *chip,
4357 unsigned int gpio)
4358{
4359 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4360 int ret;
4361 unsigned long flags;
4362
4363 ret = __atlas7_gpio_to_pin(a7gc, gpio);
4364 if (ret < 0)
4365 return ret;
4366
4367 if (pinctrl_request_gpio(chip->base + gpio))
4368 return -ENODEV;
4369
4370 spin_lock_irqsave(&a7gc->lock, flags);
4371
4372 /*
4373 * default status:
4374 * set direction as input and mask irq
4375 */
4376 __atlas7_gpio_set_input(a7gc, gpio);
4377 __atlas7_gpio_irq_mask(a7gc, gpio);
4378
4379 spin_unlock_irqrestore(&a7gc->lock, flags);
4380
4381 return 0;
4382}
4383
4384static void atlas7_gpio_free(struct gpio_chip *chip,
4385 unsigned int gpio)
4386{
4387 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4388 unsigned long flags;
4389
4390 spin_lock_irqsave(&a7gc->lock, flags);
4391
4392 __atlas7_gpio_irq_mask(a7gc, gpio);
4393 __atlas7_gpio_set_input(a7gc, gpio);
4394
4395 spin_unlock_irqrestore(&a7gc->lock, flags);
4396
4397 pinctrl_free_gpio(chip->base + gpio);
4398}
4399
4400static int atlas7_gpio_direction_input(struct gpio_chip *chip,
4401 unsigned int gpio)
4402{
4403 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4404 unsigned long flags;
4405
4406 spin_lock_irqsave(&a7gc->lock, flags);
4407
4408 __atlas7_gpio_set_input(a7gc, gpio);
4409
4410 spin_unlock_irqrestore(&a7gc->lock, flags);
4411
4412 return 0;
4413}
4414
4415static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
4416 unsigned int gpio, int value)
4417{
4418 struct atlas7_gpio_bank *bank;
4419 void __iomem *ctrl_reg;
4420 u32 out_ctrl, pin_in_bank;
4421
4422 bank = atlas7_gpio_to_bank(a7gc, gpio);
4423 pin_in_bank = gpio - bank->gpio_offset;
4424 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4425
4426 out_ctrl = readl(ctrl_reg);
4427 if (value)
4428 out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
4429 else
4430 out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
4431
4432 out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
4433 out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
4434 writel(out_ctrl, ctrl_reg);
4435}
4436
4437static int atlas7_gpio_direction_output(struct gpio_chip *chip,
4438 unsigned int gpio, int value)
4439{
4440 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4441 unsigned long flags;
4442
4443 spin_lock_irqsave(&a7gc->lock, flags);
4444
4445 __atlas7_gpio_set_output(a7gc, gpio, value);
4446
4447 spin_unlock_irqrestore(&a7gc->lock, flags);
4448
4449 return 0;
4450}
4451
4452static int atlas7_gpio_get_value(struct gpio_chip *chip,
4453 unsigned int gpio)
4454{
4455 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4456 struct atlas7_gpio_bank *bank;
4457 u32 val, pin_in_bank;
4458 unsigned long flags;
4459
4460 bank = atlas7_gpio_to_bank(a7gc, gpio);
4461 pin_in_bank = gpio - bank->gpio_offset;
4462
4463 spin_lock_irqsave(&a7gc->lock, flags);
4464
4465 val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
4466
4467 spin_unlock_irqrestore(&a7gc->lock, flags);
4468
4469 return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
4470}
4471
4472static void atlas7_gpio_set_value(struct gpio_chip *chip,
4473 unsigned int gpio, int value)
4474{
4475 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(chip);
4476 struct atlas7_gpio_bank *bank;
4477 void __iomem *ctrl_reg;
4478 u32 ctrl, pin_in_bank;
4479 unsigned long flags;
4480
4481 bank = atlas7_gpio_to_bank(a7gc, gpio);
4482 pin_in_bank = gpio - bank->gpio_offset;
4483 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
4484
4485 spin_lock_irqsave(&a7gc->lock, flags);
4486
4487 ctrl = readl(ctrl_reg);
4488 if (value)
4489 ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
4490 else
4491 ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
4492 writel(ctrl, ctrl_reg);
4493
4494 spin_unlock_irqrestore(&a7gc->lock, flags);
4495}
4496
4497static const struct of_device_id atlas7_gpio_ids[] = {
4498 { .compatible = "sirf,atlas7-gpio", },
4499};
4500
4501static int atlas7_gpio_probe(struct platform_device *pdev)
4502{
4503 struct device_node *np = pdev->dev.of_node;
4504 struct atlas7_gpio_chip *a7gc;
4505 struct gpio_chip *chip;
4506 u32 nbank;
4507 int ret, idx;
4508
4509 ret = of_property_read_u32(np, "gpio-banks", &nbank);
4510 if (ret) {
4511 dev_err(&pdev->dev,
4512 "Could not find GPIO bank info,ret=%d!\n",
4513 ret);
4514 return ret;
4515 }
4516
4517 /* retrieve gpio descriptor data */
4518 a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
4519 sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
4520 if (!a7gc)
4521 return -ENOMEM;
4522
4523 /* Get Gpio clk */
4524 a7gc->clk = of_clk_get(np, 0);
4525 if (!IS_ERR(a7gc->clk)) {
4526 ret = clk_prepare_enable(a7gc->clk);
4527 if (ret) {
4528 dev_err(&pdev->dev,
4529 "Could not enable clock!\n");
4530 return ret;
4531 }
4532 }
4533
4534 /* Get Gpio Registers */
4535 a7gc->reg = of_iomap(np, 0);
4536 if (!a7gc->reg) {
4537 dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
4538 return -ENOMEM;
4539 }
4540
4541 a7gc->nbank = nbank;
4542 spin_lock_init(&a7gc->lock);
4543
4544 /* Setup GPIO Chip */
4545 chip = &a7gc->chip;
4546 chip->request = atlas7_gpio_request;
4547 chip->free = atlas7_gpio_free;
4548 chip->direction_input = atlas7_gpio_direction_input;
4549 chip->get = atlas7_gpio_get_value;
4550 chip->direction_output = atlas7_gpio_direction_output;
4551 chip->set = atlas7_gpio_set_value;
4552 chip->base = -1;
4553 /* Each chip can support 32 pins at one bank */
4554 chip->ngpio = NGPIO_OF_BANK * nbank;
4555 chip->label = kstrdup(np->name, GFP_KERNEL);
4556 chip->of_node = np;
4557 chip->of_gpio_n_cells = 2;
4558 chip->dev = &pdev->dev;
4559
4560 /* Add gpio chip to system */
4561 ret = gpiochip_add(chip);
4562 if (ret) {
4563 dev_err(&pdev->dev,
4564 "%s: error in probe function with status %d\n",
4565 np->name, ret);
4566 goto failed;
4567 }
4568
4569 /* Add gpio chip to irq subsystem */
4570 ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
4571 0, handle_level_irq, IRQ_TYPE_NONE);
4572 if (ret) {
4573 dev_err(&pdev->dev,
4574 "could not connect irqchip to gpiochip\n");
4575 goto failed;
4576 }
4577
4578 for (idx = 0; idx < nbank; idx++) {
4579 struct gpio_pin_range *pin_range;
4580 struct atlas7_gpio_bank *bank;
4581
4582 bank = &a7gc->banks[idx];
4583 /* Set ctrl registers' base of this bank */
4584 bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
4585
4586 /* Get interrupt number from DTS */
4587 ret = of_irq_get(np, idx);
4588 if (ret == -EPROBE_DEFER) {
4589 dev_err(&pdev->dev,
4590 "Unable to find IRQ number. ret=%d\n", ret);
4591 goto failed;
4592 }
4593 bank->irq = ret;
4594
4595 gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
4596 bank->irq, atlas7_gpio_handle_irq);
4597
4598 /* Records gpio_pin_range to a7gc */
4599 list_for_each_entry(pin_range, &chip->pin_ranges, node) {
4600 struct pinctrl_gpio_range *range;
4601
4602 range = &pin_range->range;
4603 if (range->id == NGPIO_OF_BANK * idx) {
4604 bank->gpio_offset = range->id;
4605 bank->ngpio = range->npins;
4606 bank->gpio_pins = range->pins;
4607 bank->pctldev = pin_range->pctldev;
4608 break;
4609 }
4610 }
4611
4612 BUG_ON(!bank->pctldev);
4613 }
4614
4615 dev_info(&pdev->dev, "add to system.\n");
4616 return 0;
4617failed:
4618 return ret;
4619}
4620
4621static struct platform_driver atlas7_gpio_driver = {
4622 .driver = {
4623 .name = "atlas7-gpio",
4624 .owner = THIS_MODULE,
4625 .of_match_table = atlas7_gpio_ids,
4626 },
4627 .probe = atlas7_gpio_probe,
4628};
4629
4630static int __init atlas7_gpio_init(void)
4631{
4632 return platform_driver_register(&atlas7_gpio_driver);
4633}
4634subsys_initcall(atlas7_gpio_init);
4635
4636MODULE_DESCRIPTION("SIRFSOC Atlas7 pin control driver");
4637MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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