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3370dc91 BS |
1 | /* |
2 | * pinmux driver for CSR SiRFprimaII | |
3 | * | |
019c12f4 BS |
4 | * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group |
5 | * company. | |
3370dc91 BS |
6 | * |
7 | * Licensed under GPLv2 or later. | |
8 | */ | |
9 | ||
10 | #include <linux/init.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
3370dc91 BS |
17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | |
19 | #include <linux/pinctrl/consumer.h> | |
20 | #include <linux/pinctrl/machine.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/of_gpio.h> | |
3370dc91 BS |
28 | |
29 | #include "pinctrl-sirf.h" | |
30 | ||
31 | #define DRIVER_NAME "pinmux-sirf" | |
32 | ||
33 | struct sirfsoc_gpio_bank { | |
3370dc91 BS |
34 | int id; |
35 | int parent_irq; | |
36 | spinlock_t lock; | |
c5eb757c BS |
37 | }; |
38 | ||
39 | struct sirfsoc_gpio_chip { | |
40 | struct of_mm_gpio_chip chip; | |
c5eb757c | 41 | struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; |
1dfe0d15 | 42 | spinlock_t lock; |
3370dc91 BS |
43 | }; |
44 | ||
3370dc91 BS |
45 | static struct sirfsoc_pin_group *sirfsoc_pin_groups; |
46 | static int sirfsoc_pingrp_cnt; | |
47 | ||
48 | static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) | |
49 | { | |
50 | return sirfsoc_pingrp_cnt; | |
51 | } | |
52 | ||
53 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, | |
54 | unsigned selector) | |
55 | { | |
56 | return sirfsoc_pin_groups[selector].name; | |
57 | } | |
58 | ||
c09f80db BS |
59 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, |
60 | unsigned selector, | |
61 | const unsigned **pins, | |
62 | unsigned *num_pins) | |
3370dc91 BS |
63 | { |
64 | *pins = sirfsoc_pin_groups[selector].pins; | |
65 | *num_pins = sirfsoc_pin_groups[selector].num_pins; | |
66 | return 0; | |
67 | } | |
68 | ||
c09f80db BS |
69 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, |
70 | struct seq_file *s, unsigned offset) | |
3370dc91 BS |
71 | { |
72 | seq_printf(s, " " DRIVER_NAME); | |
73 | } | |
74 | ||
75 | static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, | |
76 | struct device_node *np_config, | |
77 | struct pinctrl_map **map, unsigned *num_maps) | |
78 | { | |
79 | struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); | |
80 | struct device_node *np; | |
81 | struct property *prop; | |
82 | const char *function, *group; | |
83 | int ret, index = 0, count = 0; | |
84 | ||
85 | /* calculate number of maps required */ | |
86 | for_each_child_of_node(np_config, np) { | |
87 | ret = of_property_read_string(np, "sirf,function", &function); | |
2d98023c JL |
88 | if (ret < 0) { |
89 | of_node_put(np); | |
3370dc91 | 90 | return ret; |
2d98023c | 91 | } |
3370dc91 BS |
92 | |
93 | ret = of_property_count_strings(np, "sirf,pins"); | |
2d98023c JL |
94 | if (ret < 0) { |
95 | of_node_put(np); | |
3370dc91 | 96 | return ret; |
2d98023c | 97 | } |
3370dc91 BS |
98 | |
99 | count += ret; | |
100 | } | |
101 | ||
102 | if (!count) { | |
103 | dev_err(spmx->dev, "No child nodes passed via DT\n"); | |
104 | return -ENODEV; | |
105 | } | |
106 | ||
107 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | |
108 | if (!*map) | |
109 | return -ENOMEM; | |
110 | ||
111 | for_each_child_of_node(np_config, np) { | |
112 | of_property_read_string(np, "sirf,function", &function); | |
113 | of_property_for_each_string(np, "sirf,pins", prop, group) { | |
114 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | |
115 | (*map)[index].data.mux.group = group; | |
116 | (*map)[index].data.mux.function = function; | |
117 | index++; | |
118 | } | |
119 | } | |
120 | ||
121 | *num_maps = count; | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, | |
127 | struct pinctrl_map *map, unsigned num_maps) | |
128 | { | |
129 | kfree(map); | |
130 | } | |
131 | ||
132 | static struct pinctrl_ops sirfsoc_pctrl_ops = { | |
133 | .get_groups_count = sirfsoc_get_groups_count, | |
134 | .get_group_name = sirfsoc_get_group_name, | |
135 | .get_group_pins = sirfsoc_get_group_pins, | |
136 | .pin_dbg_show = sirfsoc_pin_dbg_show, | |
137 | .dt_node_to_map = sirfsoc_dt_node_to_map, | |
138 | .dt_free_map = sirfsoc_dt_free_map, | |
139 | }; | |
140 | ||
141 | static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; | |
142 | static int sirfsoc_pmxfunc_cnt; | |
143 | ||
c09f80db BS |
144 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, |
145 | unsigned selector, bool enable) | |
3370dc91 BS |
146 | { |
147 | int i; | |
c09f80db BS |
148 | const struct sirfsoc_padmux *mux = |
149 | sirfsoc_pmx_functions[selector].padmux; | |
3370dc91 BS |
150 | const struct sirfsoc_muxmask *mask = mux->muxmask; |
151 | ||
152 | for (i = 0; i < mux->muxmask_counts; i++) { | |
153 | u32 muxval; | |
a17272a4 BS |
154 | muxval = readl(spmx->gpio_virtbase + |
155 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
156 | if (enable) | |
157 | muxval = muxval & ~mask[i].mask; | |
158 | else | |
159 | muxval = muxval | mask[i].mask; | |
160 | writel(muxval, spmx->gpio_virtbase + | |
161 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
3370dc91 BS |
162 | } |
163 | ||
164 | if (mux->funcmask && enable) { | |
165 | u32 func_en_val; | |
6a08a92e | 166 | |
3370dc91 | 167 | func_en_val = |
6a08a92e | 168 | readl(spmx->rsc_virtbase + mux->ctrlreg); |
3370dc91 | 169 | func_en_val = |
6a08a92e RW |
170 | (func_en_val & ~mux->funcmask) | (mux->funcval); |
171 | writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); | |
3370dc91 BS |
172 | } |
173 | } | |
174 | ||
03e9f0ca LW |
175 | static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev, |
176 | unsigned selector, | |
177 | unsigned group) | |
3370dc91 BS |
178 | { |
179 | struct sirfsoc_pmx *spmx; | |
180 | ||
181 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
182 | sirfsoc_pinmux_endisable(spmx, selector, true); | |
183 | ||
184 | return 0; | |
185 | } | |
186 | ||
3370dc91 BS |
187 | static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) |
188 | { | |
189 | return sirfsoc_pmxfunc_cnt; | |
190 | } | |
191 | ||
192 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, | |
193 | unsigned selector) | |
194 | { | |
195 | return sirfsoc_pmx_functions[selector].name; | |
196 | } | |
197 | ||
c09f80db BS |
198 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, |
199 | unsigned selector, | |
200 | const char * const **groups, | |
201 | unsigned * const num_groups) | |
3370dc91 BS |
202 | { |
203 | *groups = sirfsoc_pmx_functions[selector].groups; | |
204 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, | |
209 | struct pinctrl_gpio_range *range, unsigned offset) | |
210 | { | |
211 | struct sirfsoc_pmx *spmx; | |
212 | ||
213 | int group = range->id; | |
214 | ||
215 | u32 muxval; | |
216 | ||
217 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
218 | ||
a17272a4 BS |
219 | muxval = readl(spmx->gpio_virtbase + |
220 | SIRFSOC_GPIO_PAD_EN(group)); | |
221 | muxval = muxval | (1 << (offset - range->pin_base)); | |
222 | writel(muxval, spmx->gpio_virtbase + | |
223 | SIRFSOC_GPIO_PAD_EN(group)); | |
3370dc91 BS |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
228 | static struct pinmux_ops sirfsoc_pinmux_ops = { | |
03e9f0ca | 229 | .set_mux = sirfsoc_pinmux_set_mux, |
3370dc91 BS |
230 | .get_functions_count = sirfsoc_pinmux_get_funcs_count, |
231 | .get_function_name = sirfsoc_pinmux_get_func_name, | |
232 | .get_function_groups = sirfsoc_pinmux_get_groups, | |
233 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, | |
234 | }; | |
235 | ||
236 | static struct pinctrl_desc sirfsoc_pinmux_desc = { | |
237 | .name = DRIVER_NAME, | |
238 | .pctlops = &sirfsoc_pctrl_ops, | |
239 | .pmxops = &sirfsoc_pinmux_ops, | |
240 | .owner = THIS_MODULE, | |
241 | }; | |
242 | ||
3370dc91 BS |
243 | static void __iomem *sirfsoc_rsc_of_iomap(void) |
244 | { | |
245 | const struct of_device_id rsc_ids[] = { | |
246 | { .compatible = "sirf,prima2-rsc" }, | |
3370dc91 BS |
247 | {} |
248 | }; | |
249 | struct device_node *np; | |
250 | ||
251 | np = of_find_matching_node(NULL, rsc_ids); | |
252 | if (!np) | |
253 | panic("unable to find compatible rsc node in dtb\n"); | |
254 | ||
255 | return of_iomap(np, 0); | |
256 | } | |
257 | ||
258 | static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, | |
c5eb757c BS |
259 | const struct of_phandle_args *gpiospec, |
260 | u32 *flags) | |
3370dc91 | 261 | { |
c5eb757c | 262 | if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) |
9c956909 | 263 | return -EINVAL; |
3370dc91 | 264 | |
c5eb757c | 265 | if (flags) |
9c956909 | 266 | *flags = gpiospec->args[1]; |
3370dc91 | 267 | |
c5eb757c | 268 | return gpiospec->args[0]; |
3370dc91 BS |
269 | } |
270 | ||
271 | static const struct of_device_id pinmux_ids[] = { | |
272 | { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, | |
273 | { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, | |
3370dc91 BS |
274 | {} |
275 | }; | |
276 | ||
277 | static int sirfsoc_pinmux_probe(struct platform_device *pdev) | |
278 | { | |
279 | int ret; | |
280 | struct sirfsoc_pmx *spmx; | |
281 | struct device_node *np = pdev->dev.of_node; | |
282 | const struct sirfsoc_pinctrl_data *pdata; | |
3370dc91 BS |
283 | |
284 | /* Create state holders etc for this driver */ | |
285 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); | |
286 | if (!spmx) | |
287 | return -ENOMEM; | |
288 | ||
289 | spmx->dev = &pdev->dev; | |
290 | ||
291 | platform_set_drvdata(pdev, spmx); | |
292 | ||
293 | spmx->gpio_virtbase = of_iomap(np, 0); | |
294 | if (!spmx->gpio_virtbase) { | |
295 | dev_err(&pdev->dev, "can't map gpio registers\n"); | |
296 | return -ENOMEM; | |
297 | } | |
298 | ||
299 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); | |
300 | if (!spmx->rsc_virtbase) { | |
301 | ret = -ENOMEM; | |
302 | dev_err(&pdev->dev, "can't map rsc registers\n"); | |
303 | goto out_no_rsc_remap; | |
304 | } | |
305 | ||
3370dc91 BS |
306 | pdata = of_match_node(pinmux_ids, np)->data; |
307 | sirfsoc_pin_groups = pdata->grps; | |
308 | sirfsoc_pingrp_cnt = pdata->grps_cnt; | |
309 | sirfsoc_pmx_functions = pdata->funcs; | |
310 | sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; | |
311 | sirfsoc_pinmux_desc.pins = pdata->pads; | |
312 | sirfsoc_pinmux_desc.npins = pdata->pads_cnt; | |
313 | ||
314 | ||
315 | /* Now register the pin controller and all pins it handles */ | |
316 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); | |
323de9ef | 317 | if (IS_ERR(spmx->pmx)) { |
3370dc91 | 318 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); |
323de9ef | 319 | ret = PTR_ERR(spmx->pmx); |
3370dc91 BS |
320 | goto out_no_pmx; |
321 | } | |
322 | ||
3370dc91 BS |
323 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); |
324 | ||
325 | return 0; | |
326 | ||
327 | out_no_pmx: | |
328 | iounmap(spmx->rsc_virtbase); | |
329 | out_no_rsc_remap: | |
330 | iounmap(spmx->gpio_virtbase); | |
331 | return ret; | |
332 | } | |
333 | ||
bc8d25a4 BS |
334 | #ifdef CONFIG_PM_SLEEP |
335 | static int sirfsoc_pinmux_suspend_noirq(struct device *dev) | |
336 | { | |
337 | int i, j; | |
338 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
339 | ||
340 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
341 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
342 | spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + | |
343 | SIRFSOC_GPIO_CTRL(i, j)); | |
344 | } | |
345 | spmx->ints_regs[i] = readl(spmx->gpio_virtbase + | |
346 | SIRFSOC_GPIO_INT_STATUS(i)); | |
347 | spmx->paden_regs[i] = readl(spmx->gpio_virtbase + | |
348 | SIRFSOC_GPIO_PAD_EN(i)); | |
349 | } | |
350 | spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
351 | ||
352 | for (i = 0; i < 3; i++) | |
353 | spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static int sirfsoc_pinmux_resume_noirq(struct device *dev) | |
359 | { | |
360 | int i, j; | |
361 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
362 | ||
363 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
364 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
365 | writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + | |
366 | SIRFSOC_GPIO_CTRL(i, j)); | |
367 | } | |
368 | writel(spmx->ints_regs[i], spmx->gpio_virtbase + | |
369 | SIRFSOC_GPIO_INT_STATUS(i)); | |
370 | writel(spmx->paden_regs[i], spmx->gpio_virtbase + | |
371 | SIRFSOC_GPIO_PAD_EN(i)); | |
372 | } | |
373 | writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
374 | ||
375 | for (i = 0; i < 3; i++) | |
376 | writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { | |
382 | .suspend_noirq = sirfsoc_pinmux_suspend_noirq, | |
383 | .resume_noirq = sirfsoc_pinmux_resume_noirq, | |
f6b17885 BS |
384 | .freeze_noirq = sirfsoc_pinmux_suspend_noirq, |
385 | .restore_noirq = sirfsoc_pinmux_resume_noirq, | |
bc8d25a4 BS |
386 | }; |
387 | #endif | |
388 | ||
3370dc91 BS |
389 | static struct platform_driver sirfsoc_pinmux_driver = { |
390 | .driver = { | |
391 | .name = DRIVER_NAME, | |
3370dc91 | 392 | .of_match_table = pinmux_ids, |
bc8d25a4 BS |
393 | #ifdef CONFIG_PM_SLEEP |
394 | .pm = &sirfsoc_pinmux_pm_ops, | |
395 | #endif | |
3370dc91 BS |
396 | }, |
397 | .probe = sirfsoc_pinmux_probe, | |
398 | }; | |
399 | ||
400 | static int __init sirfsoc_pinmux_init(void) | |
401 | { | |
402 | return platform_driver_register(&sirfsoc_pinmux_driver); | |
403 | } | |
404 | arch_initcall(sirfsoc_pinmux_init); | |
405 | ||
294d1351 LW |
406 | static inline struct sirfsoc_gpio_bank * |
407 | sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) | |
3370dc91 | 408 | { |
294d1351 | 409 | return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; |
3370dc91 BS |
410 | } |
411 | ||
294d1351 | 412 | static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) |
3370dc91 | 413 | { |
294d1351 | 414 | return offset % SIRFSOC_GPIO_BANK_SIZE; |
3370dc91 | 415 | } |
7420d2d0 | 416 | |
3370dc91 BS |
417 | static void sirfsoc_gpio_irq_ack(struct irq_data *d) |
418 | { | |
294d1351 | 419 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
192d3507 | 420 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); |
294d1351 LW |
421 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); |
422 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
423 | u32 val, offset; |
424 | unsigned long flags; | |
425 | ||
426 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
427 | ||
1dfe0d15 | 428 | spin_lock_irqsave(&sgpio->lock, flags); |
3370dc91 | 429 | |
294d1351 | 430 | val = readl(sgpio->chip.regs + offset); |
3370dc91 | 431 | |
294d1351 | 432 | writel(val, sgpio->chip.regs + offset); |
3370dc91 | 433 | |
1dfe0d15 | 434 | spin_unlock_irqrestore(&sgpio->lock, flags); |
3370dc91 BS |
435 | } |
436 | ||
294d1351 LW |
437 | static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, |
438 | struct sirfsoc_gpio_bank *bank, | |
439 | int idx) | |
3370dc91 BS |
440 | { |
441 | u32 val, offset; | |
442 | unsigned long flags; | |
443 | ||
444 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
445 | ||
1dfe0d15 | 446 | spin_lock_irqsave(&sgpio->lock, flags); |
3370dc91 | 447 | |
294d1351 | 448 | val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
449 | val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; |
450 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
294d1351 | 451 | writel(val, sgpio->chip.regs + offset); |
3370dc91 | 452 | |
1dfe0d15 | 453 | spin_unlock_irqrestore(&sgpio->lock, flags); |
3370dc91 BS |
454 | } |
455 | ||
456 | static void sirfsoc_gpio_irq_mask(struct irq_data *d) | |
457 | { | |
294d1351 | 458 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
192d3507 | 459 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); |
294d1351 | 460 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); |
3370dc91 | 461 | |
294d1351 | 462 | __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); |
3370dc91 BS |
463 | } |
464 | ||
465 | static void sirfsoc_gpio_irq_unmask(struct irq_data *d) | |
466 | { | |
294d1351 | 467 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
192d3507 | 468 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); |
294d1351 LW |
469 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); |
470 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
471 | u32 val, offset; |
472 | unsigned long flags; | |
473 | ||
474 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
475 | ||
1dfe0d15 | 476 | spin_lock_irqsave(&sgpio->lock, flags); |
3370dc91 | 477 | |
294d1351 | 478 | val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
479 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; |
480 | val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
294d1351 | 481 | writel(val, sgpio->chip.regs + offset); |
3370dc91 | 482 | |
1dfe0d15 | 483 | spin_unlock_irqrestore(&sgpio->lock, flags); |
3370dc91 BS |
484 | } |
485 | ||
486 | static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |
487 | { | |
294d1351 | 488 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
192d3507 | 489 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); |
294d1351 LW |
490 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); |
491 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
492 | u32 val, offset; |
493 | unsigned long flags; | |
494 | ||
495 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
496 | ||
1dfe0d15 | 497 | spin_lock_irqsave(&sgpio->lock, flags); |
3370dc91 | 498 | |
294d1351 | 499 | val = readl(sgpio->chip.regs + offset); |
b07ddcdc | 500 | val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); |
3370dc91 BS |
501 | |
502 | switch (type) { | |
503 | case IRQ_TYPE_NONE: | |
504 | break; | |
505 | case IRQ_TYPE_EDGE_RISING: | |
c09f80db BS |
506 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
507 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
508 | val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; |
509 | break; | |
510 | case IRQ_TYPE_EDGE_FALLING: | |
511 | val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
c09f80db BS |
512 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | |
513 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
514 | break; |
515 | case IRQ_TYPE_EDGE_BOTH: | |
c09f80db BS |
516 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
517 | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | | |
518 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
519 | break; |
520 | case IRQ_TYPE_LEVEL_LOW: | |
c09f80db BS |
521 | val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
522 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
3370dc91 BS |
523 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; |
524 | break; | |
525 | case IRQ_TYPE_LEVEL_HIGH: | |
526 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
c09f80db BS |
527 | val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | |
528 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
3370dc91 BS |
529 | break; |
530 | } | |
531 | ||
294d1351 | 532 | writel(val, sgpio->chip.regs + offset); |
3370dc91 | 533 | |
1dfe0d15 | 534 | spin_unlock_irqrestore(&sgpio->lock, flags); |
3370dc91 BS |
535 | |
536 | return 0; | |
537 | } | |
538 | ||
539 | static struct irq_chip sirfsoc_irq_chip = { | |
540 | .name = "sirf-gpio-irq", | |
541 | .irq_ack = sirfsoc_gpio_irq_ack, | |
542 | .irq_mask = sirfsoc_gpio_irq_mask, | |
543 | .irq_unmask = sirfsoc_gpio_irq_unmask, | |
544 | .irq_set_type = sirfsoc_gpio_irq_type, | |
545 | }; | |
546 | ||
bd0b9ac4 | 547 | static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) |
3370dc91 | 548 | { |
3b0d1561 | 549 | unsigned int irq = irq_desc_get_irq(desc); |
294d1351 | 550 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
192d3507 | 551 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(gc); |
7420d2d0 | 552 | struct sirfsoc_gpio_bank *bank; |
3370dc91 BS |
553 | u32 status, ctrl; |
554 | int idx = 0; | |
5663bb27 | 555 | struct irq_chip *chip = irq_desc_get_chip(desc); |
7420d2d0 LW |
556 | int i; |
557 | ||
648e42e1 | 558 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { |
29c7f1f5 | 559 | bank = &sgpio->sgpio_bank[i]; |
7420d2d0 LW |
560 | if (bank->parent_irq == irq) |
561 | break; | |
562 | } | |
648e42e1 | 563 | BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); |
3370dc91 BS |
564 | |
565 | chained_irq_enter(chip, desc); | |
566 | ||
294d1351 | 567 | status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); |
3370dc91 BS |
568 | if (!status) { |
569 | printk(KERN_WARNING | |
28b30c30 | 570 | "%s: gpio id %d status %#x no interrupt is flagged\n", |
3370dc91 | 571 | __func__, bank->id, status); |
bd0b9ac4 | 572 | handle_bad_irq(desc); |
3370dc91 BS |
573 | return; |
574 | } | |
575 | ||
576 | while (status) { | |
294d1351 | 577 | ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); |
3370dc91 BS |
578 | |
579 | /* | |
580 | * Here we must check whether the corresponding GPIO's interrupt | |
581 | * has been enabled, otherwise just skip it | |
582 | */ | |
583 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | |
584 | pr_debug("%s: gpio id %d idx %d happens\n", | |
585 | __func__, bank->id, idx); | |
294d1351 | 586 | generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + |
8daeffb0 | 587 | bank->id * SIRFSOC_GPIO_BANK_SIZE)); |
3370dc91 BS |
588 | } |
589 | ||
590 | idx++; | |
591 | status = status >> 1; | |
592 | } | |
593 | ||
594 | chained_irq_exit(chip, desc); | |
595 | } | |
596 | ||
294d1351 LW |
597 | static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, |
598 | unsigned ctrl_offset) | |
3370dc91 BS |
599 | { |
600 | u32 val; | |
601 | ||
294d1351 | 602 | val = readl(sgpio->chip.regs + ctrl_offset); |
3370dc91 | 603 | val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; |
294d1351 | 604 | writel(val, sgpio->chip.regs + ctrl_offset); |
3370dc91 BS |
605 | } |
606 | ||
607 | static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) | |
608 | { | |
192d3507 | 609 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 610 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); |
3370dc91 BS |
611 | unsigned long flags; |
612 | ||
613 | if (pinctrl_request_gpio(chip->base + offset)) | |
614 | return -ENODEV; | |
615 | ||
616 | spin_lock_irqsave(&bank->lock, flags); | |
617 | ||
618 | /* | |
619 | * default status: | |
620 | * set direction as input and mask irq | |
621 | */ | |
294d1351 LW |
622 | sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); |
623 | __sirfsoc_gpio_irq_mask(sgpio, bank, offset); | |
3370dc91 BS |
624 | |
625 | spin_unlock_irqrestore(&bank->lock, flags); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
630 | static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) | |
631 | { | |
192d3507 | 632 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 633 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); |
3370dc91 BS |
634 | unsigned long flags; |
635 | ||
636 | spin_lock_irqsave(&bank->lock, flags); | |
637 | ||
294d1351 LW |
638 | __sirfsoc_gpio_irq_mask(sgpio, bank, offset); |
639 | sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
3370dc91 BS |
640 | |
641 | spin_unlock_irqrestore(&bank->lock, flags); | |
642 | ||
643 | pinctrl_free_gpio(chip->base + offset); | |
644 | } | |
645 | ||
646 | static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
647 | { | |
192d3507 | 648 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 649 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); |
c5eb757c | 650 | int idx = sirfsoc_gpio_to_bankoff(gpio); |
3370dc91 BS |
651 | unsigned long flags; |
652 | unsigned offset; | |
653 | ||
654 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
655 | ||
656 | spin_lock_irqsave(&bank->lock, flags); | |
657 | ||
294d1351 | 658 | sirfsoc_gpio_set_input(sgpio, offset); |
3370dc91 BS |
659 | |
660 | spin_unlock_irqrestore(&bank->lock, flags); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
294d1351 LW |
665 | static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, |
666 | struct sirfsoc_gpio_bank *bank, | |
667 | unsigned offset, | |
668 | int value) | |
3370dc91 BS |
669 | { |
670 | u32 out_ctrl; | |
671 | unsigned long flags; | |
672 | ||
673 | spin_lock_irqsave(&bank->lock, flags); | |
674 | ||
294d1351 | 675 | out_ctrl = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
676 | if (value) |
677 | out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
678 | else | |
679 | out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
680 | ||
681 | out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
682 | out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
294d1351 | 683 | writel(out_ctrl, sgpio->chip.regs + offset); |
3370dc91 BS |
684 | |
685 | spin_unlock_irqrestore(&bank->lock, flags); | |
686 | } | |
687 | ||
c09f80db BS |
688 | static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, |
689 | unsigned gpio, int value) | |
3370dc91 | 690 | { |
192d3507 | 691 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 692 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); |
c5eb757c | 693 | int idx = sirfsoc_gpio_to_bankoff(gpio); |
3370dc91 BS |
694 | u32 offset; |
695 | unsigned long flags; | |
696 | ||
697 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
698 | ||
1dfe0d15 | 699 | spin_lock_irqsave(&sgpio->lock, flags); |
3370dc91 | 700 | |
294d1351 | 701 | sirfsoc_gpio_set_output(sgpio, bank, offset, value); |
3370dc91 | 702 | |
1dfe0d15 | 703 | spin_unlock_irqrestore(&sgpio->lock, flags); |
3370dc91 BS |
704 | |
705 | return 0; | |
706 | } | |
707 | ||
708 | static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) | |
709 | { | |
192d3507 | 710 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 711 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); |
3370dc91 BS |
712 | u32 val; |
713 | unsigned long flags; | |
714 | ||
715 | spin_lock_irqsave(&bank->lock, flags); | |
716 | ||
294d1351 | 717 | val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
718 | |
719 | spin_unlock_irqrestore(&bank->lock, flags); | |
720 | ||
721 | return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); | |
722 | } | |
723 | ||
724 | static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, | |
725 | int value) | |
726 | { | |
192d3507 | 727 | struct sirfsoc_gpio_chip *sgpio = gpiochip_get_data(chip); |
294d1351 | 728 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); |
3370dc91 BS |
729 | u32 ctrl; |
730 | unsigned long flags; | |
731 | ||
732 | spin_lock_irqsave(&bank->lock, flags); | |
733 | ||
294d1351 | 734 | ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
735 | if (value) |
736 | ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
737 | else | |
738 | ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
294d1351 | 739 | writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
740 | |
741 | spin_unlock_irqrestore(&bank->lock, flags); | |
742 | } | |
743 | ||
294d1351 LW |
744 | static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, |
745 | const u32 *pullups) | |
3370dc91 BS |
746 | { |
747 | int i, n; | |
748 | const unsigned long *p = (const unsigned long *)pullups; | |
749 | ||
750 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
751 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
752 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
294d1351 | 753 | u32 val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
754 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; |
755 | val |= SIRFSOC_GPIO_CTL_PULL_HIGH; | |
294d1351 | 756 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
757 | } |
758 | } | |
759 | } | |
760 | ||
294d1351 LW |
761 | static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, |
762 | const u32 *pulldowns) | |
3370dc91 BS |
763 | { |
764 | int i, n; | |
765 | const unsigned long *p = (const unsigned long *)pulldowns; | |
766 | ||
767 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
768 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
769 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
294d1351 | 770 | u32 val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
771 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; |
772 | val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; | |
294d1351 | 773 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
774 | } |
775 | } | |
776 | } | |
777 | ||
778 | static int sirfsoc_gpio_probe(struct device_node *np) | |
779 | { | |
780 | int i, err = 0; | |
294d1351 | 781 | static struct sirfsoc_gpio_chip *sgpio; |
3370dc91 | 782 | struct sirfsoc_gpio_bank *bank; |
2c9fdcf1 | 783 | void __iomem *regs; |
3370dc91 | 784 | struct platform_device *pdev; |
3370dc91 BS |
785 | |
786 | u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; | |
787 | ||
788 | pdev = of_find_device_by_node(np); | |
789 | if (!pdev) | |
790 | return -ENODEV; | |
791 | ||
294d1351 LW |
792 | sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); |
793 | if (!sgpio) | |
794 | return -ENOMEM; | |
1dfe0d15 | 795 | spin_lock_init(&sgpio->lock); |
294d1351 | 796 | |
3370dc91 BS |
797 | regs = of_iomap(np, 0); |
798 | if (!regs) | |
799 | return -ENOMEM; | |
800 | ||
294d1351 LW |
801 | sgpio->chip.gc.request = sirfsoc_gpio_request; |
802 | sgpio->chip.gc.free = sirfsoc_gpio_free; | |
803 | sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; | |
804 | sgpio->chip.gc.get = sirfsoc_gpio_get_value; | |
805 | sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; | |
806 | sgpio->chip.gc.set = sirfsoc_gpio_set_value; | |
807 | sgpio->chip.gc.base = 0; | |
808 | sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; | |
809 | sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); | |
810 | sgpio->chip.gc.of_node = np; | |
811 | sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; | |
812 | sgpio->chip.gc.of_gpio_n_cells = 2; | |
58383c78 | 813 | sgpio->chip.gc.parent = &pdev->dev; |
294d1351 | 814 | sgpio->chip.regs = regs; |
294d1351 | 815 | |
192d3507 | 816 | err = gpiochip_add_data(&sgpio->chip.gc, sgpio); |
c5eb757c | 817 | if (err) { |
7420d2d0 | 818 | dev_err(&pdev->dev, "%s: error in probe function with status %d\n", |
c5eb757c BS |
819 | np->full_name, err); |
820 | goto out; | |
821 | } | |
822 | ||
294d1351 | 823 | err = gpiochip_irqchip_add(&sgpio->chip.gc, |
7420d2d0 LW |
824 | &sirfsoc_irq_chip, |
825 | 0, handle_level_irq, | |
826 | IRQ_TYPE_NONE); | |
827 | if (err) { | |
828 | dev_err(&pdev->dev, | |
829 | "could not connect irqchip to gpiochip\n"); | |
0a5d6670 | 830 | goto out_banks; |
7420d2d0 LW |
831 | } |
832 | ||
3370dc91 | 833 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { |
294d1351 | 834 | bank = &sgpio->sgpio_bank[i]; |
3370dc91 | 835 | spin_lock_init(&bank->lock); |
3370dc91 BS |
836 | bank->parent_irq = platform_get_irq(pdev, i); |
837 | if (bank->parent_irq < 0) { | |
838 | err = bank->parent_irq; | |
294d1351 | 839 | goto out_banks; |
3370dc91 BS |
840 | } |
841 | ||
294d1351 | 842 | gpiochip_set_chained_irqchip(&sgpio->chip.gc, |
7420d2d0 LW |
843 | &sirfsoc_irq_chip, |
844 | bank->parent_irq, | |
845 | sirfsoc_gpio_handle_irq); | |
3370dc91 BS |
846 | } |
847 | ||
294d1351 LW |
848 | err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), |
849 | 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); | |
850 | if (err) { | |
851 | dev_err(&pdev->dev, | |
852 | "could not add gpiochip pin range\n"); | |
853 | goto out_no_range; | |
854 | } | |
855 | ||
3370dc91 BS |
856 | if (!of_property_read_u32_array(np, "sirf,pullups", pullups, |
857 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
294d1351 | 858 | sirfsoc_gpio_set_pullup(sgpio, pullups); |
3370dc91 BS |
859 | |
860 | if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, | |
861 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
294d1351 | 862 | sirfsoc_gpio_set_pulldown(sgpio, pulldowns); |
3370dc91 BS |
863 | |
864 | return 0; | |
865 | ||
294d1351 LW |
866 | out_no_range: |
867 | out_banks: | |
2fcea6ce | 868 | gpiochip_remove(&sgpio->chip.gc); |
3370dc91 BS |
869 | out: |
870 | iounmap(regs); | |
871 | return err; | |
872 | } | |
873 | ||
874 | static int __init sirfsoc_gpio_init(void) | |
875 | { | |
876 | ||
877 | struct device_node *np; | |
878 | ||
879 | np = of_find_matching_node(NULL, pinmux_ids); | |
880 | ||
881 | if (!np) | |
882 | return -ENODEV; | |
883 | ||
884 | return sirfsoc_gpio_probe(np); | |
885 | } | |
886 | subsys_initcall(sirfsoc_gpio_init); | |
887 | ||
4bee325c BS |
888 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>"); |
889 | MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>"); | |
890 | MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); | |
3370dc91 BS |
891 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); |
892 | MODULE_LICENSE("GPL"); |