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1 | /* |
2 | * pinmux driver for CSR SiRFprimaII | |
3 | * | |
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4 | * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group |
5 | * company. | |
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6 | * |
7 | * Licensed under GPLv2 or later. | |
8 | */ | |
9 | ||
10 | #include <linux/init.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
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17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | |
19 | #include <linux/pinctrl/consumer.h> | |
20 | #include <linux/pinctrl/machine.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_address.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/bitops.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/of_gpio.h> | |
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28 | |
29 | #include "pinctrl-sirf.h" | |
30 | ||
31 | #define DRIVER_NAME "pinmux-sirf" | |
32 | ||
33 | struct sirfsoc_gpio_bank { | |
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34 | int id; |
35 | int parent_irq; | |
36 | spinlock_t lock; | |
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37 | }; |
38 | ||
39 | struct sirfsoc_gpio_chip { | |
40 | struct of_mm_gpio_chip chip; | |
3370dc91 | 41 | bool is_marco; /* for marco, some registers are different with prima2 */ |
c5eb757c | 42 | struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; |
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43 | }; |
44 | ||
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45 | static DEFINE_SPINLOCK(sgpio_lock); |
46 | ||
47 | static struct sirfsoc_pin_group *sirfsoc_pin_groups; | |
48 | static int sirfsoc_pingrp_cnt; | |
49 | ||
50 | static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) | |
51 | { | |
52 | return sirfsoc_pingrp_cnt; | |
53 | } | |
54 | ||
55 | static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, | |
56 | unsigned selector) | |
57 | { | |
58 | return sirfsoc_pin_groups[selector].name; | |
59 | } | |
60 | ||
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61 | static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, |
62 | unsigned selector, | |
63 | const unsigned **pins, | |
64 | unsigned *num_pins) | |
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65 | { |
66 | *pins = sirfsoc_pin_groups[selector].pins; | |
67 | *num_pins = sirfsoc_pin_groups[selector].num_pins; | |
68 | return 0; | |
69 | } | |
70 | ||
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71 | static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, |
72 | struct seq_file *s, unsigned offset) | |
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73 | { |
74 | seq_printf(s, " " DRIVER_NAME); | |
75 | } | |
76 | ||
77 | static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev, | |
78 | struct device_node *np_config, | |
79 | struct pinctrl_map **map, unsigned *num_maps) | |
80 | { | |
81 | struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev); | |
82 | struct device_node *np; | |
83 | struct property *prop; | |
84 | const char *function, *group; | |
85 | int ret, index = 0, count = 0; | |
86 | ||
87 | /* calculate number of maps required */ | |
88 | for_each_child_of_node(np_config, np) { | |
89 | ret = of_property_read_string(np, "sirf,function", &function); | |
90 | if (ret < 0) | |
91 | return ret; | |
92 | ||
93 | ret = of_property_count_strings(np, "sirf,pins"); | |
94 | if (ret < 0) | |
95 | return ret; | |
96 | ||
97 | count += ret; | |
98 | } | |
99 | ||
100 | if (!count) { | |
101 | dev_err(spmx->dev, "No child nodes passed via DT\n"); | |
102 | return -ENODEV; | |
103 | } | |
104 | ||
105 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | |
106 | if (!*map) | |
107 | return -ENOMEM; | |
108 | ||
109 | for_each_child_of_node(np_config, np) { | |
110 | of_property_read_string(np, "sirf,function", &function); | |
111 | of_property_for_each_string(np, "sirf,pins", prop, group) { | |
112 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | |
113 | (*map)[index].data.mux.group = group; | |
114 | (*map)[index].data.mux.function = function; | |
115 | index++; | |
116 | } | |
117 | } | |
118 | ||
119 | *num_maps = count; | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev, | |
125 | struct pinctrl_map *map, unsigned num_maps) | |
126 | { | |
127 | kfree(map); | |
128 | } | |
129 | ||
130 | static struct pinctrl_ops sirfsoc_pctrl_ops = { | |
131 | .get_groups_count = sirfsoc_get_groups_count, | |
132 | .get_group_name = sirfsoc_get_group_name, | |
133 | .get_group_pins = sirfsoc_get_group_pins, | |
134 | .pin_dbg_show = sirfsoc_pin_dbg_show, | |
135 | .dt_node_to_map = sirfsoc_dt_node_to_map, | |
136 | .dt_free_map = sirfsoc_dt_free_map, | |
137 | }; | |
138 | ||
139 | static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; | |
140 | static int sirfsoc_pmxfunc_cnt; | |
141 | ||
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142 | static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, |
143 | unsigned selector, bool enable) | |
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144 | { |
145 | int i; | |
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146 | const struct sirfsoc_padmux *mux = |
147 | sirfsoc_pmx_functions[selector].padmux; | |
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148 | const struct sirfsoc_muxmask *mask = mux->muxmask; |
149 | ||
150 | for (i = 0; i < mux->muxmask_counts; i++) { | |
151 | u32 muxval; | |
152 | if (!spmx->is_marco) { | |
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153 | muxval = readl(spmx->gpio_virtbase + |
154 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
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155 | if (enable) |
156 | muxval = muxval & ~mask[i].mask; | |
157 | else | |
158 | muxval = muxval | mask[i].mask; | |
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159 | writel(muxval, spmx->gpio_virtbase + |
160 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
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161 | } else { |
162 | if (enable) | |
163 | writel(mask[i].mask, spmx->gpio_virtbase + | |
164 | SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group)); | |
165 | else | |
166 | writel(mask[i].mask, spmx->gpio_virtbase + | |
167 | SIRFSOC_GPIO_PAD_EN(mask[i].group)); | |
168 | } | |
169 | } | |
170 | ||
171 | if (mux->funcmask && enable) { | |
172 | u32 func_en_val; | |
6a08a92e | 173 | |
3370dc91 | 174 | func_en_val = |
6a08a92e | 175 | readl(spmx->rsc_virtbase + mux->ctrlreg); |
3370dc91 | 176 | func_en_val = |
6a08a92e RW |
177 | (func_en_val & ~mux->funcmask) | (mux->funcval); |
178 | writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); | |
3370dc91 BS |
179 | } |
180 | } | |
181 | ||
182 | static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, | |
183 | unsigned group) | |
184 | { | |
185 | struct sirfsoc_pmx *spmx; | |
186 | ||
187 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
188 | sirfsoc_pinmux_endisable(spmx, selector, true); | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
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193 | static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) |
194 | { | |
195 | return sirfsoc_pmxfunc_cnt; | |
196 | } | |
197 | ||
198 | static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, | |
199 | unsigned selector) | |
200 | { | |
201 | return sirfsoc_pmx_functions[selector].name; | |
202 | } | |
203 | ||
c09f80db BS |
204 | static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, |
205 | unsigned selector, | |
206 | const char * const **groups, | |
207 | unsigned * const num_groups) | |
3370dc91 BS |
208 | { |
209 | *groups = sirfsoc_pmx_functions[selector].groups; | |
210 | *num_groups = sirfsoc_pmx_functions[selector].num_groups; | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, | |
215 | struct pinctrl_gpio_range *range, unsigned offset) | |
216 | { | |
217 | struct sirfsoc_pmx *spmx; | |
218 | ||
219 | int group = range->id; | |
220 | ||
221 | u32 muxval; | |
222 | ||
223 | spmx = pinctrl_dev_get_drvdata(pmxdev); | |
224 | ||
225 | if (!spmx->is_marco) { | |
c09f80db BS |
226 | muxval = readl(spmx->gpio_virtbase + |
227 | SIRFSOC_GPIO_PAD_EN(group)); | |
3370dc91 | 228 | muxval = muxval | (1 << (offset - range->pin_base)); |
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229 | writel(muxval, spmx->gpio_virtbase + |
230 | SIRFSOC_GPIO_PAD_EN(group)); | |
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231 | } else { |
232 | writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + | |
233 | SIRFSOC_GPIO_PAD_EN(group)); | |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static struct pinmux_ops sirfsoc_pinmux_ops = { | |
240 | .enable = sirfsoc_pinmux_enable, | |
3370dc91 BS |
241 | .get_functions_count = sirfsoc_pinmux_get_funcs_count, |
242 | .get_function_name = sirfsoc_pinmux_get_func_name, | |
243 | .get_function_groups = sirfsoc_pinmux_get_groups, | |
244 | .gpio_request_enable = sirfsoc_pinmux_request_gpio, | |
245 | }; | |
246 | ||
247 | static struct pinctrl_desc sirfsoc_pinmux_desc = { | |
248 | .name = DRIVER_NAME, | |
249 | .pctlops = &sirfsoc_pctrl_ops, | |
250 | .pmxops = &sirfsoc_pinmux_ops, | |
251 | .owner = THIS_MODULE, | |
252 | }; | |
253 | ||
3370dc91 BS |
254 | static void __iomem *sirfsoc_rsc_of_iomap(void) |
255 | { | |
256 | const struct of_device_id rsc_ids[] = { | |
257 | { .compatible = "sirf,prima2-rsc" }, | |
258 | { .compatible = "sirf,marco-rsc" }, | |
259 | {} | |
260 | }; | |
261 | struct device_node *np; | |
262 | ||
263 | np = of_find_matching_node(NULL, rsc_ids); | |
264 | if (!np) | |
265 | panic("unable to find compatible rsc node in dtb\n"); | |
266 | ||
267 | return of_iomap(np, 0); | |
268 | } | |
269 | ||
270 | static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc, | |
c5eb757c BS |
271 | const struct of_phandle_args *gpiospec, |
272 | u32 *flags) | |
3370dc91 | 273 | { |
c5eb757c | 274 | if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE) |
9c956909 | 275 | return -EINVAL; |
3370dc91 | 276 | |
c5eb757c | 277 | if (flags) |
9c956909 | 278 | *flags = gpiospec->args[1]; |
3370dc91 | 279 | |
c5eb757c | 280 | return gpiospec->args[0]; |
3370dc91 BS |
281 | } |
282 | ||
283 | static const struct of_device_id pinmux_ids[] = { | |
284 | { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, | |
285 | { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, | |
286 | { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, }, | |
287 | {} | |
288 | }; | |
289 | ||
290 | static int sirfsoc_pinmux_probe(struct platform_device *pdev) | |
291 | { | |
292 | int ret; | |
293 | struct sirfsoc_pmx *spmx; | |
294 | struct device_node *np = pdev->dev.of_node; | |
295 | const struct sirfsoc_pinctrl_data *pdata; | |
3370dc91 BS |
296 | |
297 | /* Create state holders etc for this driver */ | |
298 | spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL); | |
299 | if (!spmx) | |
300 | return -ENOMEM; | |
301 | ||
302 | spmx->dev = &pdev->dev; | |
303 | ||
304 | platform_set_drvdata(pdev, spmx); | |
305 | ||
306 | spmx->gpio_virtbase = of_iomap(np, 0); | |
307 | if (!spmx->gpio_virtbase) { | |
308 | dev_err(&pdev->dev, "can't map gpio registers\n"); | |
309 | return -ENOMEM; | |
310 | } | |
311 | ||
312 | spmx->rsc_virtbase = sirfsoc_rsc_of_iomap(); | |
313 | if (!spmx->rsc_virtbase) { | |
314 | ret = -ENOMEM; | |
315 | dev_err(&pdev->dev, "can't map rsc registers\n"); | |
316 | goto out_no_rsc_remap; | |
317 | } | |
318 | ||
319 | if (of_device_is_compatible(np, "sirf,marco-pinctrl")) | |
320 | spmx->is_marco = 1; | |
321 | ||
322 | pdata = of_match_node(pinmux_ids, np)->data; | |
323 | sirfsoc_pin_groups = pdata->grps; | |
324 | sirfsoc_pingrp_cnt = pdata->grps_cnt; | |
325 | sirfsoc_pmx_functions = pdata->funcs; | |
326 | sirfsoc_pmxfunc_cnt = pdata->funcs_cnt; | |
327 | sirfsoc_pinmux_desc.pins = pdata->pads; | |
328 | sirfsoc_pinmux_desc.npins = pdata->pads_cnt; | |
329 | ||
330 | ||
331 | /* Now register the pin controller and all pins it handles */ | |
332 | spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx); | |
333 | if (!spmx->pmx) { | |
334 | dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n"); | |
335 | ret = -EINVAL; | |
336 | goto out_no_pmx; | |
337 | } | |
338 | ||
3370dc91 BS |
339 | dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n"); |
340 | ||
341 | return 0; | |
342 | ||
343 | out_no_pmx: | |
344 | iounmap(spmx->rsc_virtbase); | |
345 | out_no_rsc_remap: | |
346 | iounmap(spmx->gpio_virtbase); | |
347 | return ret; | |
348 | } | |
349 | ||
bc8d25a4 BS |
350 | #ifdef CONFIG_PM_SLEEP |
351 | static int sirfsoc_pinmux_suspend_noirq(struct device *dev) | |
352 | { | |
353 | int i, j; | |
354 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
355 | ||
356 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
357 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
358 | spmx->gpio_regs[i][j] = readl(spmx->gpio_virtbase + | |
359 | SIRFSOC_GPIO_CTRL(i, j)); | |
360 | } | |
361 | spmx->ints_regs[i] = readl(spmx->gpio_virtbase + | |
362 | SIRFSOC_GPIO_INT_STATUS(i)); | |
363 | spmx->paden_regs[i] = readl(spmx->gpio_virtbase + | |
364 | SIRFSOC_GPIO_PAD_EN(i)); | |
365 | } | |
366 | spmx->dspen_regs = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
367 | ||
368 | for (i = 0; i < 3; i++) | |
369 | spmx->rsc_regs[i] = readl(spmx->rsc_virtbase + 4 * i); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | static int sirfsoc_pinmux_resume_noirq(struct device *dev) | |
375 | { | |
376 | int i, j; | |
377 | struct sirfsoc_pmx *spmx = dev_get_drvdata(dev); | |
378 | ||
379 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
380 | for (j = 0; j < SIRFSOC_GPIO_BANK_SIZE; j++) { | |
381 | writel(spmx->gpio_regs[i][j], spmx->gpio_virtbase + | |
382 | SIRFSOC_GPIO_CTRL(i, j)); | |
383 | } | |
384 | writel(spmx->ints_regs[i], spmx->gpio_virtbase + | |
385 | SIRFSOC_GPIO_INT_STATUS(i)); | |
386 | writel(spmx->paden_regs[i], spmx->gpio_virtbase + | |
387 | SIRFSOC_GPIO_PAD_EN(i)); | |
388 | } | |
389 | writel(spmx->dspen_regs, spmx->gpio_virtbase + SIRFSOC_GPIO_DSP_EN0); | |
390 | ||
391 | for (i = 0; i < 3; i++) | |
392 | writel(spmx->rsc_regs[i], spmx->rsc_virtbase + 4 * i); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static const struct dev_pm_ops sirfsoc_pinmux_pm_ops = { | |
398 | .suspend_noirq = sirfsoc_pinmux_suspend_noirq, | |
399 | .resume_noirq = sirfsoc_pinmux_resume_noirq, | |
f6b17885 BS |
400 | .freeze_noirq = sirfsoc_pinmux_suspend_noirq, |
401 | .restore_noirq = sirfsoc_pinmux_resume_noirq, | |
bc8d25a4 BS |
402 | }; |
403 | #endif | |
404 | ||
3370dc91 BS |
405 | static struct platform_driver sirfsoc_pinmux_driver = { |
406 | .driver = { | |
407 | .name = DRIVER_NAME, | |
408 | .owner = THIS_MODULE, | |
409 | .of_match_table = pinmux_ids, | |
bc8d25a4 BS |
410 | #ifdef CONFIG_PM_SLEEP |
411 | .pm = &sirfsoc_pinmux_pm_ops, | |
412 | #endif | |
3370dc91 BS |
413 | }, |
414 | .probe = sirfsoc_pinmux_probe, | |
415 | }; | |
416 | ||
417 | static int __init sirfsoc_pinmux_init(void) | |
418 | { | |
419 | return platform_driver_register(&sirfsoc_pinmux_driver); | |
420 | } | |
421 | arch_initcall(sirfsoc_pinmux_init); | |
422 | ||
294d1351 LW |
423 | static inline struct sirfsoc_gpio_chip *to_sirfsoc_gpio(struct gpio_chip *gc) |
424 | { | |
425 | return container_of(gc, struct sirfsoc_gpio_chip, chip.gc); | |
426 | } | |
427 | ||
428 | static inline struct sirfsoc_gpio_bank * | |
429 | sirfsoc_gpio_to_bank(struct sirfsoc_gpio_chip *sgpio, unsigned int offset) | |
3370dc91 | 430 | { |
294d1351 | 431 | return &sgpio->sgpio_bank[offset / SIRFSOC_GPIO_BANK_SIZE]; |
3370dc91 BS |
432 | } |
433 | ||
294d1351 | 434 | static inline int sirfsoc_gpio_to_bankoff(unsigned int offset) |
3370dc91 | 435 | { |
294d1351 | 436 | return offset % SIRFSOC_GPIO_BANK_SIZE; |
3370dc91 | 437 | } |
7420d2d0 | 438 | |
3370dc91 BS |
439 | static void sirfsoc_gpio_irq_ack(struct irq_data *d) |
440 | { | |
294d1351 LW |
441 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
442 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); | |
443 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); | |
444 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
445 | u32 val, offset; |
446 | unsigned long flags; | |
447 | ||
448 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
449 | ||
450 | spin_lock_irqsave(&sgpio_lock, flags); | |
451 | ||
294d1351 | 452 | val = readl(sgpio->chip.regs + offset); |
3370dc91 | 453 | |
294d1351 | 454 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
455 | |
456 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
457 | } | |
458 | ||
294d1351 LW |
459 | static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, |
460 | struct sirfsoc_gpio_bank *bank, | |
461 | int idx) | |
3370dc91 BS |
462 | { |
463 | u32 val, offset; | |
464 | unsigned long flags; | |
465 | ||
466 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
467 | ||
468 | spin_lock_irqsave(&sgpio_lock, flags); | |
469 | ||
294d1351 | 470 | val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
471 | val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; |
472 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; | |
294d1351 | 473 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
474 | |
475 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
476 | } | |
477 | ||
478 | static void sirfsoc_gpio_irq_mask(struct irq_data *d) | |
479 | { | |
294d1351 LW |
480 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
481 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); | |
482 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); | |
3370dc91 | 483 | |
294d1351 | 484 | __sirfsoc_gpio_irq_mask(sgpio, bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE); |
3370dc91 BS |
485 | } |
486 | ||
487 | static void sirfsoc_gpio_irq_unmask(struct irq_data *d) | |
488 | { | |
294d1351 LW |
489 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
490 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); | |
491 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); | |
492 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
493 | u32 val, offset; |
494 | unsigned long flags; | |
495 | ||
496 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
497 | ||
498 | spin_lock_irqsave(&sgpio_lock, flags); | |
499 | ||
294d1351 | 500 | val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
501 | val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; |
502 | val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
294d1351 | 503 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
504 | |
505 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
506 | } | |
507 | ||
508 | static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) | |
509 | { | |
294d1351 LW |
510 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
511 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); | |
512 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, d->hwirq); | |
513 | int idx = sirfsoc_gpio_to_bankoff(d->hwirq); | |
3370dc91 BS |
514 | u32 val, offset; |
515 | unsigned long flags; | |
516 | ||
517 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
518 | ||
519 | spin_lock_irqsave(&sgpio_lock, flags); | |
520 | ||
294d1351 | 521 | val = readl(sgpio->chip.regs + offset); |
b07ddcdc | 522 | val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); |
3370dc91 BS |
523 | |
524 | switch (type) { | |
525 | case IRQ_TYPE_NONE: | |
526 | break; | |
527 | case IRQ_TYPE_EDGE_RISING: | |
c09f80db BS |
528 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
529 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
530 | val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; |
531 | break; | |
532 | case IRQ_TYPE_EDGE_FALLING: | |
533 | val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
c09f80db BS |
534 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | |
535 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
536 | break; |
537 | case IRQ_TYPE_EDGE_BOTH: | |
c09f80db BS |
538 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
539 | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | | |
540 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; | |
3370dc91 BS |
541 | break; |
542 | case IRQ_TYPE_LEVEL_LOW: | |
c09f80db BS |
543 | val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | |
544 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
3370dc91 BS |
545 | val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; |
546 | break; | |
547 | case IRQ_TYPE_LEVEL_HIGH: | |
548 | val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; | |
c09f80db BS |
549 | val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | |
550 | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); | |
3370dc91 BS |
551 | break; |
552 | } | |
553 | ||
294d1351 | 554 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
555 | |
556 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
561 | static struct irq_chip sirfsoc_irq_chip = { | |
562 | .name = "sirf-gpio-irq", | |
563 | .irq_ack = sirfsoc_gpio_irq_ack, | |
564 | .irq_mask = sirfsoc_gpio_irq_mask, | |
565 | .irq_unmask = sirfsoc_gpio_irq_unmask, | |
566 | .irq_set_type = sirfsoc_gpio_irq_type, | |
567 | }; | |
568 | ||
569 | static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |
570 | { | |
294d1351 LW |
571 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
572 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); | |
7420d2d0 | 573 | struct sirfsoc_gpio_bank *bank; |
3370dc91 BS |
574 | u32 status, ctrl; |
575 | int idx = 0; | |
576 | struct irq_chip *chip = irq_get_chip(irq); | |
7420d2d0 LW |
577 | int i; |
578 | ||
648e42e1 | 579 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { |
29c7f1f5 | 580 | bank = &sgpio->sgpio_bank[i]; |
7420d2d0 LW |
581 | if (bank->parent_irq == irq) |
582 | break; | |
583 | } | |
648e42e1 | 584 | BUG_ON(i == SIRFSOC_GPIO_NO_OF_BANKS); |
3370dc91 BS |
585 | |
586 | chained_irq_enter(chip, desc); | |
587 | ||
294d1351 | 588 | status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); |
3370dc91 BS |
589 | if (!status) { |
590 | printk(KERN_WARNING | |
591 | "%s: gpio id %d status %#x no interrupt is flaged\n", | |
592 | __func__, bank->id, status); | |
593 | handle_bad_irq(irq, desc); | |
594 | return; | |
595 | } | |
596 | ||
597 | while (status) { | |
294d1351 | 598 | ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); |
3370dc91 BS |
599 | |
600 | /* | |
601 | * Here we must check whether the corresponding GPIO's interrupt | |
602 | * has been enabled, otherwise just skip it | |
603 | */ | |
604 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | |
605 | pr_debug("%s: gpio id %d idx %d happens\n", | |
606 | __func__, bank->id, idx); | |
294d1351 | 607 | generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + |
8daeffb0 | 608 | bank->id * SIRFSOC_GPIO_BANK_SIZE)); |
3370dc91 BS |
609 | } |
610 | ||
611 | idx++; | |
612 | status = status >> 1; | |
613 | } | |
614 | ||
615 | chained_irq_exit(chip, desc); | |
616 | } | |
617 | ||
294d1351 LW |
618 | static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_chip *sgpio, |
619 | unsigned ctrl_offset) | |
3370dc91 BS |
620 | { |
621 | u32 val; | |
622 | ||
294d1351 | 623 | val = readl(sgpio->chip.regs + ctrl_offset); |
3370dc91 | 624 | val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK; |
294d1351 | 625 | writel(val, sgpio->chip.regs + ctrl_offset); |
3370dc91 BS |
626 | } |
627 | ||
628 | static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) | |
629 | { | |
294d1351 LW |
630 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
631 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); | |
3370dc91 BS |
632 | unsigned long flags; |
633 | ||
634 | if (pinctrl_request_gpio(chip->base + offset)) | |
635 | return -ENODEV; | |
636 | ||
637 | spin_lock_irqsave(&bank->lock, flags); | |
638 | ||
639 | /* | |
640 | * default status: | |
641 | * set direction as input and mask irq | |
642 | */ | |
294d1351 LW |
643 | sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); |
644 | __sirfsoc_gpio_irq_mask(sgpio, bank, offset); | |
3370dc91 BS |
645 | |
646 | spin_unlock_irqrestore(&bank->lock, flags); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) | |
652 | { | |
294d1351 LW |
653 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
654 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); | |
3370dc91 BS |
655 | unsigned long flags; |
656 | ||
657 | spin_lock_irqsave(&bank->lock, flags); | |
658 | ||
294d1351 LW |
659 | __sirfsoc_gpio_irq_mask(sgpio, bank, offset); |
660 | sirfsoc_gpio_set_input(sgpio, SIRFSOC_GPIO_CTRL(bank->id, offset)); | |
3370dc91 BS |
661 | |
662 | spin_unlock_irqrestore(&bank->lock, flags); | |
663 | ||
664 | pinctrl_free_gpio(chip->base + offset); | |
665 | } | |
666 | ||
667 | static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |
668 | { | |
294d1351 LW |
669 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
670 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); | |
c5eb757c | 671 | int idx = sirfsoc_gpio_to_bankoff(gpio); |
3370dc91 BS |
672 | unsigned long flags; |
673 | unsigned offset; | |
674 | ||
675 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
676 | ||
677 | spin_lock_irqsave(&bank->lock, flags); | |
678 | ||
294d1351 | 679 | sirfsoc_gpio_set_input(sgpio, offset); |
3370dc91 BS |
680 | |
681 | spin_unlock_irqrestore(&bank->lock, flags); | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
294d1351 LW |
686 | static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio, |
687 | struct sirfsoc_gpio_bank *bank, | |
688 | unsigned offset, | |
689 | int value) | |
3370dc91 BS |
690 | { |
691 | u32 out_ctrl; | |
692 | unsigned long flags; | |
693 | ||
694 | spin_lock_irqsave(&bank->lock, flags); | |
695 | ||
294d1351 | 696 | out_ctrl = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
697 | if (value) |
698 | out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
699 | else | |
700 | out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
701 | ||
702 | out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; | |
703 | out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK; | |
294d1351 | 704 | writel(out_ctrl, sgpio->chip.regs + offset); |
3370dc91 BS |
705 | |
706 | spin_unlock_irqrestore(&bank->lock, flags); | |
707 | } | |
708 | ||
c09f80db BS |
709 | static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, |
710 | unsigned gpio, int value) | |
3370dc91 | 711 | { |
294d1351 LW |
712 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
713 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); | |
c5eb757c | 714 | int idx = sirfsoc_gpio_to_bankoff(gpio); |
3370dc91 BS |
715 | u32 offset; |
716 | unsigned long flags; | |
717 | ||
718 | offset = SIRFSOC_GPIO_CTRL(bank->id, idx); | |
719 | ||
720 | spin_lock_irqsave(&sgpio_lock, flags); | |
721 | ||
294d1351 | 722 | sirfsoc_gpio_set_output(sgpio, bank, offset, value); |
3370dc91 BS |
723 | |
724 | spin_unlock_irqrestore(&sgpio_lock, flags); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset) | |
730 | { | |
294d1351 LW |
731 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
732 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); | |
3370dc91 BS |
733 | u32 val; |
734 | unsigned long flags; | |
735 | ||
736 | spin_lock_irqsave(&bank->lock, flags); | |
737 | ||
294d1351 | 738 | val = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
739 | |
740 | spin_unlock_irqrestore(&bank->lock, flags); | |
741 | ||
742 | return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK); | |
743 | } | |
744 | ||
745 | static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset, | |
746 | int value) | |
747 | { | |
294d1351 LW |
748 | struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); |
749 | struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); | |
3370dc91 BS |
750 | u32 ctrl; |
751 | unsigned long flags; | |
752 | ||
753 | spin_lock_irqsave(&bank->lock, flags); | |
754 | ||
294d1351 | 755 | ctrl = readl(sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
756 | if (value) |
757 | ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
758 | else | |
759 | ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK; | |
294d1351 | 760 | writel(ctrl, sgpio->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset)); |
3370dc91 BS |
761 | |
762 | spin_unlock_irqrestore(&bank->lock, flags); | |
763 | } | |
764 | ||
294d1351 LW |
765 | static void sirfsoc_gpio_set_pullup(struct sirfsoc_gpio_chip *sgpio, |
766 | const u32 *pullups) | |
3370dc91 BS |
767 | { |
768 | int i, n; | |
769 | const unsigned long *p = (const unsigned long *)pullups; | |
770 | ||
771 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
772 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
773 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
294d1351 | 774 | u32 val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
775 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; |
776 | val |= SIRFSOC_GPIO_CTL_PULL_HIGH; | |
294d1351 | 777 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
778 | } |
779 | } | |
780 | } | |
781 | ||
294d1351 LW |
782 | static void sirfsoc_gpio_set_pulldown(struct sirfsoc_gpio_chip *sgpio, |
783 | const u32 *pulldowns) | |
3370dc91 BS |
784 | { |
785 | int i, n; | |
786 | const unsigned long *p = (const unsigned long *)pulldowns; | |
787 | ||
788 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { | |
789 | for_each_set_bit(n, p + i, BITS_PER_LONG) { | |
790 | u32 offset = SIRFSOC_GPIO_CTRL(i, n); | |
294d1351 | 791 | u32 val = readl(sgpio->chip.regs + offset); |
3370dc91 BS |
792 | val |= SIRFSOC_GPIO_CTL_PULL_MASK; |
793 | val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH; | |
294d1351 | 794 | writel(val, sgpio->chip.regs + offset); |
3370dc91 BS |
795 | } |
796 | } | |
797 | } | |
798 | ||
799 | static int sirfsoc_gpio_probe(struct device_node *np) | |
800 | { | |
801 | int i, err = 0; | |
294d1351 | 802 | static struct sirfsoc_gpio_chip *sgpio; |
3370dc91 | 803 | struct sirfsoc_gpio_bank *bank; |
2c9fdcf1 | 804 | void __iomem *regs; |
3370dc91 BS |
805 | struct platform_device *pdev; |
806 | bool is_marco = false; | |
807 | ||
808 | u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; | |
809 | ||
810 | pdev = of_find_device_by_node(np); | |
811 | if (!pdev) | |
812 | return -ENODEV; | |
813 | ||
294d1351 LW |
814 | sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); |
815 | if (!sgpio) | |
816 | return -ENOMEM; | |
817 | ||
3370dc91 BS |
818 | regs = of_iomap(np, 0); |
819 | if (!regs) | |
820 | return -ENOMEM; | |
821 | ||
822 | if (of_device_is_compatible(np, "sirf,marco-pinctrl")) | |
823 | is_marco = 1; | |
824 | ||
294d1351 LW |
825 | sgpio->chip.gc.request = sirfsoc_gpio_request; |
826 | sgpio->chip.gc.free = sirfsoc_gpio_free; | |
827 | sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; | |
828 | sgpio->chip.gc.get = sirfsoc_gpio_get_value; | |
829 | sgpio->chip.gc.direction_output = sirfsoc_gpio_direction_output; | |
830 | sgpio->chip.gc.set = sirfsoc_gpio_set_value; | |
831 | sgpio->chip.gc.base = 0; | |
832 | sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS; | |
833 | sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL); | |
834 | sgpio->chip.gc.of_node = np; | |
835 | sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; | |
836 | sgpio->chip.gc.of_gpio_n_cells = 2; | |
837 | sgpio->chip.gc.dev = &pdev->dev; | |
838 | sgpio->chip.regs = regs; | |
839 | sgpio->is_marco = is_marco; | |
840 | ||
841 | err = gpiochip_add(&sgpio->chip.gc); | |
c5eb757c | 842 | if (err) { |
7420d2d0 | 843 | dev_err(&pdev->dev, "%s: error in probe function with status %d\n", |
c5eb757c BS |
844 | np->full_name, err); |
845 | goto out; | |
846 | } | |
847 | ||
294d1351 | 848 | err = gpiochip_irqchip_add(&sgpio->chip.gc, |
7420d2d0 LW |
849 | &sirfsoc_irq_chip, |
850 | 0, handle_level_irq, | |
851 | IRQ_TYPE_NONE); | |
852 | if (err) { | |
853 | dev_err(&pdev->dev, | |
854 | "could not connect irqchip to gpiochip\n"); | |
855 | goto out; | |
856 | } | |
857 | ||
3370dc91 | 858 | for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { |
294d1351 | 859 | bank = &sgpio->sgpio_bank[i]; |
3370dc91 | 860 | spin_lock_init(&bank->lock); |
3370dc91 BS |
861 | bank->parent_irq = platform_get_irq(pdev, i); |
862 | if (bank->parent_irq < 0) { | |
863 | err = bank->parent_irq; | |
294d1351 | 864 | goto out_banks; |
3370dc91 BS |
865 | } |
866 | ||
294d1351 | 867 | gpiochip_set_chained_irqchip(&sgpio->chip.gc, |
7420d2d0 LW |
868 | &sirfsoc_irq_chip, |
869 | bank->parent_irq, | |
870 | sirfsoc_gpio_handle_irq); | |
3370dc91 BS |
871 | } |
872 | ||
294d1351 LW |
873 | err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev), |
874 | 0, 0, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS); | |
875 | if (err) { | |
876 | dev_err(&pdev->dev, | |
877 | "could not add gpiochip pin range\n"); | |
878 | goto out_no_range; | |
879 | } | |
880 | ||
3370dc91 BS |
881 | if (!of_property_read_u32_array(np, "sirf,pullups", pullups, |
882 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
294d1351 | 883 | sirfsoc_gpio_set_pullup(sgpio, pullups); |
3370dc91 BS |
884 | |
885 | if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns, | |
886 | SIRFSOC_GPIO_NO_OF_BANKS)) | |
294d1351 | 887 | sirfsoc_gpio_set_pulldown(sgpio, pulldowns); |
3370dc91 BS |
888 | |
889 | return 0; | |
890 | ||
294d1351 LW |
891 | out_no_range: |
892 | out_banks: | |
893 | if (gpiochip_remove(&sgpio->chip.gc)) | |
894 | dev_err(&pdev->dev, "could not remove gpio chip\n"); | |
3370dc91 BS |
895 | out: |
896 | iounmap(regs); | |
897 | return err; | |
898 | } | |
899 | ||
900 | static int __init sirfsoc_gpio_init(void) | |
901 | { | |
902 | ||
903 | struct device_node *np; | |
904 | ||
905 | np = of_find_matching_node(NULL, pinmux_ids); | |
906 | ||
907 | if (!np) | |
908 | return -ENODEV; | |
909 | ||
910 | return sirfsoc_gpio_probe(np); | |
911 | } | |
912 | subsys_initcall(sirfsoc_gpio_init); | |
913 | ||
4bee325c BS |
914 | MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>"); |
915 | MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>"); | |
916 | MODULE_AUTHOR("Barry Song <baohua.song@csr.com>"); | |
3370dc91 BS |
917 | MODULE_DESCRIPTION("SIRFSOC pin control driver"); |
918 | MODULE_LICENSE("GPL"); |