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aceb16dc MC |
1 | /* |
2 | * Copyright (C) Maxime Coquelin 2015 | |
3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | * | |
6 | * Heavily based on Mediatek's pinctrl driver | |
7 | */ | |
8 | #include <linux/clk.h> | |
1300568a | 9 | #include <linux/gpio/driver.h> |
aceb16dc MC |
10 | #include <linux/io.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/of_irq.h> | |
16 | #include <linux/pinctrl/consumer.h> | |
17 | #include <linux/pinctrl/machine.h> | |
18 | #include <linux/pinctrl/pinconf.h> | |
19 | #include <linux/pinctrl/pinconf-generic.h> | |
20 | #include <linux/pinctrl/pinctrl.h> | |
21 | #include <linux/pinctrl/pinmux.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/slab.h> | |
25 | ||
aceb16dc MC |
26 | #include "../core.h" |
27 | #include "../pinconf.h" | |
28 | #include "../pinctrl-utils.h" | |
29 | #include "pinctrl-stm32.h" | |
30 | ||
31 | #define STM32_GPIO_MODER 0x00 | |
32 | #define STM32_GPIO_TYPER 0x04 | |
33 | #define STM32_GPIO_SPEEDR 0x08 | |
34 | #define STM32_GPIO_PUPDR 0x0c | |
35 | #define STM32_GPIO_IDR 0x10 | |
36 | #define STM32_GPIO_ODR 0x14 | |
37 | #define STM32_GPIO_BSRR 0x18 | |
38 | #define STM32_GPIO_LCKR 0x1c | |
39 | #define STM32_GPIO_AFRL 0x20 | |
40 | #define STM32_GPIO_AFRH 0x24 | |
41 | ||
42 | #define STM32_GPIO_PINS_PER_BANK 16 | |
43 | ||
44 | #define gpio_range_to_bank(chip) \ | |
45 | container_of(chip, struct stm32_gpio_bank, range) | |
46 | ||
aceb16dc MC |
47 | static const char * const stm32_gpio_functions[] = { |
48 | "gpio", "af0", "af1", | |
49 | "af2", "af3", "af4", | |
50 | "af5", "af6", "af7", | |
51 | "af8", "af9", "af10", | |
52 | "af11", "af12", "af13", | |
53 | "af14", "af15", "analog", | |
54 | }; | |
55 | ||
56 | struct stm32_pinctrl_group { | |
57 | const char *name; | |
58 | unsigned long config; | |
59 | unsigned pin; | |
60 | }; | |
61 | ||
62 | struct stm32_gpio_bank { | |
63 | void __iomem *base; | |
64 | struct clk *clk; | |
65 | spinlock_t lock; | |
66 | struct gpio_chip gpio_chip; | |
67 | struct pinctrl_gpio_range range; | |
68 | }; | |
69 | ||
70 | struct stm32_pinctrl { | |
71 | struct device *dev; | |
72 | struct pinctrl_dev *pctl_dev; | |
73 | struct pinctrl_desc pctl_desc; | |
74 | struct stm32_pinctrl_group *groups; | |
75 | unsigned ngroups; | |
76 | const char **grp_names; | |
77 | struct stm32_gpio_bank *banks; | |
78 | unsigned nbanks; | |
79 | const struct stm32_pinctrl_match_data *match_data; | |
80 | }; | |
81 | ||
82 | static inline int stm32_gpio_pin(int gpio) | |
83 | { | |
84 | return gpio % STM32_GPIO_PINS_PER_BANK; | |
85 | } | |
86 | ||
87 | static inline u32 stm32_gpio_get_mode(u32 function) | |
88 | { | |
89 | switch (function) { | |
90 | case STM32_PIN_GPIO: | |
91 | return 0; | |
92 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
93 | return 2; | |
94 | case STM32_PIN_ANALOG: | |
95 | return 3; | |
96 | } | |
97 | ||
98 | return 0; | |
99 | } | |
100 | ||
101 | static inline u32 stm32_gpio_get_alt(u32 function) | |
102 | { | |
103 | switch (function) { | |
104 | case STM32_PIN_GPIO: | |
105 | return 0; | |
106 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
107 | return function - 1; | |
108 | case STM32_PIN_ANALOG: | |
109 | return 0; | |
110 | } | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | /* GPIO functions */ | |
116 | ||
117 | static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, | |
118 | unsigned offset, int value) | |
119 | { | |
120 | if (!value) | |
121 | offset += STM32_GPIO_PINS_PER_BANK; | |
122 | ||
123 | clk_enable(bank->clk); | |
124 | ||
125 | writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); | |
126 | ||
127 | clk_disable(bank->clk); | |
128 | } | |
129 | ||
130 | static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) | |
131 | { | |
132 | return pinctrl_request_gpio(chip->base + offset); | |
133 | } | |
134 | ||
135 | static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) | |
136 | { | |
137 | pinctrl_free_gpio(chip->base + offset); | |
138 | } | |
139 | ||
140 | static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) | |
141 | { | |
1300568a | 142 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
143 | int ret; |
144 | ||
145 | clk_enable(bank->clk); | |
146 | ||
147 | ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); | |
148 | ||
149 | clk_disable(bank->clk); | |
150 | ||
151 | return ret; | |
152 | } | |
153 | ||
154 | static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
155 | { | |
1300568a | 156 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
157 | |
158 | __stm32_gpio_set(bank, offset, value); | |
159 | } | |
160 | ||
161 | static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
162 | { | |
163 | return pinctrl_gpio_direction_input(chip->base + offset); | |
164 | } | |
165 | ||
166 | static int stm32_gpio_direction_output(struct gpio_chip *chip, | |
167 | unsigned offset, int value) | |
168 | { | |
1300568a | 169 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
170 | |
171 | __stm32_gpio_set(bank, offset, value); | |
172 | pinctrl_gpio_direction_output(chip->base + offset); | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | static struct gpio_chip stm32_gpio_template = { | |
178 | .request = stm32_gpio_request, | |
179 | .free = stm32_gpio_free, | |
180 | .get = stm32_gpio_get, | |
181 | .set = stm32_gpio_set, | |
182 | .direction_input = stm32_gpio_direction_input, | |
183 | .direction_output = stm32_gpio_direction_output, | |
184 | }; | |
185 | ||
186 | /* Pinctrl functions */ | |
187 | ||
188 | static struct stm32_pinctrl_group * | |
189 | stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) | |
190 | { | |
191 | int i; | |
192 | ||
193 | for (i = 0; i < pctl->ngroups; i++) { | |
194 | struct stm32_pinctrl_group *grp = pctl->groups + i; | |
195 | ||
196 | if (grp->pin == pin) | |
197 | return grp; | |
198 | } | |
199 | ||
200 | return NULL; | |
201 | } | |
202 | ||
203 | static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, | |
204 | u32 pin_num, u32 fnum) | |
205 | { | |
206 | int i; | |
207 | ||
208 | for (i = 0; i < pctl->match_data->npins; i++) { | |
209 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
210 | const struct stm32_desc_function *func = pin->functions; | |
211 | ||
212 | if (pin->pin.number != pin_num) | |
213 | continue; | |
214 | ||
215 | while (func && func->name) { | |
216 | if (func->num == fnum) | |
217 | return true; | |
218 | func++; | |
219 | } | |
220 | ||
221 | break; | |
222 | } | |
223 | ||
224 | return false; | |
225 | } | |
226 | ||
227 | static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, | |
228 | u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, | |
229 | struct pinctrl_map **map, unsigned *reserved_maps, | |
230 | unsigned *num_maps) | |
231 | { | |
232 | if (*num_maps == *reserved_maps) | |
233 | return -ENOSPC; | |
234 | ||
235 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
236 | (*map)[*num_maps].data.mux.group = grp->name; | |
237 | ||
238 | if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { | |
239 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", | |
240 | fnum, pin); | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
244 | (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; | |
245 | (*num_maps)++; | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
250 | static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
251 | struct device_node *node, | |
252 | struct pinctrl_map **map, | |
253 | unsigned *reserved_maps, | |
254 | unsigned *num_maps) | |
255 | { | |
256 | struct stm32_pinctrl *pctl; | |
257 | struct stm32_pinctrl_group *grp; | |
258 | struct property *pins; | |
259 | u32 pinfunc, pin, func; | |
260 | unsigned long *configs; | |
261 | unsigned int num_configs; | |
262 | bool has_config = 0; | |
263 | unsigned reserve = 0; | |
264 | int num_pins, num_funcs, maps_per_pin, i, err; | |
265 | ||
266 | pctl = pinctrl_dev_get_drvdata(pctldev); | |
267 | ||
268 | pins = of_find_property(node, "pinmux", NULL); | |
269 | if (!pins) { | |
270 | dev_err(pctl->dev, "missing pins property in node %s .\n", | |
271 | node->name); | |
272 | return -EINVAL; | |
273 | } | |
274 | ||
275 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, | |
276 | &num_configs); | |
277 | if (err) | |
278 | return err; | |
279 | ||
280 | if (num_configs) | |
281 | has_config = 1; | |
282 | ||
283 | num_pins = pins->length / sizeof(u32); | |
284 | num_funcs = num_pins; | |
285 | maps_per_pin = 0; | |
286 | if (num_funcs) | |
287 | maps_per_pin++; | |
288 | if (has_config && num_pins >= 1) | |
289 | maps_per_pin++; | |
290 | ||
291 | if (!num_pins || !maps_per_pin) | |
292 | return -EINVAL; | |
293 | ||
294 | reserve = num_pins * maps_per_pin; | |
295 | ||
296 | err = pinctrl_utils_reserve_map(pctldev, map, | |
297 | reserved_maps, num_maps, reserve); | |
298 | if (err) | |
299 | return err; | |
300 | ||
301 | for (i = 0; i < num_pins; i++) { | |
302 | err = of_property_read_u32_index(node, "pinmux", | |
303 | i, &pinfunc); | |
304 | if (err) | |
305 | return err; | |
306 | ||
307 | pin = STM32_GET_PIN_NO(pinfunc); | |
308 | func = STM32_GET_PIN_FUNC(pinfunc); | |
309 | ||
310 | if (pin >= pctl->match_data->npins) { | |
311 | dev_err(pctl->dev, "invalid pin number.\n"); | |
312 | return -EINVAL; | |
313 | } | |
314 | ||
315 | if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { | |
316 | dev_err(pctl->dev, "invalid function.\n"); | |
317 | return -EINVAL; | |
318 | } | |
319 | ||
320 | grp = stm32_pctrl_find_group_by_pin(pctl, pin); | |
321 | if (!grp) { | |
322 | dev_err(pctl->dev, "unable to match pin %d to group\n", | |
323 | pin); | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, | |
328 | reserved_maps, num_maps); | |
329 | if (err) | |
330 | return err; | |
331 | ||
332 | if (has_config) { | |
333 | err = pinctrl_utils_add_map_configs(pctldev, map, | |
334 | reserved_maps, num_maps, grp->name, | |
335 | configs, num_configs, | |
336 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
337 | if (err) | |
338 | return err; | |
339 | } | |
340 | } | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
346 | struct device_node *np_config, | |
347 | struct pinctrl_map **map, unsigned *num_maps) | |
348 | { | |
349 | struct device_node *np; | |
350 | unsigned reserved_maps; | |
351 | int ret; | |
352 | ||
353 | *map = NULL; | |
354 | *num_maps = 0; | |
355 | reserved_maps = 0; | |
356 | ||
357 | for_each_child_of_node(np_config, np) { | |
358 | ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, | |
359 | &reserved_maps, num_maps); | |
360 | if (ret < 0) { | |
d32f7fd3 | 361 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
aceb16dc MC |
362 | return ret; |
363 | } | |
364 | } | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
369 | static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
370 | { | |
371 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
372 | ||
373 | return pctl->ngroups; | |
374 | } | |
375 | ||
376 | static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
377 | unsigned group) | |
378 | { | |
379 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
380 | ||
381 | return pctl->groups[group].name; | |
382 | } | |
383 | ||
384 | static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
385 | unsigned group, | |
386 | const unsigned **pins, | |
387 | unsigned *num_pins) | |
388 | { | |
389 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
390 | ||
391 | *pins = (unsigned *)&pctl->groups[group].pin; | |
392 | *num_pins = 1; | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | static const struct pinctrl_ops stm32_pctrl_ops = { | |
398 | .dt_node_to_map = stm32_pctrl_dt_node_to_map, | |
d32f7fd3 | 399 | .dt_free_map = pinctrl_utils_free_map, |
aceb16dc MC |
400 | .get_groups_count = stm32_pctrl_get_groups_count, |
401 | .get_group_name = stm32_pctrl_get_group_name, | |
402 | .get_group_pins = stm32_pctrl_get_group_pins, | |
403 | }; | |
404 | ||
405 | ||
406 | /* Pinmux functions */ | |
407 | ||
408 | static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
409 | { | |
410 | return ARRAY_SIZE(stm32_gpio_functions); | |
411 | } | |
412 | ||
413 | static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
414 | unsigned selector) | |
415 | { | |
416 | return stm32_gpio_functions[selector]; | |
417 | } | |
418 | ||
419 | static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
420 | unsigned function, | |
421 | const char * const **groups, | |
422 | unsigned * const num_groups) | |
423 | { | |
424 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
425 | ||
426 | *groups = pctl->grp_names; | |
427 | *num_groups = pctl->ngroups; | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, | |
433 | int pin, u32 mode, u32 alt) | |
434 | { | |
435 | u32 val; | |
436 | int alt_shift = (pin % 8) * 4; | |
437 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
438 | unsigned long flags; | |
439 | ||
440 | clk_enable(bank->clk); | |
441 | spin_lock_irqsave(&bank->lock, flags); | |
442 | ||
443 | val = readl_relaxed(bank->base + alt_offset); | |
444 | val &= ~GENMASK(alt_shift + 3, alt_shift); | |
445 | val |= (alt << alt_shift); | |
446 | writel_relaxed(val, bank->base + alt_offset); | |
447 | ||
448 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
449 | val &= ~GENMASK(pin * 2 + 1, pin * 2); | |
450 | val |= mode << (pin * 2); | |
451 | writel_relaxed(val, bank->base + STM32_GPIO_MODER); | |
452 | ||
453 | spin_unlock_irqrestore(&bank->lock, flags); | |
454 | clk_disable(bank->clk); | |
455 | } | |
456 | ||
3beed93c PC |
457 | static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, |
458 | int pin, u32 *mode, u32 *alt) | |
459 | { | |
460 | u32 val; | |
461 | int alt_shift = (pin % 8) * 4; | |
462 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
463 | unsigned long flags; | |
464 | ||
465 | clk_enable(bank->clk); | |
466 | spin_lock_irqsave(&bank->lock, flags); | |
467 | ||
468 | val = readl_relaxed(bank->base + alt_offset); | |
469 | val &= GENMASK(alt_shift + 3, alt_shift); | |
470 | *alt = val >> alt_shift; | |
471 | ||
472 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
473 | val &= GENMASK(pin * 2 + 1, pin * 2); | |
474 | *mode = val >> (pin * 2); | |
475 | ||
476 | spin_unlock_irqrestore(&bank->lock, flags); | |
477 | clk_disable(bank->clk); | |
478 | } | |
479 | ||
aceb16dc MC |
480 | static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, |
481 | unsigned function, | |
482 | unsigned group) | |
483 | { | |
484 | bool ret; | |
485 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
486 | struct stm32_pinctrl_group *g = pctl->groups + group; | |
487 | struct pinctrl_gpio_range *range; | |
488 | struct stm32_gpio_bank *bank; | |
489 | u32 mode, alt; | |
490 | int pin; | |
491 | ||
492 | ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); | |
493 | if (!ret) { | |
494 | dev_err(pctl->dev, "invalid function %d on group %d .\n", | |
495 | function, group); | |
496 | return -EINVAL; | |
497 | } | |
498 | ||
499 | range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); | |
500 | bank = gpio_range_to_bank(range); | |
501 | pin = stm32_gpio_pin(g->pin); | |
502 | ||
503 | mode = stm32_gpio_get_mode(function); | |
504 | alt = stm32_gpio_get_alt(function); | |
505 | ||
506 | stm32_pmx_set_mode(bank, pin, mode, alt); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
512 | struct pinctrl_gpio_range *range, unsigned gpio, | |
513 | bool input) | |
514 | { | |
515 | struct stm32_gpio_bank *bank = gpio_range_to_bank(range); | |
516 | int pin = stm32_gpio_pin(gpio); | |
517 | ||
518 | stm32_pmx_set_mode(bank, pin, !input, 0); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | ||
523 | static const struct pinmux_ops stm32_pmx_ops = { | |
524 | .get_functions_count = stm32_pmx_get_funcs_cnt, | |
525 | .get_function_name = stm32_pmx_get_func_name, | |
526 | .get_function_groups = stm32_pmx_get_func_groups, | |
527 | .set_mux = stm32_pmx_set_mux, | |
528 | .gpio_set_direction = stm32_pmx_gpio_set_direction, | |
529 | }; | |
530 | ||
531 | /* Pinconf functions */ | |
532 | ||
533 | static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, | |
534 | unsigned offset, u32 drive) | |
535 | { | |
536 | unsigned long flags; | |
537 | u32 val; | |
538 | ||
539 | clk_enable(bank->clk); | |
540 | spin_lock_irqsave(&bank->lock, flags); | |
541 | ||
542 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
543 | val &= ~BIT(offset); | |
544 | val |= drive << offset; | |
545 | writel_relaxed(val, bank->base + STM32_GPIO_TYPER); | |
546 | ||
547 | spin_unlock_irqrestore(&bank->lock, flags); | |
548 | clk_disable(bank->clk); | |
549 | } | |
550 | ||
3beed93c PC |
551 | static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, |
552 | unsigned int offset) | |
553 | { | |
554 | unsigned long flags; | |
555 | u32 val; | |
556 | ||
557 | clk_enable(bank->clk); | |
558 | spin_lock_irqsave(&bank->lock, flags); | |
559 | ||
560 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
561 | val &= BIT(offset); | |
562 | ||
563 | spin_unlock_irqrestore(&bank->lock, flags); | |
564 | clk_disable(bank->clk); | |
565 | ||
566 | return (val >> offset); | |
567 | } | |
568 | ||
aceb16dc MC |
569 | static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, |
570 | unsigned offset, u32 speed) | |
571 | { | |
572 | unsigned long flags; | |
573 | u32 val; | |
574 | ||
575 | clk_enable(bank->clk); | |
576 | spin_lock_irqsave(&bank->lock, flags); | |
577 | ||
578 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
579 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
580 | val |= speed << (offset * 2); | |
581 | writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); | |
582 | ||
583 | spin_unlock_irqrestore(&bank->lock, flags); | |
584 | clk_disable(bank->clk); | |
585 | } | |
586 | ||
3beed93c PC |
587 | static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, |
588 | unsigned int offset) | |
589 | { | |
590 | unsigned long flags; | |
591 | u32 val; | |
592 | ||
593 | clk_enable(bank->clk); | |
594 | spin_lock_irqsave(&bank->lock, flags); | |
595 | ||
596 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
597 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
598 | ||
599 | spin_unlock_irqrestore(&bank->lock, flags); | |
600 | clk_disable(bank->clk); | |
601 | ||
602 | return (val >> (offset * 2)); | |
603 | } | |
604 | ||
aceb16dc MC |
605 | static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, |
606 | unsigned offset, u32 bias) | |
607 | { | |
608 | unsigned long flags; | |
609 | u32 val; | |
610 | ||
611 | clk_enable(bank->clk); | |
612 | spin_lock_irqsave(&bank->lock, flags); | |
613 | ||
614 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
615 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
616 | val |= bias << (offset * 2); | |
617 | writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); | |
618 | ||
619 | spin_unlock_irqrestore(&bank->lock, flags); | |
620 | clk_disable(bank->clk); | |
621 | } | |
622 | ||
3beed93c PC |
623 | static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, |
624 | unsigned int offset) | |
625 | { | |
626 | unsigned long flags; | |
627 | u32 val; | |
628 | ||
629 | clk_enable(bank->clk); | |
630 | spin_lock_irqsave(&bank->lock, flags); | |
631 | ||
632 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
633 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
634 | ||
635 | spin_unlock_irqrestore(&bank->lock, flags); | |
636 | clk_disable(bank->clk); | |
637 | ||
638 | return (val >> (offset * 2)); | |
639 | } | |
640 | ||
4fac724f PC |
641 | static bool stm32_pconf_get(struct stm32_gpio_bank *bank, |
642 | unsigned int offset, bool dir) | |
3beed93c PC |
643 | { |
644 | unsigned long flags; | |
645 | u32 val; | |
646 | ||
647 | clk_enable(bank->clk); | |
648 | spin_lock_irqsave(&bank->lock, flags); | |
649 | ||
4fac724f PC |
650 | if (dir) |
651 | val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & | |
652 | BIT(offset)); | |
653 | else | |
654 | val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & | |
655 | BIT(offset)); | |
3beed93c PC |
656 | |
657 | spin_unlock_irqrestore(&bank->lock, flags); | |
658 | clk_disable(bank->clk); | |
659 | ||
660 | return val; | |
661 | } | |
662 | ||
aceb16dc MC |
663 | static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, |
664 | unsigned int pin, enum pin_config_param param, | |
665 | enum pin_config_param arg) | |
666 | { | |
667 | struct pinctrl_gpio_range *range; | |
668 | struct stm32_gpio_bank *bank; | |
669 | int offset, ret = 0; | |
670 | ||
671 | range = pinctrl_find_gpio_range_from_pin(pctldev, pin); | |
672 | bank = gpio_range_to_bank(range); | |
673 | offset = stm32_gpio_pin(pin); | |
674 | ||
675 | switch (param) { | |
676 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
677 | stm32_pconf_set_driving(bank, offset, 0); | |
678 | break; | |
679 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
680 | stm32_pconf_set_driving(bank, offset, 1); | |
681 | break; | |
682 | case PIN_CONFIG_SLEW_RATE: | |
683 | stm32_pconf_set_speed(bank, offset, arg); | |
684 | break; | |
685 | case PIN_CONFIG_BIAS_DISABLE: | |
686 | stm32_pconf_set_bias(bank, offset, 0); | |
687 | break; | |
688 | case PIN_CONFIG_BIAS_PULL_UP: | |
689 | stm32_pconf_set_bias(bank, offset, 1); | |
690 | break; | |
691 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
692 | stm32_pconf_set_bias(bank, offset, 2); | |
693 | break; | |
694 | case PIN_CONFIG_OUTPUT: | |
695 | __stm32_gpio_set(bank, offset, arg); | |
696 | ret = stm32_pmx_gpio_set_direction(pctldev, NULL, pin, false); | |
697 | break; | |
698 | default: | |
699 | ret = -EINVAL; | |
700 | } | |
701 | ||
702 | return ret; | |
703 | } | |
704 | ||
705 | static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, | |
706 | unsigned group, | |
707 | unsigned long *config) | |
708 | { | |
709 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
710 | ||
711 | *config = pctl->groups[group].config; | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, | |
717 | unsigned long *configs, unsigned num_configs) | |
718 | { | |
719 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
720 | struct stm32_pinctrl_group *g = &pctl->groups[group]; | |
721 | int i, ret; | |
722 | ||
723 | for (i = 0; i < num_configs; i++) { | |
724 | ret = stm32_pconf_parse_conf(pctldev, g->pin, | |
725 | pinconf_to_config_param(configs[i]), | |
726 | pinconf_to_config_argument(configs[i])); | |
727 | if (ret < 0) | |
728 | return ret; | |
729 | ||
730 | g->config = configs[i]; | |
731 | } | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
3beed93c PC |
736 | static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, |
737 | struct seq_file *s, | |
738 | unsigned int pin) | |
739 | { | |
740 | struct pinctrl_gpio_range *range; | |
741 | struct stm32_gpio_bank *bank; | |
742 | int offset; | |
743 | u32 mode, alt, drive, speed, bias; | |
744 | static const char * const modes[] = { | |
745 | "input", "output", "alternate", "analog" }; | |
746 | static const char * const speeds[] = { | |
747 | "low", "medium", "high", "very high" }; | |
748 | static const char * const biasing[] = { | |
749 | "floating", "pull up", "pull down", "" }; | |
750 | bool val; | |
751 | ||
752 | range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); | |
753 | bank = gpio_range_to_bank(range); | |
754 | offset = stm32_gpio_pin(pin); | |
755 | ||
756 | stm32_pmx_get_mode(bank, offset, &mode, &alt); | |
757 | bias = stm32_pconf_get_bias(bank, offset); | |
758 | ||
759 | seq_printf(s, "%s ", modes[mode]); | |
760 | ||
761 | switch (mode) { | |
762 | /* input */ | |
763 | case 0: | |
4fac724f | 764 | val = stm32_pconf_get(bank, offset, true); |
3beed93c PC |
765 | seq_printf(s, "- %s - %s", |
766 | val ? "high" : "low", | |
767 | biasing[bias]); | |
768 | break; | |
769 | ||
770 | /* output */ | |
771 | case 1: | |
772 | drive = stm32_pconf_get_driving(bank, offset); | |
773 | speed = stm32_pconf_get_speed(bank, offset); | |
4fac724f | 774 | val = stm32_pconf_get(bank, offset, false); |
3beed93c PC |
775 | seq_printf(s, "- %s - %s - %s - %s %s", |
776 | val ? "high" : "low", | |
777 | drive ? "open drain" : "push pull", | |
778 | biasing[bias], | |
779 | speeds[speed], "speed"); | |
780 | break; | |
781 | ||
782 | /* alternate */ | |
783 | case 2: | |
784 | drive = stm32_pconf_get_driving(bank, offset); | |
785 | speed = stm32_pconf_get_speed(bank, offset); | |
a37571a2 | 786 | seq_printf(s, "%d - %s - %s - %s %s", alt, |
3beed93c PC |
787 | drive ? "open drain" : "push pull", |
788 | biasing[bias], | |
789 | speeds[speed], "speed"); | |
790 | break; | |
791 | ||
792 | /* analog */ | |
793 | case 3: | |
794 | break; | |
795 | } | |
796 | } | |
797 | ||
798 | ||
aceb16dc MC |
799 | static const struct pinconf_ops stm32_pconf_ops = { |
800 | .pin_config_group_get = stm32_pconf_group_get, | |
801 | .pin_config_group_set = stm32_pconf_group_set, | |
3beed93c | 802 | .pin_config_dbg_show = stm32_pconf_dbg_show, |
aceb16dc MC |
803 | }; |
804 | ||
805 | static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, | |
806 | struct device_node *np) | |
807 | { | |
808 | int bank_nr = pctl->nbanks; | |
809 | struct stm32_gpio_bank *bank = &pctl->banks[bank_nr]; | |
810 | struct pinctrl_gpio_range *range = &bank->range; | |
811 | struct device *dev = pctl->dev; | |
812 | struct resource res; | |
813 | struct reset_control *rstc; | |
814 | int err, npins; | |
815 | ||
816 | rstc = of_reset_control_get(np, NULL); | |
817 | if (!IS_ERR(rstc)) | |
818 | reset_control_deassert(rstc); | |
819 | ||
820 | if (of_address_to_resource(np, 0, &res)) | |
821 | return -ENODEV; | |
822 | ||
823 | bank->base = devm_ioremap_resource(dev, &res); | |
824 | if (IS_ERR(bank->base)) | |
825 | return PTR_ERR(bank->base); | |
826 | ||
827 | bank->clk = of_clk_get_by_name(np, NULL); | |
828 | if (IS_ERR(bank->clk)) { | |
829 | dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); | |
830 | return PTR_ERR(bank->clk); | |
831 | } | |
832 | ||
833 | err = clk_prepare(bank->clk); | |
834 | if (err) { | |
835 | dev_err(dev, "failed to prepare clk (%d)\n", err); | |
836 | return err; | |
837 | } | |
838 | ||
839 | npins = pctl->match_data->npins; | |
840 | npins -= bank_nr * STM32_GPIO_PINS_PER_BANK; | |
841 | if (npins < 0) | |
842 | return -EINVAL; | |
843 | else if (npins > STM32_GPIO_PINS_PER_BANK) | |
844 | npins = STM32_GPIO_PINS_PER_BANK; | |
845 | ||
846 | bank->gpio_chip = stm32_gpio_template; | |
847 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; | |
848 | bank->gpio_chip.ngpio = npins; | |
849 | bank->gpio_chip.of_node = np; | |
1300568a | 850 | bank->gpio_chip.parent = dev; |
aceb16dc MC |
851 | spin_lock_init(&bank->lock); |
852 | ||
853 | of_property_read_string(np, "st,bank-name", &range->name); | |
854 | bank->gpio_chip.label = range->name; | |
855 | ||
856 | range->id = bank_nr; | |
857 | range->pin_base = range->base = range->id * STM32_GPIO_PINS_PER_BANK; | |
858 | range->npins = bank->gpio_chip.ngpio; | |
859 | range->gc = &bank->gpio_chip; | |
1300568a | 860 | err = gpiochip_add_data(&bank->gpio_chip, bank); |
aceb16dc MC |
861 | if (err) { |
862 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); | |
863 | return err; | |
864 | } | |
865 | ||
866 | dev_info(dev, "%s bank added\n", range->name); | |
867 | return 0; | |
868 | } | |
869 | ||
870 | static int stm32_pctrl_build_state(struct platform_device *pdev) | |
871 | { | |
872 | struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); | |
873 | int i; | |
874 | ||
875 | pctl->ngroups = pctl->match_data->npins; | |
876 | ||
877 | /* Allocate groups */ | |
878 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
879 | sizeof(*pctl->groups), GFP_KERNEL); | |
880 | if (!pctl->groups) | |
881 | return -ENOMEM; | |
882 | ||
883 | /* We assume that one pin is one group, use pin name as group name. */ | |
884 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
885 | sizeof(*pctl->grp_names), GFP_KERNEL); | |
886 | if (!pctl->grp_names) | |
887 | return -ENOMEM; | |
888 | ||
889 | for (i = 0; i < pctl->match_data->npins; i++) { | |
890 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
891 | struct stm32_pinctrl_group *group = pctl->groups + i; | |
892 | ||
893 | group->name = pin->pin.name; | |
894 | group->pin = pin->pin.number; | |
895 | ||
896 | pctl->grp_names[i] = pin->pin.name; | |
897 | } | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
902 | int stm32_pctl_probe(struct platform_device *pdev) | |
903 | { | |
904 | struct device_node *np = pdev->dev.of_node; | |
905 | struct device_node *child; | |
906 | const struct of_device_id *match; | |
907 | struct device *dev = &pdev->dev; | |
908 | struct stm32_pinctrl *pctl; | |
909 | struct pinctrl_pin_desc *pins; | |
910 | int i, ret, banks = 0; | |
911 | ||
912 | if (!np) | |
913 | return -EINVAL; | |
914 | ||
915 | match = of_match_device(dev->driver->of_match_table, dev); | |
916 | if (!match || !match->data) | |
917 | return -EINVAL; | |
918 | ||
919 | if (!of_find_property(np, "pins-are-numbered", NULL)) { | |
920 | dev_err(dev, "only support pins-are-numbered format\n"); | |
921 | return -EINVAL; | |
922 | } | |
923 | ||
924 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
925 | if (!pctl) | |
926 | return -ENOMEM; | |
927 | ||
928 | platform_set_drvdata(pdev, pctl); | |
929 | ||
930 | pctl->dev = dev; | |
931 | pctl->match_data = match->data; | |
932 | ret = stm32_pctrl_build_state(pdev); | |
933 | if (ret) { | |
934 | dev_err(dev, "build state failed: %d\n", ret); | |
935 | return -EINVAL; | |
936 | } | |
937 | ||
938 | for_each_child_of_node(np, child) | |
939 | if (of_property_read_bool(child, "gpio-controller")) | |
940 | banks++; | |
941 | ||
942 | if (!banks) { | |
943 | dev_err(dev, "at least one GPIO bank is required\n"); | |
944 | return -EINVAL; | |
945 | } | |
946 | ||
947 | pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), | |
948 | GFP_KERNEL); | |
949 | if (!pctl->banks) | |
950 | return -ENOMEM; | |
951 | ||
952 | for_each_child_of_node(np, child) { | |
953 | if (of_property_read_bool(child, "gpio-controller")) { | |
954 | ret = stm32_gpiolib_register_bank(pctl, child); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | pctl->nbanks++; | |
959 | } | |
960 | } | |
961 | ||
962 | pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), | |
963 | GFP_KERNEL); | |
964 | if (!pins) | |
965 | return -ENOMEM; | |
966 | ||
967 | for (i = 0; i < pctl->match_data->npins; i++) | |
968 | pins[i] = pctl->match_data->pins[i].pin; | |
969 | ||
970 | pctl->pctl_desc.name = dev_name(&pdev->dev); | |
971 | pctl->pctl_desc.owner = THIS_MODULE; | |
972 | pctl->pctl_desc.pins = pins; | |
973 | pctl->pctl_desc.npins = pctl->match_data->npins; | |
974 | pctl->pctl_desc.confops = &stm32_pconf_ops; | |
975 | pctl->pctl_desc.pctlops = &stm32_pctrl_ops; | |
976 | pctl->pctl_desc.pmxops = &stm32_pmx_ops; | |
977 | pctl->dev = &pdev->dev; | |
978 | ||
88edad04 LD |
979 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, |
980 | pctl); | |
981 | if (IS_ERR(pctl->pctl_dev)) { | |
aceb16dc | 982 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
88edad04 | 983 | return PTR_ERR(pctl->pctl_dev); |
aceb16dc MC |
984 | } |
985 | ||
986 | for (i = 0; i < pctl->nbanks; i++) | |
987 | pinctrl_add_gpio_range(pctl->pctl_dev, &pctl->banks[i].range); | |
988 | ||
989 | dev_info(dev, "Pinctrl STM32 initialized\n"); | |
990 | ||
991 | return 0; | |
992 | } | |
993 |