pwm: i.MX: add functions to enable/disable pwm.
[deliverable/linux.git] / drivers / pwm / pwm-imx.c
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1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
5a0e3ad6 14#include <linux/slab.h>
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15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/pwm.h>
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19#include <mach/hardware.h>
20
21
22/* i.MX1 and i.MX21 share the same PWM function block: */
23
24#define MX1_PWMC 0x00 /* PWM Control Register */
25#define MX1_PWMS 0x04 /* PWM Sample Register */
26#define MX1_PWMP 0x08 /* PWM Period Register */
27
66ad6a61 28#define MX1_PWMC_EN (1 << 4)
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29
30/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
31
32#define MX3_PWMCR 0x00 /* PWM Control Register */
33#define MX3_PWMSAR 0x0C /* PWM Sample Register */
34#define MX3_PWMPR 0x10 /* PWM Period Register */
35#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
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36#define MX3_PWMCR_DOZEEN (1 << 24)
37#define MX3_PWMCR_WAITEN (1 << 23)
38#define MX3_PWMCR_DBGEN (1 << 22)
c010dba8 39#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
a058cbc1 40#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
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41#define MX3_PWMCR_EN (1 << 0)
42
29693248 43struct imx_chip {
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44 struct clk *clk;
45
140827c1 46 int enabled;
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47 void __iomem *mmio_base;
48
29693248 49 struct pwm_chip chip;
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50
51 int (*config)(struct pwm_chip *chip,
52 struct pwm_device *pwm, int duty_ns, int period_ns);
66ad6a61 53 void (*set_enable)(struct pwm_chip *chip, bool enable);
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54};
55
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56#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
57
19e73333 58static int imx_pwm_config_v1(struct pwm_chip *chip,
29693248 59 struct pwm_device *pwm, int duty_ns, int period_ns)
166091b1 60{
29693248 61 struct imx_chip *imx = to_imx_chip(chip);
166091b1 62
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63 /*
64 * The PWM subsystem allows for exact frequencies. However,
65 * I cannot connect a scope on my device to the PWM line and
66 * thus cannot provide the program the PWM controller
67 * exactly. Instead, I'm relying on the fact that the
68 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
69 * function group already. So I'll just modify the PWM sample
70 * register to follow the ratio of duty_ns vs. period_ns
71 * accordingly.
72 *
73 * This is good enough for programming the brightness of
74 * the LCD backlight.
75 *
76 * The real implementation would divide PERCLK[0] first by
77 * both the prescaler (/1 .. /128) and then by CLKSEL
78 * (/2 .. /16).
79 */
80 u32 max = readl(imx->mmio_base + MX1_PWMP);
81 u32 p = max * duty_ns / period_ns;
82 writel(max - p, imx->mmio_base + MX1_PWMS);
83
84 return 0;
85}
86
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87static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
88{
89 struct imx_chip *imx = to_imx_chip(chip);
90 u32 val;
91
92 val = readl(imx->mmio_base + MX1_PWMC);
93
94 if (enable)
95 val |= MX1_PWMC_EN;
96 else
97 val &= ~MX1_PWMC_EN;
98
99 writel(val, imx->mmio_base + MX1_PWMC);
100}
101
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102static int imx_pwm_config_v2(struct pwm_chip *chip,
103 struct pwm_device *pwm, int duty_ns, int period_ns)
104{
105 struct imx_chip *imx = to_imx_chip(chip);
106 unsigned long long c;
107 unsigned long period_cycles, duty_cycles, prescale;
108 u32 cr;
109
110 c = clk_get_rate(imx->clk);
111 c = c * period_ns;
112 do_div(c, 1000000000);
113 period_cycles = c;
114
115 prescale = period_cycles / 0x10000 + 1;
116
117 period_cycles /= prescale;
118 c = (unsigned long long)period_cycles * duty_ns;
119 do_div(c, period_ns);
120 duty_cycles = c;
121
122 /*
123 * according to imx pwm RM, the real period value should be
124 * PERIOD value in PWMPR plus 2.
125 */
126 if (period_cycles > 2)
127 period_cycles -= 2;
128 else
129 period_cycles = 0;
130
131 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
132 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
133
134 cr = MX3_PWMCR_PRESCALER(prescale) |
135 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
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136 MX3_PWMCR_DBGEN;
137
138 if (imx->enabled)
139 cr |= MX3_PWMCR_EN;
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140
141 if (cpu_is_mx25())
142 cr |= MX3_PWMCR_CLKSRC_IPG;
143 else
144 cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
145
146 writel(cr, imx->mmio_base + MX3_PWMCR);
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147
148 return 0;
149}
166091b1 150
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151static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
152{
153 struct imx_chip *imx = to_imx_chip(chip);
154 u32 val;
155
156 val = readl(imx->mmio_base + MX3_PWMCR);
157
158 if (enable)
159 val |= MX3_PWMCR_EN;
160 else
161 val &= ~MX3_PWMCR_EN;
162
163 writel(val, imx->mmio_base + MX3_PWMCR);
164}
165
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166static int imx_pwm_config(struct pwm_chip *chip,
167 struct pwm_device *pwm, int duty_ns, int period_ns)
168{
169 struct imx_chip *imx = to_imx_chip(chip);
170
171 return imx->config(chip, pwm, duty_ns, period_ns);
172}
173
29693248 174static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
166091b1 175{
29693248 176 struct imx_chip *imx = to_imx_chip(chip);
140827c1 177 int ret;
166091b1 178
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179 ret = clk_prepare_enable(imx->clk);
180 if (ret)
181 return ret;
182
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183 imx->set_enable(chip, true);
184
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185 imx->enabled = 1;
186
187 return 0;
166091b1 188}
166091b1 189
29693248 190static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
166091b1 191{
29693248 192 struct imx_chip *imx = to_imx_chip(chip);
166091b1 193
66ad6a61 194 imx->set_enable(chip, false);
166091b1 195
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196 clk_disable_unprepare(imx->clk);
197 imx->enabled = 0;
166091b1 198}
166091b1 199
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200static struct pwm_ops imx_pwm_ops = {
201 .enable = imx_pwm_enable,
202 .disable = imx_pwm_disable,
203 .config = imx_pwm_config,
204 .owner = THIS_MODULE,
205};
166091b1 206
29693248 207static int __devinit imx_pwm_probe(struct platform_device *pdev)
166091b1 208{
29693248 209 struct imx_chip *imx;
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210 struct resource *r;
211 int ret = 0;
212
a9970e3b 213 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
29693248 214 if (imx == NULL) {
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215 dev_err(&pdev->dev, "failed to allocate memory\n");
216 return -ENOMEM;
217 }
218
a9970e3b 219 imx->clk = devm_clk_get(&pdev->dev, "pwm");
166091b1 220
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221 if (IS_ERR(imx->clk))
222 return PTR_ERR(imx->clk);
166091b1 223
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224 imx->chip.ops = &imx_pwm_ops;
225 imx->chip.dev = &pdev->dev;
226 imx->chip.base = -1;
227 imx->chip.npwm = 1;
166091b1 228
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229 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
230 if (r == NULL) {
231 dev_err(&pdev->dev, "no memory resource defined\n");
a9970e3b 232 return -ENODEV;
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233 }
234
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235 imx->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
236 if (imx->mmio_base == NULL)
237 return -EADDRNOTAVAIL;
166091b1 238
66ad6a61 239 if (cpu_is_mx1() || cpu_is_mx21()) {
19e73333 240 imx->config = imx_pwm_config_v1;
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241 imx->set_enable = imx_pwm_set_enable_v1;
242 } else {
19e73333 243 imx->config = imx_pwm_config_v2;
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244 imx->set_enable = imx_pwm_set_enable_v2;
245 }
19e73333 246
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247 ret = pwmchip_add(&imx->chip);
248 if (ret < 0)
a9970e3b 249 return ret;
166091b1 250
29693248 251 platform_set_drvdata(pdev, imx);
166091b1 252 return 0;
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253}
254
29693248 255static int __devexit imx_pwm_remove(struct platform_device *pdev)
166091b1 256{
29693248 257 struct imx_chip *imx;
166091b1 258
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259 imx = platform_get_drvdata(pdev);
260 if (imx == NULL)
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261 return -ENODEV;
262
a9970e3b 263 return pwmchip_remove(&imx->chip);
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264}
265
29693248 266static struct platform_driver imx_pwm_driver = {
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267 .driver = {
268 .name = "mxc_pwm",
269 },
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270 .probe = imx_pwm_probe,
271 .remove = __devexit_p(imx_pwm_remove),
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272};
273
29693248 274static int __init imx_pwm_init(void)
166091b1 275{
29693248 276 return platform_driver_register(&imx_pwm_driver);
166091b1 277}
29693248 278arch_initcall(imx_pwm_init);
166091b1 279
29693248 280static void __exit imx_pwm_exit(void)
166091b1 281{
29693248 282 platform_driver_unregister(&imx_pwm_driver);
166091b1 283}
29693248 284module_exit(imx_pwm_exit);
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285
286MODULE_LICENSE("GPL v2");
287MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
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