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2132fa8d APS |
1 | /* |
2 | * Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; version 2. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/clk.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/of_address.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pwm.h> | |
19 | #include <linux/slab.h> | |
20 | ||
21 | struct lpc32xx_pwm_chip { | |
22 | struct pwm_chip chip; | |
23 | struct clk *clk; | |
24 | void __iomem *base; | |
25 | }; | |
26 | ||
5a9fc9c6 | 27 | #define PWM_ENABLE BIT(31) |
acfd92fd | 28 | #define PWM_PIN_LEVEL BIT(30) |
2132fa8d APS |
29 | |
30 | #define to_lpc32xx_pwm_chip(_chip) \ | |
31 | container_of(_chip, struct lpc32xx_pwm_chip, chip) | |
32 | ||
33 | static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
34 | int duty_ns, int period_ns) | |
35 | { | |
36 | struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); | |
37 | unsigned long long c; | |
38 | int period_cycles, duty_cycles; | |
affb923d | 39 | u32 val; |
5a9fc9c6 | 40 | c = clk_get_rate(lpc32xx->clk); |
2132fa8d | 41 | |
5a9fc9c6 VZ |
42 | /* The highest acceptable divisor is 256, which is represented by 0 */ |
43 | period_cycles = div64_u64(c * period_ns, | |
44 | (unsigned long long)NSEC_PER_SEC * 256); | |
d6dbdf0d VZ |
45 | if (!period_cycles || period_cycles > 256) |
46 | return -ERANGE; | |
47 | if (period_cycles == 256) | |
5a9fc9c6 | 48 | period_cycles = 0; |
2132fa8d | 49 | |
5a9fc9c6 VZ |
50 | /* Compute 256 x #duty/period value and care for corner cases */ |
51 | duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256, | |
52 | period_ns); | |
53 | if (!duty_cycles) | |
54 | duty_cycles = 1; | |
55 | if (duty_cycles > 255) | |
56 | duty_cycles = 255; | |
2132fa8d | 57 | |
affb923d AL |
58 | val = readl(lpc32xx->base + (pwm->hwpwm << 2)); |
59 | val &= ~0xFFFF; | |
5a9fc9c6 | 60 | val |= (period_cycles << 8) | duty_cycles; |
affb923d | 61 | writel(val, lpc32xx->base + (pwm->hwpwm << 2)); |
2132fa8d APS |
62 | |
63 | return 0; | |
64 | } | |
65 | ||
66 | static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
67 | { | |
68 | struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); | |
08ee77b5 AL |
69 | u32 val; |
70 | int ret; | |
71 | ||
82aff048 | 72 | ret = clk_prepare_enable(lpc32xx->clk); |
08ee77b5 AL |
73 | if (ret) |
74 | return ret; | |
75 | ||
76 | val = readl(lpc32xx->base + (pwm->hwpwm << 2)); | |
77 | val |= PWM_ENABLE; | |
78 | writel(val, lpc32xx->base + (pwm->hwpwm << 2)); | |
2132fa8d | 79 | |
08ee77b5 | 80 | return 0; |
2132fa8d APS |
81 | } |
82 | ||
83 | static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
84 | { | |
85 | struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); | |
08ee77b5 AL |
86 | u32 val; |
87 | ||
88 | val = readl(lpc32xx->base + (pwm->hwpwm << 2)); | |
89 | val &= ~PWM_ENABLE; | |
90 | writel(val, lpc32xx->base + (pwm->hwpwm << 2)); | |
2132fa8d | 91 | |
82aff048 | 92 | clk_disable_unprepare(lpc32xx->clk); |
2132fa8d APS |
93 | } |
94 | ||
95 | static const struct pwm_ops lpc32xx_pwm_ops = { | |
96 | .config = lpc32xx_pwm_config, | |
97 | .enable = lpc32xx_pwm_enable, | |
98 | .disable = lpc32xx_pwm_disable, | |
99 | .owner = THIS_MODULE, | |
100 | }; | |
101 | ||
102 | static int lpc32xx_pwm_probe(struct platform_device *pdev) | |
103 | { | |
104 | struct lpc32xx_pwm_chip *lpc32xx; | |
105 | struct resource *res; | |
106 | int ret; | |
acfd92fd | 107 | u32 val; |
2132fa8d APS |
108 | |
109 | lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL); | |
110 | if (!lpc32xx) | |
111 | return -ENOMEM; | |
112 | ||
113 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6d4294d1 TR |
114 | lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); |
115 | if (IS_ERR(lpc32xx->base)) | |
116 | return PTR_ERR(lpc32xx->base); | |
2132fa8d APS |
117 | |
118 | lpc32xx->clk = devm_clk_get(&pdev->dev, NULL); | |
119 | if (IS_ERR(lpc32xx->clk)) | |
120 | return PTR_ERR(lpc32xx->clk); | |
121 | ||
122 | lpc32xx->chip.dev = &pdev->dev; | |
123 | lpc32xx->chip.ops = &lpc32xx_pwm_ops; | |
ebe1fca3 | 124 | lpc32xx->chip.npwm = 1; |
8fc6d09d | 125 | lpc32xx->chip.base = -1; |
2132fa8d APS |
126 | |
127 | ret = pwmchip_add(&lpc32xx->chip); | |
128 | if (ret < 0) { | |
129 | dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret); | |
130 | return ret; | |
131 | } | |
132 | ||
acfd92fd SL |
133 | /* When PWM is disable, configure the output to the default value */ |
134 | val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); | |
135 | val &= ~PWM_PIN_LEVEL; | |
136 | writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); | |
137 | ||
2132fa8d APS |
138 | platform_set_drvdata(pdev, lpc32xx); |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
77f37917 | 143 | static int lpc32xx_pwm_remove(struct platform_device *pdev) |
2132fa8d APS |
144 | { |
145 | struct lpc32xx_pwm_chip *lpc32xx = platform_get_drvdata(pdev); | |
54b2a999 AB |
146 | unsigned int i; |
147 | ||
148 | for (i = 0; i < lpc32xx->chip.npwm; i++) | |
149 | pwm_disable(&lpc32xx->chip.pwms[i]); | |
2132fa8d | 150 | |
2132fa8d APS |
151 | return pwmchip_remove(&lpc32xx->chip); |
152 | } | |
153 | ||
f1a8870a | 154 | static const struct of_device_id lpc32xx_pwm_dt_ids[] = { |
2132fa8d APS |
155 | { .compatible = "nxp,lpc3220-pwm", }, |
156 | { /* sentinel */ } | |
157 | }; | |
158 | MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids); | |
159 | ||
160 | static struct platform_driver lpc32xx_pwm_driver = { | |
161 | .driver = { | |
162 | .name = "lpc32xx-pwm", | |
3cb3b2bf | 163 | .of_match_table = lpc32xx_pwm_dt_ids, |
2132fa8d APS |
164 | }, |
165 | .probe = lpc32xx_pwm_probe, | |
fd109112 | 166 | .remove = lpc32xx_pwm_remove, |
2132fa8d APS |
167 | }; |
168 | module_platform_driver(lpc32xx_pwm_driver); | |
169 | ||
170 | MODULE_ALIAS("platform:lpc32xx-pwm"); | |
171 | MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>"); | |
172 | MODULE_DESCRIPTION("LPC32XX PWM Driver"); | |
173 | MODULE_LICENSE("GPL v2"); |