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d16a5aa9 MW |
1 | /* |
2 | * Intel Low Power Subsystem PWM controller driver | |
3 | * | |
4 | * Copyright (C) 2014, Intel Corporation | |
5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
6 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> | |
7 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> | |
8 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> | |
093e00bb | 9 | * Author: Alan Cox <alan@linux.intel.com> |
d16a5aa9 MW |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
37670676 | 16 | #include <linux/delay.h> |
e0c86a3b | 17 | #include <linux/io.h> |
d16a5aa9 MW |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
f080be27 | 20 | #include <linux/pm_runtime.h> |
883e4d07 | 21 | #include <linux/time.h> |
093e00bb | 22 | |
c558e39e | 23 | #include "pwm-lpss.h" |
d16a5aa9 MW |
24 | |
25 | #define PWM 0x00000000 | |
26 | #define PWM_ENABLE BIT(31) | |
27 | #define PWM_SW_UPDATE BIT(30) | |
28 | #define PWM_BASE_UNIT_SHIFT 8 | |
d16a5aa9 MW |
29 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
30 | #define PWM_DIVISION_CORRECTION 0x2 | |
d16a5aa9 | 31 | |
4e11f5ac MW |
32 | /* Size of each PWM register space if multiple */ |
33 | #define PWM_SIZE 0x400 | |
34 | ||
d16a5aa9 MW |
35 | struct pwm_lpss_chip { |
36 | struct pwm_chip chip; | |
37 | void __iomem *regs; | |
883e4d07 | 38 | const struct pwm_lpss_boardinfo *info; |
093e00bb AC |
39 | }; |
40 | ||
093e00bb | 41 | /* BayTrail */ |
c558e39e | 42 | const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { |
4e11f5ac MW |
43 | .clk_rate = 25000000, |
44 | .npwm = 1, | |
883e4d07 | 45 | .base_unit_bits = 16, |
d16a5aa9 | 46 | }; |
c558e39e | 47 | EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); |
d16a5aa9 | 48 | |
373c5782 | 49 | /* Braswell */ |
c558e39e | 50 | const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { |
4e11f5ac MW |
51 | .clk_rate = 19200000, |
52 | .npwm = 1, | |
883e4d07 | 53 | .base_unit_bits = 16, |
373c5782 | 54 | }; |
c558e39e | 55 | EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); |
373c5782 | 56 | |
87219cb4 MW |
57 | /* Broxton */ |
58 | const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { | |
59 | .clk_rate = 19200000, | |
60 | .npwm = 4, | |
883e4d07 | 61 | .base_unit_bits = 22, |
87219cb4 MW |
62 | }; |
63 | EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info); | |
64 | ||
d16a5aa9 MW |
65 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
66 | { | |
67 | return container_of(chip, struct pwm_lpss_chip, chip); | |
68 | } | |
69 | ||
4e11f5ac MW |
70 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
71 | { | |
72 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
73 | ||
74 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
75 | } | |
76 | ||
77 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) | |
78 | { | |
79 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); | |
80 | ||
81 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); | |
82 | } | |
83 | ||
37670676 MW |
84 | static void pwm_lpss_update(struct pwm_device *pwm) |
85 | { | |
86 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE); | |
87 | /* Give it some time to propagate */ | |
88 | usleep_range(10, 50); | |
89 | } | |
90 | ||
d16a5aa9 MW |
91 | static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
92 | int duty_ns, int period_ns) | |
93 | { | |
94 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); | |
95 | u8 on_time_div; | |
883e4d07 | 96 | unsigned long c, base_unit_range; |
97 | unsigned long long base_unit, freq = NSEC_PER_SEC; | |
d16a5aa9 MW |
98 | u32 ctrl; |
99 | ||
100 | do_div(freq, period_ns); | |
101 | ||
883e4d07 | 102 | /* |
103 | * The equation is: | |
104 | * base_unit = ((freq / c) * base_unit_range) + correction | |
105 | */ | |
106 | base_unit_range = BIT(lpwm->info->base_unit_bits); | |
107 | base_unit = freq * base_unit_range; | |
d16a5aa9 | 108 | |
883e4d07 | 109 | c = lpwm->info->clk_rate; |
d16a5aa9 MW |
110 | if (!c) |
111 | return -EINVAL; | |
112 | ||
113 | do_div(base_unit, c); | |
114 | base_unit += PWM_DIVISION_CORRECTION; | |
d16a5aa9 MW |
115 | |
116 | if (duty_ns <= 0) | |
117 | duty_ns = 1; | |
118 | on_time_div = 255 - (255 * duty_ns / period_ns); | |
119 | ||
f080be27 QZ |
120 | pm_runtime_get_sync(chip->dev); |
121 | ||
4e11f5ac | 122 | ctrl = pwm_lpss_read(pwm); |
883e4d07 | 123 | ctrl &= ~PWM_ON_TIME_DIV_MASK; |
124 | ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); | |
125 | base_unit &= (base_unit_range - 1); | |
126 | ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; | |
d16a5aa9 | 127 | ctrl |= on_time_div; |
4e11f5ac | 128 | pwm_lpss_write(pwm, ctrl); |
d16a5aa9 | 129 | |
37670676 MW |
130 | /* |
131 | * If the PWM is already enabled we need to notify the hardware | |
132 | * about the change by setting PWM_SW_UPDATE. | |
133 | */ | |
134 | if (pwm_is_enabled(pwm)) | |
135 | pwm_lpss_update(pwm); | |
136 | ||
f080be27 QZ |
137 | pm_runtime_put(chip->dev); |
138 | ||
d16a5aa9 MW |
139 | return 0; |
140 | } | |
141 | ||
142 | static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
143 | { | |
f080be27 | 144 | pm_runtime_get_sync(chip->dev); |
37670676 MW |
145 | |
146 | /* | |
147 | * Hardware must first see PWM_SW_UPDATE before the PWM can be | |
148 | * enabled. | |
149 | */ | |
150 | pwm_lpss_update(pwm); | |
4e11f5ac | 151 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); |
d16a5aa9 MW |
152 | return 0; |
153 | } | |
154 | ||
155 | static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
156 | { | |
4e11f5ac | 157 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); |
f080be27 | 158 | pm_runtime_put(chip->dev); |
d16a5aa9 MW |
159 | } |
160 | ||
161 | static const struct pwm_ops pwm_lpss_ops = { | |
162 | .config = pwm_lpss_config, | |
163 | .enable = pwm_lpss_enable, | |
164 | .disable = pwm_lpss_disable, | |
165 | .owner = THIS_MODULE, | |
166 | }; | |
167 | ||
c558e39e AS |
168 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
169 | const struct pwm_lpss_boardinfo *info) | |
d16a5aa9 MW |
170 | { |
171 | struct pwm_lpss_chip *lpwm; | |
d16a5aa9 MW |
172 | int ret; |
173 | ||
093e00bb | 174 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
d16a5aa9 | 175 | if (!lpwm) |
093e00bb | 176 | return ERR_PTR(-ENOMEM); |
d16a5aa9 | 177 | |
093e00bb | 178 | lpwm->regs = devm_ioremap_resource(dev, r); |
d16a5aa9 | 179 | if (IS_ERR(lpwm->regs)) |
89c0339e | 180 | return ERR_CAST(lpwm->regs); |
093e00bb | 181 | |
883e4d07 | 182 | lpwm->info = info; |
093e00bb | 183 | lpwm->chip.dev = dev; |
d16a5aa9 MW |
184 | lpwm->chip.ops = &pwm_lpss_ops; |
185 | lpwm->chip.base = -1; | |
4e11f5ac | 186 | lpwm->chip.npwm = info->npwm; |
d16a5aa9 MW |
187 | |
188 | ret = pwmchip_add(&lpwm->chip); | |
189 | if (ret) { | |
093e00bb AC |
190 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
191 | return ERR_PTR(ret); | |
d16a5aa9 MW |
192 | } |
193 | ||
093e00bb | 194 | return lpwm; |
d16a5aa9 | 195 | } |
c558e39e | 196 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
d16a5aa9 | 197 | |
c558e39e | 198 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
d16a5aa9 | 199 | { |
d16a5aa9 MW |
200 | return pwmchip_remove(&lpwm->chip); |
201 | } | |
c558e39e | 202 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
d16a5aa9 MW |
203 | |
204 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); | |
205 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
206 | MODULE_LICENSE("GPL v2"); |