[deliverable/linux.git] / drivers / pwm / pwm-lpss.c

/*
 * Intel Low Power Subsystem PWM controller driver
 *
 * Copyright (C) 2014, Intel Corporation
 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
 * Author: Alan Cox <alan@linux.intel.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>

#include "pwm-lpss.h"

#define PWM				0x00000000
#define PWM_ENABLE			BIT(31)
#define PWM_SW_UPDATE			BIT(30)
#define PWM_BASE_UNIT_SHIFT		8
#define PWM_BASE_UNIT_MASK		0x00ffff00
#define PWM_ON_TIME_DIV_MASK		0x000000ff
#define PWM_DIVISION_CORRECTION		0x2
#define PWM_LIMIT			(0x8000 + PWM_DIVISION_CORRECTION)
#define NSECS_PER_SEC			1000000000UL

struct pwm_lpss_chip {
	struct pwm_chip chip;
	void __iomem *regs;
	unsigned long clk_rate;
};

/* BayTrail */
const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
	25000000
};
EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);

/* Braswell */
const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
	19200000
};
EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);

static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
{
	return container_of(chip, struct pwm_lpss_chip, chip);
}

static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
			   int duty_ns, int period_ns)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u8 on_time_div;
	unsigned long c;
	unsigned long long base_unit, freq = NSECS_PER_SEC;
	u32 ctrl;

	do_div(freq, period_ns);

	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	base_unit = freq * 65536;

	c = lpwm->clk_rate;
	if (!c)
		return -EINVAL;

	do_div(base_unit, c);
	base_unit += PWM_DIVISION_CORRECTION;
	if (base_unit > PWM_LIMIT)
		return -EINVAL;

	if (duty_ns <= 0)
		duty_ns = 1;
	on_time_div = 255 - (255 * duty_ns / period_ns);

	ctrl = readl(lpwm->regs + PWM);
	ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
	ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	ctrl |= on_time_div;
	/* request PWM to update on next cycle */
	ctrl |= PWM_SW_UPDATE;
	writel(ctrl, lpwm->regs + PWM);

	return 0;
}

static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);

	return 0;
}

static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
}

static const struct pwm_ops pwm_lpss_ops = {
	.config = pwm_lpss_config,
	.enable = pwm_lpss_enable,
	.disable = pwm_lpss_disable,
	.owner = THIS_MODULE,
};

struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
				     const struct pwm_lpss_boardinfo *info)
{
	struct pwm_lpss_chip *lpwm;
	int ret;

	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
	if (!lpwm)
		return ERR_PTR(-ENOMEM);

	lpwm->regs = devm_ioremap_resource(dev, r);
	if (IS_ERR(lpwm->regs))
		return ERR_CAST(lpwm->regs);

	lpwm->clk_rate = info->clk_rate;
	lpwm->chip.dev = dev;
	lpwm->chip.ops = &pwm_lpss_ops;
	lpwm->chip.base = -1;
	lpwm->chip.npwm = 1;

	ret = pwmchip_add(&lpwm->chip);
	if (ret) {
		dev_err(dev, "failed to add PWM chip: %d\n", ret);
		return ERR_PTR(ret);
	}

	return lpwm;
}
EXPORT_SYMBOL_GPL(pwm_lpss_probe);

int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
{
	u32 ctrl;

	ctrl = readl(lpwm->regs + PWM);
	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);

	return pwmchip_remove(&lpwm->chip);
}
EXPORT_SYMBOL_GPL(pwm_lpss_remove);

MODULE_DESCRIPTION("PWM driver for Intel LPSS");
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d16a5aa9 MW	1	/*
	2	* Intel Low Power Subsystem PWM controller driver
	3	*
	4	* Copyright (C) 2014, Intel Corporation
	5	* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
	6	* Author: Chew Kean Ho <kean.ho.chew@intel.com>
	7	* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
	8	* Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
093e00bb	9	* Author: Alan Cox <alan@linux.intel.com>
d16a5aa9 MW	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
d16a5aa9 MW	16	#include <linux/kernel.h>
d16a5aa9 MW	17	#include <linux/module.h>
093e00bb	18
c558e39e	19	#include "pwm-lpss.h"
d16a5aa9 MW	20
	21	#define PWM 0x00000000
	22	#define PWM_ENABLE BIT(31)
	23	#define PWM_SW_UPDATE BIT(30)
	24	#define PWM_BASE_UNIT_SHIFT 8
	25	#define PWM_BASE_UNIT_MASK 0x00ffff00
	26	#define PWM_ON_TIME_DIV_MASK 0x000000ff
	27	#define PWM_DIVISION_CORRECTION 0x2
	28	#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
	29	#define NSECS_PER_SEC 1000000000UL
	30
	31	struct pwm_lpss_chip {
	32	struct pwm_chip chip;
	33	void __iomem *regs;
093e00bb AC	34	unsigned long clk_rate;
	35	};
	36
093e00bb	37	/* BayTrail */
c558e39e	38	const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
093e00bb	39	25000000
d16a5aa9	40	};
c558e39e	41	EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
d16a5aa9	42
373c5782	43	/* Braswell */
c558e39e	44	const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
373c5782 AC	45	19200000
373c5782 AC	46	};
c558e39e	47	EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
373c5782	48
d16a5aa9 MW	49	static inline struct pwm_lpss_chip to_lpwm(struct pwm_chip chip)
	50	{
	51	return container_of(chip, struct pwm_lpss_chip, chip);
	52	}
	53
	54	static int pwm_lpss_config(struct pwm_chip chip, struct pwm_device pwm,
	55	int duty_ns, int period_ns)
	56	{
	57	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	58	u8 on_time_div;
	59	unsigned long c;
	60	unsigned long long base_unit, freq = NSECS_PER_SEC;
	61	u32 ctrl;
	62
	63	do_div(freq, period_ns);
	64
	65	/* The equation is: base_unit = ((freq / c) * 65536) + correction */
	66	base_unit = freq * 65536;
	67
093e00bb	68	c = lpwm->clk_rate;
d16a5aa9 MW	69	if (!c)
	70	return -EINVAL;
	71
	72	do_div(base_unit, c);
	73	base_unit += PWM_DIVISION_CORRECTION;
	74	if (base_unit > PWM_LIMIT)
	75	return -EINVAL;
	76
	77	if (duty_ns <= 0)
	78	duty_ns = 1;
	79	on_time_div = 255 - (255 * duty_ns / period_ns);
	80
	81	ctrl = readl(lpwm->regs + PWM);
	82	ctrl &= ~(PWM_BASE_UNIT_MASK \| PWM_ON_TIME_DIV_MASK);
	83	ctrl \|= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
	84	ctrl \|= on_time_div;
	85	/* request PWM to update on next cycle */
	86	ctrl \|= PWM_SW_UPDATE;
	87	writel(ctrl, lpwm->regs + PWM);
	88
	89	return 0;
	90	}
	91
	92	static int pwm_lpss_enable(struct pwm_chip chip, struct pwm_device pwm)
	93	{
	94	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	95	u32 ctrl;
d16a5aa9 MW	96
	97	ctrl = readl(lpwm->regs + PWM);
	98	writel(ctrl \| PWM_ENABLE, lpwm->regs + PWM);
	99
	100	return 0;
	101	}
	102
	103	static void pwm_lpss_disable(struct pwm_chip chip, struct pwm_device pwm)
	104	{
	105	struct pwm_lpss_chip *lpwm = to_lpwm(chip);
	106	u32 ctrl;
	107
	108	ctrl = readl(lpwm->regs + PWM);
	109	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
d16a5aa9 MW	110	}
	111
	112	static const struct pwm_ops pwm_lpss_ops = {
	113	.config = pwm_lpss_config,
	114	.enable = pwm_lpss_enable,
	115	.disable = pwm_lpss_disable,
	116	.owner = THIS_MODULE,
	117	};
	118
c558e39e AS	119	struct pwm_lpss_chip pwm_lpss_probe(struct device dev, struct resource *r,
c558e39e AS	120	const struct pwm_lpss_boardinfo *info)
d16a5aa9 MW	121	{
d16a5aa9 MW	122	struct pwm_lpss_chip *lpwm;
d16a5aa9 MW	123	int ret;
d16a5aa9 MW	124
093e00bb	125	lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
d16a5aa9	126	if (!lpwm)
093e00bb	127	return ERR_PTR(-ENOMEM);
d16a5aa9	128
093e00bb	129	lpwm->regs = devm_ioremap_resource(dev, r);
d16a5aa9	130	if (IS_ERR(lpwm->regs))
89c0339e	131	return ERR_CAST(lpwm->regs);
093e00bb	132
65accd87	133	lpwm->clk_rate = info->clk_rate;
093e00bb	134	lpwm->chip.dev = dev;
d16a5aa9 MW	135	lpwm->chip.ops = &pwm_lpss_ops;
	136	lpwm->chip.base = -1;
	137	lpwm->chip.npwm = 1;
	138
	139	ret = pwmchip_add(&lpwm->chip);
	140	if (ret) {
093e00bb AC	141	dev_err(dev, "failed to add PWM chip: %d\n", ret);
093e00bb AC	142	return ERR_PTR(ret);
d16a5aa9 MW	143	}
d16a5aa9 MW	144
093e00bb	145	return lpwm;
d16a5aa9	146	}
c558e39e	147	EXPORT_SYMBOL_GPL(pwm_lpss_probe);
d16a5aa9	148
c558e39e	149	int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
d16a5aa9	150	{
d16a5aa9 MW	151	u32 ctrl;
	152
	153	ctrl = readl(lpwm->regs + PWM);
	154	writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
	155
	156	return pwmchip_remove(&lpwm->chip);
	157	}
c558e39e	158	EXPORT_SYMBOL_GPL(pwm_lpss_remove);
d16a5aa9 MW	159
	160	MODULE_DESCRIPTION("PWM driver for Intel LPSS");
	161	MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	162	MODULE_LICENSE("GPL v2");