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regulator: ab8500-ext: Remove enable() and disable() functions
[deliverable/linux.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
7ce4669c 49 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 50 * @update_bank: bank to control on/off
c789ca20 51 * @update_reg: register to control on/off
bd28a157
EV		 52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
47c16975 61 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
a0a7014c 64 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 65 */
66struct ab8500_regulator_info {
67 struct device *dev;
68 struct regulator_desc desc;
c789ca20 69 struct regulator_dev *regulator;
3fe52289 70 struct ab8500_shared_mode *shared_mode;
7ce4669c 71 int load_lp_uA;
47c16975
MW		 72 u8 update_bank;
73 u8 update_reg;
e1159e6d 74 u8 update_mask;
bd28a157
EV		 75 u8 update_val;
76 u8 update_val_idle;
77 u8 update_val_normal;
3fe52289
LJ		 78 u8 mode_bank;
79 u8 mode_reg;
80 u8 mode_mask;
81 u8 mode_val_idle;
82 u8 mode_val_normal;
47c16975
MW		 83 u8 voltage_bank;
84 u8 voltage_reg;
85 u8 voltage_mask;
a0a7014c 86 u8 voltage_shift;
d7607baf
LJ		 87 struct {
88 u8 voltage_limit;
89 u8 voltage_bank;
90 u8 voltage_reg;
91 u8 voltage_mask;
92 u8 voltage_shift;
93 } expand_register;
c789ca20
SI		 94};
95
96/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 97static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 98 1100000,
99 1200000,
100 1300000,
101 1400000,
102 1500000,
103 1800000,
104 1850000,
105 1900000,
106 2500000,
107 2650000,
108 2700000,
109 2750000,
110 2800000,
111 2900000,
112 3000000,
113 3300000,
114};
115
ec1cc4d9 116static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 117 1200000,
118 1500000,
119 1800000,
120 2100000,
121 2500000,
122 2750000,
123 2790000,
124 2910000,
125};
126
62ab4111 127static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 128 1800000,
129 1050000,
130 1100000,
131 1200000,
132 1500000,
133 2200000,
134 2500000,
135 2790000,
136};
137
62ab4111 138static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 139 1200000,
140 1500000,
141 1800000,
142 2100000,
143 2500000,
144 2750000,
145 2790000,
146 2910000,
147 3050000,
148};
149
684d5ce4
ZH		 150static const unsigned int ldo_vaux56_ab8540_voltages[] = {
151 750000, 760000, 770000, 780000, 790000, 800000,
152 810000, 820000, 830000, 840000, 850000, 860000,
153 870000, 880000, 890000, 900000, 910000, 920000,
154 930000, 940000, 950000, 960000, 970000, 980000,
155 990000, 1000000, 1010000, 1020000, 1030000,
156 1040000, 1050000, 1060000, 1070000, 1080000,
157 1090000, 1100000, 1110000, 1120000, 1130000,
158 1140000, 1150000, 1160000, 1170000, 1180000,
159 1190000, 1200000, 1210000, 1220000, 1230000,
160 1240000, 1250000, 1260000, 1270000, 1280000,
161 1290000, 1300000, 1310000, 1320000, 1330000,
162 1340000, 1350000, 1360000, 1800000, 2790000,
163};
164
ec1cc4d9 165static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 166 1200000,
167 1225000,
168 1250000,
169 1275000,
170 1300000,
171 1325000,
172 1350000,
173};
174
62ab4111 175static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 176 1160000,
177 1050000,
178 1100000,
179 1500000,
180 1800000,
181 2200000,
182 2910000,
183 3050000,
184};
185
b080c78a
LJ		 186static const unsigned int fixed_1200000_voltage[] = {
187 1200000,
188};
189
190static const unsigned int fixed_1800000_voltage[] = {
191 1800000,
192};
193
194static const unsigned int fixed_2000000_voltage[] = {
195 2000000,
196};
197
198static const unsigned int fixed_2050000_voltage[] = {
199 2050000,
200};
201
202static const unsigned int fixed_3300000_voltage[] = {
203 3300000,
204};
205
8a3b1b87
LJ		 206static const unsigned int ldo_vana_voltages[] = {
207 1050000,
208 1075000,
209 1100000,
210 1125000,
211 1150000,
212 1175000,
213 1200000,
214 1225000,
215};
216
217static const unsigned int ldo_vaudio_voltages[] = {
218 2000000,
219 2100000,
220 2200000,
221 2300000,
222 2400000,
223 2500000,
224 2600000,
225 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
226};
227
4c84b4dd
LJ		 228static const unsigned int ldo_vdmic_voltages[] = {
229 1800000,
230 1900000,
231 2000000,
232 2850000,
233};
234
3fe52289
LJ		 235static DEFINE_MUTEX(shared_mode_mutex);
236static struct ab8500_shared_mode ldo_anamic1_shared;
237static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 238static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
239static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 240
c789ca20
SI		 241static int ab8500_regulator_enable(struct regulator_dev *rdev)
242{
fc24b426 243 int ret;
c789ca20
SI		 244 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
245
fc24b426
BJ		 246 if (info == NULL) {
247 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 248 return -EINVAL;
fc24b426 249 }
c789ca20 250
47c16975 251 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 252 info->update_bank, info->update_reg,
bd28a157 253 info->update_mask, info->update_val);
f71bf528 254 if (ret < 0) {
c789ca20
SI		 255 dev_err(rdev_get_dev(rdev),
256 "couldn't set enable bits for regulator\n");
f71bf528
AL		 257 return ret;
258 }
09aefa12
BJ		 259
260 dev_vdbg(rdev_get_dev(rdev),
261 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
262 info->desc.name, info->update_bank, info->update_reg,
bd28a157 263 info->update_mask, info->update_val);
09aefa12 264
c789ca20
SI		 265 return ret;
266}
267
268static int ab8500_regulator_disable(struct regulator_dev *rdev)
269{
fc24b426 270 int ret;
c789ca20
SI		 271 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
272
fc24b426
BJ		 273 if (info == NULL) {
274 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 275 return -EINVAL;
fc24b426 276 }
c789ca20 277
47c16975 278 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 279 info->update_bank, info->update_reg,
280 info->update_mask, 0x0);
f71bf528 281 if (ret < 0) {
c789ca20
SI		 282 dev_err(rdev_get_dev(rdev),
283 "couldn't set disable bits for regulator\n");
f71bf528
AL		 284 return ret;
285 }
09aefa12
BJ		 286
287 dev_vdbg(rdev_get_dev(rdev),
288 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
289 info->desc.name, info->update_bank, info->update_reg,
290 info->update_mask, 0x0);
291
c789ca20
SI		 292 return ret;
293}
294
438e695b
AL		 295static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
296{
297 int ret;
298 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
299 u8 regval;
300
301 if (info == NULL) {
302 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
303 return -EINVAL;
304 }
305
306 ret = abx500_get_register_interruptible(info->dev,
307 info->update_bank, info->update_reg, &regval);
308 if (ret < 0) {
309 dev_err(rdev_get_dev(rdev),
310 "couldn't read 0x%x register\n", info->update_reg);
311 return ret;
312 }
313
314 dev_vdbg(rdev_get_dev(rdev),
315 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
316 " 0x%x\n",
317 info->desc.name, info->update_bank, info->update_reg,
318 info->update_mask, regval);
319
320 if (regval & info->update_mask)
321 return 1;
322 else
323 return 0;
324}
325
7ce4669c
BJ		 326static unsigned int ab8500_regulator_get_optimum_mode(
327 struct regulator_dev *rdev, int input_uV,
328 int output_uV, int load_uA)
329{
330 unsigned int mode;
331
332 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
333
334 if (info == NULL) {
335 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
336 return -EINVAL;
337 }
338
339 if (load_uA <= info->load_lp_uA)
340 mode = REGULATOR_MODE_IDLE;
341 else
342 mode = REGULATOR_MODE_NORMAL;
343
344 return mode;
345}
346
bd28a157
EV		 347static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
348 unsigned int mode)
349{
3fe52289 350 int ret = 0;
0b665062
AL		 351 u8 bank, reg, mask, val;
352 bool lp_mode_req = false;
bd28a157
EV		 353 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
354
355 if (info == NULL) {
356 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
357 return -EINVAL;
358 }
359
3fe52289 360 if (info->mode_mask) {
3fe52289
LJ		 361 bank = info->mode_bank;
362 reg = info->mode_reg;
363 mask = info->mode_mask;
364 } else {
0b665062
AL		 365 bank = info->update_bank;
366 reg = info->update_reg;
367 mask = info->update_mask;
368 }
3fe52289 369
0b665062
AL		 370 if (info->shared_mode)
371 mutex_lock(&shared_mode_mutex);
372
373 switch (mode) {
374 case REGULATOR_MODE_NORMAL:
375 if (info->shared_mode)
376 lp_mode_req = false;
377
378 if (info->mode_mask)
379 val = info->mode_val_normal;
380 else
3fe52289 381 val = info->update_val_normal;
0b665062
AL		 382 break;
383 case REGULATOR_MODE_IDLE:
384 if (info->shared_mode) {
385 struct ab8500_regulator_info *shared_regulator;
386
387 shared_regulator = info->shared_mode->shared_regulator;
388 if (!shared_regulator->shared_mode->lp_mode_req) {
389 /* Other regulator prevent LP mode */
390 info->shared_mode->lp_mode_req = true;
391 goto out_unlock;
392 }
393
394 lp_mode_req = true;
3fe52289
LJ		 395 }
396
0b665062
AL		 397 if (info->mode_mask)
398 val = info->mode_val_idle;
399 else
400 val = info->update_val_idle;
401 break;
402 default:
403 ret = -EINVAL;
404 goto out_unlock;
bd28a157
EV		 405 }
406
0b665062 407 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
bd28a157 408 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289 409 bank, reg, mask, val);
f04adc5a 410 if (ret < 0) {
bd28a157
EV		 411 dev_err(rdev_get_dev(rdev),
412 "couldn't set regulator mode\n");
f04adc5a
AL		 413 goto out_unlock;
414 }
7ce4669c
BJ		 415
416 dev_vdbg(rdev_get_dev(rdev),
417 "%s-set_mode (bank, reg, mask, value): "
418 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 419 info->desc.name, bank, reg,
420 mask, val);
bd28a157
EV		 421 }
422
0b665062 423 if (!info->mode_mask)
f04adc5a
AL		 424 info->update_val = val;
425
0b665062
AL		 426 if (info->shared_mode)
427 info->shared_mode->lp_mode_req = lp_mode_req;
428
f04adc5a 429out_unlock:
3fe52289
LJ		 430 if (info->shared_mode)
431 mutex_unlock(&shared_mode_mutex);
742a7325 432
3fe52289 433 return ret;
bd28a157
EV		 434}
435
436static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
437{
438 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
439 int ret;
3fe52289
LJ		 440 u8 val;
441 u8 val_normal;
442 u8 val_idle;
bd28a157
EV		 443
444 if (info == NULL) {
445 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
446 return -EINVAL;
447 }
448
3fe52289
LJ		 449 /* Need special handling for shared mode */
450 if (info->shared_mode) {
451 if (info->shared_mode->lp_mode_req)
452 return REGULATOR_MODE_IDLE;
453 else
454 return REGULATOR_MODE_NORMAL;
455 }
456
457 if (info->mode_mask) {
458 /* Dedicated register for handling mode */
459 ret = abx500_get_register_interruptible(info->dev,
460 info->mode_bank, info->mode_reg, &val);
461 val = val & info->mode_mask;
462
463 val_normal = info->mode_val_normal;
464 val_idle = info->mode_val_idle;
465 } else {
466 /* Mode register same as enable register */
467 val = info->update_val;
468 val_normal = info->update_val_normal;
469 val_idle = info->update_val_idle;
470 }
471
472 if (val == val_normal)
bd28a157 473 ret = REGULATOR_MODE_NORMAL;
3fe52289 474 else if (val == val_idle)
bd28a157
EV		 475 ret = REGULATOR_MODE_IDLE;
476 else
477 ret = -EINVAL;
478
479 return ret;
480}
481
3bf6e90e 482static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 483{
09aefa12 484 int ret, val;
c789ca20 485 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 486 u8 regval;
c789ca20 487
fc24b426
BJ		 488 if (info == NULL) {
489 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 490 return -EINVAL;
fc24b426 491 }
c789ca20 492
09aefa12
BJ		 493 ret = abx500_get_register_interruptible(info->dev,
494 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 495 if (ret < 0) {
496 dev_err(rdev_get_dev(rdev),
497 "couldn't read voltage reg for regulator\n");
498 return ret;
499 }
500
09aefa12 501 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 502 "%s-get_voltage (bank, reg, mask, shift, value): "
503 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
504 info->desc.name, info->voltage_bank,
505 info->voltage_reg, info->voltage_mask,
506 info->voltage_shift, regval);
09aefa12 507
09aefa12 508 val = regval & info->voltage_mask;
a0a7014c 509 return val >> info->voltage_shift;
c789ca20
SI		 510}
511
d7607baf
LJ		 512static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
513{
241896ce 514 int ret;
d7607baf
LJ		 515 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
516 u8 regval, regval_expand;
517
518 if (info == NULL) {
519 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
520 return -EINVAL;
521 }
522
523 ret = abx500_get_register_interruptible(info->dev,
241896ce
AL		 524 info->expand_register.voltage_bank,
525 info->expand_register.voltage_reg, &regval_expand);
d7607baf
LJ		 526 if (ret < 0) {
527 dev_err(rdev_get_dev(rdev),
241896ce 528 "couldn't read voltage expand reg for regulator\n");
d7607baf
LJ		 529 return ret;
530 }
531
241896ce
AL		 532 dev_vdbg(rdev_get_dev(rdev),
533 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
534 info->desc.name, info->expand_register.voltage_bank,
535 info->expand_register.voltage_reg,
536 info->expand_register.voltage_mask, regval_expand);
d7607baf 537
241896ce
AL		 538 if (regval_expand & info->expand_register.voltage_mask)
539 return info->expand_register.voltage_limit;
540
541 ret = abx500_get_register_interruptible(info->dev,
542 info->voltage_bank, info->voltage_reg, &regval);
d7607baf
LJ		 543 if (ret < 0) {
544 dev_err(rdev_get_dev(rdev),
545 "couldn't read voltage reg for regulator\n");
546 return ret;
547 }
548
549 dev_vdbg(rdev_get_dev(rdev),
241896ce
AL		 550 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
551 info->desc.name, info->voltage_bank, info->voltage_reg,
552 info->voltage_mask, regval);
d7607baf 553
241896ce 554 return (regval & info->voltage_mask) >> info->voltage_shift;
d7607baf
LJ		 555}
556
ae713d39
AL		 557static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
558 unsigned selector)
c789ca20 559{
fc24b426 560 int ret;
c789ca20 561 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 562 u8 regval;
c789ca20 563
fc24b426
BJ		 564 if (info == NULL) {
565 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 566 return -EINVAL;
fc24b426 567 }
c789ca20 568
c789ca20 569 /* set the registers for the request */
a0a7014c 570 regval = (u8)selector << info->voltage_shift;
47c16975 571 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 572 info->voltage_bank, info->voltage_reg,
573 info->voltage_mask, regval);
c789ca20
SI		 574 if (ret < 0)
575 dev_err(rdev_get_dev(rdev),
576 "couldn't set voltage reg for regulator\n");
577
09aefa12
BJ		 578 dev_vdbg(rdev_get_dev(rdev),
579 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
580 " 0x%x\n",
581 info->desc.name, info->voltage_bank, info->voltage_reg,
582 info->voltage_mask, regval);
583
c789ca20
SI		 584 return ret;
585}
586
d7607baf
LJ		 587static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
588 unsigned selector)
589{
590 int ret;
591 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
592 u8 regval;
593
594 if (info == NULL) {
595 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
596 return -EINVAL;
597 }
598
599 if (selector >= info->expand_register.voltage_limit) {
600 /* Vaux3 bit4 has different layout */
601 regval = (u8)selector << info->expand_register.voltage_shift;
602 ret = abx500_mask_and_set_register_interruptible(info->dev,
603 info->expand_register.voltage_bank,
604 info->expand_register.voltage_reg,
605 info->expand_register.voltage_mask,
606 regval);
607 } else {
608 /* set the registers for the request */
609 regval = (u8)selector << info->voltage_shift;
610 ret = abx500_mask_and_set_register_interruptible(info->dev,
611 info->voltage_bank, info->voltage_reg,
612 info->voltage_mask, regval);
613 }
614 if (ret < 0)
615 dev_err(rdev_get_dev(rdev),
616 "couldn't set voltage reg for regulator\n");
617
618 dev_vdbg(rdev_get_dev(rdev),
619 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
620 " 0x%x\n",
621 info->desc.name, info->voltage_bank, info->voltage_reg,
622 info->voltage_mask, regval);
623
624 return ret;
625}
626
7ce4669c
BJ		 627static struct regulator_ops ab8500_regulator_volt_mode_ops = {
628 .enable = ab8500_regulator_enable,
629 .disable = ab8500_regulator_disable,
630 .is_enabled = ab8500_regulator_is_enabled,
631 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
632 .set_mode = ab8500_regulator_set_mode,
633 .get_mode = ab8500_regulator_get_mode,
634 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
635 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
636 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 637};
638
d7607baf
LJ		 639static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
640 .enable = ab8500_regulator_enable,
641 .disable = ab8500_regulator_disable,
642 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
643 .set_mode = ab8500_regulator_set_mode,
644 .get_mode = ab8500_regulator_get_mode,
645 .is_enabled = ab8500_regulator_is_enabled,
646 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
647 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
648 .list_voltage = regulator_list_voltage_table,
d7607baf
LJ		 649};
650
8a3b1b87
LJ		 651static struct regulator_ops ab8500_regulator_volt_ops = {
652 .enable = ab8500_regulator_enable,
653 .disable = ab8500_regulator_disable,
654 .is_enabled = ab8500_regulator_is_enabled,
655 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
656 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
657 .list_voltage = regulator_list_voltage_table,
8a3b1b87
LJ		 658};
659
7ce4669c
BJ		 660static struct regulator_ops ab8500_regulator_mode_ops = {
661 .enable = ab8500_regulator_enable,
662 .disable = ab8500_regulator_disable,
663 .is_enabled = ab8500_regulator_is_enabled,
664 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
665 .set_mode = ab8500_regulator_set_mode,
666 .get_mode = ab8500_regulator_get_mode,
d7816ab0 667 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 668};
669
670static struct regulator_ops ab8500_regulator_ops = {
671 .enable = ab8500_regulator_enable,
672 .disable = ab8500_regulator_disable,
673 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 674 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 675};
676
3fe52289
LJ		 677static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
678 .enable = ab8500_regulator_enable,
679 .disable = ab8500_regulator_disable,
680 .is_enabled = ab8500_regulator_is_enabled,
681 .set_mode = ab8500_regulator_set_mode,
682 .get_mode = ab8500_regulator_get_mode,
683 .list_voltage = regulator_list_voltage_table,
684};
685
8e6a8d7d 686/* AB8500 regulator information */
6909b452
BJ		 687static struct ab8500_regulator_info
688 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 689 /*
e1159e6d
BJ		 690 * Variable Voltage Regulators
691 * name, min mV, max mV,
692 * update bank, reg, mask, enable val
ec1cc4d9 693 * volt bank, reg, mask
c789ca20 694 */
6909b452
BJ		 695 [AB8500_LDO_AUX1] = {
696 .desc = {
697 .name = "LDO-AUX1",
7ce4669c 698 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 699 .type = REGULATOR_VOLTAGE,
700 .id = AB8500_LDO_AUX1,
701 .owner = THIS_MODULE,
702 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 703 .volt_table = ldo_vauxn_voltages,
530158b6 704 .enable_time = 200,
6909b452 705 },
7ce4669c 706 .load_lp_uA = 5000,
6909b452
BJ		 707 .update_bank = 0x04,
708 .update_reg = 0x09,
709 .update_mask = 0x03,
bd28a157
EV		 710 .update_val = 0x01,
711 .update_val_idle = 0x03,
712 .update_val_normal = 0x01,
6909b452
BJ		 713 .voltage_bank = 0x04,
714 .voltage_reg = 0x1f,
715 .voltage_mask = 0x0f,
6909b452
BJ		 716 },
717 [AB8500_LDO_AUX2] = {
718 .desc = {
719 .name = "LDO-AUX2",
7ce4669c 720 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 721 .type = REGULATOR_VOLTAGE,
722 .id = AB8500_LDO_AUX2,
723 .owner = THIS_MODULE,
724 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 725 .volt_table = ldo_vauxn_voltages,
530158b6 726 .enable_time = 200,
6909b452 727 },
7ce4669c 728 .load_lp_uA = 5000,
6909b452
BJ		 729 .update_bank = 0x04,
730 .update_reg = 0x09,
731 .update_mask = 0x0c,
bd28a157
EV		 732 .update_val = 0x04,
733 .update_val_idle = 0x0c,
734 .update_val_normal = 0x04,
6909b452
BJ		 735 .voltage_bank = 0x04,
736 .voltage_reg = 0x20,
737 .voltage_mask = 0x0f,
6909b452
BJ		 738 },
739 [AB8500_LDO_AUX3] = {
740 .desc = {
741 .name = "LDO-AUX3",
7ce4669c 742 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 743 .type = REGULATOR_VOLTAGE,
744 .id = AB8500_LDO_AUX3,
745 .owner = THIS_MODULE,
746 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 747 .volt_table = ldo_vaux3_voltages,
530158b6 748 .enable_time = 450,
6909b452 749 },
7ce4669c 750 .load_lp_uA = 5000,
6909b452
BJ		 751 .update_bank = 0x04,
752 .update_reg = 0x0a,
753 .update_mask = 0x03,
bd28a157
EV		 754 .update_val = 0x01,
755 .update_val_idle = 0x03,
756 .update_val_normal = 0x01,
6909b452
BJ		 757 .voltage_bank = 0x04,
758 .voltage_reg = 0x21,
759 .voltage_mask = 0x07,
6909b452
BJ		 760 },
761 [AB8500_LDO_INTCORE] = {
762 .desc = {
763 .name = "LDO-INTCORE",
7ce4669c 764 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 765 .type = REGULATOR_VOLTAGE,
766 .id = AB8500_LDO_INTCORE,
767 .owner = THIS_MODULE,
768 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 769 .volt_table = ldo_vintcore_voltages,
530158b6 770 .enable_time = 750,
6909b452 771 },
7ce4669c 772 .load_lp_uA = 5000,
6909b452
BJ		 773 .update_bank = 0x03,
774 .update_reg = 0x80,
775 .update_mask = 0x44,
cc40dc29 776 .update_val = 0x44,
bd28a157
EV		 777 .update_val_idle = 0x44,
778 .update_val_normal = 0x04,
6909b452
BJ		 779 .voltage_bank = 0x03,
780 .voltage_reg = 0x80,
781 .voltage_mask = 0x38,
a0a7014c 782 .voltage_shift = 3,
6909b452 783 },
c789ca20
SI		 784
785 /*
e1159e6d
BJ		 786 * Fixed Voltage Regulators
787 * name, fixed mV,
788 * update bank, reg, mask, enable val
c789ca20 789 */
6909b452
BJ		 790 [AB8500_LDO_TVOUT] = {
791 .desc = {
792 .name = "LDO-TVOUT",
7ce4669c 793 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 794 .type = REGULATOR_VOLTAGE,
795 .id = AB8500_LDO_TVOUT,
796 .owner = THIS_MODULE,
797 .n_voltages = 1,
b080c78a 798 .volt_table = fixed_2000000_voltage,
ed3c138e 799 .enable_time = 500,
6909b452 800 },
7ce4669c 801 .load_lp_uA = 1000,
6909b452
BJ		 802 .update_bank = 0x03,
803 .update_reg = 0x80,
804 .update_mask = 0x82,
bd28a157 805 .update_val = 0x02,
7ce4669c
BJ		 806 .update_val_idle = 0x82,
807 .update_val_normal = 0x02,
6909b452
BJ		 808 },
809 [AB8500_LDO_AUDIO] = {
810 .desc = {
811 .name = "LDO-AUDIO",
7ce4669c 812 .ops = &ab8500_regulator_ops,
6909b452
BJ		 813 .type = REGULATOR_VOLTAGE,
814 .id = AB8500_LDO_AUDIO,
815 .owner = THIS_MODULE,
816 .n_voltages = 1,
530158b6 817 .enable_time = 140,
b080c78a 818 .volt_table = fixed_2000000_voltage,
6909b452 819 },
6909b452
BJ		 820 .update_bank = 0x03,
821 .update_reg = 0x83,
822 .update_mask = 0x02,
bd28a157 823 .update_val = 0x02,
6909b452
BJ		 824 },
825 [AB8500_LDO_ANAMIC1] = {
826 .desc = {
827 .name = "LDO-ANAMIC1",
7ce4669c 828 .ops = &ab8500_regulator_ops,
6909b452
BJ		 829 .type = REGULATOR_VOLTAGE,
830 .id = AB8500_LDO_ANAMIC1,
831 .owner = THIS_MODULE,
832 .n_voltages = 1,
530158b6 833 .enable_time = 500,
b080c78a 834 .volt_table = fixed_2050000_voltage,
6909b452 835 },
6909b452
BJ		 836 .update_bank = 0x03,
837 .update_reg = 0x83,
838 .update_mask = 0x08,
bd28a157 839 .update_val = 0x08,
6909b452
BJ		 840 },
841 [AB8500_LDO_ANAMIC2] = {
842 .desc = {
843 .name = "LDO-ANAMIC2",
7ce4669c 844 .ops = &ab8500_regulator_ops,
6909b452
BJ		 845 .type = REGULATOR_VOLTAGE,
846 .id = AB8500_LDO_ANAMIC2,
847 .owner = THIS_MODULE,
848 .n_voltages = 1,
530158b6 849 .enable_time = 500,
b080c78a 850 .volt_table = fixed_2050000_voltage,
6909b452 851 },
6909b452
BJ		 852 .update_bank = 0x03,
853 .update_reg = 0x83,
854 .update_mask = 0x10,
bd28a157 855 .update_val = 0x10,
6909b452
BJ		 856 },
857 [AB8500_LDO_DMIC] = {
858 .desc = {
859 .name = "LDO-DMIC",
7ce4669c 860 .ops = &ab8500_regulator_ops,
6909b452
BJ		 861 .type = REGULATOR_VOLTAGE,
862 .id = AB8500_LDO_DMIC,
863 .owner = THIS_MODULE,
864 .n_voltages = 1,
530158b6 865 .enable_time = 420,
b080c78a 866 .volt_table = fixed_1800000_voltage,
6909b452 867 },
6909b452
BJ		 868 .update_bank = 0x03,
869 .update_reg = 0x83,
870 .update_mask = 0x04,
bd28a157 871 .update_val = 0x04,
6909b452 872 },
7ce4669c
BJ		 873
874 /*
875 * Regulators with fixed voltage and normal/idle modes
876 */
6909b452
BJ		 877 [AB8500_LDO_ANA] = {
878 .desc = {
879 .name = "LDO-ANA",
7ce4669c 880 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 881 .type = REGULATOR_VOLTAGE,
882 .id = AB8500_LDO_ANA,
883 .owner = THIS_MODULE,
884 .n_voltages = 1,
530158b6 885 .enable_time = 140,
b080c78a 886 .volt_table = fixed_1200000_voltage,
6909b452 887 },
7ce4669c 888 .load_lp_uA = 1000,
6909b452
BJ		 889 .update_bank = 0x04,
890 .update_reg = 0x06,
891 .update_mask = 0x0c,
bd28a157 892 .update_val = 0x04,
7ce4669c
BJ		 893 .update_val_idle = 0x0c,
894 .update_val_normal = 0x04,
6909b452 895 },
8e6a8d7d 896};
6909b452 897
547f384f
LJ		 898/* AB8505 regulator information */
899static struct ab8500_regulator_info
900 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
901 /*
902 * Variable Voltage Regulators
903 * name, min mV, max mV,
904 * update bank, reg, mask, enable val
d3193103 905 * volt bank, reg, mask
547f384f
LJ		 906 */
907 [AB8505_LDO_AUX1] = {
908 .desc = {
909 .name = "LDO-AUX1",
910 .ops = &ab8500_regulator_volt_mode_ops,
911 .type = REGULATOR_VOLTAGE,
0b946411 912 .id = AB8505_LDO_AUX1,
547f384f
LJ		 913 .owner = THIS_MODULE,
914 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 915 .volt_table = ldo_vauxn_voltages,
547f384f 916 },
547f384f
LJ		 917 .load_lp_uA = 5000,
918 .update_bank = 0x04,
919 .update_reg = 0x09,
920 .update_mask = 0x03,
921 .update_val = 0x01,
922 .update_val_idle = 0x03,
923 .update_val_normal = 0x01,
924 .voltage_bank = 0x04,
925 .voltage_reg = 0x1f,
926 .voltage_mask = 0x0f,
547f384f
LJ		 927 },
928 [AB8505_LDO_AUX2] = {
929 .desc = {
930 .name = "LDO-AUX2",
931 .ops = &ab8500_regulator_volt_mode_ops,
932 .type = REGULATOR_VOLTAGE,
0b946411 933 .id = AB8505_LDO_AUX2,
547f384f
LJ		 934 .owner = THIS_MODULE,
935 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 936 .volt_table = ldo_vauxn_voltages,
547f384f 937 },
547f384f
LJ		 938 .load_lp_uA = 5000,
939 .update_bank = 0x04,
940 .update_reg = 0x09,
941 .update_mask = 0x0c,
942 .update_val = 0x04,
943 .update_val_idle = 0x0c,
944 .update_val_normal = 0x04,
945 .voltage_bank = 0x04,
946 .voltage_reg = 0x20,
947 .voltage_mask = 0x0f,
547f384f
LJ		 948 },
949 [AB8505_LDO_AUX3] = {
950 .desc = {
951 .name = "LDO-AUX3",
952 .ops = &ab8500_regulator_volt_mode_ops,
953 .type = REGULATOR_VOLTAGE,
0b946411 954 .id = AB8505_LDO_AUX3,
547f384f
LJ		 955 .owner = THIS_MODULE,
956 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 957 .volt_table = ldo_vaux3_voltages,
547f384f 958 },
547f384f
LJ		 959 .load_lp_uA = 5000,
960 .update_bank = 0x04,
961 .update_reg = 0x0a,
962 .update_mask = 0x03,
963 .update_val = 0x01,
964 .update_val_idle = 0x03,
965 .update_val_normal = 0x01,
966 .voltage_bank = 0x04,
967 .voltage_reg = 0x21,
968 .voltage_mask = 0x07,
547f384f
LJ		 969 },
970 [AB8505_LDO_AUX4] = {
971 .desc = {
972 .name = "LDO-AUX4",
973 .ops = &ab8500_regulator_volt_mode_ops,
974 .type = REGULATOR_VOLTAGE,
0b946411 975 .id = AB8505_LDO_AUX4,
547f384f
LJ		 976 .owner = THIS_MODULE,
977 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 978 .volt_table = ldo_vauxn_voltages,
547f384f 979 },
547f384f
LJ		 980 .load_lp_uA = 5000,
981 /* values for Vaux4Regu register */
982 .update_bank = 0x04,
983 .update_reg = 0x2e,
984 .update_mask = 0x03,
985 .update_val = 0x01,
986 .update_val_idle = 0x03,
987 .update_val_normal = 0x01,
988 /* values for Vaux4SEL register */
989 .voltage_bank = 0x04,
990 .voltage_reg = 0x2f,
991 .voltage_mask = 0x0f,
547f384f
LJ		 992 },
993 [AB8505_LDO_AUX5] = {
994 .desc = {
995 .name = "LDO-AUX5",
996 .ops = &ab8500_regulator_volt_mode_ops,
997 .type = REGULATOR_VOLTAGE,
998 .id = AB8505_LDO_AUX5,
999 .owner = THIS_MODULE,
1000 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1001 .volt_table = ldo_vaux56_voltages,
547f384f 1002 },
547f384f
LJ		 1003 .load_lp_uA = 2000,
1004 /* values for CtrlVaux5 register */
1005 .update_bank = 0x01,
1006 .update_reg = 0x55,
ae0a9a3e
LJ		 1007 .update_mask = 0x18,
1008 .update_val = 0x10,
1009 .update_val_idle = 0x18,
1010 .update_val_normal = 0x10,
547f384f
LJ		 1011 .voltage_bank = 0x01,
1012 .voltage_reg = 0x55,
1013 .voltage_mask = 0x07,
547f384f
LJ		 1014 },
1015 [AB8505_LDO_AUX6] = {
1016 .desc = {
1017 .name = "LDO-AUX6",
1018 .ops = &ab8500_regulator_volt_mode_ops,
1019 .type = REGULATOR_VOLTAGE,
1020 .id = AB8505_LDO_AUX6,
1021 .owner = THIS_MODULE,
1022 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1023 .volt_table = ldo_vaux56_voltages,
547f384f 1024 },
547f384f
LJ		 1025 .load_lp_uA = 2000,
1026 /* values for CtrlVaux6 register */
1027 .update_bank = 0x01,
1028 .update_reg = 0x56,
ae0a9a3e
LJ		 1029 .update_mask = 0x18,
1030 .update_val = 0x10,
1031 .update_val_idle = 0x18,
1032 .update_val_normal = 0x10,
547f384f
LJ		 1033 .voltage_bank = 0x01,
1034 .voltage_reg = 0x56,
1035 .voltage_mask = 0x07,
547f384f
LJ		 1036 },
1037 [AB8505_LDO_INTCORE] = {
1038 .desc = {
1039 .name = "LDO-INTCORE",
1040 .ops = &ab8500_regulator_volt_mode_ops,
1041 .type = REGULATOR_VOLTAGE,
0b946411 1042 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1043 .owner = THIS_MODULE,
1044 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1045 .volt_table = ldo_vintcore_voltages,
547f384f 1046 },
547f384f
LJ		 1047 .load_lp_uA = 5000,
1048 .update_bank = 0x03,
1049 .update_reg = 0x80,
1050 .update_mask = 0x44,
1051 .update_val = 0x04,
1052 .update_val_idle = 0x44,
1053 .update_val_normal = 0x04,
1054 .voltage_bank = 0x03,
1055 .voltage_reg = 0x80,
1056 .voltage_mask = 0x38,
547f384f
LJ		 1057 .voltage_shift = 3,
1058 },
1059
1060 /*
1061 * Fixed Voltage Regulators
1062 * name, fixed mV,
1063 * update bank, reg, mask, enable val
1064 */
1065 [AB8505_LDO_ADC] = {
1066 .desc = {
1067 .name = "LDO-ADC",
1068 .ops = &ab8500_regulator_mode_ops,
1069 .type = REGULATOR_VOLTAGE,
1070 .id = AB8505_LDO_ADC,
1071 .owner = THIS_MODULE,
1072 .n_voltages = 1,
b080c78a 1073 .volt_table = fixed_2000000_voltage,
a4d68468 1074 .enable_time = 10000,
547f384f 1075 },
547f384f
LJ		 1076 .load_lp_uA = 1000,
1077 .update_bank = 0x03,
1078 .update_reg = 0x80,
1079 .update_mask = 0x82,
1080 .update_val = 0x02,
1081 .update_val_idle = 0x82,
1082 .update_val_normal = 0x02,
1083 },
1084 [AB8505_LDO_USB] = {
1085 .desc = {
1086 .name = "LDO-USB",
1087 .ops = &ab8500_regulator_mode_ops,
1088 .type = REGULATOR_VOLTAGE,
0b946411 1089 .id = AB8505_LDO_USB,
547f384f
LJ		 1090 .owner = THIS_MODULE,
1091 .n_voltages = 1,
b080c78a 1092 .volt_table = fixed_3300000_voltage,
547f384f 1093 },
547f384f
LJ		 1094 .update_bank = 0x03,
1095 .update_reg = 0x82,
1096 .update_mask = 0x03,
1097 .update_val = 0x01,
1098 .update_val_idle = 0x03,
1099 .update_val_normal = 0x01,
1100 },
1101 [AB8505_LDO_AUDIO] = {
1102 .desc = {
1103 .name = "LDO-AUDIO",
8a3b1b87 1104 .ops = &ab8500_regulator_volt_ops,
547f384f 1105 .type = REGULATOR_VOLTAGE,
0b946411 1106 .id = AB8505_LDO_AUDIO,
547f384f 1107 .owner = THIS_MODULE,
8a3b1b87
LJ		 1108 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1109 .volt_table = ldo_vaudio_voltages,
547f384f 1110 },
547f384f
LJ		 1111 .update_bank = 0x03,
1112 .update_reg = 0x83,
1113 .update_mask = 0x02,
1114 .update_val = 0x02,
8a3b1b87
LJ		 1115 .voltage_bank = 0x01,
1116 .voltage_reg = 0x57,
e4fc9d6d 1117 .voltage_mask = 0x70,
8a3b1b87 1118 .voltage_shift = 4,
547f384f
LJ		 1119 },
1120 [AB8505_LDO_ANAMIC1] = {
1121 .desc = {
1122 .name = "LDO-ANAMIC1",
3fe52289 1123 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1124 .type = REGULATOR_VOLTAGE,
0b946411 1125 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1126 .owner = THIS_MODULE,
1127 .n_voltages = 1,
b080c78a 1128 .volt_table = fixed_2050000_voltage,
547f384f 1129 },
4c84b4dd 1130 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1131 .update_bank = 0x03,
1132 .update_reg = 0x83,
1133 .update_mask = 0x08,
1134 .update_val = 0x08,
3fe52289
LJ		 1135 .mode_bank = 0x01,
1136 .mode_reg = 0x54,
1137 .mode_mask = 0x04,
1138 .mode_val_idle = 0x04,
1139 .mode_val_normal = 0x00,
547f384f
LJ		 1140 },
1141 [AB8505_LDO_ANAMIC2] = {
1142 .desc = {
1143 .name = "LDO-ANAMIC2",
3fe52289 1144 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1145 .type = REGULATOR_VOLTAGE,
0b946411 1146 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1147 .owner = THIS_MODULE,
1148 .n_voltages = 1,
b080c78a 1149 .volt_table = fixed_2050000_voltage,
547f384f 1150 },
3fe52289 1151 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1152 .update_bank = 0x03,
1153 .update_reg = 0x83,
1154 .update_mask = 0x10,
1155 .update_val = 0x10,
3fe52289
LJ		 1156 .mode_bank = 0x01,
1157 .mode_reg = 0x54,
1158 .mode_mask = 0x04,
1159 .mode_val_idle = 0x04,
1160 .mode_val_normal = 0x00,
547f384f
LJ		 1161 },
1162 [AB8505_LDO_AUX8] = {
1163 .desc = {
1164 .name = "LDO-AUX8",
1165 .ops = &ab8500_regulator_ops,
1166 .type = REGULATOR_VOLTAGE,
1167 .id = AB8505_LDO_AUX8,
1168 .owner = THIS_MODULE,
1169 .n_voltages = 1,
b080c78a 1170 .volt_table = fixed_1800000_voltage,
547f384f 1171 },
547f384f
LJ		 1172 .update_bank = 0x03,
1173 .update_reg = 0x83,
1174 .update_mask = 0x04,
1175 .update_val = 0x04,
1176 },
1177 /*
1178 * Regulators with fixed voltage and normal/idle modes
1179 */
1180 [AB8505_LDO_ANA] = {
1181 .desc = {
1182 .name = "LDO-ANA",
8a3b1b87 1183 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1184 .type = REGULATOR_VOLTAGE,
0b946411 1185 .id = AB8505_LDO_ANA,
547f384f 1186 .owner = THIS_MODULE,
8a3b1b87
LJ		 1187 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1188 .volt_table = ldo_vana_voltages,
547f384f 1189 },
547f384f
LJ		 1190 .load_lp_uA = 1000,
1191 .update_bank = 0x04,
1192 .update_reg = 0x06,
1193 .update_mask = 0x0c,
1194 .update_val = 0x04,
1195 .update_val_idle = 0x0c,
1196 .update_val_normal = 0x04,
8a3b1b87
LJ		 1197 .voltage_bank = 0x04,
1198 .voltage_reg = 0x29,
1199 .voltage_mask = 0x7,
547f384f
LJ		 1200 },
1201};
1202
8e6a8d7d
LJ		 1203/* AB9540 regulator information */
1204static struct ab8500_regulator_info
1205 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1206 /*
1207 * Variable Voltage Regulators
1208 * name, min mV, max mV,
1209 * update bank, reg, mask, enable val
d3193103 1210 * volt bank, reg, mask
8e6a8d7d
LJ		 1211 */
1212 [AB9540_LDO_AUX1] = {
1213 .desc = {
1214 .name = "LDO-AUX1",
1215 .ops = &ab8500_regulator_volt_mode_ops,
1216 .type = REGULATOR_VOLTAGE,
0b946411 1217 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1218 .owner = THIS_MODULE,
1219 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1220 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1221 },
8e6a8d7d
LJ		 1222 .load_lp_uA = 5000,
1223 .update_bank = 0x04,
1224 .update_reg = 0x09,
1225 .update_mask = 0x03,
1226 .update_val = 0x01,
1227 .update_val_idle = 0x03,
1228 .update_val_normal = 0x01,
1229 .voltage_bank = 0x04,
1230 .voltage_reg = 0x1f,
1231 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1232 },
1233 [AB9540_LDO_AUX2] = {
1234 .desc = {
1235 .name = "LDO-AUX2",
1236 .ops = &ab8500_regulator_volt_mode_ops,
1237 .type = REGULATOR_VOLTAGE,
0b946411 1238 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1239 .owner = THIS_MODULE,
1240 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1241 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1242 },
8e6a8d7d
LJ		 1243 .load_lp_uA = 5000,
1244 .update_bank = 0x04,
1245 .update_reg = 0x09,
1246 .update_mask = 0x0c,
1247 .update_val = 0x04,
1248 .update_val_idle = 0x0c,
1249 .update_val_normal = 0x04,
1250 .voltage_bank = 0x04,
1251 .voltage_reg = 0x20,
1252 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1253 },
1254 [AB9540_LDO_AUX3] = {
1255 .desc = {
1256 .name = "LDO-AUX3",
1257 .ops = &ab8500_regulator_volt_mode_ops,
1258 .type = REGULATOR_VOLTAGE,
0b946411 1259 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1260 .owner = THIS_MODULE,
1261 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1262 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1263 },
8e6a8d7d
LJ		 1264 .load_lp_uA = 5000,
1265 .update_bank = 0x04,
1266 .update_reg = 0x0a,
1267 .update_mask = 0x03,
1268 .update_val = 0x01,
1269 .update_val_idle = 0x03,
1270 .update_val_normal = 0x01,
1271 .voltage_bank = 0x04,
1272 .voltage_reg = 0x21,
1273 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1274 },
1275 [AB9540_LDO_AUX4] = {
1276 .desc = {
1277 .name = "LDO-AUX4",
1278 .ops = &ab8500_regulator_volt_mode_ops,
1279 .type = REGULATOR_VOLTAGE,
1280 .id = AB9540_LDO_AUX4,
1281 .owner = THIS_MODULE,
1282 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1283 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1284 },
8e6a8d7d
LJ		 1285 .load_lp_uA = 5000,
1286 /* values for Vaux4Regu register */
1287 .update_bank = 0x04,
1288 .update_reg = 0x2e,
1289 .update_mask = 0x03,
1290 .update_val = 0x01,
1291 .update_val_idle = 0x03,
1292 .update_val_normal = 0x01,
1293 /* values for Vaux4SEL register */
1294 .voltage_bank = 0x04,
1295 .voltage_reg = 0x2f,
1296 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1297 },
1298 [AB9540_LDO_INTCORE] = {
1299 .desc = {
1300 .name = "LDO-INTCORE",
1301 .ops = &ab8500_regulator_volt_mode_ops,
1302 .type = REGULATOR_VOLTAGE,
0b946411 1303 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1304 .owner = THIS_MODULE,
1305 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1306 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1307 },
8e6a8d7d
LJ		 1308 .load_lp_uA = 5000,
1309 .update_bank = 0x03,
1310 .update_reg = 0x80,
1311 .update_mask = 0x44,
1312 .update_val = 0x44,
1313 .update_val_idle = 0x44,
1314 .update_val_normal = 0x04,
1315 .voltage_bank = 0x03,
1316 .voltage_reg = 0x80,
1317 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1318 .voltage_shift = 3,
1319 },
6909b452 1320
8e6a8d7d
LJ		 1321 /*
1322 * Fixed Voltage Regulators
1323 * name, fixed mV,
1324 * update bank, reg, mask, enable val
1325 */
1326 [AB9540_LDO_TVOUT] = {
1327 .desc = {
1328 .name = "LDO-TVOUT",
1329 .ops = &ab8500_regulator_mode_ops,
1330 .type = REGULATOR_VOLTAGE,
0b946411 1331 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1332 .owner = THIS_MODULE,
1333 .n_voltages = 1,
b080c78a 1334 .volt_table = fixed_2000000_voltage,
a4d68468 1335 .enable_time = 10000,
8e6a8d7d 1336 },
8e6a8d7d
LJ		 1337 .load_lp_uA = 1000,
1338 .update_bank = 0x03,
1339 .update_reg = 0x80,
1340 .update_mask = 0x82,
1341 .update_val = 0x02,
1342 .update_val_idle = 0x82,
1343 .update_val_normal = 0x02,
1344 },
1345 [AB9540_LDO_USB] = {
1346 .desc = {
1347 .name = "LDO-USB",
1348 .ops = &ab8500_regulator_ops,
1349 .type = REGULATOR_VOLTAGE,
1350 .id = AB9540_LDO_USB,
1351 .owner = THIS_MODULE,
1352 .n_voltages = 1,
b080c78a 1353 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1354 },
8e6a8d7d
LJ		 1355 .update_bank = 0x03,
1356 .update_reg = 0x82,
1357 .update_mask = 0x03,
1358 .update_val = 0x01,
1359 .update_val_idle = 0x03,
1360 .update_val_normal = 0x01,
1361 },
1362 [AB9540_LDO_AUDIO] = {
1363 .desc = {
1364 .name = "LDO-AUDIO",
1365 .ops = &ab8500_regulator_ops,
1366 .type = REGULATOR_VOLTAGE,
0b946411 1367 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1368 .owner = THIS_MODULE,
1369 .n_voltages = 1,
b080c78a 1370 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1371 },
8e6a8d7d
LJ		 1372 .update_bank = 0x03,
1373 .update_reg = 0x83,
1374 .update_mask = 0x02,
1375 .update_val = 0x02,
1376 },
1377 [AB9540_LDO_ANAMIC1] = {
1378 .desc = {
1379 .name = "LDO-ANAMIC1",
1380 .ops = &ab8500_regulator_ops,
1381 .type = REGULATOR_VOLTAGE,
0b946411 1382 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1383 .owner = THIS_MODULE,
1384 .n_voltages = 1,
b080c78a 1385 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1386 },
8e6a8d7d
LJ		 1387 .update_bank = 0x03,
1388 .update_reg = 0x83,
1389 .update_mask = 0x08,
1390 .update_val = 0x08,
1391 },
1392 [AB9540_LDO_ANAMIC2] = {
1393 .desc = {
1394 .name = "LDO-ANAMIC2",
1395 .ops = &ab8500_regulator_ops,
1396 .type = REGULATOR_VOLTAGE,
0b946411 1397 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1398 .owner = THIS_MODULE,
1399 .n_voltages = 1,
b080c78a 1400 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1401 },
8e6a8d7d
LJ		 1402 .update_bank = 0x03,
1403 .update_reg = 0x83,
1404 .update_mask = 0x10,
1405 .update_val = 0x10,
1406 },
1407 [AB9540_LDO_DMIC] = {
1408 .desc = {
1409 .name = "LDO-DMIC",
1410 .ops = &ab8500_regulator_ops,
1411 .type = REGULATOR_VOLTAGE,
0b946411 1412 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1413 .owner = THIS_MODULE,
1414 .n_voltages = 1,
b080c78a 1415 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1416 },
8e6a8d7d
LJ		 1417 .update_bank = 0x03,
1418 .update_reg = 0x83,
1419 .update_mask = 0x04,
1420 .update_val = 0x04,
1421 },
1422
1423 /*
1424 * Regulators with fixed voltage and normal/idle modes
1425 */
1426 [AB9540_LDO_ANA] = {
1427 .desc = {
1428 .name = "LDO-ANA",
1429 .ops = &ab8500_regulator_mode_ops,
1430 .type = REGULATOR_VOLTAGE,
0b946411 1431 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1432 .owner = THIS_MODULE,
1433 .n_voltages = 1,
b080c78a 1434 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1435 },
8e6a8d7d
LJ		 1436 .load_lp_uA = 1000,
1437 .update_bank = 0x04,
1438 .update_reg = 0x06,
1439 .update_mask = 0x0c,
1440 .update_val = 0x08,
1441 .update_val_idle = 0x0c,
1442 .update_val_normal = 0x08,
1443 },
c789ca20
SI		 1444};
1445
ae0a9a3e
LJ		 1446/* AB8540 regulator information */
1447static struct ab8500_regulator_info
1448 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1449 /*
1450 * Variable Voltage Regulators
1451 * name, min mV, max mV,
1452 * update bank, reg, mask, enable val
d3193103 1453 * volt bank, reg, mask
ae0a9a3e
LJ		 1454 */
1455 [AB8540_LDO_AUX1] = {
1456 .desc = {
1457 .name = "LDO-AUX1",
1458 .ops = &ab8500_regulator_volt_mode_ops,
1459 .type = REGULATOR_VOLTAGE,
0b946411 1460 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1461 .owner = THIS_MODULE,
1462 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1463 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1464 },
1465 .load_lp_uA = 5000,
1466 .update_bank = 0x04,
1467 .update_reg = 0x09,
1468 .update_mask = 0x03,
1469 .update_val = 0x01,
1470 .update_val_idle = 0x03,
1471 .update_val_normal = 0x01,
1472 .voltage_bank = 0x04,
1473 .voltage_reg = 0x1f,
1474 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1475 },
1476 [AB8540_LDO_AUX2] = {
1477 .desc = {
1478 .name = "LDO-AUX2",
1479 .ops = &ab8500_regulator_volt_mode_ops,
1480 .type = REGULATOR_VOLTAGE,
0b946411 1481 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1482 .owner = THIS_MODULE,
1483 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1484 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1485 },
1486 .load_lp_uA = 5000,
1487 .update_bank = 0x04,
1488 .update_reg = 0x09,
1489 .update_mask = 0x0c,
1490 .update_val = 0x04,
1491 .update_val_idle = 0x0c,
1492 .update_val_normal = 0x04,
1493 .voltage_bank = 0x04,
1494 .voltage_reg = 0x20,
1495 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1496 },
1497 [AB8540_LDO_AUX3] = {
1498 .desc = {
1499 .name = "LDO-AUX3",
d7607baf 1500 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1501 .type = REGULATOR_VOLTAGE,
0b946411 1502 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1503 .owner = THIS_MODULE,
1504 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1505 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1506 },
1507 .load_lp_uA = 5000,
1508 .update_bank = 0x04,
1509 .update_reg = 0x0a,
1510 .update_mask = 0x03,
1511 .update_val = 0x01,
1512 .update_val_idle = 0x03,
1513 .update_val_normal = 0x01,
1514 .voltage_bank = 0x04,
1515 .voltage_reg = 0x21,
1516 .voltage_mask = 0x07,
d7607baf
LJ		 1517 .expand_register = {
1518 .voltage_limit = 8,
1519 .voltage_bank = 0x04,
1520 .voltage_reg = 0x01,
1521 .voltage_mask = 0x10,
1522 .voltage_shift = 1,
1523 }
ae0a9a3e
LJ		 1524 },
1525 [AB8540_LDO_AUX4] = {
1526 .desc = {
1527 .name = "LDO-AUX4",
1528 .ops = &ab8500_regulator_volt_mode_ops,
1529 .type = REGULATOR_VOLTAGE,
0b946411 1530 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1531 .owner = THIS_MODULE,
1532 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1533 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1534 },
1535 .load_lp_uA = 5000,
1536 /* values for Vaux4Regu register */
1537 .update_bank = 0x04,
1538 .update_reg = 0x2e,
1539 .update_mask = 0x03,
1540 .update_val = 0x01,
1541 .update_val_idle = 0x03,
1542 .update_val_normal = 0x01,
1543 /* values for Vaux4SEL register */
1544 .voltage_bank = 0x04,
1545 .voltage_reg = 0x2f,
1546 .voltage_mask = 0x0f,
ae0a9a3e 1547 },
684d5ce4
ZH		 1548 [AB8540_LDO_AUX5] = {
1549 .desc = {
1550 .name = "LDO-AUX5",
1551 .ops = &ab8500_regulator_volt_mode_ops,
1552 .type = REGULATOR_VOLTAGE,
1553 .id = AB8540_LDO_AUX5,
1554 .owner = THIS_MODULE,
1555 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1556 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1557 },
1558 .load_lp_uA = 20000,
1559 /* values for Vaux5Regu register */
1560 .update_bank = 0x04,
1561 .update_reg = 0x32,
1562 .update_mask = 0x03,
1563 .update_val = 0x01,
1564 .update_val_idle = 0x03,
1565 .update_val_normal = 0x01,
1566 /* values for Vaux5SEL register */
1567 .voltage_bank = 0x04,
1568 .voltage_reg = 0x33,
1569 .voltage_mask = 0x3f,
684d5ce4
ZH		 1570 },
1571 [AB8540_LDO_AUX6] = {
1572 .desc = {
1573 .name = "LDO-AUX6",
1574 .ops = &ab8500_regulator_volt_mode_ops,
1575 .type = REGULATOR_VOLTAGE,
1576 .id = AB8540_LDO_AUX6,
1577 .owner = THIS_MODULE,
1578 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1579 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1580 },
1581 .load_lp_uA = 20000,
1582 /* values for Vaux6Regu register */
1583 .update_bank = 0x04,
1584 .update_reg = 0x35,
1585 .update_mask = 0x03,
1586 .update_val = 0x01,
1587 .update_val_idle = 0x03,
1588 .update_val_normal = 0x01,
1589 /* values for Vaux6SEL register */
1590 .voltage_bank = 0x04,
1591 .voltage_reg = 0x36,
1592 .voltage_mask = 0x3f,
684d5ce4 1593 },
ae0a9a3e
LJ		 1594 [AB8540_LDO_INTCORE] = {
1595 .desc = {
1596 .name = "LDO-INTCORE",
1597 .ops = &ab8500_regulator_volt_mode_ops,
1598 .type = REGULATOR_VOLTAGE,
0b946411 1599 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1600 .owner = THIS_MODULE,
1601 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1602 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1603 },
1604 .load_lp_uA = 5000,
1605 .update_bank = 0x03,
1606 .update_reg = 0x80,
1607 .update_mask = 0x44,
1608 .update_val = 0x44,
1609 .update_val_idle = 0x44,
1610 .update_val_normal = 0x04,
1611 .voltage_bank = 0x03,
1612 .voltage_reg = 0x80,
1613 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1614 .voltage_shift = 3,
1615 },
1616
1617 /*
1618 * Fixed Voltage Regulators
1619 * name, fixed mV,
1620 * update bank, reg, mask, enable val
1621 */
1622 [AB8540_LDO_TVOUT] = {
1623 .desc = {
1624 .name = "LDO-TVOUT",
1625 .ops = &ab8500_regulator_mode_ops,
1626 .type = REGULATOR_VOLTAGE,
0b946411 1627 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1628 .owner = THIS_MODULE,
1629 .n_voltages = 1,
aca45e9e 1630 .volt_table = fixed_2000000_voltage,
a4d68468 1631 .enable_time = 10000,
ae0a9a3e 1632 },
ae0a9a3e
LJ		 1633 .load_lp_uA = 1000,
1634 .update_bank = 0x03,
1635 .update_reg = 0x80,
1636 .update_mask = 0x82,
1637 .update_val = 0x02,
1638 .update_val_idle = 0x82,
1639 .update_val_normal = 0x02,
1640 },
1641 [AB8540_LDO_AUDIO] = {
1642 .desc = {
1643 .name = "LDO-AUDIO",
1644 .ops = &ab8500_regulator_ops,
1645 .type = REGULATOR_VOLTAGE,
0b946411 1646 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1647 .owner = THIS_MODULE,
1648 .n_voltages = 1,
b080c78a 1649 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1650 },
1651 .update_bank = 0x03,
1652 .update_reg = 0x83,
1653 .update_mask = 0x02,
1654 .update_val = 0x02,
1655 },
1656 [AB8540_LDO_ANAMIC1] = {
1657 .desc = {
1658 .name = "LDO-ANAMIC1",
4c84b4dd 1659 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1660 .type = REGULATOR_VOLTAGE,
0b946411 1661 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1662 .owner = THIS_MODULE,
1663 .n_voltages = 1,
b080c78a 1664 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1665 },
4c84b4dd 1666 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1667 .update_bank = 0x03,
1668 .update_reg = 0x83,
1669 .update_mask = 0x08,
1670 .update_val = 0x08,
4c84b4dd
LJ		 1671 .mode_bank = 0x03,
1672 .mode_reg = 0x83,
1673 .mode_mask = 0x20,
1674 .mode_val_idle = 0x20,
1675 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1676 },
1677 [AB8540_LDO_ANAMIC2] = {
1678 .desc = {
1679 .name = "LDO-ANAMIC2",
4c84b4dd 1680 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1681 .type = REGULATOR_VOLTAGE,
0b946411 1682 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1683 .owner = THIS_MODULE,
1684 .n_voltages = 1,
b080c78a 1685 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1686 },
4c84b4dd 1687 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1688 .update_bank = 0x03,
1689 .update_reg = 0x83,
1690 .update_mask = 0x10,
1691 .update_val = 0x10,
4c84b4dd
LJ		 1692 .mode_bank = 0x03,
1693 .mode_reg = 0x83,
1694 .mode_mask = 0x20,
1695 .mode_val_idle = 0x20,
1696 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1697 },
1698 [AB8540_LDO_DMIC] = {
1699 .desc = {
1700 .name = "LDO-DMIC",
4c84b4dd 1701 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1702 .type = REGULATOR_VOLTAGE,
0b946411 1703 .id = AB8540_LDO_DMIC,
ae0a9a3e 1704 .owner = THIS_MODULE,
4c84b4dd 1705 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1706 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1707 },
4c84b4dd 1708 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1709 .update_bank = 0x03,
1710 .update_reg = 0x83,
1711 .update_mask = 0x04,
1712 .update_val = 0x04,
4c84b4dd
LJ		 1713 .voltage_bank = 0x03,
1714 .voltage_reg = 0x83,
1715 .voltage_mask = 0xc0,
375dc9c1 1716 .voltage_shift = 6,
ae0a9a3e
LJ		 1717 },
1718
1719 /*
1720 * Regulators with fixed voltage and normal/idle modes
1721 */
1722 [AB8540_LDO_ANA] = {
1723 .desc = {
1724 .name = "LDO-ANA",
1725 .ops = &ab8500_regulator_mode_ops,
1726 .type = REGULATOR_VOLTAGE,
0b946411 1727 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1728 .owner = THIS_MODULE,
1729 .n_voltages = 1,
b080c78a 1730 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1731 },
1732 .load_lp_uA = 1000,
1733 .update_bank = 0x04,
1734 .update_reg = 0x06,
1735 .update_mask = 0x0c,
1736 .update_val = 0x04,
1737 .update_val_idle = 0x0c,
1738 .update_val_normal = 0x04,
1739 },
1740 [AB8540_LDO_SDIO] = {
1741 .desc = {
1742 .name = "LDO-SDIO",
1743 .ops = &ab8500_regulator_volt_mode_ops,
1744 .type = REGULATOR_VOLTAGE,
1745 .id = AB8540_LDO_SDIO,
1746 .owner = THIS_MODULE,
62ab4111
LJ		 1747 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1748 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1749 },
ae0a9a3e
LJ		 1750 .load_lp_uA = 5000,
1751 .update_bank = 0x03,
1752 .update_reg = 0x88,
1753 .update_mask = 0x30,
1754 .update_val = 0x10,
1755 .update_val_idle = 0x30,
1756 .update_val_normal = 0x10,
1757 .voltage_bank = 0x03,
1758 .voltage_reg = 0x88,
1759 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1760 },
1761};
1762
3fe52289
LJ		 1763static struct ab8500_shared_mode ldo_anamic1_shared = {
1764 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1765};
1766
1767static struct ab8500_shared_mode ldo_anamic2_shared = {
1768 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1769};
1770
4c84b4dd
LJ		 1771static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1772 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1773};
1774
1775static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1776 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1777};
1778
79568b94
BJ		 1779struct ab8500_reg_init {
1780 u8 bank;
1781 u8 addr;
1782 u8 mask;
1783};
1784
1785#define REG_INIT(_id, _bank, _addr, _mask) \
1786 [_id] = { \
1787 .bank = _bank, \
1788 .addr = _addr, \
1789 .mask = _mask, \
1790 }
1791
8e6a8d7d 1792/* AB8500 register init */
79568b94
BJ		 1793static struct ab8500_reg_init ab8500_reg_init[] = {
1794 /*
33bc8f46 1795 * 0x30, VanaRequestCtrl
79568b94
BJ		 1796 * 0xc0, VextSupply1RequestCtrl
1797 */
43a5911b 1798 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1799 /*
1800 * 0x03, VextSupply2RequestCtrl
1801 * 0x0c, VextSupply3RequestCtrl
1802 * 0x30, Vaux1RequestCtrl
1803 * 0xc0, Vaux2RequestCtrl
1804 */
1805 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1806 /*
1807 * 0x03, Vaux3RequestCtrl
1808 * 0x04, SwHPReq
1809 */
1810 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1811 /*
1812 * 0x08, VanaSysClkReq1HPValid
1813 * 0x20, Vaux1SysClkReq1HPValid
1814 * 0x40, Vaux2SysClkReq1HPValid
1815 * 0x80, Vaux3SysClkReq1HPValid
1816 */
43a5911b 1817 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1818 /*
1819 * 0x10, VextSupply1SysClkReq1HPValid
1820 * 0x20, VextSupply2SysClkReq1HPValid
1821 * 0x40, VextSupply3SysClkReq1HPValid
1822 */
43a5911b 1823 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1824 /*
1825 * 0x08, VanaHwHPReq1Valid
1826 * 0x20, Vaux1HwHPReq1Valid
1827 * 0x40, Vaux2HwHPReq1Valid
1828 * 0x80, Vaux3HwHPReq1Valid
1829 */
43a5911b 1830 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1831 /*
1832 * 0x01, VextSupply1HwHPReq1Valid
1833 * 0x02, VextSupply2HwHPReq1Valid
1834 * 0x04, VextSupply3HwHPReq1Valid
1835 */
43a5911b 1836 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1837 /*
1838 * 0x08, VanaHwHPReq2Valid
1839 * 0x20, Vaux1HwHPReq2Valid
1840 * 0x40, Vaux2HwHPReq2Valid
1841 * 0x80, Vaux3HwHPReq2Valid
1842 */
43a5911b 1843 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1844 /*
1845 * 0x01, VextSupply1HwHPReq2Valid
1846 * 0x02, VextSupply2HwHPReq2Valid
1847 * 0x04, VextSupply3HwHPReq2Valid
1848 */
43a5911b 1849 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1850 /*
1851 * 0x20, VanaSwHPReqValid
1852 * 0x80, Vaux1SwHPReqValid
1853 */
43a5911b 1854 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1855 /*
1856 * 0x01, Vaux2SwHPReqValid
1857 * 0x02, Vaux3SwHPReqValid
1858 * 0x04, VextSupply1SwHPReqValid
1859 * 0x08, VextSupply2SwHPReqValid
1860 * 0x10, VextSupply3SwHPReqValid
1861 */
43a5911b 1862 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1863 /*
1864 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1865 * 0x04, SysClkReq3Valid1
1866 * 0x08, SysClkReq4Valid1
1867 * 0x10, SysClkReq5Valid1
1868 * 0x20, SysClkReq6Valid1
1869 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1870 * 0x80, SysClkReq8Valid1
1871 */
1872 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1873 /*
1874 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1875 * 0x04, SysClkReq3Valid2
1876 * 0x08, SysClkReq4Valid2
1877 * 0x10, SysClkReq5Valid2
1878 * 0x20, SysClkReq6Valid2
1879 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1880 * 0x80, SysClkReq8Valid2
1881 */
1882 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1883 /*
1884 * 0x02, VTVoutEna
1885 * 0x04, Vintcore12Ena
1886 * 0x38, Vintcore12Sel
1887 * 0x40, Vintcore12LP
1888 * 0x80, VTVoutLP
1889 */
1890 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1891 /*
1892 * 0x02, VaudioEna
1893 * 0x04, VdmicEna
1894 * 0x08, Vamic1Ena
1895 * 0x10, Vamic2Ena
1896 */
1897 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1898 /*
1899 * 0x01, Vamic1_dzout
1900 * 0x02, Vamic2_dzout
1901 */
1902 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1903 /*
43a5911b 1904 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1905 * 0x0c, VanaRegu
79568b94
BJ		 1906 */
1907 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1908 /*
1909 * 0x01, VrefDDREna
1910 * 0x02, VrefDDRSleepMode
1911 */
1912 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1913 /*
1914 * 0x03, VextSupply1Regu
1915 * 0x0c, VextSupply2Regu
1916 * 0x30, VextSupply3Regu
1917 * 0x40, ExtSupply2Bypass
1918 * 0x80, ExtSupply3Bypass
1919 */
1920 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1921 /*
1922 * 0x03, Vaux1Regu
1923 * 0x0c, Vaux2Regu
1924 */
1925 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1926 /*
1927 * 0x03, Vaux3Regu
1928 */
43a5911b 1929 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1930 /*
1931 * 0x0f, Vaux1Sel
1932 */
1933 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1934 /*
1935 * 0x0f, Vaux2Sel
1936 */
1937 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1938 /*
1939 * 0x07, Vaux3Sel
1940 */
43a5911b 1941 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1942 /*
1943 * 0x01, VextSupply12LP
1944 */
1945 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1946 /*
1947 * 0x04, Vaux1Disch
1948 * 0x08, Vaux2Disch
1949 * 0x10, Vaux3Disch
1950 * 0x20, Vintcore12Disch
1951 * 0x40, VTVoutDisch
1952 * 0x80, VaudioDisch
1953 */
43a5911b 1954 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1955 /*
1956 * 0x02, VanaDisch
1957 * 0x04, VdmicPullDownEna
1958 * 0x10, VdmicDisch
1959 */
43a5911b 1960 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1961};
1962
547f384f
LJ		 1963/* AB8505 register init */
1964static struct ab8500_reg_init ab8505_reg_init[] = {
1965 /*
1966 * 0x03, VarmRequestCtrl
1967 * 0x0c, VsmpsCRequestCtrl
1968 * 0x30, VsmpsARequestCtrl
1969 * 0xc0, VsmpsBRequestCtrl
1970 */
1971 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1972 /*
1973 * 0x03, VsafeRequestCtrl
1974 * 0x0c, VpllRequestCtrl
1975 * 0x30, VanaRequestCtrl
1976 */
1977 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1978 /*
1979 * 0x30, Vaux1RequestCtrl
1980 * 0xc0, Vaux2RequestCtrl
1981 */
1982 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1983 /*
1984 * 0x03, Vaux3RequestCtrl
1985 * 0x04, SwHPReq
1986 */
1987 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1988 /*
1989 * 0x01, VsmpsASysClkReq1HPValid
1990 * 0x02, VsmpsBSysClkReq1HPValid
1991 * 0x04, VsafeSysClkReq1HPValid
1992 * 0x08, VanaSysClkReq1HPValid
1993 * 0x10, VpllSysClkReq1HPValid
1994 * 0x20, Vaux1SysClkReq1HPValid
1995 * 0x40, Vaux2SysClkReq1HPValid
1996 * 0x80, Vaux3SysClkReq1HPValid
1997 */
1998 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1999 /*
2000 * 0x01, VsmpsCSysClkReq1HPValid
2001 * 0x02, VarmSysClkReq1HPValid
2002 * 0x04, VbbSysClkReq1HPValid
2003 * 0x08, VsmpsMSysClkReq1HPValid
2004 */
2005 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2006 /*
2007 * 0x01, VsmpsAHwHPReq1Valid
2008 * 0x02, VsmpsBHwHPReq1Valid
2009 * 0x04, VsafeHwHPReq1Valid
2010 * 0x08, VanaHwHPReq1Valid
2011 * 0x10, VpllHwHPReq1Valid
2012 * 0x20, Vaux1HwHPReq1Valid
2013 * 0x40, Vaux2HwHPReq1Valid
2014 * 0x80, Vaux3HwHPReq1Valid
2015 */
2016 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2017 /*
2018 * 0x08, VsmpsMHwHPReq1Valid
2019 */
2020 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2021 /*
2022 * 0x01, VsmpsAHwHPReq2Valid
2023 * 0x02, VsmpsBHwHPReq2Valid
2024 * 0x04, VsafeHwHPReq2Valid
2025 * 0x08, VanaHwHPReq2Valid
2026 * 0x10, VpllHwHPReq2Valid
2027 * 0x20, Vaux1HwHPReq2Valid
2028 * 0x40, Vaux2HwHPReq2Valid
2029 * 0x80, Vaux3HwHPReq2Valid
2030 */
2031 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2032 /*
2033 * 0x08, VsmpsMHwHPReq2Valid
2034 */
2035 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2036 /*
2037 * 0x01, VsmpsCSwHPReqValid
2038 * 0x02, VarmSwHPReqValid
2039 * 0x04, VsmpsASwHPReqValid
2040 * 0x08, VsmpsBSwHPReqValid
2041 * 0x10, VsafeSwHPReqValid
2042 * 0x20, VanaSwHPReqValid
2043 * 0x40, VpllSwHPReqValid
2044 * 0x80, Vaux1SwHPReqValid
2045 */
2046 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2047 /*
2048 * 0x01, Vaux2SwHPReqValid
2049 * 0x02, Vaux3SwHPReqValid
2050 * 0x20, VsmpsMSwHPReqValid
2051 */
2052 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2053 /*
2054 * 0x02, SysClkReq2Valid1
2055 * 0x04, SysClkReq3Valid1
2056 * 0x08, SysClkReq4Valid1
2057 */
2058 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2059 /*
2060 * 0x02, SysClkReq2Valid2
2061 * 0x04, SysClkReq3Valid2
2062 * 0x08, SysClkReq4Valid2
2063 */
2064 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2065 /*
2066 * 0x01, Vaux4SwHPReqValid
2067 * 0x02, Vaux4HwHPReq2Valid
2068 * 0x04, Vaux4HwHPReq1Valid
2069 * 0x08, Vaux4SysClkReq1HPValid
2070 */
2071 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2072 /*
2073 * 0x02, VadcEna
2074 * 0x04, VintCore12Ena
2075 * 0x38, VintCore12Sel
2076 * 0x40, VintCore12LP
2077 * 0x80, VadcLP
2078 */
2079 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2080 /*
2081 * 0x02, VaudioEna
2082 * 0x04, VdmicEna
2083 * 0x08, Vamic1Ena
2084 * 0x10, Vamic2Ena
2085 */
2086 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2087 /*
2088 * 0x01, Vamic1_dzout
2089 * 0x02, Vamic2_dzout
2090 */
2091 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2092 /*
2093 * 0x03, VsmpsARegu
2094 * 0x0c, VsmpsASelCtrl
2095 * 0x10, VsmpsAAutoMode
2096 * 0x20, VsmpsAPWMMode
2097 */
2098 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2099 /*
2100 * 0x03, VsmpsBRegu
2101 * 0x0c, VsmpsBSelCtrl
2102 * 0x10, VsmpsBAutoMode
2103 * 0x20, VsmpsBPWMMode
2104 */
2105 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2106 /*
2107 * 0x03, VsafeRegu
2108 * 0x0c, VsafeSelCtrl
2109 * 0x10, VsafeAutoMode
2110 * 0x20, VsafePWMMode
2111 */
2112 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2113 /*
2114 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2115 * 0x0c, VanaRegu
2116 */
2117 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2118 /*
2119 * 0x03, VextSupply1Regu
2120 * 0x0c, VextSupply2Regu
2121 * 0x30, VextSupply3Regu
2122 * 0x40, ExtSupply2Bypass
2123 * 0x80, ExtSupply3Bypass
2124 */
2125 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2126 /*
2127 * 0x03, Vaux1Regu
2128 * 0x0c, Vaux2Regu
2129 */
2130 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2131 /*
2132 * 0x0f, Vaux3Regu
2133 */
2134 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2135 /*
2136 * 0x3f, VsmpsASel1
2137 */
2138 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2139 /*
2140 * 0x3f, VsmpsASel2
2141 */
2142 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2143 /*
2144 * 0x3f, VsmpsASel3
2145 */
2146 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2147 /*
2148 * 0x3f, VsmpsBSel1
2149 */
2150 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2151 /*
2152 * 0x3f, VsmpsBSel2
2153 */
2154 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2155 /*
2156 * 0x3f, VsmpsBSel3
2157 */
2158 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2159 /*
2160 * 0x7f, VsafeSel1
2161 */
2162 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2163 /*
2164 * 0x3f, VsafeSel2
2165 */
2166 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2167 /*
2168 * 0x3f, VsafeSel3
2169 */
2170 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2171 /*
2172 * 0x0f, Vaux1Sel
2173 */
2174 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2175 /*
2176 * 0x0f, Vaux2Sel
2177 */
2178 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2179 /*
2180 * 0x07, Vaux3Sel
2181 * 0x30, VRF1Sel
2182 */
2183 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2184 /*
2185 * 0x03, Vaux4RequestCtrl
2186 */
2187 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2188 /*
2189 * 0x03, Vaux4Regu
2190 */
2191 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2192 /*
2193 * 0x0f, Vaux4Sel
2194 */
2195 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2196 /*
2197 * 0x04, Vaux1Disch
2198 * 0x08, Vaux2Disch
2199 * 0x10, Vaux3Disch
2200 * 0x20, Vintcore12Disch
2201 * 0x40, VTVoutDisch
2202 * 0x80, VaudioDisch
2203 */
2204 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2205 /*
2206 * 0x02, VanaDisch
2207 * 0x04, VdmicPullDownEna
2208 * 0x10, VdmicDisch
2209 */
2210 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2211 /*
2212 * 0x01, Vaux4Disch
2213 */
2214 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2215 /*
2216 * 0x07, Vaux5Sel
2217 * 0x08, Vaux5LP
2218 * 0x10, Vaux5Ena
2219 * 0x20, Vaux5Disch
2220 * 0x40, Vaux5DisSfst
2221 * 0x80, Vaux5DisPulld
2222 */
2223 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2224 /*
2225 * 0x07, Vaux6Sel
2226 * 0x08, Vaux6LP
2227 * 0x10, Vaux6Ena
2228 * 0x80, Vaux6DisPulld
2229 */
2230 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2231};
2232
8e6a8d7d
LJ		 2233/* AB9540 register init */
2234static struct ab8500_reg_init ab9540_reg_init[] = {
2235 /*
2236 * 0x03, VarmRequestCtrl
2237 * 0x0c, VapeRequestCtrl
2238 * 0x30, Vsmps1RequestCtrl
2239 * 0xc0, Vsmps2RequestCtrl
2240 */
2241 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2242 /*
2243 * 0x03, Vsmps3RequestCtrl
2244 * 0x0c, VpllRequestCtrl
2245 * 0x30, VanaRequestCtrl
2246 * 0xc0, VextSupply1RequestCtrl
2247 */
2248 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2249 /*
2250 * 0x03, VextSupply2RequestCtrl
2251 * 0x0c, VextSupply3RequestCtrl
2252 * 0x30, Vaux1RequestCtrl
2253 * 0xc0, Vaux2RequestCtrl
2254 */
2255 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2256 /*
2257 * 0x03, Vaux3RequestCtrl
2258 * 0x04, SwHPReq
2259 */
2260 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2261 /*
2262 * 0x01, Vsmps1SysClkReq1HPValid
2263 * 0x02, Vsmps2SysClkReq1HPValid
2264 * 0x04, Vsmps3SysClkReq1HPValid
2265 * 0x08, VanaSysClkReq1HPValid
2266 * 0x10, VpllSysClkReq1HPValid
2267 * 0x20, Vaux1SysClkReq1HPValid
2268 * 0x40, Vaux2SysClkReq1HPValid
2269 * 0x80, Vaux3SysClkReq1HPValid
2270 */
2271 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2272 /*
2273 * 0x01, VapeSysClkReq1HPValid
2274 * 0x02, VarmSysClkReq1HPValid
2275 * 0x04, VbbSysClkReq1HPValid
2276 * 0x08, VmodSysClkReq1HPValid
2277 * 0x10, VextSupply1SysClkReq1HPValid
2278 * 0x20, VextSupply2SysClkReq1HPValid
2279 * 0x40, VextSupply3SysClkReq1HPValid
2280 */
2281 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2282 /*
2283 * 0x01, Vsmps1HwHPReq1Valid
2284 * 0x02, Vsmps2HwHPReq1Valid
2285 * 0x04, Vsmps3HwHPReq1Valid
2286 * 0x08, VanaHwHPReq1Valid
2287 * 0x10, VpllHwHPReq1Valid
2288 * 0x20, Vaux1HwHPReq1Valid
2289 * 0x40, Vaux2HwHPReq1Valid
2290 * 0x80, Vaux3HwHPReq1Valid
2291 */
2292 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2293 /*
2294 * 0x01, VextSupply1HwHPReq1Valid
2295 * 0x02, VextSupply2HwHPReq1Valid
2296 * 0x04, VextSupply3HwHPReq1Valid
2297 * 0x08, VmodHwHPReq1Valid
2298 */
2299 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2300 /*
2301 * 0x01, Vsmps1HwHPReq2Valid
2302 * 0x02, Vsmps2HwHPReq2Valid
2303 * 0x03, Vsmps3HwHPReq2Valid
2304 * 0x08, VanaHwHPReq2Valid
2305 * 0x10, VpllHwHPReq2Valid
2306 * 0x20, Vaux1HwHPReq2Valid
2307 * 0x40, Vaux2HwHPReq2Valid
2308 * 0x80, Vaux3HwHPReq2Valid
2309 */
2310 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2311 /*
2312 * 0x01, VextSupply1HwHPReq2Valid
2313 * 0x02, VextSupply2HwHPReq2Valid
2314 * 0x04, VextSupply3HwHPReq2Valid
2315 * 0x08, VmodHwHPReq2Valid
2316 */
2317 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2318 /*
2319 * 0x01, VapeSwHPReqValid
2320 * 0x02, VarmSwHPReqValid
2321 * 0x04, Vsmps1SwHPReqValid
2322 * 0x08, Vsmps2SwHPReqValid
2323 * 0x10, Vsmps3SwHPReqValid
2324 * 0x20, VanaSwHPReqValid
2325 * 0x40, VpllSwHPReqValid
2326 * 0x80, Vaux1SwHPReqValid
2327 */
2328 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2329 /*
2330 * 0x01, Vaux2SwHPReqValid
2331 * 0x02, Vaux3SwHPReqValid
2332 * 0x04, VextSupply1SwHPReqValid
2333 * 0x08, VextSupply2SwHPReqValid
2334 * 0x10, VextSupply3SwHPReqValid
2335 * 0x20, VmodSwHPReqValid
2336 */
2337 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2338 /*
2339 * 0x02, SysClkReq2Valid1
2340 * ...
2341 * 0x80, SysClkReq8Valid1
2342 */
2343 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2344 /*
2345 * 0x02, SysClkReq2Valid2
2346 * ...
2347 * 0x80, SysClkReq8Valid2
2348 */
2349 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2350 /*
2351 * 0x01, Vaux4SwHPReqValid
2352 * 0x02, Vaux4HwHPReq2Valid
2353 * 0x04, Vaux4HwHPReq1Valid
2354 * 0x08, Vaux4SysClkReq1HPValid
2355 */
2356 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2357 /*
2358 * 0x02, VTVoutEna
2359 * 0x04, Vintcore12Ena
2360 * 0x38, Vintcore12Sel
2361 * 0x40, Vintcore12LP
2362 * 0x80, VTVoutLP
2363 */
2364 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2365 /*
2366 * 0x02, VaudioEna
2367 * 0x04, VdmicEna
2368 * 0x08, Vamic1Ena
2369 * 0x10, Vamic2Ena
2370 */
2371 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2372 /*
2373 * 0x01, Vamic1_dzout
2374 * 0x02, Vamic2_dzout
2375 */
2376 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2377 /*
2378 * 0x03, Vsmps1Regu
2379 * 0x0c, Vsmps1SelCtrl
2380 * 0x10, Vsmps1AutoMode
2381 * 0x20, Vsmps1PWMMode
2382 */
2383 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2384 /*
2385 * 0x03, Vsmps2Regu
2386 * 0x0c, Vsmps2SelCtrl
2387 * 0x10, Vsmps2AutoMode
2388 * 0x20, Vsmps2PWMMode
2389 */
2390 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2391 /*
2392 * 0x03, Vsmps3Regu
2393 * 0x0c, Vsmps3SelCtrl
2394 * NOTE! PRCMU register
2395 */
2396 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2397 /*
2398 * 0x03, VpllRegu
2399 * 0x0c, VanaRegu
2400 */
2401 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2402 /*
2403 * 0x03, VextSupply1Regu
2404 * 0x0c, VextSupply2Regu
2405 * 0x30, VextSupply3Regu
2406 * 0x40, ExtSupply2Bypass
2407 * 0x80, ExtSupply3Bypass
2408 */
2409 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2410 /*
2411 * 0x03, Vaux1Regu
2412 * 0x0c, Vaux2Regu
2413 */
2414 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2415 /*
2416 * 0x0c, Vrf1Regu
2417 * 0x03, Vaux3Regu
2418 */
2419 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2420 /*
2421 * 0x3f, Vsmps1Sel1
2422 */
2423 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2424 /*
2425 * 0x3f, Vsmps1Sel2
2426 */
2427 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2428 /*
2429 * 0x3f, Vsmps1Sel3
2430 */
2431 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2432 /*
2433 * 0x3f, Vsmps2Sel1
2434 */
2435 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2436 /*
2437 * 0x3f, Vsmps2Sel2
2438 */
2439 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2440 /*
2441 * 0x3f, Vsmps2Sel3
2442 */
2443 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2444 /*
2445 * 0x7f, Vsmps3Sel1
2446 * NOTE! PRCMU register
2447 */
2448 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2449 /*
2450 * 0x7f, Vsmps3Sel2
2451 * NOTE! PRCMU register
2452 */
2453 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2454 /*
2455 * 0x0f, Vaux1Sel
2456 */
2457 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2458 /*
2459 * 0x0f, Vaux2Sel
2460 */
2461 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2462 /*
2463 * 0x07, Vaux3Sel
2464 * 0x30, Vrf1Sel
2465 */
2466 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2467 /*
2468 * 0x01, VextSupply12LP
2469 */
2470 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2471 /*
2472 * 0x03, Vaux4RequestCtrl
2473 */
2474 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2475 /*
2476 * 0x03, Vaux4Regu
2477 */
2478 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2479 /*
2480 * 0x08, Vaux4Sel
2481 */
2482 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2483 /*
2484 * 0x01, VpllDisch
2485 * 0x02, Vrf1Disch
2486 * 0x04, Vaux1Disch
2487 * 0x08, Vaux2Disch
2488 * 0x10, Vaux3Disch
2489 * 0x20, Vintcore12Disch
2490 * 0x40, VTVoutDisch
2491 * 0x80, VaudioDisch
2492 */
2493 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2494 /*
2495 * 0x01, VsimDisch
2496 * 0x02, VanaDisch
2497 * 0x04, VdmicPullDownEna
2498 * 0x08, VpllPullDownEna
2499 * 0x10, VdmicDisch
2500 */
2501 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2502 /*
2503 * 0x01, Vaux4Disch
2504 */
2505 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2506};
2507
ae0a9a3e
LJ		 2508/* AB8540 register init */
2509static struct ab8500_reg_init ab8540_reg_init[] = {
2510 /*
2511 * 0x01, VSimSycClkReq1Valid
2512 * 0x02, VSimSycClkReq2Valid
2513 * 0x04, VSimSycClkReq3Valid
2514 * 0x08, VSimSycClkReq4Valid
2515 * 0x10, VSimSycClkReq5Valid
2516 * 0x20, VSimSycClkReq6Valid
2517 * 0x40, VSimSycClkReq7Valid
2518 * 0x80, VSimSycClkReq8Valid
2519 */
2520 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2521 /*
2522 * 0x03, VarmRequestCtrl
2523 * 0x0c, VapeRequestCtrl
2524 * 0x30, Vsmps1RequestCtrl
2525 * 0xc0, Vsmps2RequestCtrl
2526 */
2527 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2528 /*
2529 * 0x03, Vsmps3RequestCtrl
2530 * 0x0c, VpllRequestCtrl
2531 * 0x30, VanaRequestCtrl
2532 * 0xc0, VextSupply1RequestCtrl
2533 */
2534 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2535 /*
2536 * 0x03, VextSupply2RequestCtrl
2537 * 0x0c, VextSupply3RequestCtrl
2538 * 0x30, Vaux1RequestCtrl
2539 * 0xc0, Vaux2RequestCtrl
2540 */
2541 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2542 /*
2543 * 0x03, Vaux3RequestCtrl
2544 * 0x04, SwHPReq
2545 */
2546 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2547 /*
2548 * 0x01, Vsmps1SysClkReq1HPValid
2549 * 0x02, Vsmps2SysClkReq1HPValid
2550 * 0x04, Vsmps3SysClkReq1HPValid
2551 * 0x08, VanaSysClkReq1HPValid
2552 * 0x10, VpllSysClkReq1HPValid
2553 * 0x20, Vaux1SysClkReq1HPValid
2554 * 0x40, Vaux2SysClkReq1HPValid
2555 * 0x80, Vaux3SysClkReq1HPValid
2556 */
2557 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2558 /*
2559 * 0x01, VapeSysClkReq1HPValid
2560 * 0x02, VarmSysClkReq1HPValid
2561 * 0x04, VbbSysClkReq1HPValid
2562 * 0x10, VextSupply1SysClkReq1HPValid
2563 * 0x20, VextSupply2SysClkReq1HPValid
2564 * 0x40, VextSupply3SysClkReq1HPValid
2565 */
2566 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2567 /*
2568 * 0x01, Vsmps1HwHPReq1Valid
2569 * 0x02, Vsmps2HwHPReq1Valid
2570 * 0x04, Vsmps3HwHPReq1Valid
2571 * 0x08, VanaHwHPReq1Valid
2572 * 0x10, VpllHwHPReq1Valid
2573 * 0x20, Vaux1HwHPReq1Valid
2574 * 0x40, Vaux2HwHPReq1Valid
2575 * 0x80, Vaux3HwHPReq1Valid
2576 */
2577 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2578 /*
2579 * 0x01, VextSupply1HwHPReq1Valid
2580 * 0x02, VextSupply2HwHPReq1Valid
2581 * 0x04, VextSupply3HwHPReq1Valid
2582 */
2583 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2584 /*
2585 * 0x01, Vsmps1HwHPReq2Valid
2586 * 0x02, Vsmps2HwHPReq2Valid
2587 * 0x03, Vsmps3HwHPReq2Valid
2588 * 0x08, VanaHwHPReq2Valid
2589 * 0x10, VpllHwHPReq2Valid
2590 * 0x20, Vaux1HwHPReq2Valid
2591 * 0x40, Vaux2HwHPReq2Valid
2592 * 0x80, Vaux3HwHPReq2Valid
2593 */
2594 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2595 /*
2596 * 0x01, VextSupply1HwHPReq2Valid
2597 * 0x02, VextSupply2HwHPReq2Valid
2598 * 0x04, VextSupply3HwHPReq2Valid
2599 */
2600 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2601 /*
2602 * 0x01, VapeSwHPReqValid
2603 * 0x02, VarmSwHPReqValid
2604 * 0x04, Vsmps1SwHPReqValid
2605 * 0x08, Vsmps2SwHPReqValid
2606 * 0x10, Vsmps3SwHPReqValid
2607 * 0x20, VanaSwHPReqValid
2608 * 0x40, VpllSwHPReqValid
2609 * 0x80, Vaux1SwHPReqValid
2610 */
2611 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2612 /*
2613 * 0x01, Vaux2SwHPReqValid
2614 * 0x02, Vaux3SwHPReqValid
2615 * 0x04, VextSupply1SwHPReqValid
2616 * 0x08, VextSupply2SwHPReqValid
2617 * 0x10, VextSupply3SwHPReqValid
2618 */
2619 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2620 /*
2621 * 0x02, SysClkReq2Valid1
2622 * ...
2623 * 0x80, SysClkReq8Valid1
2624 */
2625 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2626 /*
2627 * 0x02, SysClkReq2Valid2
2628 * ...
2629 * 0x80, SysClkReq8Valid2
2630 */
2631 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2632 /*
2633 * 0x01, Vaux4SwHPReqValid
2634 * 0x02, Vaux4HwHPReq2Valid
2635 * 0x04, Vaux4HwHPReq1Valid
2636 * 0x08, Vaux4SysClkReq1HPValid
2637 */
2638 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2639 /*
2640 * 0x01, Vaux5SwHPReqValid
2641 * 0x02, Vaux5HwHPReq2Valid
2642 * 0x04, Vaux5HwHPReq1Valid
2643 * 0x08, Vaux5SysClkReq1HPValid
2644 */
2645 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2646 /*
2647 * 0x01, Vaux6SwHPReqValid
2648 * 0x02, Vaux6HwHPReq2Valid
2649 * 0x04, Vaux6HwHPReq1Valid
2650 * 0x08, Vaux6SysClkReq1HPValid
2651 */
2652 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2653 /*
2654 * 0x01, VclkbSwHPReqValid
2655 * 0x02, VclkbHwHPReq2Valid
2656 * 0x04, VclkbHwHPReq1Valid
2657 * 0x08, VclkbSysClkReq1HPValid
2658 */
2659 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2660 /*
2661 * 0x01, Vrf1SwHPReqValid
2662 * 0x02, Vrf1HwHPReq2Valid
2663 * 0x04, Vrf1HwHPReq1Valid
2664 * 0x08, Vrf1SysClkReq1HPValid
2665 */
2666 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2667 /*
2668 * 0x02, VTVoutEna
2669 * 0x04, Vintcore12Ena
2670 * 0x38, Vintcore12Sel
2671 * 0x40, Vintcore12LP
2672 * 0x80, VTVoutLP
2673 */
2674 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2675 /*
2676 * 0x02, VaudioEna
2677 * 0x04, VdmicEna
2678 * 0x08, Vamic1Ena
2679 * 0x10, Vamic2Ena
2680 * 0x20, Vamic12LP
2681 * 0xC0, VdmicSel
2682 */
2683 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2684 /*
2685 * 0x01, Vamic1_dzout
2686 * 0x02, Vamic2_dzout
2687 */
2688 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2689 /*
2690 * 0x07, VHSICSel
2691 * 0x08, VHSICOffState
2692 * 0x10, VHSIEna
2693 * 0x20, VHSICLP
2694 */
2695 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2696 /*
2697 * 0x07, VSDIOSel
2698 * 0x08, VSDIOOffState
2699 * 0x10, VSDIOEna
2700 * 0x20, VSDIOLP
2701 */
2702 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2703 /*
2704 * 0x03, Vsmps1Regu
2705 * 0x0c, Vsmps1SelCtrl
2706 * 0x10, Vsmps1AutoMode
2707 * 0x20, Vsmps1PWMMode
2708 */
2709 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2710 /*
2711 * 0x03, Vsmps2Regu
2712 * 0x0c, Vsmps2SelCtrl
2713 * 0x10, Vsmps2AutoMode
2714 * 0x20, Vsmps2PWMMode
2715 */
2716 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2717 /*
2718 * 0x03, Vsmps3Regu
2719 * 0x0c, Vsmps3SelCtrl
2720 * 0x10, Vsmps3AutoMode
2721 * 0x20, Vsmps3PWMMode
2722 * NOTE! PRCMU register
2723 */
2724 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2725 /*
2726 * 0x03, VpllRegu
2727 * 0x0c, VanaRegu
2728 */
2729 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2730 /*
2731 * 0x03, VextSupply1Regu
2732 * 0x0c, VextSupply2Regu
2733 * 0x30, VextSupply3Regu
2734 * 0x40, ExtSupply2Bypass
2735 * 0x80, ExtSupply3Bypass
2736 */
2737 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2738 /*
2739 * 0x03, Vaux1Regu
2740 * 0x0c, Vaux2Regu
2741 */
2742 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2743 /*
2744 * 0x0c, VRF1Regu
2745 * 0x03, Vaux3Regu
2746 */
2747 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2748 /*
2749 * 0x3f, Vsmps1Sel1
2750 */
2751 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2752 /*
2753 * 0x3f, Vsmps1Sel2
2754 */
2755 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2756 /*
2757 * 0x3f, Vsmps1Sel3
2758 */
2759 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2760 /*
2761 * 0x3f, Vsmps2Sel1
2762 */
2763 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2764 /*
2765 * 0x3f, Vsmps2Sel2
2766 */
2767 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2768 /*
2769 * 0x3f, Vsmps2Sel3
2770 */
2771 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2772 /*
2773 * 0x7f, Vsmps3Sel1
2774 * NOTE! PRCMU register
2775 */
2776 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2777 /*
2778 * 0x7f, Vsmps3Sel2
2779 * NOTE! PRCMU register
2780 */
2781 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2782 /*
2783 * 0x0f, Vaux1Sel
2784 */
2785 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2786 /*
2787 * 0x0f, Vaux2Sel
2788 */
2789 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2790 /*
2791 * 0x07, Vaux3Sel
2792 * 0x70, Vrf1Sel
2793 */
2794 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2795 /*
2796 * 0x01, VextSupply12LP
2797 */
2798 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2799 /*
2800 * 0x07, Vanasel
2801 * 0x30, Vpllsel
2802 */
2803 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2804 /*
2805 * 0x03, Vaux4RequestCtrl
2806 */
2807 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2808 /*
2809 * 0x03, Vaux4Regu
2810 */
2811 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2812 /*
2813 * 0x0f, Vaux4Sel
2814 */
2815 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2816 /*
2817 * 0x03, Vaux5RequestCtrl
2818 */
2819 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2820 /*
2821 * 0x03, Vaux5Regu
2822 */
2823 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2824 /*
2825 * 0x3f, Vaux5Sel
2826 */
2827 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2828 /*
2829 * 0x03, Vaux6RequestCtrl
2830 */
2831 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2832 /*
2833 * 0x03, Vaux6Regu
2834 */
2835 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2836 /*
2837 * 0x3f, Vaux6Sel
2838 */
2839 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2840 /*
2841 * 0x03, VCLKBRequestCtrl
2842 */
2843 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2844 /*
2845 * 0x03, VCLKBRegu
2846 */
2847 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2848 /*
2849 * 0x07, VCLKBSel
2850 */
2851 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2852 /*
2853 * 0x03, Vrf1RequestCtrl
2854 */
2855 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2856 /*
2857 * 0x01, VpllDisch
2858 * 0x02, Vrf1Disch
2859 * 0x04, Vaux1Disch
2860 * 0x08, Vaux2Disch
2861 * 0x10, Vaux3Disch
2862 * 0x20, Vintcore12Disch
2863 * 0x40, VTVoutDisch
2864 * 0x80, VaudioDisch
2865 */
2866 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2867 /*
2868 * 0x02, VanaDisch
2869 * 0x04, VdmicPullDownEna
2870 * 0x08, VpllPullDownEna
2871 * 0x10, VdmicDisch
2872 */
2873 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2874 /*
2875 * 0x01, Vaux4Disch
2876 */
2877 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2878 /*
2879 * 0x01, Vaux5Disch
2880 * 0x02, Vaux6Disch
2881 * 0x04, VCLKBDisch
2882 */
2883 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2884};
2885
b54969ac 2886static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2887 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2888 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2889 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2890 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2891 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2892 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2893 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2894 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2895 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2896 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2897};
2898
547f384f
LJ		 2899static struct of_regulator_match ab8505_regulator_match[] = {
2900 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2901 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2902 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2903 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2904 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2905 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2906 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2907 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2908 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2909 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2910 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2911 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2912 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2913};
2914
ae0a9a3e
LJ		 2915static struct of_regulator_match ab8540_regulator_match[] = {
2916 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2917 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2918 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2919 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2920 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2921 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2922 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2923 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2924 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2925 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2926 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2927 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2928 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2929 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2930};
2931
8e6a8d7d
LJ		 2932static struct of_regulator_match ab9540_regulator_match[] = {
2933 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2934 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2935 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2936 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2937 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2938 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2939 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2940 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2941 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2942 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2943 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2944};
2945
da45edc7
LJ		 2946static struct {
2947 struct ab8500_regulator_info *info;
2948 int info_size;
2949 struct ab8500_reg_init *init;
2950 int init_size;
2951 struct of_regulator_match *match;
2952 int match_size;
2953} abx500_regulator;
2954
33aeb49e
LJ		 2955static void abx500_get_regulator_info(struct ab8500 *ab8500)
2956{
2957 if (is_ab9540(ab8500)) {
2958 abx500_regulator.info = ab9540_regulator_info;
2959 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2960 abx500_regulator.init = ab9540_reg_init;
2961 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2962 abx500_regulator.match = ab9540_regulator_match;
2963 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2964 } else if (is_ab8505(ab8500)) {
2965 abx500_regulator.info = ab8505_regulator_info;
2966 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2967 abx500_regulator.init = ab8505_reg_init;
2968 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2969 abx500_regulator.match = ab8505_regulator_match;
2970 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2971 } else if (is_ab8540(ab8500)) {
2972 abx500_regulator.info = ab8540_regulator_info;
2973 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2974 abx500_regulator.init = ab8540_reg_init;
2975 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2976 abx500_regulator.match = ab8540_regulator_match;
2977 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2978 } else {
2979 abx500_regulator.info = ab8500_regulator_info;
2980 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2981 abx500_regulator.init = ab8500_reg_init;
2982 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2983 abx500_regulator.match = ab8500_regulator_match;
2984 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
2985 }
2986}
2987
da45edc7
LJ		 2988static int ab8500_regulator_init_registers(struct platform_device *pdev,
2989 int id, int mask, int value)
2990{
2991 struct ab8500_reg_init *reg_init = abx500_regulator.init;
2992 int err;
2993
2994 BUG_ON(value & ~mask);
2995 BUG_ON(mask & ~reg_init[id].mask);
2996
2997 /* initialize register */
2998 err = abx500_mask_and_set_register_interruptible(
2999 &pdev->dev,
3000 reg_init[id].bank,
3001 reg_init[id].addr,
3002 mask, value);
3003 if (err < 0) {
3004 dev_err(&pdev->dev,
3005 "Failed to initialize 0x%02x, 0x%02x.\n",
3006 reg_init[id].bank,
3007 reg_init[id].addr);
3008 return err;
3009 }
3010 dev_vdbg(&pdev->dev,
3011 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3012 reg_init[id].bank,
3013 reg_init[id].addr,
3014 mask, value);
3015
3016 return 0;
3017}
3018
3019static int ab8500_regulator_register(struct platform_device *pdev,
3020 struct regulator_init_data *init_data,
3021 int id, struct device_node *np)
3022{
3023 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3024 struct ab8500_regulator_info *info = NULL;
3025 struct regulator_config config = { };
3026 int err;
3027
3028 /* assign per-regulator data */
3029 info = &abx500_regulator.info[id];
3030 info->dev = &pdev->dev;
3031
3032 config.dev = &pdev->dev;
3033 config.init_data = init_data;
3034 config.driver_data = info;
3035 config.of_node = np;
3036
3037 /* fix for hardware before ab8500v2.0 */
3038 if (is_ab8500_1p1_or_earlier(ab8500)) {
3039 if (info->desc.id == AB8500_LDO_AUX3) {
3040 info->desc.n_voltages =
3041 ARRAY_SIZE(ldo_vauxn_voltages);
3042 info->desc.volt_table = ldo_vauxn_voltages;
3043 info->voltage_mask = 0xf;
3044 }
3045 }
3046
3047 /* register regulator with framework */
3048 info->regulator = regulator_register(&info->desc, &config);
3049 if (IS_ERR(info->regulator)) {
3050 err = PTR_ERR(info->regulator);
3051 dev_err(&pdev->dev, "failed to register regulator %s\n",
3052 info->desc.name);
3053 /* when we fail, un-register all earlier regulators */
3054 while (--id >= 0) {
3055 info = &abx500_regulator.info[id];
3056 regulator_unregister(info->regulator);
3057 }
3058 return err;
3059 }
3060
3061 return 0;
3062}
3063
a5023574 3064static int
b54969ac 3065ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3066 struct device_node *np)
3a8334b9 3067{
33aeb49e 3068 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3069 int err, i;
3070
33aeb49e 3071 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3072 err = ab8500_regulator_register(
33aeb49e 3073 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3074 if (err)
3075 return err;
3076 }
3077
3078 return 0;
3079}
3080
a5023574 3081static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3082{
3083 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3084 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3085 struct ab8500_platform_data *ppdata;
3086 struct ab8500_regulator_platform_data *pdata;
c789ca20 3087 int i, err;
b54969ac 3088
33aeb49e
LJ		 3089 if (!ab8500) {
3090 dev_err(&pdev->dev, "null mfd parent\n");
3091 return -EINVAL;
8e6a8d7d 3092 }
c789ca20 3093
33aeb49e
LJ		 3094 abx500_get_regulator_info(ab8500);
3095
3a8334b9 3096 if (np) {
33aeb49e
LJ		 3097 err = of_regulator_match(&pdev->dev, np,
3098 abx500_regulator.match,
3099 abx500_regulator.match_size);
3a8334b9
LJ		 3100 if (err < 0) {
3101 dev_err(&pdev->dev,
3102 "Error parsing regulator init data: %d\n", err);
3103 return err;
3104 }
3105
33aeb49e 3106 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3107 return err;
3108 }
3109
732805a5
BJ		 3110 ppdata = dev_get_platdata(ab8500->dev);
3111 if (!ppdata) {
3112 dev_err(&pdev->dev, "null parent pdata\n");
3113 return -EINVAL;
3114 }
3115
3116 pdata = ppdata->regulator;
fc24b426
BJ		 3117 if (!pdata) {
3118 dev_err(&pdev->dev, "null pdata\n");
3119 return -EINVAL;
3120 }
c789ca20 3121
cb189b07 3122 /* make sure the platform data has the correct size */
33aeb49e 3123 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3124 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3125 return -EINVAL;
3126 }
3127
da0b0c47
LJ		 3128 /* initialize debug (initial state is recorded with this call) */
3129 err = ab8500_regulator_debug_init(pdev);
3130 if (err)
3131 return err;
3132
79568b94 3133 /* initialize registers */
732805a5 3134 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3135 int id, mask, value;
79568b94 3136
732805a5
BJ		 3137 id = pdata->reg_init[i].id;
3138 mask = pdata->reg_init[i].mask;
3139 value = pdata->reg_init[i].value;
79568b94
BJ		 3140
3141 /* check for configuration errors */
33aeb49e 3142 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3143
33aeb49e 3144 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3145 if (err < 0)
79568b94 3146 return err;
79568b94
BJ		 3147 }
3148
f7eae37f
RV		 3149 if (!is_ab8505(ab8500)) {
3150 /* register external regulators (before Vaux1, 2 and 3) */
3151 err = ab8500_ext_regulator_init(pdev);
3152 if (err)
3153 return err;
3154 }
d1a82001 3155
c789ca20 3156 /* register all regulators */
33aeb49e 3157 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3158 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3159 i, NULL);
42e8c811
AL		 3160 if (err < 0) {
3161 if (!is_ab8505(ab8500))
3162 ab8500_ext_regulator_exit(pdev);
c789ca20 3163 return err;
42e8c811 3164 }
c789ca20
SI		 3165 }
3166
3167 return 0;
3168}
3169
8dc995f5 3170static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3171{
d1a82001 3172 int i, err;
8e6a8d7d 3173 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3174
33aeb49e 3175 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3176 struct ab8500_regulator_info *info = NULL;
33aeb49e 3177 info = &abx500_regulator.info[i];
09aefa12
BJ		 3178
3179 dev_vdbg(rdev_get_dev(info->regulator),
3180 "%s-remove\n", info->desc.name);
3181
c789ca20
SI		 3182 regulator_unregister(info->regulator);
3183 }
3184
3480c0ca
AL		 3185 /* remove external regulators (after Vaux1, 2 and 3) */
3186 if (!is_ab8505(ab8500))
3187 ab8500_ext_regulator_exit(pdev);
d1a82001 3188
da0b0c47
LJ		 3189 /* remove regulator debug */
3190 err = ab8500_regulator_debug_exit(pdev);
3191 if (err)
3192 return err;
3193
c789ca20
SI		 3194 return 0;
3195}
3196
3197static struct platform_driver ab8500_regulator_driver = {
3198 .probe = ab8500_regulator_probe,
5eb9f2b9 3199 .remove = ab8500_regulator_remove,
c789ca20
SI		 3200 .driver = {
3201 .name = "ab8500-regulator",
3202 .owner = THIS_MODULE,
3203 },
3204};
3205
3206static int __init ab8500_regulator_init(void)
3207{
3208 int ret;
3209
3210 ret = platform_driver_register(&ab8500_regulator_driver);
3211 if (ret != 0)
3212 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3213
3214 return ret;
3215}
3216subsys_initcall(ab8500_regulator_init);
3217
3218static void __exit ab8500_regulator_exit(void)
3219{
3220 platform_driver_unregister(&ab8500_regulator_driver);
3221}
3222module_exit(ab8500_regulator_exit);
3223
3224MODULE_LICENSE("GPL v2");
3225MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3226MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3227MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3228MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3229MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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