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regulator: ab8500: Set enable enable_time in regulator_desc
[deliverable/linux.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
bd28a157 49 * @is_enabled: status of regulator (on/off)
7ce4669c 50 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 51 * @update_bank: bank to control on/off
c789ca20 52 * @update_reg: register to control on/off
bd28a157
EV		 53 * @update_mask: mask to enable/disable and set mode of regulator
54 * @update_val: bits holding the regulator current mode
55 * @update_val_idle: bits to enable the regulator in idle (low power) mode
56 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 57 * @mode_bank: bank with location of mode register
58 * @mode_reg: mode register
59 * @mode_mask: mask for setting mode
60 * @mode_val_idle: mode setting for low power
61 * @mode_val_normal: mode setting for normal power
47c16975 62 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 63 * @voltage_reg: register to control regulator voltage
64 * @voltage_mask: mask to control regulator voltage
a0a7014c 65 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 66 */
67struct ab8500_regulator_info {
68 struct device *dev;
69 struct regulator_desc desc;
c789ca20 70 struct regulator_dev *regulator;
3fe52289 71 struct ab8500_shared_mode *shared_mode;
bd28a157 72 bool is_enabled;
7ce4669c 73 int load_lp_uA;
47c16975
MW		 74 u8 update_bank;
75 u8 update_reg;
e1159e6d 76 u8 update_mask;
bd28a157
EV		 77 u8 update_val;
78 u8 update_val_idle;
79 u8 update_val_normal;
3fe52289
LJ		 80 u8 mode_bank;
81 u8 mode_reg;
82 u8 mode_mask;
83 u8 mode_val_idle;
84 u8 mode_val_normal;
47c16975
MW		 85 u8 voltage_bank;
86 u8 voltage_reg;
87 u8 voltage_mask;
a0a7014c 88 u8 voltage_shift;
d7607baf
LJ		 89 struct {
90 u8 voltage_limit;
91 u8 voltage_bank;
92 u8 voltage_reg;
93 u8 voltage_mask;
94 u8 voltage_shift;
95 } expand_register;
c789ca20
SI		 96};
97
98/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 99static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 100 1100000,
101 1200000,
102 1300000,
103 1400000,
104 1500000,
105 1800000,
106 1850000,
107 1900000,
108 2500000,
109 2650000,
110 2700000,
111 2750000,
112 2800000,
113 2900000,
114 3000000,
115 3300000,
116};
117
ec1cc4d9 118static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 119 1200000,
120 1500000,
121 1800000,
122 2100000,
123 2500000,
124 2750000,
125 2790000,
126 2910000,
127};
128
62ab4111 129static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 130 1800000,
131 1050000,
132 1100000,
133 1200000,
134 1500000,
135 2200000,
136 2500000,
137 2790000,
138};
139
62ab4111 140static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 141 1200000,
142 1500000,
143 1800000,
144 2100000,
145 2500000,
146 2750000,
147 2790000,
148 2910000,
149 3050000,
150};
151
684d5ce4
ZH		 152static const unsigned int ldo_vaux56_ab8540_voltages[] = {
153 750000, 760000, 770000, 780000, 790000, 800000,
154 810000, 820000, 830000, 840000, 850000, 860000,
155 870000, 880000, 890000, 900000, 910000, 920000,
156 930000, 940000, 950000, 960000, 970000, 980000,
157 990000, 1000000, 1010000, 1020000, 1030000,
158 1040000, 1050000, 1060000, 1070000, 1080000,
159 1090000, 1100000, 1110000, 1120000, 1130000,
160 1140000, 1150000, 1160000, 1170000, 1180000,
161 1190000, 1200000, 1210000, 1220000, 1230000,
162 1240000, 1250000, 1260000, 1270000, 1280000,
163 1290000, 1300000, 1310000, 1320000, 1330000,
164 1340000, 1350000, 1360000, 1800000, 2790000,
165};
166
ec1cc4d9 167static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 168 1200000,
169 1225000,
170 1250000,
171 1275000,
172 1300000,
173 1325000,
174 1350000,
175};
176
62ab4111 177static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 178 1160000,
179 1050000,
180 1100000,
181 1500000,
182 1800000,
183 2200000,
184 2910000,
185 3050000,
186};
187
b080c78a
LJ		 188static const unsigned int fixed_1200000_voltage[] = {
189 1200000,
190};
191
192static const unsigned int fixed_1800000_voltage[] = {
193 1800000,
194};
195
196static const unsigned int fixed_2000000_voltage[] = {
197 2000000,
198};
199
200static const unsigned int fixed_2050000_voltage[] = {
201 2050000,
202};
203
204static const unsigned int fixed_3300000_voltage[] = {
205 3300000,
206};
207
8a3b1b87
LJ		 208static const unsigned int ldo_vana_voltages[] = {
209 1050000,
210 1075000,
211 1100000,
212 1125000,
213 1150000,
214 1175000,
215 1200000,
216 1225000,
217};
218
219static const unsigned int ldo_vaudio_voltages[] = {
220 2000000,
221 2100000,
222 2200000,
223 2300000,
224 2400000,
225 2500000,
226 2600000,
227 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
228};
229
4c84b4dd
LJ		 230static const unsigned int ldo_vdmic_voltages[] = {
231 1800000,
232 1900000,
233 2000000,
234 2850000,
235};
236
3fe52289
LJ		 237static DEFINE_MUTEX(shared_mode_mutex);
238static struct ab8500_shared_mode ldo_anamic1_shared;
239static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 240static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
241static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 242
c789ca20
SI		 243static int ab8500_regulator_enable(struct regulator_dev *rdev)
244{
fc24b426 245 int ret;
c789ca20
SI		 246 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
247
fc24b426
BJ		 248 if (info == NULL) {
249 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 250 return -EINVAL;
fc24b426 251 }
c789ca20 252
47c16975 253 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 254 info->update_bank, info->update_reg,
bd28a157 255 info->update_mask, info->update_val);
f71bf528 256 if (ret < 0) {
c789ca20
SI		 257 dev_err(rdev_get_dev(rdev),
258 "couldn't set enable bits for regulator\n");
f71bf528
AL		 259 return ret;
260 }
09aefa12 261
bd28a157
EV		 262 info->is_enabled = true;
263
09aefa12
BJ		 264 dev_vdbg(rdev_get_dev(rdev),
265 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
266 info->desc.name, info->update_bank, info->update_reg,
bd28a157 267 info->update_mask, info->update_val);
09aefa12 268
c789ca20
SI		 269 return ret;
270}
271
272static int ab8500_regulator_disable(struct regulator_dev *rdev)
273{
fc24b426 274 int ret;
c789ca20
SI		 275 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
276
fc24b426
BJ		 277 if (info == NULL) {
278 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 279 return -EINVAL;
fc24b426 280 }
c789ca20 281
47c16975 282 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 283 info->update_bank, info->update_reg,
284 info->update_mask, 0x0);
f71bf528 285 if (ret < 0) {
c789ca20
SI		 286 dev_err(rdev_get_dev(rdev),
287 "couldn't set disable bits for regulator\n");
f71bf528
AL		 288 return ret;
289 }
09aefa12 290
bd28a157
EV		 291 info->is_enabled = false;
292
09aefa12
BJ		 293 dev_vdbg(rdev_get_dev(rdev),
294 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
295 info->desc.name, info->update_bank, info->update_reg,
296 info->update_mask, 0x0);
297
c789ca20
SI		 298 return ret;
299}
300
7ce4669c
BJ		 301static unsigned int ab8500_regulator_get_optimum_mode(
302 struct regulator_dev *rdev, int input_uV,
303 int output_uV, int load_uA)
304{
305 unsigned int mode;
306
307 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
308
309 if (info == NULL) {
310 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
311 return -EINVAL;
312 }
313
314 if (load_uA <= info->load_lp_uA)
315 mode = REGULATOR_MODE_IDLE;
316 else
317 mode = REGULATOR_MODE_NORMAL;
318
319 return mode;
320}
321
bd28a157
EV		 322static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
323 unsigned int mode)
324{
3fe52289
LJ		 325 int ret = 0;
326 u8 bank;
327 u8 reg;
328 u8 mask;
329 u8 val;
330 bool dmr = false; /* Dedicated mode register */
bd28a157
EV		 331 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
332
333 if (info == NULL) {
334 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
335 return -EINVAL;
336 }
337
3fe52289
LJ		 338 if (info->shared_mode) {
339 /*
340 * Special case where mode is shared between two regulators.
341 */
342 struct ab8500_shared_mode *sm = info->shared_mode;
343 mutex_lock(&shared_mode_mutex);
344
345 if (mode == REGULATOR_MODE_IDLE) {
346 sm->lp_mode_req = true; /* Low power mode requested */
347 if (!((sm->shared_regulator)->
348 shared_mode->lp_mode_req)) {
349 mutex_unlock(&shared_mode_mutex);
350 return 0; /* Other regulator prevent LP mode */
351 }
352 } else {
353 sm->lp_mode_req = false;
354 }
355 }
356
357 if (info->mode_mask) {
358 /* Dedicated register for handling mode */
359
360 dmr = true;
361
362 switch (mode) {
363 case REGULATOR_MODE_NORMAL:
364 val = info->mode_val_normal;
365 break;
366 case REGULATOR_MODE_IDLE:
367 val = info->mode_val_idle;
368 break;
369 default:
370 if (info->shared_mode)
371 mutex_unlock(&shared_mode_mutex);
372 return -EINVAL;
373 }
374
375 bank = info->mode_bank;
376 reg = info->mode_reg;
377 mask = info->mode_mask;
378 } else {
379 /* Mode register same as enable register */
380
381 switch (mode) {
382 case REGULATOR_MODE_NORMAL:
383 info->update_val = info->update_val_normal;
384 val = info->update_val_normal;
385 break;
386 case REGULATOR_MODE_IDLE:
387 info->update_val = info->update_val_idle;
388 val = info->update_val_idle;
389 break;
390 default:
391 if (info->shared_mode)
392 mutex_unlock(&shared_mode_mutex);
393 return -EINVAL;
394 }
395
396 bank = info->update_bank;
397 reg = info->update_reg;
398 mask = info->update_mask;
bd28a157
EV		 399 }
400
3fe52289 401 if (info->is_enabled || dmr) {
bd28a157 402 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289
LJ		 403 bank, reg, mask, val);
404 if (ret < 0)
bd28a157
EV		 405 dev_err(rdev_get_dev(rdev),
406 "couldn't set regulator mode\n");
7ce4669c
BJ		 407
408 dev_vdbg(rdev_get_dev(rdev),
409 "%s-set_mode (bank, reg, mask, value): "
410 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 411 info->desc.name, bank, reg,
412 mask, val);
bd28a157
EV		 413 }
414
3fe52289
LJ		 415 if (info->shared_mode)
416 mutex_unlock(&shared_mode_mutex);
742a7325 417
3fe52289 418 return ret;
bd28a157
EV		 419}
420
421static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
422{
423 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
424 int ret;
3fe52289
LJ		 425 u8 val;
426 u8 val_normal;
427 u8 val_idle;
bd28a157
EV		 428
429 if (info == NULL) {
430 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
431 return -EINVAL;
432 }
433
3fe52289
LJ		 434 /* Need special handling for shared mode */
435 if (info->shared_mode) {
436 if (info->shared_mode->lp_mode_req)
437 return REGULATOR_MODE_IDLE;
438 else
439 return REGULATOR_MODE_NORMAL;
440 }
441
442 if (info->mode_mask) {
443 /* Dedicated register for handling mode */
444 ret = abx500_get_register_interruptible(info->dev,
445 info->mode_bank, info->mode_reg, &val);
446 val = val & info->mode_mask;
447
448 val_normal = info->mode_val_normal;
449 val_idle = info->mode_val_idle;
450 } else {
451 /* Mode register same as enable register */
452 val = info->update_val;
453 val_normal = info->update_val_normal;
454 val_idle = info->update_val_idle;
455 }
456
457 if (val == val_normal)
bd28a157 458 ret = REGULATOR_MODE_NORMAL;
3fe52289 459 else if (val == val_idle)
bd28a157
EV		 460 ret = REGULATOR_MODE_IDLE;
461 else
462 ret = -EINVAL;
463
464 return ret;
465}
466
c789ca20
SI		 467static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
468{
fc24b426 469 int ret;
c789ca20 470 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 471 u8 regval;
c789ca20 472
fc24b426
BJ		 473 if (info == NULL) {
474 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 475 return -EINVAL;
fc24b426 476 }
c789ca20 477
47c16975 478 ret = abx500_get_register_interruptible(info->dev,
09aefa12 479 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 480 if (ret < 0) {
481 dev_err(rdev_get_dev(rdev),
482 "couldn't read 0x%x register\n", info->update_reg);
483 return ret;
484 }
485
09aefa12
BJ		 486 dev_vdbg(rdev_get_dev(rdev),
487 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
488 " 0x%x\n",
489 info->desc.name, info->update_bank, info->update_reg,
490 info->update_mask, regval);
491
492 if (regval & info->update_mask)
bd28a157 493 info->is_enabled = true;
c789ca20 494 else
bd28a157
EV		 495 info->is_enabled = false;
496
497 return info->is_enabled;
c789ca20
SI		 498}
499
3bf6e90e 500static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 501{
09aefa12 502 int ret, val;
c789ca20 503 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 504 u8 regval;
c789ca20 505
fc24b426
BJ		 506 if (info == NULL) {
507 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 508 return -EINVAL;
fc24b426 509 }
c789ca20 510
09aefa12
BJ		 511 ret = abx500_get_register_interruptible(info->dev,
512 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 513 if (ret < 0) {
514 dev_err(rdev_get_dev(rdev),
515 "couldn't read voltage reg for regulator\n");
516 return ret;
517 }
518
09aefa12 519 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 520 "%s-get_voltage (bank, reg, mask, shift, value): "
521 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
522 info->desc.name, info->voltage_bank,
523 info->voltage_reg, info->voltage_mask,
524 info->voltage_shift, regval);
09aefa12 525
09aefa12 526 val = regval & info->voltage_mask;
a0a7014c 527 return val >> info->voltage_shift;
c789ca20
SI		 528}
529
d7607baf
LJ		 530static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
531{
532 int ret, val;
533 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
534 u8 regval, regval_expand;
535
536 if (info == NULL) {
537 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
538 return -EINVAL;
539 }
540
541 ret = abx500_get_register_interruptible(info->dev,
542 info->voltage_bank, info->voltage_reg, &regval);
543
544 if (ret < 0) {
545 dev_err(rdev_get_dev(rdev),
546 "couldn't read voltage reg for regulator\n");
547 return ret;
548 }
549
550 ret = abx500_get_register_interruptible(info->dev,
551 info->expand_register.voltage_bank,
552 info->expand_register.voltage_reg, &regval_expand);
553
554 if (ret < 0) {
555 dev_err(rdev_get_dev(rdev),
556 "couldn't read voltage reg for regulator\n");
557 return ret;
558 }
559
560 dev_vdbg(rdev_get_dev(rdev),
561 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
562 " 0x%x\n",
563 info->desc.name, info->voltage_bank, info->voltage_reg,
564 info->voltage_mask, regval);
565 dev_vdbg(rdev_get_dev(rdev),
566 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
567 " 0x%x\n",
568 info->desc.name, info->expand_register.voltage_bank,
569 info->expand_register.voltage_reg,
570 info->expand_register.voltage_mask, regval_expand);
571
572 if (regval_expand&(info->expand_register.voltage_mask))
573 /* Vaux3 has a different layout */
574 val = info->expand_register.voltage_limit;
575 else
576 val = (regval & info->voltage_mask) >> info->voltage_shift;
577
578 return val;
579}
580
ae713d39
AL		 581static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
582 unsigned selector)
c789ca20 583{
fc24b426 584 int ret;
c789ca20 585 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 586 u8 regval;
c789ca20 587
fc24b426
BJ		 588 if (info == NULL) {
589 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 590 return -EINVAL;
fc24b426 591 }
c789ca20 592
c789ca20 593 /* set the registers for the request */
a0a7014c 594 regval = (u8)selector << info->voltage_shift;
47c16975 595 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 596 info->voltage_bank, info->voltage_reg,
597 info->voltage_mask, regval);
c789ca20
SI		 598 if (ret < 0)
599 dev_err(rdev_get_dev(rdev),
600 "couldn't set voltage reg for regulator\n");
601
09aefa12
BJ		 602 dev_vdbg(rdev_get_dev(rdev),
603 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
604 " 0x%x\n",
605 info->desc.name, info->voltage_bank, info->voltage_reg,
606 info->voltage_mask, regval);
607
c789ca20
SI		 608 return ret;
609}
610
d7607baf
LJ		 611static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
612 unsigned selector)
613{
614 int ret;
615 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
616 u8 regval;
617
618 if (info == NULL) {
619 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
620 return -EINVAL;
621 }
622
623 if (selector >= info->expand_register.voltage_limit) {
624 /* Vaux3 bit4 has different layout */
625 regval = (u8)selector << info->expand_register.voltage_shift;
626 ret = abx500_mask_and_set_register_interruptible(info->dev,
627 info->expand_register.voltage_bank,
628 info->expand_register.voltage_reg,
629 info->expand_register.voltage_mask,
630 regval);
631 } else {
632 /* set the registers for the request */
633 regval = (u8)selector << info->voltage_shift;
634 ret = abx500_mask_and_set_register_interruptible(info->dev,
635 info->voltage_bank, info->voltage_reg,
636 info->voltage_mask, regval);
637 }
638 if (ret < 0)
639 dev_err(rdev_get_dev(rdev),
640 "couldn't set voltage reg for regulator\n");
641
642 dev_vdbg(rdev_get_dev(rdev),
643 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
644 " 0x%x\n",
645 info->desc.name, info->voltage_bank, info->voltage_reg,
646 info->voltage_mask, regval);
647
648 return ret;
649}
650
651static int ab8500_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
652 unsigned int old_sel,
653 unsigned int new_sel)
654{
655 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
656
657 return info->delay;
658}
659
7ce4669c
BJ		 660static struct regulator_ops ab8500_regulator_volt_mode_ops = {
661 .enable = ab8500_regulator_enable,
662 .disable = ab8500_regulator_disable,
663 .is_enabled = ab8500_regulator_is_enabled,
664 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
665 .set_mode = ab8500_regulator_set_mode,
666 .get_mode = ab8500_regulator_get_mode,
667 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
668 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
669 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 670};
671
d7607baf
LJ		 672static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
673 .enable = ab8500_regulator_enable,
674 .disable = ab8500_regulator_disable,
675 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
676 .set_mode = ab8500_regulator_set_mode,
677 .get_mode = ab8500_regulator_get_mode,
678 .is_enabled = ab8500_regulator_is_enabled,
679 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
680 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
681 .list_voltage = regulator_list_voltage_table,
682 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
683};
684
8a3b1b87
LJ		 685static struct regulator_ops ab8500_regulator_volt_ops = {
686 .enable = ab8500_regulator_enable,
687 .disable = ab8500_regulator_disable,
688 .is_enabled = ab8500_regulator_is_enabled,
689 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
690 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
691 .list_voltage = regulator_list_voltage_table,
692 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
693};
694
7ce4669c
BJ		 695static struct regulator_ops ab8500_regulator_mode_ops = {
696 .enable = ab8500_regulator_enable,
697 .disable = ab8500_regulator_disable,
698 .is_enabled = ab8500_regulator_is_enabled,
699 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
700 .set_mode = ab8500_regulator_set_mode,
701 .get_mode = ab8500_regulator_get_mode,
5689e830 702 .list_voltage = regulator_list_voltage_linear,
7ce4669c
BJ		 703};
704
705static struct regulator_ops ab8500_regulator_ops = {
706 .enable = ab8500_regulator_enable,
707 .disable = ab8500_regulator_disable,
708 .is_enabled = ab8500_regulator_is_enabled,
5689e830 709 .list_voltage = regulator_list_voltage_linear,
c789ca20
SI		 710};
711
3fe52289
LJ		 712static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
713 .enable = ab8500_regulator_enable,
714 .disable = ab8500_regulator_disable,
715 .is_enabled = ab8500_regulator_is_enabled,
716 .set_mode = ab8500_regulator_set_mode,
717 .get_mode = ab8500_regulator_get_mode,
718 .list_voltage = regulator_list_voltage_table,
719};
720
8e6a8d7d 721/* AB8500 regulator information */
6909b452
BJ		 722static struct ab8500_regulator_info
723 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 724 /*
e1159e6d
BJ		 725 * Variable Voltage Regulators
726 * name, min mV, max mV,
727 * update bank, reg, mask, enable val
ec1cc4d9 728 * volt bank, reg, mask
c789ca20 729 */
6909b452
BJ		 730 [AB8500_LDO_AUX1] = {
731 .desc = {
732 .name = "LDO-AUX1",
7ce4669c 733 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 734 .type = REGULATOR_VOLTAGE,
735 .id = AB8500_LDO_AUX1,
736 .owner = THIS_MODULE,
737 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 738 .volt_table = ldo_vauxn_voltages,
530158b6 739 .enable_time = 200,
6909b452 740 },
7ce4669c 741 .load_lp_uA = 5000,
6909b452
BJ		 742 .update_bank = 0x04,
743 .update_reg = 0x09,
744 .update_mask = 0x03,
bd28a157
EV		 745 .update_val = 0x01,
746 .update_val_idle = 0x03,
747 .update_val_normal = 0x01,
6909b452
BJ		 748 .voltage_bank = 0x04,
749 .voltage_reg = 0x1f,
750 .voltage_mask = 0x0f,
6909b452
BJ		 751 },
752 [AB8500_LDO_AUX2] = {
753 .desc = {
754 .name = "LDO-AUX2",
7ce4669c 755 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 756 .type = REGULATOR_VOLTAGE,
757 .id = AB8500_LDO_AUX2,
758 .owner = THIS_MODULE,
759 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 760 .volt_table = ldo_vauxn_voltages,
530158b6 761 .enable_time = 200,
6909b452 762 },
7ce4669c 763 .load_lp_uA = 5000,
6909b452
BJ		 764 .update_bank = 0x04,
765 .update_reg = 0x09,
766 .update_mask = 0x0c,
bd28a157
EV		 767 .update_val = 0x04,
768 .update_val_idle = 0x0c,
769 .update_val_normal = 0x04,
6909b452
BJ		 770 .voltage_bank = 0x04,
771 .voltage_reg = 0x20,
772 .voltage_mask = 0x0f,
6909b452
BJ		 773 },
774 [AB8500_LDO_AUX3] = {
775 .desc = {
776 .name = "LDO-AUX3",
7ce4669c 777 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 778 .type = REGULATOR_VOLTAGE,
779 .id = AB8500_LDO_AUX3,
780 .owner = THIS_MODULE,
781 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 782 .volt_table = ldo_vaux3_voltages,
530158b6 783 .enable_time = 450,
6909b452 784 },
7ce4669c 785 .load_lp_uA = 5000,
6909b452
BJ		 786 .update_bank = 0x04,
787 .update_reg = 0x0a,
788 .update_mask = 0x03,
bd28a157
EV		 789 .update_val = 0x01,
790 .update_val_idle = 0x03,
791 .update_val_normal = 0x01,
6909b452
BJ		 792 .voltage_bank = 0x04,
793 .voltage_reg = 0x21,
794 .voltage_mask = 0x07,
6909b452
BJ		 795 },
796 [AB8500_LDO_INTCORE] = {
797 .desc = {
798 .name = "LDO-INTCORE",
7ce4669c 799 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 800 .type = REGULATOR_VOLTAGE,
801 .id = AB8500_LDO_INTCORE,
802 .owner = THIS_MODULE,
803 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 804 .volt_table = ldo_vintcore_voltages,
530158b6 805 .enable_time = 750,
6909b452 806 },
7ce4669c 807 .load_lp_uA = 5000,
6909b452
BJ		 808 .update_bank = 0x03,
809 .update_reg = 0x80,
810 .update_mask = 0x44,
cc40dc29 811 .update_val = 0x44,
bd28a157
EV		 812 .update_val_idle = 0x44,
813 .update_val_normal = 0x04,
6909b452
BJ		 814 .voltage_bank = 0x03,
815 .voltage_reg = 0x80,
816 .voltage_mask = 0x38,
a0a7014c 817 .voltage_shift = 3,
6909b452 818 },
c789ca20
SI		 819
820 /*
e1159e6d
BJ		 821 * Fixed Voltage Regulators
822 * name, fixed mV,
823 * update bank, reg, mask, enable val
c789ca20 824 */
6909b452
BJ		 825 [AB8500_LDO_TVOUT] = {
826 .desc = {
827 .name = "LDO-TVOUT",
7ce4669c 828 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 829 .type = REGULATOR_VOLTAGE,
830 .id = AB8500_LDO_TVOUT,
831 .owner = THIS_MODULE,
832 .n_voltages = 1,
b080c78a 833 .volt_table = fixed_2000000_voltage,
ed3c138e 834 .enable_time = 500,
6909b452 835 },
7ce4669c 836 .load_lp_uA = 1000,
6909b452
BJ		 837 .update_bank = 0x03,
838 .update_reg = 0x80,
839 .update_mask = 0x82,
bd28a157 840 .update_val = 0x02,
7ce4669c
BJ		 841 .update_val_idle = 0x82,
842 .update_val_normal = 0x02,
6909b452
BJ		 843 },
844 [AB8500_LDO_AUDIO] = {
845 .desc = {
846 .name = "LDO-AUDIO",
7ce4669c 847 .ops = &ab8500_regulator_ops,
6909b452
BJ		 848 .type = REGULATOR_VOLTAGE,
849 .id = AB8500_LDO_AUDIO,
850 .owner = THIS_MODULE,
851 .n_voltages = 1,
530158b6 852 .enable_time = 140,
b080c78a 853 .volt_table = fixed_2000000_voltage,
6909b452 854 },
6909b452
BJ		 855 .update_bank = 0x03,
856 .update_reg = 0x83,
857 .update_mask = 0x02,
bd28a157 858 .update_val = 0x02,
6909b452
BJ		 859 },
860 [AB8500_LDO_ANAMIC1] = {
861 .desc = {
862 .name = "LDO-ANAMIC1",
7ce4669c 863 .ops = &ab8500_regulator_ops,
6909b452
BJ		 864 .type = REGULATOR_VOLTAGE,
865 .id = AB8500_LDO_ANAMIC1,
866 .owner = THIS_MODULE,
867 .n_voltages = 1,
530158b6 868 .enable_time = 500,
b080c78a 869 .volt_table = fixed_2050000_voltage,
6909b452 870 },
6909b452
BJ		 871 .update_bank = 0x03,
872 .update_reg = 0x83,
873 .update_mask = 0x08,
bd28a157 874 .update_val = 0x08,
6909b452
BJ		 875 },
876 [AB8500_LDO_ANAMIC2] = {
877 .desc = {
878 .name = "LDO-ANAMIC2",
7ce4669c 879 .ops = &ab8500_regulator_ops,
6909b452
BJ		 880 .type = REGULATOR_VOLTAGE,
881 .id = AB8500_LDO_ANAMIC2,
882 .owner = THIS_MODULE,
883 .n_voltages = 1,
530158b6 884 .enable_time = 500,
b080c78a 885 .volt_table = fixed_2050000_voltage,
6909b452 886 },
6909b452
BJ		 887 .update_bank = 0x03,
888 .update_reg = 0x83,
889 .update_mask = 0x10,
bd28a157 890 .update_val = 0x10,
6909b452
BJ		 891 },
892 [AB8500_LDO_DMIC] = {
893 .desc = {
894 .name = "LDO-DMIC",
7ce4669c 895 .ops = &ab8500_regulator_ops,
6909b452
BJ		 896 .type = REGULATOR_VOLTAGE,
897 .id = AB8500_LDO_DMIC,
898 .owner = THIS_MODULE,
899 .n_voltages = 1,
530158b6 900 .enable_time = 420,
b080c78a 901 .volt_table = fixed_1800000_voltage,
6909b452 902 },
6909b452
BJ		 903 .update_bank = 0x03,
904 .update_reg = 0x83,
905 .update_mask = 0x04,
bd28a157 906 .update_val = 0x04,
6909b452 907 },
7ce4669c
BJ		 908
909 /*
910 * Regulators with fixed voltage and normal/idle modes
911 */
6909b452
BJ		 912 [AB8500_LDO_ANA] = {
913 .desc = {
914 .name = "LDO-ANA",
7ce4669c 915 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 916 .type = REGULATOR_VOLTAGE,
917 .id = AB8500_LDO_ANA,
918 .owner = THIS_MODULE,
919 .n_voltages = 1,
530158b6 920 .enable_time = 140,
b080c78a 921 .volt_table = fixed_1200000_voltage,
6909b452 922 },
7ce4669c 923 .load_lp_uA = 1000,
6909b452
BJ		 924 .update_bank = 0x04,
925 .update_reg = 0x06,
926 .update_mask = 0x0c,
bd28a157 927 .update_val = 0x04,
7ce4669c
BJ		 928 .update_val_idle = 0x0c,
929 .update_val_normal = 0x04,
6909b452 930 },
8e6a8d7d 931};
6909b452 932
547f384f
LJ		 933/* AB8505 regulator information */
934static struct ab8500_regulator_info
935 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
936 /*
937 * Variable Voltage Regulators
938 * name, min mV, max mV,
939 * update bank, reg, mask, enable val
940 * volt bank, reg, mask, table, table length
941 */
942 [AB8505_LDO_AUX1] = {
943 .desc = {
944 .name = "LDO-AUX1",
945 .ops = &ab8500_regulator_volt_mode_ops,
946 .type = REGULATOR_VOLTAGE,
0b946411 947 .id = AB8505_LDO_AUX1,
547f384f
LJ		 948 .owner = THIS_MODULE,
949 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 950 .volt_table = ldo_vauxn_voltages,
547f384f 951 },
547f384f
LJ		 952 .load_lp_uA = 5000,
953 .update_bank = 0x04,
954 .update_reg = 0x09,
955 .update_mask = 0x03,
956 .update_val = 0x01,
957 .update_val_idle = 0x03,
958 .update_val_normal = 0x01,
959 .voltage_bank = 0x04,
960 .voltage_reg = 0x1f,
961 .voltage_mask = 0x0f,
547f384f
LJ		 962 },
963 [AB8505_LDO_AUX2] = {
964 .desc = {
965 .name = "LDO-AUX2",
966 .ops = &ab8500_regulator_volt_mode_ops,
967 .type = REGULATOR_VOLTAGE,
0b946411 968 .id = AB8505_LDO_AUX2,
547f384f
LJ		 969 .owner = THIS_MODULE,
970 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 971 .volt_table = ldo_vauxn_voltages,
547f384f 972 },
547f384f
LJ		 973 .load_lp_uA = 5000,
974 .update_bank = 0x04,
975 .update_reg = 0x09,
976 .update_mask = 0x0c,
977 .update_val = 0x04,
978 .update_val_idle = 0x0c,
979 .update_val_normal = 0x04,
980 .voltage_bank = 0x04,
981 .voltage_reg = 0x20,
982 .voltage_mask = 0x0f,
547f384f
LJ		 983 },
984 [AB8505_LDO_AUX3] = {
985 .desc = {
986 .name = "LDO-AUX3",
987 .ops = &ab8500_regulator_volt_mode_ops,
988 .type = REGULATOR_VOLTAGE,
0b946411 989 .id = AB8505_LDO_AUX3,
547f384f
LJ		 990 .owner = THIS_MODULE,
991 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 992 .volt_table = ldo_vaux3_voltages,
547f384f 993 },
547f384f
LJ		 994 .load_lp_uA = 5000,
995 .update_bank = 0x04,
996 .update_reg = 0x0a,
997 .update_mask = 0x03,
998 .update_val = 0x01,
999 .update_val_idle = 0x03,
1000 .update_val_normal = 0x01,
1001 .voltage_bank = 0x04,
1002 .voltage_reg = 0x21,
1003 .voltage_mask = 0x07,
547f384f
LJ		 1004 },
1005 [AB8505_LDO_AUX4] = {
1006 .desc = {
1007 .name = "LDO-AUX4",
1008 .ops = &ab8500_regulator_volt_mode_ops,
1009 .type = REGULATOR_VOLTAGE,
0b946411 1010 .id = AB8505_LDO_AUX4,
547f384f
LJ		 1011 .owner = THIS_MODULE,
1012 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1013 .volt_table = ldo_vauxn_voltages,
547f384f 1014 },
547f384f
LJ		 1015 .load_lp_uA = 5000,
1016 /* values for Vaux4Regu register */
1017 .update_bank = 0x04,
1018 .update_reg = 0x2e,
1019 .update_mask = 0x03,
1020 .update_val = 0x01,
1021 .update_val_idle = 0x03,
1022 .update_val_normal = 0x01,
1023 /* values for Vaux4SEL register */
1024 .voltage_bank = 0x04,
1025 .voltage_reg = 0x2f,
1026 .voltage_mask = 0x0f,
547f384f
LJ		 1027 },
1028 [AB8505_LDO_AUX5] = {
1029 .desc = {
1030 .name = "LDO-AUX5",
1031 .ops = &ab8500_regulator_volt_mode_ops,
1032 .type = REGULATOR_VOLTAGE,
1033 .id = AB8505_LDO_AUX5,
1034 .owner = THIS_MODULE,
1035 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1036 .volt_table = ldo_vaux56_voltages,
547f384f 1037 },
547f384f
LJ		 1038 .load_lp_uA = 2000,
1039 /* values for CtrlVaux5 register */
1040 .update_bank = 0x01,
1041 .update_reg = 0x55,
ae0a9a3e
LJ		 1042 .update_mask = 0x18,
1043 .update_val = 0x10,
1044 .update_val_idle = 0x18,
1045 .update_val_normal = 0x10,
547f384f
LJ		 1046 .voltage_bank = 0x01,
1047 .voltage_reg = 0x55,
1048 .voltage_mask = 0x07,
547f384f
LJ		 1049 },
1050 [AB8505_LDO_AUX6] = {
1051 .desc = {
1052 .name = "LDO-AUX6",
1053 .ops = &ab8500_regulator_volt_mode_ops,
1054 .type = REGULATOR_VOLTAGE,
1055 .id = AB8505_LDO_AUX6,
1056 .owner = THIS_MODULE,
1057 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1058 .volt_table = ldo_vaux56_voltages,
547f384f 1059 },
547f384f
LJ		 1060 .load_lp_uA = 2000,
1061 /* values for CtrlVaux6 register */
1062 .update_bank = 0x01,
1063 .update_reg = 0x56,
ae0a9a3e
LJ		 1064 .update_mask = 0x18,
1065 .update_val = 0x10,
1066 .update_val_idle = 0x18,
1067 .update_val_normal = 0x10,
547f384f
LJ		 1068 .voltage_bank = 0x01,
1069 .voltage_reg = 0x56,
1070 .voltage_mask = 0x07,
547f384f
LJ		 1071 },
1072 [AB8505_LDO_INTCORE] = {
1073 .desc = {
1074 .name = "LDO-INTCORE",
1075 .ops = &ab8500_regulator_volt_mode_ops,
1076 .type = REGULATOR_VOLTAGE,
0b946411 1077 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1078 .owner = THIS_MODULE,
1079 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1080 .volt_table = ldo_vintcore_voltages,
547f384f 1081 },
547f384f
LJ		 1082 .load_lp_uA = 5000,
1083 .update_bank = 0x03,
1084 .update_reg = 0x80,
1085 .update_mask = 0x44,
1086 .update_val = 0x04,
1087 .update_val_idle = 0x44,
1088 .update_val_normal = 0x04,
1089 .voltage_bank = 0x03,
1090 .voltage_reg = 0x80,
1091 .voltage_mask = 0x38,
547f384f
LJ		 1092 .voltage_shift = 3,
1093 },
1094
1095 /*
1096 * Fixed Voltage Regulators
1097 * name, fixed mV,
1098 * update bank, reg, mask, enable val
1099 */
1100 [AB8505_LDO_ADC] = {
1101 .desc = {
1102 .name = "LDO-ADC",
1103 .ops = &ab8500_regulator_mode_ops,
1104 .type = REGULATOR_VOLTAGE,
1105 .id = AB8505_LDO_ADC,
1106 .owner = THIS_MODULE,
1107 .n_voltages = 1,
b080c78a 1108 .volt_table = fixed_2000000_voltage,
a4d68468 1109 .enable_time = 10000,
547f384f
LJ		 1110 },
1111 .delay = 10000,
547f384f
LJ		 1112 .load_lp_uA = 1000,
1113 .update_bank = 0x03,
1114 .update_reg = 0x80,
1115 .update_mask = 0x82,
1116 .update_val = 0x02,
1117 .update_val_idle = 0x82,
1118 .update_val_normal = 0x02,
1119 },
1120 [AB8505_LDO_USB] = {
1121 .desc = {
1122 .name = "LDO-USB",
1123 .ops = &ab8500_regulator_mode_ops,
1124 .type = REGULATOR_VOLTAGE,
0b946411 1125 .id = AB8505_LDO_USB,
547f384f
LJ		 1126 .owner = THIS_MODULE,
1127 .n_voltages = 1,
b080c78a 1128 .volt_table = fixed_3300000_voltage,
547f384f 1129 },
547f384f
LJ		 1130 .update_bank = 0x03,
1131 .update_reg = 0x82,
1132 .update_mask = 0x03,
1133 .update_val = 0x01,
1134 .update_val_idle = 0x03,
1135 .update_val_normal = 0x01,
1136 },
1137 [AB8505_LDO_AUDIO] = {
1138 .desc = {
1139 .name = "LDO-AUDIO",
8a3b1b87 1140 .ops = &ab8500_regulator_volt_ops,
547f384f 1141 .type = REGULATOR_VOLTAGE,
0b946411 1142 .id = AB8505_LDO_AUDIO,
547f384f 1143 .owner = THIS_MODULE,
8a3b1b87
LJ		 1144 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1145 .volt_table = ldo_vaudio_voltages,
547f384f 1146 },
547f384f
LJ		 1147 .update_bank = 0x03,
1148 .update_reg = 0x83,
1149 .update_mask = 0x02,
1150 .update_val = 0x02,
8a3b1b87
LJ		 1151 .voltage_bank = 0x01,
1152 .voltage_reg = 0x57,
1153 .voltage_mask = 0x7,
1154 .voltage_shift = 4,
1155 .voltages = ldo_vaudio_voltages,
1156 .voltages_len = ARRAY_SIZE(ldo_vaudio_voltages),
547f384f
LJ		 1157 },
1158 [AB8505_LDO_ANAMIC1] = {
1159 .desc = {
1160 .name = "LDO-ANAMIC1",
3fe52289 1161 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1162 .type = REGULATOR_VOLTAGE,
0b946411 1163 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1164 .owner = THIS_MODULE,
1165 .n_voltages = 1,
b080c78a 1166 .volt_table = fixed_2050000_voltage,
547f384f 1167 },
4c84b4dd 1168 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1169 .update_bank = 0x03,
1170 .update_reg = 0x83,
1171 .update_mask = 0x08,
1172 .update_val = 0x08,
3fe52289
LJ		 1173 .mode_bank = 0x01,
1174 .mode_reg = 0x54,
1175 .mode_mask = 0x04,
1176 .mode_val_idle = 0x04,
1177 .mode_val_normal = 0x00,
547f384f
LJ		 1178 },
1179 [AB8505_LDO_ANAMIC2] = {
1180 .desc = {
1181 .name = "LDO-ANAMIC2",
3fe52289 1182 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1183 .type = REGULATOR_VOLTAGE,
0b946411 1184 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1185 .owner = THIS_MODULE,
1186 .n_voltages = 1,
b080c78a 1187 .volt_table = fixed_2050000_voltage,
547f384f 1188 },
3fe52289 1189 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1190 .update_bank = 0x03,
1191 .update_reg = 0x83,
1192 .update_mask = 0x10,
1193 .update_val = 0x10,
3fe52289
LJ		 1194 .mode_bank = 0x01,
1195 .mode_reg = 0x54,
1196 .mode_mask = 0x04,
1197 .mode_val_idle = 0x04,
1198 .mode_val_normal = 0x00,
547f384f
LJ		 1199 },
1200 [AB8505_LDO_AUX8] = {
1201 .desc = {
1202 .name = "LDO-AUX8",
1203 .ops = &ab8500_regulator_ops,
1204 .type = REGULATOR_VOLTAGE,
1205 .id = AB8505_LDO_AUX8,
1206 .owner = THIS_MODULE,
1207 .n_voltages = 1,
b080c78a 1208 .volt_table = fixed_1800000_voltage,
547f384f 1209 },
547f384f
LJ		 1210 .update_bank = 0x03,
1211 .update_reg = 0x83,
1212 .update_mask = 0x04,
1213 .update_val = 0x04,
1214 },
1215 /*
1216 * Regulators with fixed voltage and normal/idle modes
1217 */
1218 [AB8505_LDO_ANA] = {
1219 .desc = {
1220 .name = "LDO-ANA",
8a3b1b87 1221 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1222 .type = REGULATOR_VOLTAGE,
0b946411 1223 .id = AB8505_LDO_ANA,
547f384f 1224 .owner = THIS_MODULE,
8a3b1b87
LJ		 1225 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1226 .volt_table = ldo_vana_voltages,
547f384f 1227 },
547f384f
LJ		 1228 .load_lp_uA = 1000,
1229 .update_bank = 0x04,
1230 .update_reg = 0x06,
1231 .update_mask = 0x0c,
1232 .update_val = 0x04,
1233 .update_val_idle = 0x0c,
1234 .update_val_normal = 0x04,
8a3b1b87
LJ		 1235 .voltage_bank = 0x04,
1236 .voltage_reg = 0x29,
1237 .voltage_mask = 0x7,
1238 .voltages = ldo_vana_voltages,
1239 .voltages_len = ARRAY_SIZE(ldo_vana_voltages),
547f384f
LJ		 1240 },
1241};
1242
8e6a8d7d
LJ		 1243/* AB9540 regulator information */
1244static struct ab8500_regulator_info
1245 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1246 /*
1247 * Variable Voltage Regulators
1248 * name, min mV, max mV,
1249 * update bank, reg, mask, enable val
1250 * volt bank, reg, mask, table, table length
1251 */
1252 [AB9540_LDO_AUX1] = {
1253 .desc = {
1254 .name = "LDO-AUX1",
1255 .ops = &ab8500_regulator_volt_mode_ops,
1256 .type = REGULATOR_VOLTAGE,
0b946411 1257 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1258 .owner = THIS_MODULE,
1259 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1260 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1261 },
8e6a8d7d
LJ		 1262 .load_lp_uA = 5000,
1263 .update_bank = 0x04,
1264 .update_reg = 0x09,
1265 .update_mask = 0x03,
1266 .update_val = 0x01,
1267 .update_val_idle = 0x03,
1268 .update_val_normal = 0x01,
1269 .voltage_bank = 0x04,
1270 .voltage_reg = 0x1f,
1271 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1272 },
1273 [AB9540_LDO_AUX2] = {
1274 .desc = {
1275 .name = "LDO-AUX2",
1276 .ops = &ab8500_regulator_volt_mode_ops,
1277 .type = REGULATOR_VOLTAGE,
0b946411 1278 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1279 .owner = THIS_MODULE,
1280 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1281 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1282 },
8e6a8d7d
LJ		 1283 .load_lp_uA = 5000,
1284 .update_bank = 0x04,
1285 .update_reg = 0x09,
1286 .update_mask = 0x0c,
1287 .update_val = 0x04,
1288 .update_val_idle = 0x0c,
1289 .update_val_normal = 0x04,
1290 .voltage_bank = 0x04,
1291 .voltage_reg = 0x20,
1292 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1293 },
1294 [AB9540_LDO_AUX3] = {
1295 .desc = {
1296 .name = "LDO-AUX3",
1297 .ops = &ab8500_regulator_volt_mode_ops,
1298 .type = REGULATOR_VOLTAGE,
0b946411 1299 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1300 .owner = THIS_MODULE,
1301 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1302 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1303 },
8e6a8d7d
LJ		 1304 .load_lp_uA = 5000,
1305 .update_bank = 0x04,
1306 .update_reg = 0x0a,
1307 .update_mask = 0x03,
1308 .update_val = 0x01,
1309 .update_val_idle = 0x03,
1310 .update_val_normal = 0x01,
1311 .voltage_bank = 0x04,
1312 .voltage_reg = 0x21,
1313 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1314 },
1315 [AB9540_LDO_AUX4] = {
1316 .desc = {
1317 .name = "LDO-AUX4",
1318 .ops = &ab8500_regulator_volt_mode_ops,
1319 .type = REGULATOR_VOLTAGE,
1320 .id = AB9540_LDO_AUX4,
1321 .owner = THIS_MODULE,
1322 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1323 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1324 },
8e6a8d7d
LJ		 1325 .load_lp_uA = 5000,
1326 /* values for Vaux4Regu register */
1327 .update_bank = 0x04,
1328 .update_reg = 0x2e,
1329 .update_mask = 0x03,
1330 .update_val = 0x01,
1331 .update_val_idle = 0x03,
1332 .update_val_normal = 0x01,
1333 /* values for Vaux4SEL register */
1334 .voltage_bank = 0x04,
1335 .voltage_reg = 0x2f,
1336 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1337 },
1338 [AB9540_LDO_INTCORE] = {
1339 .desc = {
1340 .name = "LDO-INTCORE",
1341 .ops = &ab8500_regulator_volt_mode_ops,
1342 .type = REGULATOR_VOLTAGE,
0b946411 1343 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1344 .owner = THIS_MODULE,
1345 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1346 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1347 },
8e6a8d7d
LJ		 1348 .load_lp_uA = 5000,
1349 .update_bank = 0x03,
1350 .update_reg = 0x80,
1351 .update_mask = 0x44,
1352 .update_val = 0x44,
1353 .update_val_idle = 0x44,
1354 .update_val_normal = 0x04,
1355 .voltage_bank = 0x03,
1356 .voltage_reg = 0x80,
1357 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1358 .voltage_shift = 3,
1359 },
6909b452 1360
8e6a8d7d
LJ		 1361 /*
1362 * Fixed Voltage Regulators
1363 * name, fixed mV,
1364 * update bank, reg, mask, enable val
1365 */
1366 [AB9540_LDO_TVOUT] = {
1367 .desc = {
1368 .name = "LDO-TVOUT",
1369 .ops = &ab8500_regulator_mode_ops,
1370 .type = REGULATOR_VOLTAGE,
0b946411 1371 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1372 .owner = THIS_MODULE,
1373 .n_voltages = 1,
b080c78a 1374 .volt_table = fixed_2000000_voltage,
a4d68468 1375 .enable_time = 10000,
8e6a8d7d
LJ		 1376 },
1377 .delay = 10000,
8e6a8d7d
LJ		 1378 .load_lp_uA = 1000,
1379 .update_bank = 0x03,
1380 .update_reg = 0x80,
1381 .update_mask = 0x82,
1382 .update_val = 0x02,
1383 .update_val_idle = 0x82,
1384 .update_val_normal = 0x02,
1385 },
1386 [AB9540_LDO_USB] = {
1387 .desc = {
1388 .name = "LDO-USB",
1389 .ops = &ab8500_regulator_ops,
1390 .type = REGULATOR_VOLTAGE,
1391 .id = AB9540_LDO_USB,
1392 .owner = THIS_MODULE,
1393 .n_voltages = 1,
b080c78a 1394 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1395 },
8e6a8d7d
LJ		 1396 .update_bank = 0x03,
1397 .update_reg = 0x82,
1398 .update_mask = 0x03,
1399 .update_val = 0x01,
1400 .update_val_idle = 0x03,
1401 .update_val_normal = 0x01,
1402 },
1403 [AB9540_LDO_AUDIO] = {
1404 .desc = {
1405 .name = "LDO-AUDIO",
1406 .ops = &ab8500_regulator_ops,
1407 .type = REGULATOR_VOLTAGE,
0b946411 1408 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1409 .owner = THIS_MODULE,
1410 .n_voltages = 1,
b080c78a 1411 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1412 },
8e6a8d7d
LJ		 1413 .update_bank = 0x03,
1414 .update_reg = 0x83,
1415 .update_mask = 0x02,
1416 .update_val = 0x02,
1417 },
1418 [AB9540_LDO_ANAMIC1] = {
1419 .desc = {
1420 .name = "LDO-ANAMIC1",
1421 .ops = &ab8500_regulator_ops,
1422 .type = REGULATOR_VOLTAGE,
0b946411 1423 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1424 .owner = THIS_MODULE,
1425 .n_voltages = 1,
b080c78a 1426 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1427 },
8e6a8d7d
LJ		 1428 .update_bank = 0x03,
1429 .update_reg = 0x83,
1430 .update_mask = 0x08,
1431 .update_val = 0x08,
1432 },
1433 [AB9540_LDO_ANAMIC2] = {
1434 .desc = {
1435 .name = "LDO-ANAMIC2",
1436 .ops = &ab8500_regulator_ops,
1437 .type = REGULATOR_VOLTAGE,
0b946411 1438 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1439 .owner = THIS_MODULE,
1440 .n_voltages = 1,
b080c78a 1441 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1442 },
8e6a8d7d
LJ		 1443 .update_bank = 0x03,
1444 .update_reg = 0x83,
1445 .update_mask = 0x10,
1446 .update_val = 0x10,
1447 },
1448 [AB9540_LDO_DMIC] = {
1449 .desc = {
1450 .name = "LDO-DMIC",
1451 .ops = &ab8500_regulator_ops,
1452 .type = REGULATOR_VOLTAGE,
0b946411 1453 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1454 .owner = THIS_MODULE,
1455 .n_voltages = 1,
b080c78a 1456 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1457 },
8e6a8d7d
LJ		 1458 .update_bank = 0x03,
1459 .update_reg = 0x83,
1460 .update_mask = 0x04,
1461 .update_val = 0x04,
1462 },
1463
1464 /*
1465 * Regulators with fixed voltage and normal/idle modes
1466 */
1467 [AB9540_LDO_ANA] = {
1468 .desc = {
1469 .name = "LDO-ANA",
1470 .ops = &ab8500_regulator_mode_ops,
1471 .type = REGULATOR_VOLTAGE,
0b946411 1472 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1473 .owner = THIS_MODULE,
1474 .n_voltages = 1,
b080c78a 1475 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1476 },
8e6a8d7d
LJ		 1477 .load_lp_uA = 1000,
1478 .update_bank = 0x04,
1479 .update_reg = 0x06,
1480 .update_mask = 0x0c,
1481 .update_val = 0x08,
1482 .update_val_idle = 0x0c,
1483 .update_val_normal = 0x08,
1484 },
c789ca20
SI		 1485};
1486
ae0a9a3e
LJ		 1487/* AB8540 regulator information */
1488static struct ab8500_regulator_info
1489 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1490 /*
1491 * Variable Voltage Regulators
1492 * name, min mV, max mV,
1493 * update bank, reg, mask, enable val
1494 * volt bank, reg, mask, table, table length
1495 */
1496 [AB8540_LDO_AUX1] = {
1497 .desc = {
1498 .name = "LDO-AUX1",
1499 .ops = &ab8500_regulator_volt_mode_ops,
1500 .type = REGULATOR_VOLTAGE,
0b946411 1501 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1502 .owner = THIS_MODULE,
1503 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1504 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1505 },
1506 .load_lp_uA = 5000,
1507 .update_bank = 0x04,
1508 .update_reg = 0x09,
1509 .update_mask = 0x03,
1510 .update_val = 0x01,
1511 .update_val_idle = 0x03,
1512 .update_val_normal = 0x01,
1513 .voltage_bank = 0x04,
1514 .voltage_reg = 0x1f,
1515 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1516 },
1517 [AB8540_LDO_AUX2] = {
1518 .desc = {
1519 .name = "LDO-AUX2",
1520 .ops = &ab8500_regulator_volt_mode_ops,
1521 .type = REGULATOR_VOLTAGE,
0b946411 1522 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1523 .owner = THIS_MODULE,
1524 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1525 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1526 },
1527 .load_lp_uA = 5000,
1528 .update_bank = 0x04,
1529 .update_reg = 0x09,
1530 .update_mask = 0x0c,
1531 .update_val = 0x04,
1532 .update_val_idle = 0x0c,
1533 .update_val_normal = 0x04,
1534 .voltage_bank = 0x04,
1535 .voltage_reg = 0x20,
1536 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1537 },
1538 [AB8540_LDO_AUX3] = {
1539 .desc = {
1540 .name = "LDO-AUX3",
d7607baf 1541 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1542 .type = REGULATOR_VOLTAGE,
0b946411 1543 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1544 .owner = THIS_MODULE,
1545 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1546 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1547 },
1548 .load_lp_uA = 5000,
1549 .update_bank = 0x04,
1550 .update_reg = 0x0a,
1551 .update_mask = 0x03,
1552 .update_val = 0x01,
1553 .update_val_idle = 0x03,
1554 .update_val_normal = 0x01,
1555 .voltage_bank = 0x04,
1556 .voltage_reg = 0x21,
1557 .voltage_mask = 0x07,
d7607baf
LJ		 1558 .expand_register = {
1559 .voltage_limit = 8,
1560 .voltage_bank = 0x04,
1561 .voltage_reg = 0x01,
1562 .voltage_mask = 0x10,
1563 .voltage_shift = 1,
1564 }
ae0a9a3e
LJ		 1565 },
1566 [AB8540_LDO_AUX4] = {
1567 .desc = {
1568 .name = "LDO-AUX4",
1569 .ops = &ab8500_regulator_volt_mode_ops,
1570 .type = REGULATOR_VOLTAGE,
0b946411 1571 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1572 .owner = THIS_MODULE,
1573 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1574 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1575 },
1576 .load_lp_uA = 5000,
1577 /* values for Vaux4Regu register */
1578 .update_bank = 0x04,
1579 .update_reg = 0x2e,
1580 .update_mask = 0x03,
1581 .update_val = 0x01,
1582 .update_val_idle = 0x03,
1583 .update_val_normal = 0x01,
1584 /* values for Vaux4SEL register */
1585 .voltage_bank = 0x04,
1586 .voltage_reg = 0x2f,
1587 .voltage_mask = 0x0f,
ae0a9a3e 1588 },
684d5ce4
ZH		 1589 [AB8540_LDO_AUX5] = {
1590 .desc = {
1591 .name = "LDO-AUX5",
1592 .ops = &ab8500_regulator_volt_mode_ops,
1593 .type = REGULATOR_VOLTAGE,
1594 .id = AB8540_LDO_AUX5,
1595 .owner = THIS_MODULE,
1596 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1597 },
1598 .load_lp_uA = 20000,
1599 /* values for Vaux5Regu register */
1600 .update_bank = 0x04,
1601 .update_reg = 0x32,
1602 .update_mask = 0x03,
1603 .update_val = 0x01,
1604 .update_val_idle = 0x03,
1605 .update_val_normal = 0x01,
1606 /* values for Vaux5SEL register */
1607 .voltage_bank = 0x04,
1608 .voltage_reg = 0x33,
1609 .voltage_mask = 0x3f,
1610 .voltages = ldo_vaux56_ab8540_voltages,
1611 .voltages_len = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1612 },
1613 [AB8540_LDO_AUX6] = {
1614 .desc = {
1615 .name = "LDO-AUX6",
1616 .ops = &ab8500_regulator_volt_mode_ops,
1617 .type = REGULATOR_VOLTAGE,
1618 .id = AB8540_LDO_AUX6,
1619 .owner = THIS_MODULE,
1620 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1621 },
1622 .load_lp_uA = 20000,
1623 /* values for Vaux6Regu register */
1624 .update_bank = 0x04,
1625 .update_reg = 0x35,
1626 .update_mask = 0x03,
1627 .update_val = 0x01,
1628 .update_val_idle = 0x03,
1629 .update_val_normal = 0x01,
1630 /* values for Vaux6SEL register */
1631 .voltage_bank = 0x04,
1632 .voltage_reg = 0x36,
1633 .voltage_mask = 0x3f,
1634 .voltages = ldo_vaux56_ab8540_voltages,
1635 .voltages_len = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
1636 },
ae0a9a3e
LJ		 1637 [AB8540_LDO_INTCORE] = {
1638 .desc = {
1639 .name = "LDO-INTCORE",
1640 .ops = &ab8500_regulator_volt_mode_ops,
1641 .type = REGULATOR_VOLTAGE,
0b946411 1642 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1643 .owner = THIS_MODULE,
1644 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1645 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1646 },
1647 .load_lp_uA = 5000,
1648 .update_bank = 0x03,
1649 .update_reg = 0x80,
1650 .update_mask = 0x44,
1651 .update_val = 0x44,
1652 .update_val_idle = 0x44,
1653 .update_val_normal = 0x04,
1654 .voltage_bank = 0x03,
1655 .voltage_reg = 0x80,
1656 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1657 .voltage_shift = 3,
1658 },
1659
1660 /*
1661 * Fixed Voltage Regulators
1662 * name, fixed mV,
1663 * update bank, reg, mask, enable val
1664 */
1665 [AB8540_LDO_TVOUT] = {
1666 .desc = {
1667 .name = "LDO-TVOUT",
1668 .ops = &ab8500_regulator_mode_ops,
1669 .type = REGULATOR_VOLTAGE,
0b946411 1670 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1671 .owner = THIS_MODULE,
1672 .n_voltages = 1,
a4d68468 1673 .enable_time = 10000,
ae0a9a3e
LJ		 1674 },
1675 .delay = 10000,
1676 .load_lp_uA = 1000,
1677 .update_bank = 0x03,
1678 .update_reg = 0x80,
1679 .update_mask = 0x82,
1680 .update_val = 0x02,
1681 .update_val_idle = 0x82,
1682 .update_val_normal = 0x02,
1683 },
1684 [AB8540_LDO_AUDIO] = {
1685 .desc = {
1686 .name = "LDO-AUDIO",
1687 .ops = &ab8500_regulator_ops,
1688 .type = REGULATOR_VOLTAGE,
0b946411 1689 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1690 .owner = THIS_MODULE,
1691 .n_voltages = 1,
b080c78a 1692 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1693 },
1694 .update_bank = 0x03,
1695 .update_reg = 0x83,
1696 .update_mask = 0x02,
1697 .update_val = 0x02,
1698 },
1699 [AB8540_LDO_ANAMIC1] = {
1700 .desc = {
1701 .name = "LDO-ANAMIC1",
4c84b4dd 1702 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1703 .type = REGULATOR_VOLTAGE,
0b946411 1704 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1705 .owner = THIS_MODULE,
1706 .n_voltages = 1,
b080c78a 1707 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1708 },
4c84b4dd 1709 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1710 .update_bank = 0x03,
1711 .update_reg = 0x83,
1712 .update_mask = 0x08,
1713 .update_val = 0x08,
4c84b4dd
LJ		 1714 .mode_bank = 0x03,
1715 .mode_reg = 0x83,
1716 .mode_mask = 0x20,
1717 .mode_val_idle = 0x20,
1718 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1719 },
1720 [AB8540_LDO_ANAMIC2] = {
1721 .desc = {
1722 .name = "LDO-ANAMIC2",
4c84b4dd 1723 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1724 .type = REGULATOR_VOLTAGE,
0b946411 1725 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1726 .owner = THIS_MODULE,
1727 .n_voltages = 1,
b080c78a 1728 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1729 },
4c84b4dd 1730 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1731 .update_bank = 0x03,
1732 .update_reg = 0x83,
1733 .update_mask = 0x10,
1734 .update_val = 0x10,
4c84b4dd
LJ		 1735 .mode_bank = 0x03,
1736 .mode_reg = 0x83,
1737 .mode_mask = 0x20,
1738 .mode_val_idle = 0x20,
1739 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1740 },
1741 [AB8540_LDO_DMIC] = {
1742 .desc = {
1743 .name = "LDO-DMIC",
4c84b4dd 1744 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1745 .type = REGULATOR_VOLTAGE,
0b946411 1746 .id = AB8540_LDO_DMIC,
ae0a9a3e 1747 .owner = THIS_MODULE,
4c84b4dd 1748 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
ae0a9a3e 1749 },
4c84b4dd 1750 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1751 .update_bank = 0x03,
1752 .update_reg = 0x83,
1753 .update_mask = 0x04,
1754 .update_val = 0x04,
4c84b4dd
LJ		 1755 .voltage_bank = 0x03,
1756 .voltage_reg = 0x83,
1757 .voltage_mask = 0xc0,
1758 .voltages = ldo_vdmic_voltages,
1759 .voltages_len = ARRAY_SIZE(ldo_vdmic_voltages),
ae0a9a3e
LJ		 1760 },
1761
1762 /*
1763 * Regulators with fixed voltage and normal/idle modes
1764 */
1765 [AB8540_LDO_ANA] = {
1766 .desc = {
1767 .name = "LDO-ANA",
1768 .ops = &ab8500_regulator_mode_ops,
1769 .type = REGULATOR_VOLTAGE,
0b946411 1770 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1771 .owner = THIS_MODULE,
1772 .n_voltages = 1,
b080c78a 1773 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1774 },
1775 .load_lp_uA = 1000,
1776 .update_bank = 0x04,
1777 .update_reg = 0x06,
1778 .update_mask = 0x0c,
1779 .update_val = 0x04,
1780 .update_val_idle = 0x0c,
1781 .update_val_normal = 0x04,
1782 },
1783 [AB8540_LDO_SDIO] = {
1784 .desc = {
1785 .name = "LDO-SDIO",
1786 .ops = &ab8500_regulator_volt_mode_ops,
1787 .type = REGULATOR_VOLTAGE,
1788 .id = AB8540_LDO_SDIO,
1789 .owner = THIS_MODULE,
62ab4111
LJ		 1790 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1791 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1792 },
ae0a9a3e
LJ		 1793 .load_lp_uA = 5000,
1794 .update_bank = 0x03,
1795 .update_reg = 0x88,
1796 .update_mask = 0x30,
1797 .update_val = 0x10,
1798 .update_val_idle = 0x30,
1799 .update_val_normal = 0x10,
1800 .voltage_bank = 0x03,
1801 .voltage_reg = 0x88,
1802 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1803 },
1804};
1805
3fe52289
LJ		 1806static struct ab8500_shared_mode ldo_anamic1_shared = {
1807 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1808};
1809
1810static struct ab8500_shared_mode ldo_anamic2_shared = {
1811 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1812};
1813
4c84b4dd
LJ		 1814static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1815 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1816};
1817
1818static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1819 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1820};
1821
79568b94
BJ		 1822struct ab8500_reg_init {
1823 u8 bank;
1824 u8 addr;
1825 u8 mask;
1826};
1827
1828#define REG_INIT(_id, _bank, _addr, _mask) \
1829 [_id] = { \
1830 .bank = _bank, \
1831 .addr = _addr, \
1832 .mask = _mask, \
1833 }
1834
8e6a8d7d 1835/* AB8500 register init */
79568b94
BJ		 1836static struct ab8500_reg_init ab8500_reg_init[] = {
1837 /*
33bc8f46 1838 * 0x30, VanaRequestCtrl
79568b94
BJ		 1839 * 0xc0, VextSupply1RequestCtrl
1840 */
43a5911b 1841 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1842 /*
1843 * 0x03, VextSupply2RequestCtrl
1844 * 0x0c, VextSupply3RequestCtrl
1845 * 0x30, Vaux1RequestCtrl
1846 * 0xc0, Vaux2RequestCtrl
1847 */
1848 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1849 /*
1850 * 0x03, Vaux3RequestCtrl
1851 * 0x04, SwHPReq
1852 */
1853 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1854 /*
1855 * 0x08, VanaSysClkReq1HPValid
1856 * 0x20, Vaux1SysClkReq1HPValid
1857 * 0x40, Vaux2SysClkReq1HPValid
1858 * 0x80, Vaux3SysClkReq1HPValid
1859 */
43a5911b 1860 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1861 /*
1862 * 0x10, VextSupply1SysClkReq1HPValid
1863 * 0x20, VextSupply2SysClkReq1HPValid
1864 * 0x40, VextSupply3SysClkReq1HPValid
1865 */
43a5911b 1866 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1867 /*
1868 * 0x08, VanaHwHPReq1Valid
1869 * 0x20, Vaux1HwHPReq1Valid
1870 * 0x40, Vaux2HwHPReq1Valid
1871 * 0x80, Vaux3HwHPReq1Valid
1872 */
43a5911b 1873 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1874 /*
1875 * 0x01, VextSupply1HwHPReq1Valid
1876 * 0x02, VextSupply2HwHPReq1Valid
1877 * 0x04, VextSupply3HwHPReq1Valid
1878 */
43a5911b 1879 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1880 /*
1881 * 0x08, VanaHwHPReq2Valid
1882 * 0x20, Vaux1HwHPReq2Valid
1883 * 0x40, Vaux2HwHPReq2Valid
1884 * 0x80, Vaux3HwHPReq2Valid
1885 */
43a5911b 1886 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1887 /*
1888 * 0x01, VextSupply1HwHPReq2Valid
1889 * 0x02, VextSupply2HwHPReq2Valid
1890 * 0x04, VextSupply3HwHPReq2Valid
1891 */
43a5911b 1892 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1893 /*
1894 * 0x20, VanaSwHPReqValid
1895 * 0x80, Vaux1SwHPReqValid
1896 */
43a5911b 1897 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1898 /*
1899 * 0x01, Vaux2SwHPReqValid
1900 * 0x02, Vaux3SwHPReqValid
1901 * 0x04, VextSupply1SwHPReqValid
1902 * 0x08, VextSupply2SwHPReqValid
1903 * 0x10, VextSupply3SwHPReqValid
1904 */
43a5911b 1905 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1906 /*
1907 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1908 * 0x04, SysClkReq3Valid1
1909 * 0x08, SysClkReq4Valid1
1910 * 0x10, SysClkReq5Valid1
1911 * 0x20, SysClkReq6Valid1
1912 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1913 * 0x80, SysClkReq8Valid1
1914 */
1915 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1916 /*
1917 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1918 * 0x04, SysClkReq3Valid2
1919 * 0x08, SysClkReq4Valid2
1920 * 0x10, SysClkReq5Valid2
1921 * 0x20, SysClkReq6Valid2
1922 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1923 * 0x80, SysClkReq8Valid2
1924 */
1925 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1926 /*
1927 * 0x02, VTVoutEna
1928 * 0x04, Vintcore12Ena
1929 * 0x38, Vintcore12Sel
1930 * 0x40, Vintcore12LP
1931 * 0x80, VTVoutLP
1932 */
1933 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1934 /*
1935 * 0x02, VaudioEna
1936 * 0x04, VdmicEna
1937 * 0x08, Vamic1Ena
1938 * 0x10, Vamic2Ena
1939 */
1940 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1941 /*
1942 * 0x01, Vamic1_dzout
1943 * 0x02, Vamic2_dzout
1944 */
1945 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1946 /*
43a5911b 1947 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1948 * 0x0c, VanaRegu
79568b94
BJ		 1949 */
1950 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1951 /*
1952 * 0x01, VrefDDREna
1953 * 0x02, VrefDDRSleepMode
1954 */
1955 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1956 /*
1957 * 0x03, VextSupply1Regu
1958 * 0x0c, VextSupply2Regu
1959 * 0x30, VextSupply3Regu
1960 * 0x40, ExtSupply2Bypass
1961 * 0x80, ExtSupply3Bypass
1962 */
1963 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1964 /*
1965 * 0x03, Vaux1Regu
1966 * 0x0c, Vaux2Regu
1967 */
1968 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1969 /*
1970 * 0x03, Vaux3Regu
1971 */
43a5911b 1972 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1973 /*
1974 * 0x0f, Vaux1Sel
1975 */
1976 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1977 /*
1978 * 0x0f, Vaux2Sel
1979 */
1980 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1981 /*
1982 * 0x07, Vaux3Sel
1983 */
43a5911b 1984 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1985 /*
1986 * 0x01, VextSupply12LP
1987 */
1988 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1989 /*
1990 * 0x04, Vaux1Disch
1991 * 0x08, Vaux2Disch
1992 * 0x10, Vaux3Disch
1993 * 0x20, Vintcore12Disch
1994 * 0x40, VTVoutDisch
1995 * 0x80, VaudioDisch
1996 */
43a5911b 1997 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1998 /*
1999 * 0x02, VanaDisch
2000 * 0x04, VdmicPullDownEna
2001 * 0x10, VdmicDisch
2002 */
43a5911b 2003 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 2004};
2005
547f384f
LJ		 2006/* AB8505 register init */
2007static struct ab8500_reg_init ab8505_reg_init[] = {
2008 /*
2009 * 0x03, VarmRequestCtrl
2010 * 0x0c, VsmpsCRequestCtrl
2011 * 0x30, VsmpsARequestCtrl
2012 * 0xc0, VsmpsBRequestCtrl
2013 */
2014 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2015 /*
2016 * 0x03, VsafeRequestCtrl
2017 * 0x0c, VpllRequestCtrl
2018 * 0x30, VanaRequestCtrl
2019 */
2020 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
2021 /*
2022 * 0x30, Vaux1RequestCtrl
2023 * 0xc0, Vaux2RequestCtrl
2024 */
2025 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
2026 /*
2027 * 0x03, Vaux3RequestCtrl
2028 * 0x04, SwHPReq
2029 */
2030 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2031 /*
2032 * 0x01, VsmpsASysClkReq1HPValid
2033 * 0x02, VsmpsBSysClkReq1HPValid
2034 * 0x04, VsafeSysClkReq1HPValid
2035 * 0x08, VanaSysClkReq1HPValid
2036 * 0x10, VpllSysClkReq1HPValid
2037 * 0x20, Vaux1SysClkReq1HPValid
2038 * 0x40, Vaux2SysClkReq1HPValid
2039 * 0x80, Vaux3SysClkReq1HPValid
2040 */
2041 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2042 /*
2043 * 0x01, VsmpsCSysClkReq1HPValid
2044 * 0x02, VarmSysClkReq1HPValid
2045 * 0x04, VbbSysClkReq1HPValid
2046 * 0x08, VsmpsMSysClkReq1HPValid
2047 */
2048 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2049 /*
2050 * 0x01, VsmpsAHwHPReq1Valid
2051 * 0x02, VsmpsBHwHPReq1Valid
2052 * 0x04, VsafeHwHPReq1Valid
2053 * 0x08, VanaHwHPReq1Valid
2054 * 0x10, VpllHwHPReq1Valid
2055 * 0x20, Vaux1HwHPReq1Valid
2056 * 0x40, Vaux2HwHPReq1Valid
2057 * 0x80, Vaux3HwHPReq1Valid
2058 */
2059 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2060 /*
2061 * 0x08, VsmpsMHwHPReq1Valid
2062 */
2063 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2064 /*
2065 * 0x01, VsmpsAHwHPReq2Valid
2066 * 0x02, VsmpsBHwHPReq2Valid
2067 * 0x04, VsafeHwHPReq2Valid
2068 * 0x08, VanaHwHPReq2Valid
2069 * 0x10, VpllHwHPReq2Valid
2070 * 0x20, Vaux1HwHPReq2Valid
2071 * 0x40, Vaux2HwHPReq2Valid
2072 * 0x80, Vaux3HwHPReq2Valid
2073 */
2074 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2075 /*
2076 * 0x08, VsmpsMHwHPReq2Valid
2077 */
2078 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2079 /*
2080 * 0x01, VsmpsCSwHPReqValid
2081 * 0x02, VarmSwHPReqValid
2082 * 0x04, VsmpsASwHPReqValid
2083 * 0x08, VsmpsBSwHPReqValid
2084 * 0x10, VsafeSwHPReqValid
2085 * 0x20, VanaSwHPReqValid
2086 * 0x40, VpllSwHPReqValid
2087 * 0x80, Vaux1SwHPReqValid
2088 */
2089 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2090 /*
2091 * 0x01, Vaux2SwHPReqValid
2092 * 0x02, Vaux3SwHPReqValid
2093 * 0x20, VsmpsMSwHPReqValid
2094 */
2095 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2096 /*
2097 * 0x02, SysClkReq2Valid1
2098 * 0x04, SysClkReq3Valid1
2099 * 0x08, SysClkReq4Valid1
2100 */
2101 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2102 /*
2103 * 0x02, SysClkReq2Valid2
2104 * 0x04, SysClkReq3Valid2
2105 * 0x08, SysClkReq4Valid2
2106 */
2107 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2108 /*
2109 * 0x01, Vaux4SwHPReqValid
2110 * 0x02, Vaux4HwHPReq2Valid
2111 * 0x04, Vaux4HwHPReq1Valid
2112 * 0x08, Vaux4SysClkReq1HPValid
2113 */
2114 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2115 /*
2116 * 0x02, VadcEna
2117 * 0x04, VintCore12Ena
2118 * 0x38, VintCore12Sel
2119 * 0x40, VintCore12LP
2120 * 0x80, VadcLP
2121 */
2122 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2123 /*
2124 * 0x02, VaudioEna
2125 * 0x04, VdmicEna
2126 * 0x08, Vamic1Ena
2127 * 0x10, Vamic2Ena
2128 */
2129 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2130 /*
2131 * 0x01, Vamic1_dzout
2132 * 0x02, Vamic2_dzout
2133 */
2134 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2135 /*
2136 * 0x03, VsmpsARegu
2137 * 0x0c, VsmpsASelCtrl
2138 * 0x10, VsmpsAAutoMode
2139 * 0x20, VsmpsAPWMMode
2140 */
2141 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2142 /*
2143 * 0x03, VsmpsBRegu
2144 * 0x0c, VsmpsBSelCtrl
2145 * 0x10, VsmpsBAutoMode
2146 * 0x20, VsmpsBPWMMode
2147 */
2148 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2149 /*
2150 * 0x03, VsafeRegu
2151 * 0x0c, VsafeSelCtrl
2152 * 0x10, VsafeAutoMode
2153 * 0x20, VsafePWMMode
2154 */
2155 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2156 /*
2157 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2158 * 0x0c, VanaRegu
2159 */
2160 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2161 /*
2162 * 0x03, VextSupply1Regu
2163 * 0x0c, VextSupply2Regu
2164 * 0x30, VextSupply3Regu
2165 * 0x40, ExtSupply2Bypass
2166 * 0x80, ExtSupply3Bypass
2167 */
2168 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2169 /*
2170 * 0x03, Vaux1Regu
2171 * 0x0c, Vaux2Regu
2172 */
2173 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2174 /*
2175 * 0x0f, Vaux3Regu
2176 */
2177 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2178 /*
2179 * 0x3f, VsmpsASel1
2180 */
2181 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2182 /*
2183 * 0x3f, VsmpsASel2
2184 */
2185 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2186 /*
2187 * 0x3f, VsmpsASel3
2188 */
2189 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2190 /*
2191 * 0x3f, VsmpsBSel1
2192 */
2193 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2194 /*
2195 * 0x3f, VsmpsBSel2
2196 */
2197 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2198 /*
2199 * 0x3f, VsmpsBSel3
2200 */
2201 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2202 /*
2203 * 0x7f, VsafeSel1
2204 */
2205 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2206 /*
2207 * 0x3f, VsafeSel2
2208 */
2209 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2210 /*
2211 * 0x3f, VsafeSel3
2212 */
2213 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2214 /*
2215 * 0x0f, Vaux1Sel
2216 */
2217 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2218 /*
2219 * 0x0f, Vaux2Sel
2220 */
2221 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2222 /*
2223 * 0x07, Vaux3Sel
2224 * 0x30, VRF1Sel
2225 */
2226 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2227 /*
2228 * 0x03, Vaux4RequestCtrl
2229 */
2230 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2231 /*
2232 * 0x03, Vaux4Regu
2233 */
2234 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2235 /*
2236 * 0x0f, Vaux4Sel
2237 */
2238 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2239 /*
2240 * 0x04, Vaux1Disch
2241 * 0x08, Vaux2Disch
2242 * 0x10, Vaux3Disch
2243 * 0x20, Vintcore12Disch
2244 * 0x40, VTVoutDisch
2245 * 0x80, VaudioDisch
2246 */
2247 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2248 /*
2249 * 0x02, VanaDisch
2250 * 0x04, VdmicPullDownEna
2251 * 0x10, VdmicDisch
2252 */
2253 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2254 /*
2255 * 0x01, Vaux4Disch
2256 */
2257 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2258 /*
2259 * 0x07, Vaux5Sel
2260 * 0x08, Vaux5LP
2261 * 0x10, Vaux5Ena
2262 * 0x20, Vaux5Disch
2263 * 0x40, Vaux5DisSfst
2264 * 0x80, Vaux5DisPulld
2265 */
2266 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2267 /*
2268 * 0x07, Vaux6Sel
2269 * 0x08, Vaux6LP
2270 * 0x10, Vaux6Ena
2271 * 0x80, Vaux6DisPulld
2272 */
2273 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2274};
2275
8e6a8d7d
LJ		 2276/* AB9540 register init */
2277static struct ab8500_reg_init ab9540_reg_init[] = {
2278 /*
2279 * 0x03, VarmRequestCtrl
2280 * 0x0c, VapeRequestCtrl
2281 * 0x30, Vsmps1RequestCtrl
2282 * 0xc0, Vsmps2RequestCtrl
2283 */
2284 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2285 /*
2286 * 0x03, Vsmps3RequestCtrl
2287 * 0x0c, VpllRequestCtrl
2288 * 0x30, VanaRequestCtrl
2289 * 0xc0, VextSupply1RequestCtrl
2290 */
2291 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2292 /*
2293 * 0x03, VextSupply2RequestCtrl
2294 * 0x0c, VextSupply3RequestCtrl
2295 * 0x30, Vaux1RequestCtrl
2296 * 0xc0, Vaux2RequestCtrl
2297 */
2298 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2299 /*
2300 * 0x03, Vaux3RequestCtrl
2301 * 0x04, SwHPReq
2302 */
2303 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2304 /*
2305 * 0x01, Vsmps1SysClkReq1HPValid
2306 * 0x02, Vsmps2SysClkReq1HPValid
2307 * 0x04, Vsmps3SysClkReq1HPValid
2308 * 0x08, VanaSysClkReq1HPValid
2309 * 0x10, VpllSysClkReq1HPValid
2310 * 0x20, Vaux1SysClkReq1HPValid
2311 * 0x40, Vaux2SysClkReq1HPValid
2312 * 0x80, Vaux3SysClkReq1HPValid
2313 */
2314 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2315 /*
2316 * 0x01, VapeSysClkReq1HPValid
2317 * 0x02, VarmSysClkReq1HPValid
2318 * 0x04, VbbSysClkReq1HPValid
2319 * 0x08, VmodSysClkReq1HPValid
2320 * 0x10, VextSupply1SysClkReq1HPValid
2321 * 0x20, VextSupply2SysClkReq1HPValid
2322 * 0x40, VextSupply3SysClkReq1HPValid
2323 */
2324 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2325 /*
2326 * 0x01, Vsmps1HwHPReq1Valid
2327 * 0x02, Vsmps2HwHPReq1Valid
2328 * 0x04, Vsmps3HwHPReq1Valid
2329 * 0x08, VanaHwHPReq1Valid
2330 * 0x10, VpllHwHPReq1Valid
2331 * 0x20, Vaux1HwHPReq1Valid
2332 * 0x40, Vaux2HwHPReq1Valid
2333 * 0x80, Vaux3HwHPReq1Valid
2334 */
2335 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2336 /*
2337 * 0x01, VextSupply1HwHPReq1Valid
2338 * 0x02, VextSupply2HwHPReq1Valid
2339 * 0x04, VextSupply3HwHPReq1Valid
2340 * 0x08, VmodHwHPReq1Valid
2341 */
2342 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2343 /*
2344 * 0x01, Vsmps1HwHPReq2Valid
2345 * 0x02, Vsmps2HwHPReq2Valid
2346 * 0x03, Vsmps3HwHPReq2Valid
2347 * 0x08, VanaHwHPReq2Valid
2348 * 0x10, VpllHwHPReq2Valid
2349 * 0x20, Vaux1HwHPReq2Valid
2350 * 0x40, Vaux2HwHPReq2Valid
2351 * 0x80, Vaux3HwHPReq2Valid
2352 */
2353 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2354 /*
2355 * 0x01, VextSupply1HwHPReq2Valid
2356 * 0x02, VextSupply2HwHPReq2Valid
2357 * 0x04, VextSupply3HwHPReq2Valid
2358 * 0x08, VmodHwHPReq2Valid
2359 */
2360 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2361 /*
2362 * 0x01, VapeSwHPReqValid
2363 * 0x02, VarmSwHPReqValid
2364 * 0x04, Vsmps1SwHPReqValid
2365 * 0x08, Vsmps2SwHPReqValid
2366 * 0x10, Vsmps3SwHPReqValid
2367 * 0x20, VanaSwHPReqValid
2368 * 0x40, VpllSwHPReqValid
2369 * 0x80, Vaux1SwHPReqValid
2370 */
2371 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2372 /*
2373 * 0x01, Vaux2SwHPReqValid
2374 * 0x02, Vaux3SwHPReqValid
2375 * 0x04, VextSupply1SwHPReqValid
2376 * 0x08, VextSupply2SwHPReqValid
2377 * 0x10, VextSupply3SwHPReqValid
2378 * 0x20, VmodSwHPReqValid
2379 */
2380 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2381 /*
2382 * 0x02, SysClkReq2Valid1
2383 * ...
2384 * 0x80, SysClkReq8Valid1
2385 */
2386 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2387 /*
2388 * 0x02, SysClkReq2Valid2
2389 * ...
2390 * 0x80, SysClkReq8Valid2
2391 */
2392 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2393 /*
2394 * 0x01, Vaux4SwHPReqValid
2395 * 0x02, Vaux4HwHPReq2Valid
2396 * 0x04, Vaux4HwHPReq1Valid
2397 * 0x08, Vaux4SysClkReq1HPValid
2398 */
2399 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2400 /*
2401 * 0x02, VTVoutEna
2402 * 0x04, Vintcore12Ena
2403 * 0x38, Vintcore12Sel
2404 * 0x40, Vintcore12LP
2405 * 0x80, VTVoutLP
2406 */
2407 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2408 /*
2409 * 0x02, VaudioEna
2410 * 0x04, VdmicEna
2411 * 0x08, Vamic1Ena
2412 * 0x10, Vamic2Ena
2413 */
2414 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2415 /*
2416 * 0x01, Vamic1_dzout
2417 * 0x02, Vamic2_dzout
2418 */
2419 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2420 /*
2421 * 0x03, Vsmps1Regu
2422 * 0x0c, Vsmps1SelCtrl
2423 * 0x10, Vsmps1AutoMode
2424 * 0x20, Vsmps1PWMMode
2425 */
2426 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2427 /*
2428 * 0x03, Vsmps2Regu
2429 * 0x0c, Vsmps2SelCtrl
2430 * 0x10, Vsmps2AutoMode
2431 * 0x20, Vsmps2PWMMode
2432 */
2433 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2434 /*
2435 * 0x03, Vsmps3Regu
2436 * 0x0c, Vsmps3SelCtrl
2437 * NOTE! PRCMU register
2438 */
2439 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2440 /*
2441 * 0x03, VpllRegu
2442 * 0x0c, VanaRegu
2443 */
2444 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2445 /*
2446 * 0x03, VextSupply1Regu
2447 * 0x0c, VextSupply2Regu
2448 * 0x30, VextSupply3Regu
2449 * 0x40, ExtSupply2Bypass
2450 * 0x80, ExtSupply3Bypass
2451 */
2452 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2453 /*
2454 * 0x03, Vaux1Regu
2455 * 0x0c, Vaux2Regu
2456 */
2457 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2458 /*
2459 * 0x0c, Vrf1Regu
2460 * 0x03, Vaux3Regu
2461 */
2462 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2463 /*
2464 * 0x3f, Vsmps1Sel1
2465 */
2466 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2467 /*
2468 * 0x3f, Vsmps1Sel2
2469 */
2470 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2471 /*
2472 * 0x3f, Vsmps1Sel3
2473 */
2474 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2475 /*
2476 * 0x3f, Vsmps2Sel1
2477 */
2478 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2479 /*
2480 * 0x3f, Vsmps2Sel2
2481 */
2482 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2483 /*
2484 * 0x3f, Vsmps2Sel3
2485 */
2486 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2487 /*
2488 * 0x7f, Vsmps3Sel1
2489 * NOTE! PRCMU register
2490 */
2491 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2492 /*
2493 * 0x7f, Vsmps3Sel2
2494 * NOTE! PRCMU register
2495 */
2496 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2497 /*
2498 * 0x0f, Vaux1Sel
2499 */
2500 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2501 /*
2502 * 0x0f, Vaux2Sel
2503 */
2504 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2505 /*
2506 * 0x07, Vaux3Sel
2507 * 0x30, Vrf1Sel
2508 */
2509 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2510 /*
2511 * 0x01, VextSupply12LP
2512 */
2513 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2514 /*
2515 * 0x03, Vaux4RequestCtrl
2516 */
2517 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2518 /*
2519 * 0x03, Vaux4Regu
2520 */
2521 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2522 /*
2523 * 0x08, Vaux4Sel
2524 */
2525 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2526 /*
2527 * 0x01, VpllDisch
2528 * 0x02, Vrf1Disch
2529 * 0x04, Vaux1Disch
2530 * 0x08, Vaux2Disch
2531 * 0x10, Vaux3Disch
2532 * 0x20, Vintcore12Disch
2533 * 0x40, VTVoutDisch
2534 * 0x80, VaudioDisch
2535 */
2536 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2537 /*
2538 * 0x01, VsimDisch
2539 * 0x02, VanaDisch
2540 * 0x04, VdmicPullDownEna
2541 * 0x08, VpllPullDownEna
2542 * 0x10, VdmicDisch
2543 */
2544 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2545 /*
2546 * 0x01, Vaux4Disch
2547 */
2548 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2549};
2550
ae0a9a3e
LJ		 2551/* AB8540 register init */
2552static struct ab8500_reg_init ab8540_reg_init[] = {
2553 /*
2554 * 0x01, VSimSycClkReq1Valid
2555 * 0x02, VSimSycClkReq2Valid
2556 * 0x04, VSimSycClkReq3Valid
2557 * 0x08, VSimSycClkReq4Valid
2558 * 0x10, VSimSycClkReq5Valid
2559 * 0x20, VSimSycClkReq6Valid
2560 * 0x40, VSimSycClkReq7Valid
2561 * 0x80, VSimSycClkReq8Valid
2562 */
2563 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2564 /*
2565 * 0x03, VarmRequestCtrl
2566 * 0x0c, VapeRequestCtrl
2567 * 0x30, Vsmps1RequestCtrl
2568 * 0xc0, Vsmps2RequestCtrl
2569 */
2570 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2571 /*
2572 * 0x03, Vsmps3RequestCtrl
2573 * 0x0c, VpllRequestCtrl
2574 * 0x30, VanaRequestCtrl
2575 * 0xc0, VextSupply1RequestCtrl
2576 */
2577 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2578 /*
2579 * 0x03, VextSupply2RequestCtrl
2580 * 0x0c, VextSupply3RequestCtrl
2581 * 0x30, Vaux1RequestCtrl
2582 * 0xc0, Vaux2RequestCtrl
2583 */
2584 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2585 /*
2586 * 0x03, Vaux3RequestCtrl
2587 * 0x04, SwHPReq
2588 */
2589 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2590 /*
2591 * 0x01, Vsmps1SysClkReq1HPValid
2592 * 0x02, Vsmps2SysClkReq1HPValid
2593 * 0x04, Vsmps3SysClkReq1HPValid
2594 * 0x08, VanaSysClkReq1HPValid
2595 * 0x10, VpllSysClkReq1HPValid
2596 * 0x20, Vaux1SysClkReq1HPValid
2597 * 0x40, Vaux2SysClkReq1HPValid
2598 * 0x80, Vaux3SysClkReq1HPValid
2599 */
2600 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2601 /*
2602 * 0x01, VapeSysClkReq1HPValid
2603 * 0x02, VarmSysClkReq1HPValid
2604 * 0x04, VbbSysClkReq1HPValid
2605 * 0x10, VextSupply1SysClkReq1HPValid
2606 * 0x20, VextSupply2SysClkReq1HPValid
2607 * 0x40, VextSupply3SysClkReq1HPValid
2608 */
2609 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2610 /*
2611 * 0x01, Vsmps1HwHPReq1Valid
2612 * 0x02, Vsmps2HwHPReq1Valid
2613 * 0x04, Vsmps3HwHPReq1Valid
2614 * 0x08, VanaHwHPReq1Valid
2615 * 0x10, VpllHwHPReq1Valid
2616 * 0x20, Vaux1HwHPReq1Valid
2617 * 0x40, Vaux2HwHPReq1Valid
2618 * 0x80, Vaux3HwHPReq1Valid
2619 */
2620 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2621 /*
2622 * 0x01, VextSupply1HwHPReq1Valid
2623 * 0x02, VextSupply2HwHPReq1Valid
2624 * 0x04, VextSupply3HwHPReq1Valid
2625 */
2626 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2627 /*
2628 * 0x01, Vsmps1HwHPReq2Valid
2629 * 0x02, Vsmps2HwHPReq2Valid
2630 * 0x03, Vsmps3HwHPReq2Valid
2631 * 0x08, VanaHwHPReq2Valid
2632 * 0x10, VpllHwHPReq2Valid
2633 * 0x20, Vaux1HwHPReq2Valid
2634 * 0x40, Vaux2HwHPReq2Valid
2635 * 0x80, Vaux3HwHPReq2Valid
2636 */
2637 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2638 /*
2639 * 0x01, VextSupply1HwHPReq2Valid
2640 * 0x02, VextSupply2HwHPReq2Valid
2641 * 0x04, VextSupply3HwHPReq2Valid
2642 */
2643 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2644 /*
2645 * 0x01, VapeSwHPReqValid
2646 * 0x02, VarmSwHPReqValid
2647 * 0x04, Vsmps1SwHPReqValid
2648 * 0x08, Vsmps2SwHPReqValid
2649 * 0x10, Vsmps3SwHPReqValid
2650 * 0x20, VanaSwHPReqValid
2651 * 0x40, VpllSwHPReqValid
2652 * 0x80, Vaux1SwHPReqValid
2653 */
2654 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2655 /*
2656 * 0x01, Vaux2SwHPReqValid
2657 * 0x02, Vaux3SwHPReqValid
2658 * 0x04, VextSupply1SwHPReqValid
2659 * 0x08, VextSupply2SwHPReqValid
2660 * 0x10, VextSupply3SwHPReqValid
2661 */
2662 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2663 /*
2664 * 0x02, SysClkReq2Valid1
2665 * ...
2666 * 0x80, SysClkReq8Valid1
2667 */
2668 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2669 /*
2670 * 0x02, SysClkReq2Valid2
2671 * ...
2672 * 0x80, SysClkReq8Valid2
2673 */
2674 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2675 /*
2676 * 0x01, Vaux4SwHPReqValid
2677 * 0x02, Vaux4HwHPReq2Valid
2678 * 0x04, Vaux4HwHPReq1Valid
2679 * 0x08, Vaux4SysClkReq1HPValid
2680 */
2681 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2682 /*
2683 * 0x01, Vaux5SwHPReqValid
2684 * 0x02, Vaux5HwHPReq2Valid
2685 * 0x04, Vaux5HwHPReq1Valid
2686 * 0x08, Vaux5SysClkReq1HPValid
2687 */
2688 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2689 /*
2690 * 0x01, Vaux6SwHPReqValid
2691 * 0x02, Vaux6HwHPReq2Valid
2692 * 0x04, Vaux6HwHPReq1Valid
2693 * 0x08, Vaux6SysClkReq1HPValid
2694 */
2695 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2696 /*
2697 * 0x01, VclkbSwHPReqValid
2698 * 0x02, VclkbHwHPReq2Valid
2699 * 0x04, VclkbHwHPReq1Valid
2700 * 0x08, VclkbSysClkReq1HPValid
2701 */
2702 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2703 /*
2704 * 0x01, Vrf1SwHPReqValid
2705 * 0x02, Vrf1HwHPReq2Valid
2706 * 0x04, Vrf1HwHPReq1Valid
2707 * 0x08, Vrf1SysClkReq1HPValid
2708 */
2709 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2710 /*
2711 * 0x02, VTVoutEna
2712 * 0x04, Vintcore12Ena
2713 * 0x38, Vintcore12Sel
2714 * 0x40, Vintcore12LP
2715 * 0x80, VTVoutLP
2716 */
2717 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2718 /*
2719 * 0x02, VaudioEna
2720 * 0x04, VdmicEna
2721 * 0x08, Vamic1Ena
2722 * 0x10, Vamic2Ena
2723 * 0x20, Vamic12LP
2724 * 0xC0, VdmicSel
2725 */
2726 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2727 /*
2728 * 0x01, Vamic1_dzout
2729 * 0x02, Vamic2_dzout
2730 */
2731 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2732 /*
2733 * 0x07, VHSICSel
2734 * 0x08, VHSICOffState
2735 * 0x10, VHSIEna
2736 * 0x20, VHSICLP
2737 */
2738 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2739 /*
2740 * 0x07, VSDIOSel
2741 * 0x08, VSDIOOffState
2742 * 0x10, VSDIOEna
2743 * 0x20, VSDIOLP
2744 */
2745 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2746 /*
2747 * 0x03, Vsmps1Regu
2748 * 0x0c, Vsmps1SelCtrl
2749 * 0x10, Vsmps1AutoMode
2750 * 0x20, Vsmps1PWMMode
2751 */
2752 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2753 /*
2754 * 0x03, Vsmps2Regu
2755 * 0x0c, Vsmps2SelCtrl
2756 * 0x10, Vsmps2AutoMode
2757 * 0x20, Vsmps2PWMMode
2758 */
2759 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2760 /*
2761 * 0x03, Vsmps3Regu
2762 * 0x0c, Vsmps3SelCtrl
2763 * 0x10, Vsmps3AutoMode
2764 * 0x20, Vsmps3PWMMode
2765 * NOTE! PRCMU register
2766 */
2767 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2768 /*
2769 * 0x03, VpllRegu
2770 * 0x0c, VanaRegu
2771 */
2772 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2773 /*
2774 * 0x03, VextSupply1Regu
2775 * 0x0c, VextSupply2Regu
2776 * 0x30, VextSupply3Regu
2777 * 0x40, ExtSupply2Bypass
2778 * 0x80, ExtSupply3Bypass
2779 */
2780 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2781 /*
2782 * 0x03, Vaux1Regu
2783 * 0x0c, Vaux2Regu
2784 */
2785 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2786 /*
2787 * 0x0c, VRF1Regu
2788 * 0x03, Vaux3Regu
2789 */
2790 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2791 /*
2792 * 0x3f, Vsmps1Sel1
2793 */
2794 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2795 /*
2796 * 0x3f, Vsmps1Sel2
2797 */
2798 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2799 /*
2800 * 0x3f, Vsmps1Sel3
2801 */
2802 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2803 /*
2804 * 0x3f, Vsmps2Sel1
2805 */
2806 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2807 /*
2808 * 0x3f, Vsmps2Sel2
2809 */
2810 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2811 /*
2812 * 0x3f, Vsmps2Sel3
2813 */
2814 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2815 /*
2816 * 0x7f, Vsmps3Sel1
2817 * NOTE! PRCMU register
2818 */
2819 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2820 /*
2821 * 0x7f, Vsmps3Sel2
2822 * NOTE! PRCMU register
2823 */
2824 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2825 /*
2826 * 0x0f, Vaux1Sel
2827 */
2828 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2829 /*
2830 * 0x0f, Vaux2Sel
2831 */
2832 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2833 /*
2834 * 0x07, Vaux3Sel
2835 * 0x70, Vrf1Sel
2836 */
2837 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2838 /*
2839 * 0x01, VextSupply12LP
2840 */
2841 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2842 /*
2843 * 0x07, Vanasel
2844 * 0x30, Vpllsel
2845 */
2846 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2847 /*
2848 * 0x03, Vaux4RequestCtrl
2849 */
2850 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2851 /*
2852 * 0x03, Vaux4Regu
2853 */
2854 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2855 /*
2856 * 0x0f, Vaux4Sel
2857 */
2858 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2859 /*
2860 * 0x03, Vaux5RequestCtrl
2861 */
2862 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2863 /*
2864 * 0x03, Vaux5Regu
2865 */
2866 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2867 /*
2868 * 0x3f, Vaux5Sel
2869 */
2870 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2871 /*
2872 * 0x03, Vaux6RequestCtrl
2873 */
2874 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2875 /*
2876 * 0x03, Vaux6Regu
2877 */
2878 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2879 /*
2880 * 0x3f, Vaux6Sel
2881 */
2882 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2883 /*
2884 * 0x03, VCLKBRequestCtrl
2885 */
2886 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2887 /*
2888 * 0x03, VCLKBRegu
2889 */
2890 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2891 /*
2892 * 0x07, VCLKBSel
2893 */
2894 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2895 /*
2896 * 0x03, Vrf1RequestCtrl
2897 */
2898 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2899 /*
2900 * 0x01, VpllDisch
2901 * 0x02, Vrf1Disch
2902 * 0x04, Vaux1Disch
2903 * 0x08, Vaux2Disch
2904 * 0x10, Vaux3Disch
2905 * 0x20, Vintcore12Disch
2906 * 0x40, VTVoutDisch
2907 * 0x80, VaudioDisch
2908 */
2909 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2910 /*
2911 * 0x02, VanaDisch
2912 * 0x04, VdmicPullDownEna
2913 * 0x08, VpllPullDownEna
2914 * 0x10, VdmicDisch
2915 */
2916 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2917 /*
2918 * 0x01, Vaux4Disch
2919 */
2920 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2921 /*
2922 * 0x01, Vaux5Disch
2923 * 0x02, Vaux6Disch
2924 * 0x04, VCLKBDisch
2925 */
2926 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2927};
2928
33aeb49e
LJ		 2929static struct {
2930 struct ab8500_regulator_info *info;
2931 int info_size;
2932 struct ab8500_reg_init *init;
2933 int init_size;
2934 struct of_regulator_match *match;
2935 int match_size;
2936} abx500_regulator;
2937
3c1b8438
LJ		 2938static int ab8500_regulator_init_registers(struct platform_device *pdev,
2939 int id, int mask, int value)
a7ac1d9e 2940{
33aeb49e 2941 struct ab8500_reg_init *reg_init = abx500_regulator.init;
a7ac1d9e
LJ		 2942 int err;
2943
3c1b8438 2944 BUG_ON(value & ~mask);
b54969ac 2945 BUG_ON(mask & ~reg_init[id].mask);
a7ac1d9e 2946
3c1b8438 2947 /* initialize register */
a7ac1d9e
LJ		 2948 err = abx500_mask_and_set_register_interruptible(
2949 &pdev->dev,
b54969ac
LJ		 2950 reg_init[id].bank,
2951 reg_init[id].addr,
3c1b8438 2952 mask, value);
a7ac1d9e
LJ		 2953 if (err < 0) {
2954 dev_err(&pdev->dev,
2955 "Failed to initialize 0x%02x, 0x%02x.\n",
b54969ac
LJ		 2956 reg_init[id].bank,
2957 reg_init[id].addr);
a7ac1d9e
LJ		 2958 return err;
2959 }
a7ac1d9e 2960 dev_vdbg(&pdev->dev,
3c1b8438 2961 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
b54969ac
LJ		 2962 reg_init[id].bank,
2963 reg_init[id].addr,
3c1b8438 2964 mask, value);
a7ac1d9e
LJ		 2965
2966 return 0;
2967}
2968
a5023574 2969static int ab8500_regulator_register(struct platform_device *pdev,
b54969ac 2970 struct regulator_init_data *init_data,
b54969ac 2971 int id, struct device_node *np)
a7ac1d9e 2972{
8e6a8d7d 2973 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
a7ac1d9e
LJ		 2974 struct ab8500_regulator_info *info = NULL;
2975 struct regulator_config config = { };
2976 int err;
2977
2978 /* assign per-regulator data */
33aeb49e 2979 info = &abx500_regulator.info[id];
a7ac1d9e
LJ		 2980 info->dev = &pdev->dev;
2981
2982 config.dev = &pdev->dev;
2983 config.init_data = init_data;
2984 config.driver_data = info;
2985 config.of_node = np;
2986
2987 /* fix for hardware before ab8500v2.0 */
8e6a8d7d 2988 if (is_ab8500_1p1_or_earlier(ab8500)) {
a7ac1d9e
LJ		 2989 if (info->desc.id == AB8500_LDO_AUX3) {
2990 info->desc.n_voltages =
2991 ARRAY_SIZE(ldo_vauxn_voltages);
ec1cc4d9 2992 info->desc.volt_table = ldo_vauxn_voltages;
a7ac1d9e
LJ		 2993 info->voltage_mask = 0xf;
2994 }
2995 }
2996
2997 /* register regulator with framework */
2998 info->regulator = regulator_register(&info->desc, &config);
2999 if (IS_ERR(info->regulator)) {
3000 err = PTR_ERR(info->regulator);
3001 dev_err(&pdev->dev, "failed to register regulator %s\n",
3002 info->desc.name);
3003 /* when we fail, un-register all earlier regulators */
3004 while (--id >= 0) {
33aeb49e 3005 info = &abx500_regulator.info[id];
a7ac1d9e
LJ		 3006 regulator_unregister(info->regulator);
3007 }
3008 return err;
3009 }
3010
3011 return 0;
3012}
3013
b54969ac 3014static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 3015 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
3016 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
3017 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
3018 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
3019 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 3020 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
3021 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
3022 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
3023 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
3024 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 3025};
3026
547f384f
LJ		 3027static struct of_regulator_match ab8505_regulator_match[] = {
3028 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
3029 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
3030 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
3031 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
3032 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
3033 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
3034 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
3035 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
3036 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
3037 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
3038 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
3039 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
3040 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
3041};
3042
ae0a9a3e
LJ		 3043static struct of_regulator_match ab8540_regulator_match[] = {
3044 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
3045 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
3046 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
3047 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 3048 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
3049 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 3050 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
3051 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
3052 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
3053 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
3054 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
3055 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
3056 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
3057 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
3058};
3059
8e6a8d7d
LJ		 3060static struct of_regulator_match ab9540_regulator_match[] = {
3061 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
3062 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
3063 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
3064 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
3065 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
3066 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
3067 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
3068 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
3069 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
3070 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
3071 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
3072};
3073
33aeb49e
LJ		 3074static void abx500_get_regulator_info(struct ab8500 *ab8500)
3075{
3076 if (is_ab9540(ab8500)) {
3077 abx500_regulator.info = ab9540_regulator_info;
3078 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
3079 abx500_regulator.init = ab9540_reg_init;
3080 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
3081 abx500_regulator.match = ab9540_regulator_match;
3082 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
3083 } else if (is_ab8505(ab8500)) {
3084 abx500_regulator.info = ab8505_regulator_info;
3085 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
3086 abx500_regulator.init = ab8505_reg_init;
3087 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
3088 abx500_regulator.match = ab8505_regulator_match;
3089 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
3090 } else if (is_ab8540(ab8500)) {
3091 abx500_regulator.info = ab8540_regulator_info;
3092 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
3093 abx500_regulator.init = ab8540_reg_init;
3094 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
3095 abx500_regulator.match = ab8540_regulator_match;
3096 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
3097 } else {
3098 abx500_regulator.info = ab8500_regulator_info;
3099 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
3100 abx500_regulator.init = ab8500_reg_init;
3101 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
3102 abx500_regulator.match = ab8500_regulator_match;
3103 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
3104 }
3105}
3106
a5023574 3107static int
b54969ac 3108ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3109 struct device_node *np)
3a8334b9 3110{
33aeb49e 3111 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3112 int err, i;
3113
33aeb49e 3114 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3115 err = ab8500_regulator_register(
33aeb49e 3116 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3117 if (err)
3118 return err;
3119 }
3120
3121 return 0;
3122}
3123
a5023574 3124static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3125{
3126 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3127 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3128 struct ab8500_platform_data *ppdata;
3129 struct ab8500_regulator_platform_data *pdata;
c789ca20 3130 int i, err;
b54969ac 3131
33aeb49e
LJ		 3132 if (!ab8500) {
3133 dev_err(&pdev->dev, "null mfd parent\n");
3134 return -EINVAL;
8e6a8d7d 3135 }
c789ca20 3136
33aeb49e
LJ		 3137 abx500_get_regulator_info(ab8500);
3138
3a8334b9 3139 if (np) {
33aeb49e
LJ		 3140 err = of_regulator_match(&pdev->dev, np,
3141 abx500_regulator.match,
3142 abx500_regulator.match_size);
3a8334b9
LJ		 3143 if (err < 0) {
3144 dev_err(&pdev->dev,
3145 "Error parsing regulator init data: %d\n", err);
3146 return err;
3147 }
3148
33aeb49e 3149 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3150 return err;
3151 }
3152
732805a5
BJ		 3153 ppdata = dev_get_platdata(ab8500->dev);
3154 if (!ppdata) {
3155 dev_err(&pdev->dev, "null parent pdata\n");
3156 return -EINVAL;
3157 }
3158
3159 pdata = ppdata->regulator;
fc24b426
BJ		 3160 if (!pdata) {
3161 dev_err(&pdev->dev, "null pdata\n");
3162 return -EINVAL;
3163 }
c789ca20 3164
cb189b07 3165 /* make sure the platform data has the correct size */
33aeb49e 3166 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3167 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3168 return -EINVAL;
3169 }
3170
da0b0c47
LJ		 3171 /* initialize debug (initial state is recorded with this call) */
3172 err = ab8500_regulator_debug_init(pdev);
3173 if (err)
3174 return err;
3175
79568b94 3176 /* initialize registers */
732805a5 3177 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3178 int id, mask, value;
79568b94 3179
732805a5
BJ		 3180 id = pdata->reg_init[i].id;
3181 mask = pdata->reg_init[i].mask;
3182 value = pdata->reg_init[i].value;
79568b94
BJ		 3183
3184 /* check for configuration errors */
33aeb49e 3185 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3186
33aeb49e 3187 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3188 if (err < 0)
79568b94 3189 return err;
79568b94
BJ		 3190 }
3191
f7eae37f
RV		 3192 if (!is_ab8505(ab8500)) {
3193 /* register external regulators (before Vaux1, 2 and 3) */
3194 err = ab8500_ext_regulator_init(pdev);
3195 if (err)
3196 return err;
3197 }
d1a82001 3198
c789ca20 3199 /* register all regulators */
33aeb49e 3200 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3201 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3202 i, NULL);
a7ac1d9e 3203 if (err < 0)
c789ca20 3204 return err;
c789ca20
SI		 3205 }
3206
3207 return 0;
3208}
3209
8dc995f5 3210static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3211{
d1a82001 3212 int i, err;
8e6a8d7d 3213 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3214
33aeb49e 3215 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3216 struct ab8500_regulator_info *info = NULL;
33aeb49e 3217 info = &abx500_regulator.info[i];
09aefa12
BJ		 3218
3219 dev_vdbg(rdev_get_dev(info->regulator),
3220 "%s-remove\n", info->desc.name);
3221
c789ca20
SI		 3222 regulator_unregister(info->regulator);
3223 }
3224
f7eae37f
RV		 3225 if (!is_ab8505(ab8500)) {
3226 /* remove external regulators (after Vaux1, 2 and 3) */
3227 err = ab8500_ext_regulator_exit(pdev);
3228 if (err)
3229 return err;
3230 }
d1a82001 3231
da0b0c47
LJ		 3232 /* remove regulator debug */
3233 err = ab8500_regulator_debug_exit(pdev);
3234 if (err)
3235 return err;
3236
c789ca20
SI		 3237 return 0;
3238}
3239
3240static struct platform_driver ab8500_regulator_driver = {
3241 .probe = ab8500_regulator_probe,
5eb9f2b9 3242 .remove = ab8500_regulator_remove,
c789ca20
SI		 3243 .driver = {
3244 .name = "ab8500-regulator",
3245 .owner = THIS_MODULE,
3246 },
3247};
3248
3249static int __init ab8500_regulator_init(void)
3250{
3251 int ret;
3252
3253 ret = platform_driver_register(&ab8500_regulator_driver);
3254 if (ret != 0)
3255 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3256
3257 return ret;
3258}
3259subsys_initcall(ab8500_regulator_init);
3260
3261static void __exit ab8500_regulator_exit(void)
3262{
3263 platform_driver_unregister(&ab8500_regulator_driver);
3264}
3265module_exit(ab8500_regulator_exit);
3266
3267MODULE_LICENSE("GPL v2");
3268MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3269MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3270MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3271MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3272MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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