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regulator: ab8500: Update voltage handling for fixed voltage regulators
[deliverable/linux.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20
SI		 31
32/**
33 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 34 * @dev: device pointer
c789ca20 35 * @desc: regulator description
c789ca20 36 * @regulator_dev: regulator device
bd28a157 37 * @is_enabled: status of regulator (on/off)
7ce4669c 38 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 39 * @update_bank: bank to control on/off
c789ca20 40 * @update_reg: register to control on/off
bd28a157
EV		 41 * @update_mask: mask to enable/disable and set mode of regulator
42 * @update_val: bits holding the regulator current mode
43 * @update_val_idle: bits to enable the regulator in idle (low power) mode
44 * @update_val_normal: bits to enable the regulator in normal (high power) mode
47c16975 45 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 46 * @voltage_reg: register to control regulator voltage
47 * @voltage_mask: mask to control regulator voltage
a0a7014c 48 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 49 */
50struct ab8500_regulator_info {
51 struct device *dev;
52 struct regulator_desc desc;
c789ca20 53 struct regulator_dev *regulator;
bd28a157 54 bool is_enabled;
7ce4669c 55 int load_lp_uA;
47c16975
MW		 56 u8 update_bank;
57 u8 update_reg;
e1159e6d 58 u8 update_mask;
bd28a157
EV		 59 u8 update_val;
60 u8 update_val_idle;
61 u8 update_val_normal;
47c16975
MW		 62 u8 voltage_bank;
63 u8 voltage_reg;
64 u8 voltage_mask;
a0a7014c 65 u8 voltage_shift;
c789ca20
SI		 66};
67
68/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 69static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 70 1100000,
71 1200000,
72 1300000,
73 1400000,
74 1500000,
75 1800000,
76 1850000,
77 1900000,
78 2500000,
79 2650000,
80 2700000,
81 2750000,
82 2800000,
83 2900000,
84 3000000,
85 3300000,
86};
87
ec1cc4d9 88static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 89 1200000,
90 1500000,
91 1800000,
92 2100000,
93 2500000,
94 2750000,
95 2790000,
96 2910000,
97};
98
547f384f
LJ		 99static const int ldo_vaux56_voltages[] = {
100 1800000,
101 1050000,
102 1100000,
103 1200000,
104 1500000,
105 2200000,
106 2500000,
107 2790000,
108};
109
ae0a9a3e
LJ		 110static const int ldo_vaux3_ab8540_voltages[] = {
111 1200000,
112 1500000,
113 1800000,
114 2100000,
115 2500000,
116 2750000,
117 2790000,
118 2910000,
119 3050000,
120};
121
ec1cc4d9 122static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 123 1200000,
124 1225000,
125 1250000,
126 1275000,
127 1300000,
128 1325000,
129 1350000,
130};
131
ae0a9a3e
LJ		 132static const int ldo_sdio_voltages[] = {
133 1160000,
134 1050000,
135 1100000,
136 1500000,
137 1800000,
138 2200000,
139 2910000,
140 3050000,
141};
142
b080c78a
LJ		 143static const unsigned int fixed_1200000_voltage[] = {
144 1200000,
145};
146
147static const unsigned int fixed_1800000_voltage[] = {
148 1800000,
149};
150
151static const unsigned int fixed_2000000_voltage[] = {
152 2000000,
153};
154
155static const unsigned int fixed_2050000_voltage[] = {
156 2050000,
157};
158
159static const unsigned int fixed_3300000_voltage[] = {
160 3300000,
161};
162
c789ca20
SI		 163static int ab8500_regulator_enable(struct regulator_dev *rdev)
164{
fc24b426 165 int ret;
c789ca20
SI		 166 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
167
fc24b426
BJ		 168 if (info == NULL) {
169 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 170 return -EINVAL;
fc24b426 171 }
c789ca20 172
47c16975 173 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 174 info->update_bank, info->update_reg,
bd28a157 175 info->update_mask, info->update_val);
f71bf528 176 if (ret < 0) {
c789ca20
SI		 177 dev_err(rdev_get_dev(rdev),
178 "couldn't set enable bits for regulator\n");
f71bf528
AL		 179 return ret;
180 }
09aefa12 181
bd28a157
EV		 182 info->is_enabled = true;
183
09aefa12
BJ		 184 dev_vdbg(rdev_get_dev(rdev),
185 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
186 info->desc.name, info->update_bank, info->update_reg,
bd28a157 187 info->update_mask, info->update_val);
09aefa12 188
c789ca20
SI		 189 return ret;
190}
191
192static int ab8500_regulator_disable(struct regulator_dev *rdev)
193{
fc24b426 194 int ret;
c789ca20
SI		 195 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
196
fc24b426
BJ		 197 if (info == NULL) {
198 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 199 return -EINVAL;
fc24b426 200 }
c789ca20 201
47c16975 202 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 203 info->update_bank, info->update_reg,
204 info->update_mask, 0x0);
f71bf528 205 if (ret < 0) {
c789ca20
SI		 206 dev_err(rdev_get_dev(rdev),
207 "couldn't set disable bits for regulator\n");
f71bf528
AL		 208 return ret;
209 }
09aefa12 210
bd28a157
EV		 211 info->is_enabled = false;
212
09aefa12
BJ		 213 dev_vdbg(rdev_get_dev(rdev),
214 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
215 info->desc.name, info->update_bank, info->update_reg,
216 info->update_mask, 0x0);
217
c789ca20
SI		 218 return ret;
219}
220
7ce4669c
BJ		 221static unsigned int ab8500_regulator_get_optimum_mode(
222 struct regulator_dev *rdev, int input_uV,
223 int output_uV, int load_uA)
224{
225 unsigned int mode;
226
227 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
228
229 if (info == NULL) {
230 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
231 return -EINVAL;
232 }
233
234 if (load_uA <= info->load_lp_uA)
235 mode = REGULATOR_MODE_IDLE;
236 else
237 mode = REGULATOR_MODE_NORMAL;
238
239 return mode;
240}
241
bd28a157
EV		 242static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
243 unsigned int mode)
244{
742a7325
AL		 245 int ret;
246 u8 update_val;
bd28a157
EV		 247 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
248
249 if (info == NULL) {
250 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
251 return -EINVAL;
252 }
253
254 switch (mode) {
255 case REGULATOR_MODE_NORMAL:
742a7325 256 update_val = info->update_val_normal;
bd28a157
EV		 257 break;
258 case REGULATOR_MODE_IDLE:
742a7325 259 update_val = info->update_val_idle;
bd28a157
EV		 260 break;
261 default:
262 return -EINVAL;
263 }
264
742a7325
AL		 265 /* ab8500 regulators share mode and enable in the same register bits.
266 off = 0b00
267 low power mode= 0b11
268 full powermode = 0b01
269 (HW control mode = 0b10)
270 Thus we don't write to the register when regulator is disabled.
271 */
bd28a157
EV		 272 if (info->is_enabled) {
273 ret = abx500_mask_and_set_register_interruptible(info->dev,
274 info->update_bank, info->update_reg,
742a7325
AL		 275 info->update_mask, update_val);
276 if (ret < 0) {
bd28a157
EV		 277 dev_err(rdev_get_dev(rdev),
278 "couldn't set regulator mode\n");
742a7325
AL		 279 return ret;
280 }
7ce4669c
BJ		 281
282 dev_vdbg(rdev_get_dev(rdev),
283 "%s-set_mode (bank, reg, mask, value): "
284 "0x%x, 0x%x, 0x%x, 0x%x\n",
285 info->desc.name, info->update_bank, info->update_reg,
742a7325 286 info->update_mask, update_val);
bd28a157
EV		 287 }
288
742a7325
AL		 289 info->update_val = update_val;
290
291 return 0;
bd28a157
EV		 292}
293
294static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
295{
296 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
297 int ret;
298
299 if (info == NULL) {
300 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
301 return -EINVAL;
302 }
303
304 if (info->update_val == info->update_val_normal)
305 ret = REGULATOR_MODE_NORMAL;
306 else if (info->update_val == info->update_val_idle)
307 ret = REGULATOR_MODE_IDLE;
308 else
309 ret = -EINVAL;
310
311 return ret;
312}
313
c789ca20
SI		 314static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
315{
fc24b426 316 int ret;
c789ca20 317 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 318 u8 regval;
c789ca20 319
fc24b426
BJ		 320 if (info == NULL) {
321 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 322 return -EINVAL;
fc24b426 323 }
c789ca20 324
47c16975 325 ret = abx500_get_register_interruptible(info->dev,
09aefa12 326 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 327 if (ret < 0) {
328 dev_err(rdev_get_dev(rdev),
329 "couldn't read 0x%x register\n", info->update_reg);
330 return ret;
331 }
332
09aefa12
BJ		 333 dev_vdbg(rdev_get_dev(rdev),
334 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
335 " 0x%x\n",
336 info->desc.name, info->update_bank, info->update_reg,
337 info->update_mask, regval);
338
339 if (regval & info->update_mask)
bd28a157 340 info->is_enabled = true;
c789ca20 341 else
bd28a157
EV		 342 info->is_enabled = false;
343
344 return info->is_enabled;
c789ca20
SI		 345}
346
3bf6e90e 347static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 348{
09aefa12 349 int ret, val;
c789ca20 350 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 351 u8 regval;
c789ca20 352
fc24b426
BJ		 353 if (info == NULL) {
354 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 355 return -EINVAL;
fc24b426 356 }
c789ca20 357
09aefa12
BJ		 358 ret = abx500_get_register_interruptible(info->dev,
359 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 360 if (ret < 0) {
361 dev_err(rdev_get_dev(rdev),
362 "couldn't read voltage reg for regulator\n");
363 return ret;
364 }
365
09aefa12 366 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 367 "%s-get_voltage (bank, reg, mask, shift, value): "
368 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
369 info->desc.name, info->voltage_bank,
370 info->voltage_reg, info->voltage_mask,
371 info->voltage_shift, regval);
09aefa12 372
09aefa12 373 val = regval & info->voltage_mask;
a0a7014c 374 return val >> info->voltage_shift;
c789ca20
SI		 375}
376
ae713d39
AL		 377static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
378 unsigned selector)
c789ca20 379{
fc24b426 380 int ret;
c789ca20 381 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 382 u8 regval;
c789ca20 383
fc24b426
BJ		 384 if (info == NULL) {
385 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 386 return -EINVAL;
fc24b426 387 }
c789ca20 388
c789ca20 389 /* set the registers for the request */
a0a7014c 390 regval = (u8)selector << info->voltage_shift;
47c16975 391 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 392 info->voltage_bank, info->voltage_reg,
393 info->voltage_mask, regval);
c789ca20
SI		 394 if (ret < 0)
395 dev_err(rdev_get_dev(rdev),
396 "couldn't set voltage reg for regulator\n");
397
09aefa12
BJ		 398 dev_vdbg(rdev_get_dev(rdev),
399 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
400 " 0x%x\n",
401 info->desc.name, info->voltage_bank, info->voltage_reg,
402 info->voltage_mask, regval);
403
c789ca20
SI		 404 return ret;
405}
406
7ce4669c
BJ		 407static struct regulator_ops ab8500_regulator_volt_mode_ops = {
408 .enable = ab8500_regulator_enable,
409 .disable = ab8500_regulator_disable,
410 .is_enabled = ab8500_regulator_is_enabled,
411 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
412 .set_mode = ab8500_regulator_set_mode,
413 .get_mode = ab8500_regulator_get_mode,
414 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
415 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
416 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 417};
418
7ce4669c
BJ		 419static struct regulator_ops ab8500_regulator_mode_ops = {
420 .enable = ab8500_regulator_enable,
421 .disable = ab8500_regulator_disable,
422 .is_enabled = ab8500_regulator_is_enabled,
423 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
424 .set_mode = ab8500_regulator_set_mode,
425 .get_mode = ab8500_regulator_get_mode,
5689e830 426 .list_voltage = regulator_list_voltage_linear,
7ce4669c
BJ		 427};
428
429static struct regulator_ops ab8500_regulator_ops = {
430 .enable = ab8500_regulator_enable,
431 .disable = ab8500_regulator_disable,
432 .is_enabled = ab8500_regulator_is_enabled,
5689e830 433 .list_voltage = regulator_list_voltage_linear,
c789ca20
SI		 434};
435
8e6a8d7d 436/* AB8500 regulator information */
6909b452
BJ		 437static struct ab8500_regulator_info
438 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 439 /*
e1159e6d
BJ		 440 * Variable Voltage Regulators
441 * name, min mV, max mV,
442 * update bank, reg, mask, enable val
ec1cc4d9 443 * volt bank, reg, mask
c789ca20 444 */
6909b452
BJ		 445 [AB8500_LDO_AUX1] = {
446 .desc = {
447 .name = "LDO-AUX1",
7ce4669c 448 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 449 .type = REGULATOR_VOLTAGE,
450 .id = AB8500_LDO_AUX1,
451 .owner = THIS_MODULE,
452 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 453 .volt_table = ldo_vauxn_voltages,
530158b6 454 .enable_time = 200,
6909b452 455 },
7ce4669c 456 .load_lp_uA = 5000,
6909b452
BJ		 457 .update_bank = 0x04,
458 .update_reg = 0x09,
459 .update_mask = 0x03,
bd28a157
EV		 460 .update_val = 0x01,
461 .update_val_idle = 0x03,
462 .update_val_normal = 0x01,
6909b452
BJ		 463 .voltage_bank = 0x04,
464 .voltage_reg = 0x1f,
465 .voltage_mask = 0x0f,
6909b452
BJ		 466 },
467 [AB8500_LDO_AUX2] = {
468 .desc = {
469 .name = "LDO-AUX2",
7ce4669c 470 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 471 .type = REGULATOR_VOLTAGE,
472 .id = AB8500_LDO_AUX2,
473 .owner = THIS_MODULE,
474 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 475 .volt_table = ldo_vauxn_voltages,
530158b6 476 .enable_time = 200,
6909b452 477 },
7ce4669c 478 .load_lp_uA = 5000,
6909b452
BJ		 479 .update_bank = 0x04,
480 .update_reg = 0x09,
481 .update_mask = 0x0c,
bd28a157
EV		 482 .update_val = 0x04,
483 .update_val_idle = 0x0c,
484 .update_val_normal = 0x04,
6909b452
BJ		 485 .voltage_bank = 0x04,
486 .voltage_reg = 0x20,
487 .voltage_mask = 0x0f,
6909b452
BJ		 488 },
489 [AB8500_LDO_AUX3] = {
490 .desc = {
491 .name = "LDO-AUX3",
7ce4669c 492 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 493 .type = REGULATOR_VOLTAGE,
494 .id = AB8500_LDO_AUX3,
495 .owner = THIS_MODULE,
496 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 497 .volt_table = ldo_vaux3_voltages,
530158b6 498 .enable_time = 450,
6909b452 499 },
7ce4669c 500 .load_lp_uA = 5000,
6909b452
BJ		 501 .update_bank = 0x04,
502 .update_reg = 0x0a,
503 .update_mask = 0x03,
bd28a157
EV		 504 .update_val = 0x01,
505 .update_val_idle = 0x03,
506 .update_val_normal = 0x01,
6909b452
BJ		 507 .voltage_bank = 0x04,
508 .voltage_reg = 0x21,
509 .voltage_mask = 0x07,
6909b452
BJ		 510 },
511 [AB8500_LDO_INTCORE] = {
512 .desc = {
513 .name = "LDO-INTCORE",
7ce4669c 514 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 515 .type = REGULATOR_VOLTAGE,
516 .id = AB8500_LDO_INTCORE,
517 .owner = THIS_MODULE,
518 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 519 .volt_table = ldo_vintcore_voltages,
530158b6 520 .enable_time = 750,
6909b452 521 },
7ce4669c 522 .load_lp_uA = 5000,
6909b452
BJ		 523 .update_bank = 0x03,
524 .update_reg = 0x80,
525 .update_mask = 0x44,
cc40dc29 526 .update_val = 0x44,
bd28a157
EV		 527 .update_val_idle = 0x44,
528 .update_val_normal = 0x04,
6909b452
BJ		 529 .voltage_bank = 0x03,
530 .voltage_reg = 0x80,
531 .voltage_mask = 0x38,
a0a7014c 532 .voltage_shift = 3,
6909b452 533 },
c789ca20
SI		 534
535 /*
e1159e6d
BJ		 536 * Fixed Voltage Regulators
537 * name, fixed mV,
538 * update bank, reg, mask, enable val
c789ca20 539 */
6909b452
BJ		 540 [AB8500_LDO_TVOUT] = {
541 .desc = {
542 .name = "LDO-TVOUT",
7ce4669c 543 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 544 .type = REGULATOR_VOLTAGE,
545 .id = AB8500_LDO_TVOUT,
546 .owner = THIS_MODULE,
547 .n_voltages = 1,
b080c78a 548 .volt_table = fixed_2000000_voltage,
ed3c138e 549 .enable_time = 500,
6909b452 550 },
7ce4669c 551 .load_lp_uA = 1000,
6909b452
BJ		 552 .update_bank = 0x03,
553 .update_reg = 0x80,
554 .update_mask = 0x82,
bd28a157 555 .update_val = 0x02,
7ce4669c
BJ		 556 .update_val_idle = 0x82,
557 .update_val_normal = 0x02,
6909b452
BJ		 558 },
559 [AB8500_LDO_AUDIO] = {
560 .desc = {
561 .name = "LDO-AUDIO",
7ce4669c 562 .ops = &ab8500_regulator_ops,
6909b452
BJ		 563 .type = REGULATOR_VOLTAGE,
564 .id = AB8500_LDO_AUDIO,
565 .owner = THIS_MODULE,
566 .n_voltages = 1,
530158b6 567 .enable_time = 140,
b080c78a 568 .volt_table = fixed_2000000_voltage,
6909b452 569 },
6909b452
BJ		 570 .update_bank = 0x03,
571 .update_reg = 0x83,
572 .update_mask = 0x02,
bd28a157 573 .update_val = 0x02,
6909b452
BJ		 574 },
575 [AB8500_LDO_ANAMIC1] = {
576 .desc = {
577 .name = "LDO-ANAMIC1",
7ce4669c 578 .ops = &ab8500_regulator_ops,
6909b452
BJ		 579 .type = REGULATOR_VOLTAGE,
580 .id = AB8500_LDO_ANAMIC1,
581 .owner = THIS_MODULE,
582 .n_voltages = 1,
530158b6 583 .enable_time = 500,
b080c78a 584 .volt_table = fixed_2050000_voltage,
6909b452 585 },
6909b452
BJ		 586 .update_bank = 0x03,
587 .update_reg = 0x83,
588 .update_mask = 0x08,
bd28a157 589 .update_val = 0x08,
6909b452
BJ		 590 },
591 [AB8500_LDO_ANAMIC2] = {
592 .desc = {
593 .name = "LDO-ANAMIC2",
7ce4669c 594 .ops = &ab8500_regulator_ops,
6909b452
BJ		 595 .type = REGULATOR_VOLTAGE,
596 .id = AB8500_LDO_ANAMIC2,
597 .owner = THIS_MODULE,
598 .n_voltages = 1,
530158b6 599 .enable_time = 500,
b080c78a 600 .volt_table = fixed_2050000_voltage,
6909b452 601 },
6909b452
BJ		 602 .update_bank = 0x03,
603 .update_reg = 0x83,
604 .update_mask = 0x10,
bd28a157 605 .update_val = 0x10,
6909b452
BJ		 606 },
607 [AB8500_LDO_DMIC] = {
608 .desc = {
609 .name = "LDO-DMIC",
7ce4669c 610 .ops = &ab8500_regulator_ops,
6909b452
BJ		 611 .type = REGULATOR_VOLTAGE,
612 .id = AB8500_LDO_DMIC,
613 .owner = THIS_MODULE,
614 .n_voltages = 1,
530158b6 615 .enable_time = 420,
b080c78a 616 .volt_table = fixed_1800000_voltage,
6909b452 617 },
6909b452
BJ		 618 .update_bank = 0x03,
619 .update_reg = 0x83,
620 .update_mask = 0x04,
bd28a157 621 .update_val = 0x04,
6909b452 622 },
7ce4669c
BJ		 623
624 /*
625 * Regulators with fixed voltage and normal/idle modes
626 */
6909b452
BJ		 627 [AB8500_LDO_ANA] = {
628 .desc = {
629 .name = "LDO-ANA",
7ce4669c 630 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 631 .type = REGULATOR_VOLTAGE,
632 .id = AB8500_LDO_ANA,
633 .owner = THIS_MODULE,
634 .n_voltages = 1,
530158b6 635 .enable_time = 140,
b080c78a 636 .volt_table = fixed_1200000_voltage,
6909b452 637 },
7ce4669c 638 .load_lp_uA = 1000,
6909b452
BJ		 639 .update_bank = 0x04,
640 .update_reg = 0x06,
641 .update_mask = 0x0c,
bd28a157 642 .update_val = 0x04,
7ce4669c
BJ		 643 .update_val_idle = 0x0c,
644 .update_val_normal = 0x04,
6909b452 645 },
8e6a8d7d 646};
6909b452 647
547f384f
LJ		 648/* AB8505 regulator information */
649static struct ab8500_regulator_info
650 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
651 /*
652 * Variable Voltage Regulators
653 * name, min mV, max mV,
654 * update bank, reg, mask, enable val
655 * volt bank, reg, mask, table, table length
656 */
657 [AB8505_LDO_AUX1] = {
658 .desc = {
659 .name = "LDO-AUX1",
660 .ops = &ab8500_regulator_volt_mode_ops,
661 .type = REGULATOR_VOLTAGE,
662 .id = AB8500_LDO_AUX1,
663 .owner = THIS_MODULE,
664 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
665 },
547f384f
LJ		 666 .load_lp_uA = 5000,
667 .update_bank = 0x04,
668 .update_reg = 0x09,
669 .update_mask = 0x03,
670 .update_val = 0x01,
671 .update_val_idle = 0x03,
672 .update_val_normal = 0x01,
673 .voltage_bank = 0x04,
674 .voltage_reg = 0x1f,
675 .voltage_mask = 0x0f,
676 .voltages = ldo_vauxn_voltages,
677 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
678 },
679 [AB8505_LDO_AUX2] = {
680 .desc = {
681 .name = "LDO-AUX2",
682 .ops = &ab8500_regulator_volt_mode_ops,
683 .type = REGULATOR_VOLTAGE,
684 .id = AB8500_LDO_AUX2,
685 .owner = THIS_MODULE,
686 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
687 },
547f384f
LJ		 688 .load_lp_uA = 5000,
689 .update_bank = 0x04,
690 .update_reg = 0x09,
691 .update_mask = 0x0c,
692 .update_val = 0x04,
693 .update_val_idle = 0x0c,
694 .update_val_normal = 0x04,
695 .voltage_bank = 0x04,
696 .voltage_reg = 0x20,
697 .voltage_mask = 0x0f,
698 .voltages = ldo_vauxn_voltages,
699 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
700 },
701 [AB8505_LDO_AUX3] = {
702 .desc = {
703 .name = "LDO-AUX3",
704 .ops = &ab8500_regulator_volt_mode_ops,
705 .type = REGULATOR_VOLTAGE,
706 .id = AB8500_LDO_AUX3,
707 .owner = THIS_MODULE,
708 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
709 },
547f384f
LJ		 710 .load_lp_uA = 5000,
711 .update_bank = 0x04,
712 .update_reg = 0x0a,
713 .update_mask = 0x03,
714 .update_val = 0x01,
715 .update_val_idle = 0x03,
716 .update_val_normal = 0x01,
717 .voltage_bank = 0x04,
718 .voltage_reg = 0x21,
719 .voltage_mask = 0x07,
720 .voltages = ldo_vaux3_voltages,
721 .voltages_len = ARRAY_SIZE(ldo_vaux3_voltages),
722 },
723 [AB8505_LDO_AUX4] = {
724 .desc = {
725 .name = "LDO-AUX4",
726 .ops = &ab8500_regulator_volt_mode_ops,
727 .type = REGULATOR_VOLTAGE,
728 .id = AB9540_LDO_AUX4,
729 .owner = THIS_MODULE,
730 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
731 },
547f384f
LJ		 732 .load_lp_uA = 5000,
733 /* values for Vaux4Regu register */
734 .update_bank = 0x04,
735 .update_reg = 0x2e,
736 .update_mask = 0x03,
737 .update_val = 0x01,
738 .update_val_idle = 0x03,
739 .update_val_normal = 0x01,
740 /* values for Vaux4SEL register */
741 .voltage_bank = 0x04,
742 .voltage_reg = 0x2f,
743 .voltage_mask = 0x0f,
744 .voltages = ldo_vauxn_voltages,
745 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
746 },
747 [AB8505_LDO_AUX5] = {
748 .desc = {
749 .name = "LDO-AUX5",
750 .ops = &ab8500_regulator_volt_mode_ops,
751 .type = REGULATOR_VOLTAGE,
752 .id = AB8505_LDO_AUX5,
753 .owner = THIS_MODULE,
754 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
755 },
547f384f
LJ		 756 .load_lp_uA = 2000,
757 /* values for CtrlVaux5 register */
758 .update_bank = 0x01,
759 .update_reg = 0x55,
ae0a9a3e
LJ		 760 .update_mask = 0x18,
761 .update_val = 0x10,
762 .update_val_idle = 0x18,
763 .update_val_normal = 0x10,
547f384f
LJ		 764 .voltage_bank = 0x01,
765 .voltage_reg = 0x55,
766 .voltage_mask = 0x07,
767 .voltages = ldo_vaux56_voltages,
768 .voltages_len = ARRAY_SIZE(ldo_vaux56_voltages),
769 },
770 [AB8505_LDO_AUX6] = {
771 .desc = {
772 .name = "LDO-AUX6",
773 .ops = &ab8500_regulator_volt_mode_ops,
774 .type = REGULATOR_VOLTAGE,
775 .id = AB8505_LDO_AUX6,
776 .owner = THIS_MODULE,
777 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
778 },
547f384f
LJ		 779 .load_lp_uA = 2000,
780 /* values for CtrlVaux6 register */
781 .update_bank = 0x01,
782 .update_reg = 0x56,
ae0a9a3e
LJ		 783 .update_mask = 0x18,
784 .update_val = 0x10,
785 .update_val_idle = 0x18,
786 .update_val_normal = 0x10,
547f384f
LJ		 787 .voltage_bank = 0x01,
788 .voltage_reg = 0x56,
789 .voltage_mask = 0x07,
790 .voltages = ldo_vaux56_voltages,
791 .voltages_len = ARRAY_SIZE(ldo_vaux56_voltages),
792 },
793 [AB8505_LDO_INTCORE] = {
794 .desc = {
795 .name = "LDO-INTCORE",
796 .ops = &ab8500_regulator_volt_mode_ops,
797 .type = REGULATOR_VOLTAGE,
798 .id = AB8500_LDO_INTCORE,
799 .owner = THIS_MODULE,
800 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
801 },
547f384f
LJ		 802 .load_lp_uA = 5000,
803 .update_bank = 0x03,
804 .update_reg = 0x80,
805 .update_mask = 0x44,
806 .update_val = 0x04,
807 .update_val_idle = 0x44,
808 .update_val_normal = 0x04,
809 .voltage_bank = 0x03,
810 .voltage_reg = 0x80,
811 .voltage_mask = 0x38,
812 .voltages = ldo_vintcore_voltages,
813 .voltages_len = ARRAY_SIZE(ldo_vintcore_voltages),
814 .voltage_shift = 3,
815 },
816
817 /*
818 * Fixed Voltage Regulators
819 * name, fixed mV,
820 * update bank, reg, mask, enable val
821 */
822 [AB8505_LDO_ADC] = {
823 .desc = {
824 .name = "LDO-ADC",
825 .ops = &ab8500_regulator_mode_ops,
826 .type = REGULATOR_VOLTAGE,
827 .id = AB8505_LDO_ADC,
828 .owner = THIS_MODULE,
829 .n_voltages = 1,
b080c78a 830 .volt_table = fixed_2000000_voltage,
547f384f
LJ		 831 },
832 .delay = 10000,
547f384f
LJ		 833 .load_lp_uA = 1000,
834 .update_bank = 0x03,
835 .update_reg = 0x80,
836 .update_mask = 0x82,
837 .update_val = 0x02,
838 .update_val_idle = 0x82,
839 .update_val_normal = 0x02,
840 },
841 [AB8505_LDO_USB] = {
842 .desc = {
843 .name = "LDO-USB",
844 .ops = &ab8500_regulator_mode_ops,
845 .type = REGULATOR_VOLTAGE,
846 .id = AB9540_LDO_USB,
847 .owner = THIS_MODULE,
848 .n_voltages = 1,
b080c78a 849 .volt_table = fixed_3300000_voltage,
547f384f 850 },
547f384f
LJ		 851 .update_bank = 0x03,
852 .update_reg = 0x82,
853 .update_mask = 0x03,
854 .update_val = 0x01,
855 .update_val_idle = 0x03,
856 .update_val_normal = 0x01,
857 },
858 [AB8505_LDO_AUDIO] = {
859 .desc = {
860 .name = "LDO-AUDIO",
861 .ops = &ab8500_regulator_ops,
862 .type = REGULATOR_VOLTAGE,
863 .id = AB8500_LDO_AUDIO,
864 .owner = THIS_MODULE,
865 .n_voltages = 1,
b080c78a 866 .volt_table = fixed_2000000_voltage,
547f384f 867 },
547f384f
LJ		 868 .update_bank = 0x03,
869 .update_reg = 0x83,
870 .update_mask = 0x02,
871 .update_val = 0x02,
872 },
873 [AB8505_LDO_ANAMIC1] = {
874 .desc = {
875 .name = "LDO-ANAMIC1",
876 .ops = &ab8500_regulator_ops,
877 .type = REGULATOR_VOLTAGE,
878 .id = AB8500_LDO_ANAMIC1,
879 .owner = THIS_MODULE,
880 .n_voltages = 1,
b080c78a 881 .volt_table = fixed_2050000_voltage,
547f384f 882 },
547f384f
LJ		 883 .update_bank = 0x03,
884 .update_reg = 0x83,
885 .update_mask = 0x08,
886 .update_val = 0x08,
887 },
888 [AB8505_LDO_ANAMIC2] = {
889 .desc = {
890 .name = "LDO-ANAMIC2",
891 .ops = &ab8500_regulator_ops,
892 .type = REGULATOR_VOLTAGE,
893 .id = AB8500_LDO_ANAMIC2,
894 .owner = THIS_MODULE,
895 .n_voltages = 1,
b080c78a 896 .volt_table = fixed_2050000_voltage,
547f384f 897 },
547f384f
LJ		 898 .update_bank = 0x03,
899 .update_reg = 0x83,
900 .update_mask = 0x10,
901 .update_val = 0x10,
902 },
903 [AB8505_LDO_AUX8] = {
904 .desc = {
905 .name = "LDO-AUX8",
906 .ops = &ab8500_regulator_ops,
907 .type = REGULATOR_VOLTAGE,
908 .id = AB8505_LDO_AUX8,
909 .owner = THIS_MODULE,
910 .n_voltages = 1,
b080c78a 911 .volt_table = fixed_1800000_voltage,
547f384f 912 },
547f384f
LJ		 913 .update_bank = 0x03,
914 .update_reg = 0x83,
915 .update_mask = 0x04,
916 .update_val = 0x04,
917 },
918 /*
919 * Regulators with fixed voltage and normal/idle modes
920 */
921 [AB8505_LDO_ANA] = {
922 .desc = {
923 .name = "LDO-ANA",
924 .ops = &ab8500_regulator_mode_ops,
925 .type = REGULATOR_VOLTAGE,
926 .id = AB8500_LDO_ANA,
927 .owner = THIS_MODULE,
928 .n_voltages = 1,
b080c78a 929 .volt_table = fixed_1200000_voltage,
547f384f 930 },
547f384f
LJ		 931 .load_lp_uA = 1000,
932 .update_bank = 0x04,
933 .update_reg = 0x06,
934 .update_mask = 0x0c,
935 .update_val = 0x04,
936 .update_val_idle = 0x0c,
937 .update_val_normal = 0x04,
938 },
939};
940
8e6a8d7d
LJ		 941/* AB9540 regulator information */
942static struct ab8500_regulator_info
943 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
944 /*
945 * Variable Voltage Regulators
946 * name, min mV, max mV,
947 * update bank, reg, mask, enable val
948 * volt bank, reg, mask, table, table length
949 */
950 [AB9540_LDO_AUX1] = {
951 .desc = {
952 .name = "LDO-AUX1",
953 .ops = &ab8500_regulator_volt_mode_ops,
954 .type = REGULATOR_VOLTAGE,
955 .id = AB8500_LDO_AUX1,
956 .owner = THIS_MODULE,
957 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
958 },
8e6a8d7d
LJ		 959 .load_lp_uA = 5000,
960 .update_bank = 0x04,
961 .update_reg = 0x09,
962 .update_mask = 0x03,
963 .update_val = 0x01,
964 .update_val_idle = 0x03,
965 .update_val_normal = 0x01,
966 .voltage_bank = 0x04,
967 .voltage_reg = 0x1f,
968 .voltage_mask = 0x0f,
969 .voltages = ldo_vauxn_voltages,
970 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
971 },
972 [AB9540_LDO_AUX2] = {
973 .desc = {
974 .name = "LDO-AUX2",
975 .ops = &ab8500_regulator_volt_mode_ops,
976 .type = REGULATOR_VOLTAGE,
977 .id = AB8500_LDO_AUX2,
978 .owner = THIS_MODULE,
979 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
980 },
8e6a8d7d
LJ		 981 .load_lp_uA = 5000,
982 .update_bank = 0x04,
983 .update_reg = 0x09,
984 .update_mask = 0x0c,
985 .update_val = 0x04,
986 .update_val_idle = 0x0c,
987 .update_val_normal = 0x04,
988 .voltage_bank = 0x04,
989 .voltage_reg = 0x20,
990 .voltage_mask = 0x0f,
991 .voltages = ldo_vauxn_voltages,
992 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
993 },
994 [AB9540_LDO_AUX3] = {
995 .desc = {
996 .name = "LDO-AUX3",
997 .ops = &ab8500_regulator_volt_mode_ops,
998 .type = REGULATOR_VOLTAGE,
999 .id = AB8500_LDO_AUX3,
1000 .owner = THIS_MODULE,
1001 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
1002 },
8e6a8d7d
LJ		 1003 .load_lp_uA = 5000,
1004 .update_bank = 0x04,
1005 .update_reg = 0x0a,
1006 .update_mask = 0x03,
1007 .update_val = 0x01,
1008 .update_val_idle = 0x03,
1009 .update_val_normal = 0x01,
1010 .voltage_bank = 0x04,
1011 .voltage_reg = 0x21,
1012 .voltage_mask = 0x07,
1013 .voltages = ldo_vaux3_voltages,
1014 .voltages_len = ARRAY_SIZE(ldo_vaux3_voltages),
1015 },
1016 [AB9540_LDO_AUX4] = {
1017 .desc = {
1018 .name = "LDO-AUX4",
1019 .ops = &ab8500_regulator_volt_mode_ops,
1020 .type = REGULATOR_VOLTAGE,
1021 .id = AB9540_LDO_AUX4,
1022 .owner = THIS_MODULE,
1023 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1024 },
8e6a8d7d
LJ		 1025 .load_lp_uA = 5000,
1026 /* values for Vaux4Regu register */
1027 .update_bank = 0x04,
1028 .update_reg = 0x2e,
1029 .update_mask = 0x03,
1030 .update_val = 0x01,
1031 .update_val_idle = 0x03,
1032 .update_val_normal = 0x01,
1033 /* values for Vaux4SEL register */
1034 .voltage_bank = 0x04,
1035 .voltage_reg = 0x2f,
1036 .voltage_mask = 0x0f,
1037 .voltages = ldo_vauxn_voltages,
1038 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
1039 },
1040 [AB9540_LDO_INTCORE] = {
1041 .desc = {
1042 .name = "LDO-INTCORE",
1043 .ops = &ab8500_regulator_volt_mode_ops,
1044 .type = REGULATOR_VOLTAGE,
1045 .id = AB8500_LDO_INTCORE,
1046 .owner = THIS_MODULE,
1047 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1048 },
8e6a8d7d
LJ		 1049 .load_lp_uA = 5000,
1050 .update_bank = 0x03,
1051 .update_reg = 0x80,
1052 .update_mask = 0x44,
1053 .update_val = 0x44,
1054 .update_val_idle = 0x44,
1055 .update_val_normal = 0x04,
1056 .voltage_bank = 0x03,
1057 .voltage_reg = 0x80,
1058 .voltage_mask = 0x38,
1059 .voltages = ldo_vintcore_voltages,
1060 .voltages_len = ARRAY_SIZE(ldo_vintcore_voltages),
1061 .voltage_shift = 3,
1062 },
6909b452 1063
8e6a8d7d
LJ		 1064 /*
1065 * Fixed Voltage Regulators
1066 * name, fixed mV,
1067 * update bank, reg, mask, enable val
1068 */
1069 [AB9540_LDO_TVOUT] = {
1070 .desc = {
1071 .name = "LDO-TVOUT",
1072 .ops = &ab8500_regulator_mode_ops,
1073 .type = REGULATOR_VOLTAGE,
1074 .id = AB8500_LDO_TVOUT,
1075 .owner = THIS_MODULE,
1076 .n_voltages = 1,
b080c78a 1077 .volt_table = fixed_2000000_voltage,
8e6a8d7d
LJ		 1078 },
1079 .delay = 10000,
8e6a8d7d
LJ		 1080 .load_lp_uA = 1000,
1081 .update_bank = 0x03,
1082 .update_reg = 0x80,
1083 .update_mask = 0x82,
1084 .update_val = 0x02,
1085 .update_val_idle = 0x82,
1086 .update_val_normal = 0x02,
1087 },
1088 [AB9540_LDO_USB] = {
1089 .desc = {
1090 .name = "LDO-USB",
1091 .ops = &ab8500_regulator_ops,
1092 .type = REGULATOR_VOLTAGE,
1093 .id = AB9540_LDO_USB,
1094 .owner = THIS_MODULE,
1095 .n_voltages = 1,
b080c78a 1096 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1097 },
8e6a8d7d
LJ		 1098 .update_bank = 0x03,
1099 .update_reg = 0x82,
1100 .update_mask = 0x03,
1101 .update_val = 0x01,
1102 .update_val_idle = 0x03,
1103 .update_val_normal = 0x01,
1104 },
1105 [AB9540_LDO_AUDIO] = {
1106 .desc = {
1107 .name = "LDO-AUDIO",
1108 .ops = &ab8500_regulator_ops,
1109 .type = REGULATOR_VOLTAGE,
1110 .id = AB8500_LDO_AUDIO,
1111 .owner = THIS_MODULE,
1112 .n_voltages = 1,
b080c78a 1113 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1114 },
8e6a8d7d
LJ		 1115 .update_bank = 0x03,
1116 .update_reg = 0x83,
1117 .update_mask = 0x02,
1118 .update_val = 0x02,
1119 },
1120 [AB9540_LDO_ANAMIC1] = {
1121 .desc = {
1122 .name = "LDO-ANAMIC1",
1123 .ops = &ab8500_regulator_ops,
1124 .type = REGULATOR_VOLTAGE,
1125 .id = AB8500_LDO_ANAMIC1,
1126 .owner = THIS_MODULE,
1127 .n_voltages = 1,
b080c78a 1128 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1129 },
8e6a8d7d
LJ		 1130 .update_bank = 0x03,
1131 .update_reg = 0x83,
1132 .update_mask = 0x08,
1133 .update_val = 0x08,
1134 },
1135 [AB9540_LDO_ANAMIC2] = {
1136 .desc = {
1137 .name = "LDO-ANAMIC2",
1138 .ops = &ab8500_regulator_ops,
1139 .type = REGULATOR_VOLTAGE,
1140 .id = AB8500_LDO_ANAMIC2,
1141 .owner = THIS_MODULE,
1142 .n_voltages = 1,
b080c78a 1143 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1144 },
8e6a8d7d
LJ		 1145 .update_bank = 0x03,
1146 .update_reg = 0x83,
1147 .update_mask = 0x10,
1148 .update_val = 0x10,
1149 },
1150 [AB9540_LDO_DMIC] = {
1151 .desc = {
1152 .name = "LDO-DMIC",
1153 .ops = &ab8500_regulator_ops,
1154 .type = REGULATOR_VOLTAGE,
1155 .id = AB8500_LDO_DMIC,
1156 .owner = THIS_MODULE,
1157 .n_voltages = 1,
b080c78a 1158 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1159 },
8e6a8d7d
LJ		 1160 .update_bank = 0x03,
1161 .update_reg = 0x83,
1162 .update_mask = 0x04,
1163 .update_val = 0x04,
1164 },
1165
1166 /*
1167 * Regulators with fixed voltage and normal/idle modes
1168 */
1169 [AB9540_LDO_ANA] = {
1170 .desc = {
1171 .name = "LDO-ANA",
1172 .ops = &ab8500_regulator_mode_ops,
1173 .type = REGULATOR_VOLTAGE,
1174 .id = AB8500_LDO_ANA,
1175 .owner = THIS_MODULE,
1176 .n_voltages = 1,
b080c78a 1177 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1178 },
8e6a8d7d
LJ		 1179 .load_lp_uA = 1000,
1180 .update_bank = 0x04,
1181 .update_reg = 0x06,
1182 .update_mask = 0x0c,
1183 .update_val = 0x08,
1184 .update_val_idle = 0x0c,
1185 .update_val_normal = 0x08,
1186 },
c789ca20
SI		 1187};
1188
ae0a9a3e
LJ		 1189/* AB8540 regulator information */
1190static struct ab8500_regulator_info
1191 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1192 /*
1193 * Variable Voltage Regulators
1194 * name, min mV, max mV,
1195 * update bank, reg, mask, enable val
1196 * volt bank, reg, mask, table, table length
1197 */
1198 [AB8540_LDO_AUX1] = {
1199 .desc = {
1200 .name = "LDO-AUX1",
1201 .ops = &ab8500_regulator_volt_mode_ops,
1202 .type = REGULATOR_VOLTAGE,
1203 .id = AB8500_LDO_AUX1,
1204 .owner = THIS_MODULE,
1205 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1206 },
1207 .load_lp_uA = 5000,
1208 .update_bank = 0x04,
1209 .update_reg = 0x09,
1210 .update_mask = 0x03,
1211 .update_val = 0x01,
1212 .update_val_idle = 0x03,
1213 .update_val_normal = 0x01,
1214 .voltage_bank = 0x04,
1215 .voltage_reg = 0x1f,
1216 .voltage_mask = 0x0f,
1217 .voltages = ldo_vauxn_voltages,
1218 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
1219 },
1220 [AB8540_LDO_AUX2] = {
1221 .desc = {
1222 .name = "LDO-AUX2",
1223 .ops = &ab8500_regulator_volt_mode_ops,
1224 .type = REGULATOR_VOLTAGE,
1225 .id = AB8500_LDO_AUX2,
1226 .owner = THIS_MODULE,
1227 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1228 },
1229 .load_lp_uA = 5000,
1230 .update_bank = 0x04,
1231 .update_reg = 0x09,
1232 .update_mask = 0x0c,
1233 .update_val = 0x04,
1234 .update_val_idle = 0x0c,
1235 .update_val_normal = 0x04,
1236 .voltage_bank = 0x04,
1237 .voltage_reg = 0x20,
1238 .voltage_mask = 0x0f,
1239 .voltages = ldo_vauxn_voltages,
1240 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
1241 },
1242 [AB8540_LDO_AUX3] = {
1243 .desc = {
1244 .name = "LDO-AUX3",
1245 .ops = &ab8500_regulator_volt_mode_ops,
1246 .type = REGULATOR_VOLTAGE,
1247 .id = AB8500_LDO_AUX3,
1248 .owner = THIS_MODULE,
1249 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1250 },
1251 .load_lp_uA = 5000,
1252 .update_bank = 0x04,
1253 .update_reg = 0x0a,
1254 .update_mask = 0x03,
1255 .update_val = 0x01,
1256 .update_val_idle = 0x03,
1257 .update_val_normal = 0x01,
1258 .voltage_bank = 0x04,
1259 .voltage_reg = 0x21,
1260 .voltage_mask = 0x07,
1261 .voltages = ldo_vaux3_ab8540_voltages,
1262 .voltages_len = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1263 },
1264 [AB8540_LDO_AUX4] = {
1265 .desc = {
1266 .name = "LDO-AUX4",
1267 .ops = &ab8500_regulator_volt_mode_ops,
1268 .type = REGULATOR_VOLTAGE,
1269 .id = AB9540_LDO_AUX4,
1270 .owner = THIS_MODULE,
1271 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1272 },
1273 .load_lp_uA = 5000,
1274 /* values for Vaux4Regu register */
1275 .update_bank = 0x04,
1276 .update_reg = 0x2e,
1277 .update_mask = 0x03,
1278 .update_val = 0x01,
1279 .update_val_idle = 0x03,
1280 .update_val_normal = 0x01,
1281 /* values for Vaux4SEL register */
1282 .voltage_bank = 0x04,
1283 .voltage_reg = 0x2f,
1284 .voltage_mask = 0x0f,
1285 .voltages = ldo_vauxn_voltages,
1286 .voltages_len = ARRAY_SIZE(ldo_vauxn_voltages),
1287 },
1288 [AB8540_LDO_INTCORE] = {
1289 .desc = {
1290 .name = "LDO-INTCORE",
1291 .ops = &ab8500_regulator_volt_mode_ops,
1292 .type = REGULATOR_VOLTAGE,
1293 .id = AB8500_LDO_INTCORE,
1294 .owner = THIS_MODULE,
1295 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1296 },
1297 .load_lp_uA = 5000,
1298 .update_bank = 0x03,
1299 .update_reg = 0x80,
1300 .update_mask = 0x44,
1301 .update_val = 0x44,
1302 .update_val_idle = 0x44,
1303 .update_val_normal = 0x04,
1304 .voltage_bank = 0x03,
1305 .voltage_reg = 0x80,
1306 .voltage_mask = 0x38,
1307 .voltages = ldo_vintcore_voltages,
1308 .voltages_len = ARRAY_SIZE(ldo_vintcore_voltages),
1309 .voltage_shift = 3,
1310 },
1311
1312 /*
1313 * Fixed Voltage Regulators
1314 * name, fixed mV,
1315 * update bank, reg, mask, enable val
1316 */
1317 [AB8540_LDO_TVOUT] = {
1318 .desc = {
1319 .name = "LDO-TVOUT",
1320 .ops = &ab8500_regulator_mode_ops,
1321 .type = REGULATOR_VOLTAGE,
1322 .id = AB8500_LDO_TVOUT,
1323 .owner = THIS_MODULE,
1324 .n_voltages = 1,
1325 },
1326 .delay = 10000,
1327 .load_lp_uA = 1000,
1328 .update_bank = 0x03,
1329 .update_reg = 0x80,
1330 .update_mask = 0x82,
1331 .update_val = 0x02,
1332 .update_val_idle = 0x82,
1333 .update_val_normal = 0x02,
1334 },
1335 [AB8540_LDO_AUDIO] = {
1336 .desc = {
1337 .name = "LDO-AUDIO",
1338 .ops = &ab8500_regulator_ops,
1339 .type = REGULATOR_VOLTAGE,
1340 .id = AB8500_LDO_AUDIO,
1341 .owner = THIS_MODULE,
1342 .n_voltages = 1,
b080c78a 1343 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1344 },
1345 .update_bank = 0x03,
1346 .update_reg = 0x83,
1347 .update_mask = 0x02,
1348 .update_val = 0x02,
1349 },
1350 [AB8540_LDO_ANAMIC1] = {
1351 .desc = {
1352 .name = "LDO-ANAMIC1",
1353 .ops = &ab8500_regulator_ops,
1354 .type = REGULATOR_VOLTAGE,
1355 .id = AB8500_LDO_ANAMIC1,
1356 .owner = THIS_MODULE,
1357 .n_voltages = 1,
b080c78a 1358 .volt_table = fixed_2050000_voltage,
ae0a9a3e
LJ		 1359 },
1360 .update_bank = 0x03,
1361 .update_reg = 0x83,
1362 .update_mask = 0x08,
1363 .update_val = 0x08,
1364 },
1365 [AB8540_LDO_ANAMIC2] = {
1366 .desc = {
1367 .name = "LDO-ANAMIC2",
1368 .ops = &ab8500_regulator_ops,
1369 .type = REGULATOR_VOLTAGE,
1370 .id = AB8500_LDO_ANAMIC2,
1371 .owner = THIS_MODULE,
1372 .n_voltages = 1,
b080c78a 1373 .volt_table = fixed_2050000_voltage,
ae0a9a3e
LJ		 1374 },
1375 .update_bank = 0x03,
1376 .update_reg = 0x83,
1377 .update_mask = 0x10,
1378 .update_val = 0x10,
1379 },
1380 [AB8540_LDO_DMIC] = {
1381 .desc = {
1382 .name = "LDO-DMIC",
1383 .ops = &ab8500_regulator_ops,
1384 .type = REGULATOR_VOLTAGE,
1385 .id = AB8500_LDO_DMIC,
1386 .owner = THIS_MODULE,
1387 .n_voltages = 1,
1388 },
1389 .update_bank = 0x03,
1390 .update_reg = 0x83,
1391 .update_mask = 0x04,
1392 .update_val = 0x04,
1393 },
1394
1395 /*
1396 * Regulators with fixed voltage and normal/idle modes
1397 */
1398 [AB8540_LDO_ANA] = {
1399 .desc = {
1400 .name = "LDO-ANA",
1401 .ops = &ab8500_regulator_mode_ops,
1402 .type = REGULATOR_VOLTAGE,
1403 .id = AB8500_LDO_ANA,
1404 .owner = THIS_MODULE,
1405 .n_voltages = 1,
b080c78a 1406 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1407 },
1408 .load_lp_uA = 1000,
1409 .update_bank = 0x04,
1410 .update_reg = 0x06,
1411 .update_mask = 0x0c,
1412 .update_val = 0x04,
1413 .update_val_idle = 0x0c,
1414 .update_val_normal = 0x04,
1415 },
1416 [AB8540_LDO_SDIO] = {
1417 .desc = {
1418 .name = "LDO-SDIO",
1419 .ops = &ab8500_regulator_volt_mode_ops,
1420 .type = REGULATOR_VOLTAGE,
1421 .id = AB8540_LDO_SDIO,
1422 .owner = THIS_MODULE,
1423 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1424 },
ae0a9a3e
LJ		 1425 .load_lp_uA = 5000,
1426 .update_bank = 0x03,
1427 .update_reg = 0x88,
1428 .update_mask = 0x30,
1429 .update_val = 0x10,
1430 .update_val_idle = 0x30,
1431 .update_val_normal = 0x10,
1432 .voltage_bank = 0x03,
1433 .voltage_reg = 0x88,
1434 .voltage_mask = 0x07,
1435 .voltages = ldo_sdio_voltages,
1436 .voltages_len = ARRAY_SIZE(ldo_sdio_voltages),
1437 },
1438};
1439
79568b94
BJ		 1440struct ab8500_reg_init {
1441 u8 bank;
1442 u8 addr;
1443 u8 mask;
1444};
1445
1446#define REG_INIT(_id, _bank, _addr, _mask) \
1447 [_id] = { \
1448 .bank = _bank, \
1449 .addr = _addr, \
1450 .mask = _mask, \
1451 }
1452
8e6a8d7d 1453/* AB8500 register init */
79568b94
BJ		 1454static struct ab8500_reg_init ab8500_reg_init[] = {
1455 /*
33bc8f46 1456 * 0x30, VanaRequestCtrl
79568b94
BJ		 1457 * 0xc0, VextSupply1RequestCtrl
1458 */
43a5911b 1459 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1460 /*
1461 * 0x03, VextSupply2RequestCtrl
1462 * 0x0c, VextSupply3RequestCtrl
1463 * 0x30, Vaux1RequestCtrl
1464 * 0xc0, Vaux2RequestCtrl
1465 */
1466 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1467 /*
1468 * 0x03, Vaux3RequestCtrl
1469 * 0x04, SwHPReq
1470 */
1471 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1472 /*
1473 * 0x08, VanaSysClkReq1HPValid
1474 * 0x20, Vaux1SysClkReq1HPValid
1475 * 0x40, Vaux2SysClkReq1HPValid
1476 * 0x80, Vaux3SysClkReq1HPValid
1477 */
43a5911b 1478 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1479 /*
1480 * 0x10, VextSupply1SysClkReq1HPValid
1481 * 0x20, VextSupply2SysClkReq1HPValid
1482 * 0x40, VextSupply3SysClkReq1HPValid
1483 */
43a5911b 1484 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1485 /*
1486 * 0x08, VanaHwHPReq1Valid
1487 * 0x20, Vaux1HwHPReq1Valid
1488 * 0x40, Vaux2HwHPReq1Valid
1489 * 0x80, Vaux3HwHPReq1Valid
1490 */
43a5911b 1491 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1492 /*
1493 * 0x01, VextSupply1HwHPReq1Valid
1494 * 0x02, VextSupply2HwHPReq1Valid
1495 * 0x04, VextSupply3HwHPReq1Valid
1496 */
43a5911b 1497 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1498 /*
1499 * 0x08, VanaHwHPReq2Valid
1500 * 0x20, Vaux1HwHPReq2Valid
1501 * 0x40, Vaux2HwHPReq2Valid
1502 * 0x80, Vaux3HwHPReq2Valid
1503 */
43a5911b 1504 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1505 /*
1506 * 0x01, VextSupply1HwHPReq2Valid
1507 * 0x02, VextSupply2HwHPReq2Valid
1508 * 0x04, VextSupply3HwHPReq2Valid
1509 */
43a5911b 1510 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1511 /*
1512 * 0x20, VanaSwHPReqValid
1513 * 0x80, Vaux1SwHPReqValid
1514 */
43a5911b 1515 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1516 /*
1517 * 0x01, Vaux2SwHPReqValid
1518 * 0x02, Vaux3SwHPReqValid
1519 * 0x04, VextSupply1SwHPReqValid
1520 * 0x08, VextSupply2SwHPReqValid
1521 * 0x10, VextSupply3SwHPReqValid
1522 */
43a5911b 1523 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1524 /*
1525 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1526 * 0x04, SysClkReq3Valid1
1527 * 0x08, SysClkReq4Valid1
1528 * 0x10, SysClkReq5Valid1
1529 * 0x20, SysClkReq6Valid1
1530 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1531 * 0x80, SysClkReq8Valid1
1532 */
1533 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1534 /*
1535 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1536 * 0x04, SysClkReq3Valid2
1537 * 0x08, SysClkReq4Valid2
1538 * 0x10, SysClkReq5Valid2
1539 * 0x20, SysClkReq6Valid2
1540 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1541 * 0x80, SysClkReq8Valid2
1542 */
1543 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1544 /*
1545 * 0x02, VTVoutEna
1546 * 0x04, Vintcore12Ena
1547 * 0x38, Vintcore12Sel
1548 * 0x40, Vintcore12LP
1549 * 0x80, VTVoutLP
1550 */
1551 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1552 /*
1553 * 0x02, VaudioEna
1554 * 0x04, VdmicEna
1555 * 0x08, Vamic1Ena
1556 * 0x10, Vamic2Ena
1557 */
1558 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1559 /*
1560 * 0x01, Vamic1_dzout
1561 * 0x02, Vamic2_dzout
1562 */
1563 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1564 /*
43a5911b 1565 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1566 * 0x0c, VanaRegu
79568b94
BJ		 1567 */
1568 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1569 /*
1570 * 0x01, VrefDDREna
1571 * 0x02, VrefDDRSleepMode
1572 */
1573 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1574 /*
1575 * 0x03, VextSupply1Regu
1576 * 0x0c, VextSupply2Regu
1577 * 0x30, VextSupply3Regu
1578 * 0x40, ExtSupply2Bypass
1579 * 0x80, ExtSupply3Bypass
1580 */
1581 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1582 /*
1583 * 0x03, Vaux1Regu
1584 * 0x0c, Vaux2Regu
1585 */
1586 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1587 /*
1588 * 0x03, Vaux3Regu
1589 */
43a5911b 1590 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1591 /*
1592 * 0x0f, Vaux1Sel
1593 */
1594 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1595 /*
1596 * 0x0f, Vaux2Sel
1597 */
1598 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1599 /*
1600 * 0x07, Vaux3Sel
1601 */
43a5911b 1602 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1603 /*
1604 * 0x01, VextSupply12LP
1605 */
1606 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1607 /*
1608 * 0x04, Vaux1Disch
1609 * 0x08, Vaux2Disch
1610 * 0x10, Vaux3Disch
1611 * 0x20, Vintcore12Disch
1612 * 0x40, VTVoutDisch
1613 * 0x80, VaudioDisch
1614 */
43a5911b 1615 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1616 /*
1617 * 0x02, VanaDisch
1618 * 0x04, VdmicPullDownEna
1619 * 0x10, VdmicDisch
1620 */
43a5911b 1621 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1622};
1623
547f384f
LJ		 1624/* AB8505 register init */
1625static struct ab8500_reg_init ab8505_reg_init[] = {
1626 /*
1627 * 0x03, VarmRequestCtrl
1628 * 0x0c, VsmpsCRequestCtrl
1629 * 0x30, VsmpsARequestCtrl
1630 * 0xc0, VsmpsBRequestCtrl
1631 */
1632 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1633 /*
1634 * 0x03, VsafeRequestCtrl
1635 * 0x0c, VpllRequestCtrl
1636 * 0x30, VanaRequestCtrl
1637 */
1638 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1639 /*
1640 * 0x30, Vaux1RequestCtrl
1641 * 0xc0, Vaux2RequestCtrl
1642 */
1643 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1644 /*
1645 * 0x03, Vaux3RequestCtrl
1646 * 0x04, SwHPReq
1647 */
1648 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1649 /*
1650 * 0x01, VsmpsASysClkReq1HPValid
1651 * 0x02, VsmpsBSysClkReq1HPValid
1652 * 0x04, VsafeSysClkReq1HPValid
1653 * 0x08, VanaSysClkReq1HPValid
1654 * 0x10, VpllSysClkReq1HPValid
1655 * 0x20, Vaux1SysClkReq1HPValid
1656 * 0x40, Vaux2SysClkReq1HPValid
1657 * 0x80, Vaux3SysClkReq1HPValid
1658 */
1659 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1660 /*
1661 * 0x01, VsmpsCSysClkReq1HPValid
1662 * 0x02, VarmSysClkReq1HPValid
1663 * 0x04, VbbSysClkReq1HPValid
1664 * 0x08, VsmpsMSysClkReq1HPValid
1665 */
1666 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
1667 /*
1668 * 0x01, VsmpsAHwHPReq1Valid
1669 * 0x02, VsmpsBHwHPReq1Valid
1670 * 0x04, VsafeHwHPReq1Valid
1671 * 0x08, VanaHwHPReq1Valid
1672 * 0x10, VpllHwHPReq1Valid
1673 * 0x20, Vaux1HwHPReq1Valid
1674 * 0x40, Vaux2HwHPReq1Valid
1675 * 0x80, Vaux3HwHPReq1Valid
1676 */
1677 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1678 /*
1679 * 0x08, VsmpsMHwHPReq1Valid
1680 */
1681 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
1682 /*
1683 * 0x01, VsmpsAHwHPReq2Valid
1684 * 0x02, VsmpsBHwHPReq2Valid
1685 * 0x04, VsafeHwHPReq2Valid
1686 * 0x08, VanaHwHPReq2Valid
1687 * 0x10, VpllHwHPReq2Valid
1688 * 0x20, Vaux1HwHPReq2Valid
1689 * 0x40, Vaux2HwHPReq2Valid
1690 * 0x80, Vaux3HwHPReq2Valid
1691 */
1692 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1693 /*
1694 * 0x08, VsmpsMHwHPReq2Valid
1695 */
1696 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
1697 /*
1698 * 0x01, VsmpsCSwHPReqValid
1699 * 0x02, VarmSwHPReqValid
1700 * 0x04, VsmpsASwHPReqValid
1701 * 0x08, VsmpsBSwHPReqValid
1702 * 0x10, VsafeSwHPReqValid
1703 * 0x20, VanaSwHPReqValid
1704 * 0x40, VpllSwHPReqValid
1705 * 0x80, Vaux1SwHPReqValid
1706 */
1707 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1708 /*
1709 * 0x01, Vaux2SwHPReqValid
1710 * 0x02, Vaux3SwHPReqValid
1711 * 0x20, VsmpsMSwHPReqValid
1712 */
1713 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
1714 /*
1715 * 0x02, SysClkReq2Valid1
1716 * 0x04, SysClkReq3Valid1
1717 * 0x08, SysClkReq4Valid1
1718 */
1719 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
1720 /*
1721 * 0x02, SysClkReq2Valid2
1722 * 0x04, SysClkReq3Valid2
1723 * 0x08, SysClkReq4Valid2
1724 */
1725 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
1726 /*
1727 * 0x01, Vaux4SwHPReqValid
1728 * 0x02, Vaux4HwHPReq2Valid
1729 * 0x04, Vaux4HwHPReq1Valid
1730 * 0x08, Vaux4SysClkReq1HPValid
1731 */
1732 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
1733 /*
1734 * 0x02, VadcEna
1735 * 0x04, VintCore12Ena
1736 * 0x38, VintCore12Sel
1737 * 0x40, VintCore12LP
1738 * 0x80, VadcLP
1739 */
1740 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
1741 /*
1742 * 0x02, VaudioEna
1743 * 0x04, VdmicEna
1744 * 0x08, Vamic1Ena
1745 * 0x10, Vamic2Ena
1746 */
1747 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1748 /*
1749 * 0x01, Vamic1_dzout
1750 * 0x02, Vamic2_dzout
1751 */
1752 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1753 /*
1754 * 0x03, VsmpsARegu
1755 * 0x0c, VsmpsASelCtrl
1756 * 0x10, VsmpsAAutoMode
1757 * 0x20, VsmpsAPWMMode
1758 */
1759 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
1760 /*
1761 * 0x03, VsmpsBRegu
1762 * 0x0c, VsmpsBSelCtrl
1763 * 0x10, VsmpsBAutoMode
1764 * 0x20, VsmpsBPWMMode
1765 */
1766 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
1767 /*
1768 * 0x03, VsafeRegu
1769 * 0x0c, VsafeSelCtrl
1770 * 0x10, VsafeAutoMode
1771 * 0x20, VsafePWMMode
1772 */
1773 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
1774 /*
1775 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1776 * 0x0c, VanaRegu
1777 */
1778 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1779 /*
1780 * 0x03, VextSupply1Regu
1781 * 0x0c, VextSupply2Regu
1782 * 0x30, VextSupply3Regu
1783 * 0x40, ExtSupply2Bypass
1784 * 0x80, ExtSupply3Bypass
1785 */
1786 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1787 /*
1788 * 0x03, Vaux1Regu
1789 * 0x0c, Vaux2Regu
1790 */
1791 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
1792 /*
1793 * 0x0f, Vaux3Regu
1794 */
1795 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
1796 /*
1797 * 0x3f, VsmpsASel1
1798 */
1799 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
1800 /*
1801 * 0x3f, VsmpsASel2
1802 */
1803 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
1804 /*
1805 * 0x3f, VsmpsASel3
1806 */
1807 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
1808 /*
1809 * 0x3f, VsmpsBSel1
1810 */
1811 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
1812 /*
1813 * 0x3f, VsmpsBSel2
1814 */
1815 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
1816 /*
1817 * 0x3f, VsmpsBSel3
1818 */
1819 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
1820 /*
1821 * 0x7f, VsafeSel1
1822 */
1823 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
1824 /*
1825 * 0x3f, VsafeSel2
1826 */
1827 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
1828 /*
1829 * 0x3f, VsafeSel3
1830 */
1831 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
1832 /*
1833 * 0x0f, Vaux1Sel
1834 */
1835 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
1836 /*
1837 * 0x0f, Vaux2Sel
1838 */
1839 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
1840 /*
1841 * 0x07, Vaux3Sel
1842 * 0x30, VRF1Sel
1843 */
1844 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
1845 /*
1846 * 0x03, Vaux4RequestCtrl
1847 */
1848 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
1849 /*
1850 * 0x03, Vaux4Regu
1851 */
1852 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
1853 /*
1854 * 0x0f, Vaux4Sel
1855 */
1856 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
1857 /*
1858 * 0x04, Vaux1Disch
1859 * 0x08, Vaux2Disch
1860 * 0x10, Vaux3Disch
1861 * 0x20, Vintcore12Disch
1862 * 0x40, VTVoutDisch
1863 * 0x80, VaudioDisch
1864 */
1865 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1866 /*
1867 * 0x02, VanaDisch
1868 * 0x04, VdmicPullDownEna
1869 * 0x10, VdmicDisch
1870 */
1871 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1872 /*
1873 * 0x01, Vaux4Disch
1874 */
1875 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
1876 /*
1877 * 0x07, Vaux5Sel
1878 * 0x08, Vaux5LP
1879 * 0x10, Vaux5Ena
1880 * 0x20, Vaux5Disch
1881 * 0x40, Vaux5DisSfst
1882 * 0x80, Vaux5DisPulld
1883 */
1884 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
1885 /*
1886 * 0x07, Vaux6Sel
1887 * 0x08, Vaux6LP
1888 * 0x10, Vaux6Ena
1889 * 0x80, Vaux6DisPulld
1890 */
1891 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
1892};
1893
8e6a8d7d
LJ		 1894/* AB9540 register init */
1895static struct ab8500_reg_init ab9540_reg_init[] = {
1896 /*
1897 * 0x03, VarmRequestCtrl
1898 * 0x0c, VapeRequestCtrl
1899 * 0x30, Vsmps1RequestCtrl
1900 * 0xc0, Vsmps2RequestCtrl
1901 */
1902 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1903 /*
1904 * 0x03, Vsmps3RequestCtrl
1905 * 0x0c, VpllRequestCtrl
1906 * 0x30, VanaRequestCtrl
1907 * 0xc0, VextSupply1RequestCtrl
1908 */
1909 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
1910 /*
1911 * 0x03, VextSupply2RequestCtrl
1912 * 0x0c, VextSupply3RequestCtrl
1913 * 0x30, Vaux1RequestCtrl
1914 * 0xc0, Vaux2RequestCtrl
1915 */
1916 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1917 /*
1918 * 0x03, Vaux3RequestCtrl
1919 * 0x04, SwHPReq
1920 */
1921 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1922 /*
1923 * 0x01, Vsmps1SysClkReq1HPValid
1924 * 0x02, Vsmps2SysClkReq1HPValid
1925 * 0x04, Vsmps3SysClkReq1HPValid
1926 * 0x08, VanaSysClkReq1HPValid
1927 * 0x10, VpllSysClkReq1HPValid
1928 * 0x20, Vaux1SysClkReq1HPValid
1929 * 0x40, Vaux2SysClkReq1HPValid
1930 * 0x80, Vaux3SysClkReq1HPValid
1931 */
1932 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1933 /*
1934 * 0x01, VapeSysClkReq1HPValid
1935 * 0x02, VarmSysClkReq1HPValid
1936 * 0x04, VbbSysClkReq1HPValid
1937 * 0x08, VmodSysClkReq1HPValid
1938 * 0x10, VextSupply1SysClkReq1HPValid
1939 * 0x20, VextSupply2SysClkReq1HPValid
1940 * 0x40, VextSupply3SysClkReq1HPValid
1941 */
1942 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
1943 /*
1944 * 0x01, Vsmps1HwHPReq1Valid
1945 * 0x02, Vsmps2HwHPReq1Valid
1946 * 0x04, Vsmps3HwHPReq1Valid
1947 * 0x08, VanaHwHPReq1Valid
1948 * 0x10, VpllHwHPReq1Valid
1949 * 0x20, Vaux1HwHPReq1Valid
1950 * 0x40, Vaux2HwHPReq1Valid
1951 * 0x80, Vaux3HwHPReq1Valid
1952 */
1953 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1954 /*
1955 * 0x01, VextSupply1HwHPReq1Valid
1956 * 0x02, VextSupply2HwHPReq1Valid
1957 * 0x04, VextSupply3HwHPReq1Valid
1958 * 0x08, VmodHwHPReq1Valid
1959 */
1960 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
1961 /*
1962 * 0x01, Vsmps1HwHPReq2Valid
1963 * 0x02, Vsmps2HwHPReq2Valid
1964 * 0x03, Vsmps3HwHPReq2Valid
1965 * 0x08, VanaHwHPReq2Valid
1966 * 0x10, VpllHwHPReq2Valid
1967 * 0x20, Vaux1HwHPReq2Valid
1968 * 0x40, Vaux2HwHPReq2Valid
1969 * 0x80, Vaux3HwHPReq2Valid
1970 */
1971 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1972 /*
1973 * 0x01, VextSupply1HwHPReq2Valid
1974 * 0x02, VextSupply2HwHPReq2Valid
1975 * 0x04, VextSupply3HwHPReq2Valid
1976 * 0x08, VmodHwHPReq2Valid
1977 */
1978 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
1979 /*
1980 * 0x01, VapeSwHPReqValid
1981 * 0x02, VarmSwHPReqValid
1982 * 0x04, Vsmps1SwHPReqValid
1983 * 0x08, Vsmps2SwHPReqValid
1984 * 0x10, Vsmps3SwHPReqValid
1985 * 0x20, VanaSwHPReqValid
1986 * 0x40, VpllSwHPReqValid
1987 * 0x80, Vaux1SwHPReqValid
1988 */
1989 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1990 /*
1991 * 0x01, Vaux2SwHPReqValid
1992 * 0x02, Vaux3SwHPReqValid
1993 * 0x04, VextSupply1SwHPReqValid
1994 * 0x08, VextSupply2SwHPReqValid
1995 * 0x10, VextSupply3SwHPReqValid
1996 * 0x20, VmodSwHPReqValid
1997 */
1998 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
1999 /*
2000 * 0x02, SysClkReq2Valid1
2001 * ...
2002 * 0x80, SysClkReq8Valid1
2003 */
2004 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2005 /*
2006 * 0x02, SysClkReq2Valid2
2007 * ...
2008 * 0x80, SysClkReq8Valid2
2009 */
2010 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2011 /*
2012 * 0x01, Vaux4SwHPReqValid
2013 * 0x02, Vaux4HwHPReq2Valid
2014 * 0x04, Vaux4HwHPReq1Valid
2015 * 0x08, Vaux4SysClkReq1HPValid
2016 */
2017 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2018 /*
2019 * 0x02, VTVoutEna
2020 * 0x04, Vintcore12Ena
2021 * 0x38, Vintcore12Sel
2022 * 0x40, Vintcore12LP
2023 * 0x80, VTVoutLP
2024 */
2025 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2026 /*
2027 * 0x02, VaudioEna
2028 * 0x04, VdmicEna
2029 * 0x08, Vamic1Ena
2030 * 0x10, Vamic2Ena
2031 */
2032 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2033 /*
2034 * 0x01, Vamic1_dzout
2035 * 0x02, Vamic2_dzout
2036 */
2037 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2038 /*
2039 * 0x03, Vsmps1Regu
2040 * 0x0c, Vsmps1SelCtrl
2041 * 0x10, Vsmps1AutoMode
2042 * 0x20, Vsmps1PWMMode
2043 */
2044 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2045 /*
2046 * 0x03, Vsmps2Regu
2047 * 0x0c, Vsmps2SelCtrl
2048 * 0x10, Vsmps2AutoMode
2049 * 0x20, Vsmps2PWMMode
2050 */
2051 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2052 /*
2053 * 0x03, Vsmps3Regu
2054 * 0x0c, Vsmps3SelCtrl
2055 * NOTE! PRCMU register
2056 */
2057 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2058 /*
2059 * 0x03, VpllRegu
2060 * 0x0c, VanaRegu
2061 */
2062 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2063 /*
2064 * 0x03, VextSupply1Regu
2065 * 0x0c, VextSupply2Regu
2066 * 0x30, VextSupply3Regu
2067 * 0x40, ExtSupply2Bypass
2068 * 0x80, ExtSupply3Bypass
2069 */
2070 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2071 /*
2072 * 0x03, Vaux1Regu
2073 * 0x0c, Vaux2Regu
2074 */
2075 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2076 /*
2077 * 0x0c, Vrf1Regu
2078 * 0x03, Vaux3Regu
2079 */
2080 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2081 /*
2082 * 0x3f, Vsmps1Sel1
2083 */
2084 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2085 /*
2086 * 0x3f, Vsmps1Sel2
2087 */
2088 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2089 /*
2090 * 0x3f, Vsmps1Sel3
2091 */
2092 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2093 /*
2094 * 0x3f, Vsmps2Sel1
2095 */
2096 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2097 /*
2098 * 0x3f, Vsmps2Sel2
2099 */
2100 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2101 /*
2102 * 0x3f, Vsmps2Sel3
2103 */
2104 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2105 /*
2106 * 0x7f, Vsmps3Sel1
2107 * NOTE! PRCMU register
2108 */
2109 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2110 /*
2111 * 0x7f, Vsmps3Sel2
2112 * NOTE! PRCMU register
2113 */
2114 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2115 /*
2116 * 0x0f, Vaux1Sel
2117 */
2118 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2119 /*
2120 * 0x0f, Vaux2Sel
2121 */
2122 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2123 /*
2124 * 0x07, Vaux3Sel
2125 * 0x30, Vrf1Sel
2126 */
2127 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2128 /*
2129 * 0x01, VextSupply12LP
2130 */
2131 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2132 /*
2133 * 0x03, Vaux4RequestCtrl
2134 */
2135 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2136 /*
2137 * 0x03, Vaux4Regu
2138 */
2139 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2140 /*
2141 * 0x08, Vaux4Sel
2142 */
2143 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2144 /*
2145 * 0x01, VpllDisch
2146 * 0x02, Vrf1Disch
2147 * 0x04, Vaux1Disch
2148 * 0x08, Vaux2Disch
2149 * 0x10, Vaux3Disch
2150 * 0x20, Vintcore12Disch
2151 * 0x40, VTVoutDisch
2152 * 0x80, VaudioDisch
2153 */
2154 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2155 /*
2156 * 0x01, VsimDisch
2157 * 0x02, VanaDisch
2158 * 0x04, VdmicPullDownEna
2159 * 0x08, VpllPullDownEna
2160 * 0x10, VdmicDisch
2161 */
2162 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2163 /*
2164 * 0x01, Vaux4Disch
2165 */
2166 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2167};
2168
ae0a9a3e
LJ		 2169/* AB8540 register init */
2170static struct ab8500_reg_init ab8540_reg_init[] = {
2171 /*
2172 * 0x01, VSimSycClkReq1Valid
2173 * 0x02, VSimSycClkReq2Valid
2174 * 0x04, VSimSycClkReq3Valid
2175 * 0x08, VSimSycClkReq4Valid
2176 * 0x10, VSimSycClkReq5Valid
2177 * 0x20, VSimSycClkReq6Valid
2178 * 0x40, VSimSycClkReq7Valid
2179 * 0x80, VSimSycClkReq8Valid
2180 */
2181 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2182 /*
2183 * 0x03, VarmRequestCtrl
2184 * 0x0c, VapeRequestCtrl
2185 * 0x30, Vsmps1RequestCtrl
2186 * 0xc0, Vsmps2RequestCtrl
2187 */
2188 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2189 /*
2190 * 0x03, Vsmps3RequestCtrl
2191 * 0x0c, VpllRequestCtrl
2192 * 0x30, VanaRequestCtrl
2193 * 0xc0, VextSupply1RequestCtrl
2194 */
2195 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2196 /*
2197 * 0x03, VextSupply2RequestCtrl
2198 * 0x0c, VextSupply3RequestCtrl
2199 * 0x30, Vaux1RequestCtrl
2200 * 0xc0, Vaux2RequestCtrl
2201 */
2202 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2203 /*
2204 * 0x03, Vaux3RequestCtrl
2205 * 0x04, SwHPReq
2206 */
2207 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2208 /*
2209 * 0x01, Vsmps1SysClkReq1HPValid
2210 * 0x02, Vsmps2SysClkReq1HPValid
2211 * 0x04, Vsmps3SysClkReq1HPValid
2212 * 0x08, VanaSysClkReq1HPValid
2213 * 0x10, VpllSysClkReq1HPValid
2214 * 0x20, Vaux1SysClkReq1HPValid
2215 * 0x40, Vaux2SysClkReq1HPValid
2216 * 0x80, Vaux3SysClkReq1HPValid
2217 */
2218 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2219 /*
2220 * 0x01, VapeSysClkReq1HPValid
2221 * 0x02, VarmSysClkReq1HPValid
2222 * 0x04, VbbSysClkReq1HPValid
2223 * 0x10, VextSupply1SysClkReq1HPValid
2224 * 0x20, VextSupply2SysClkReq1HPValid
2225 * 0x40, VextSupply3SysClkReq1HPValid
2226 */
2227 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2228 /*
2229 * 0x01, Vsmps1HwHPReq1Valid
2230 * 0x02, Vsmps2HwHPReq1Valid
2231 * 0x04, Vsmps3HwHPReq1Valid
2232 * 0x08, VanaHwHPReq1Valid
2233 * 0x10, VpllHwHPReq1Valid
2234 * 0x20, Vaux1HwHPReq1Valid
2235 * 0x40, Vaux2HwHPReq1Valid
2236 * 0x80, Vaux3HwHPReq1Valid
2237 */
2238 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2239 /*
2240 * 0x01, VextSupply1HwHPReq1Valid
2241 * 0x02, VextSupply2HwHPReq1Valid
2242 * 0x04, VextSupply3HwHPReq1Valid
2243 */
2244 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2245 /*
2246 * 0x01, Vsmps1HwHPReq2Valid
2247 * 0x02, Vsmps2HwHPReq2Valid
2248 * 0x03, Vsmps3HwHPReq2Valid
2249 * 0x08, VanaHwHPReq2Valid
2250 * 0x10, VpllHwHPReq2Valid
2251 * 0x20, Vaux1HwHPReq2Valid
2252 * 0x40, Vaux2HwHPReq2Valid
2253 * 0x80, Vaux3HwHPReq2Valid
2254 */
2255 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2256 /*
2257 * 0x01, VextSupply1HwHPReq2Valid
2258 * 0x02, VextSupply2HwHPReq2Valid
2259 * 0x04, VextSupply3HwHPReq2Valid
2260 */
2261 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2262 /*
2263 * 0x01, VapeSwHPReqValid
2264 * 0x02, VarmSwHPReqValid
2265 * 0x04, Vsmps1SwHPReqValid
2266 * 0x08, Vsmps2SwHPReqValid
2267 * 0x10, Vsmps3SwHPReqValid
2268 * 0x20, VanaSwHPReqValid
2269 * 0x40, VpllSwHPReqValid
2270 * 0x80, Vaux1SwHPReqValid
2271 */
2272 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2273 /*
2274 * 0x01, Vaux2SwHPReqValid
2275 * 0x02, Vaux3SwHPReqValid
2276 * 0x04, VextSupply1SwHPReqValid
2277 * 0x08, VextSupply2SwHPReqValid
2278 * 0x10, VextSupply3SwHPReqValid
2279 */
2280 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2281 /*
2282 * 0x02, SysClkReq2Valid1
2283 * ...
2284 * 0x80, SysClkReq8Valid1
2285 */
2286 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2287 /*
2288 * 0x02, SysClkReq2Valid2
2289 * ...
2290 * 0x80, SysClkReq8Valid2
2291 */
2292 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2293 /*
2294 * 0x01, Vaux4SwHPReqValid
2295 * 0x02, Vaux4HwHPReq2Valid
2296 * 0x04, Vaux4HwHPReq1Valid
2297 * 0x08, Vaux4SysClkReq1HPValid
2298 */
2299 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2300 /*
2301 * 0x01, Vaux5SwHPReqValid
2302 * 0x02, Vaux5HwHPReq2Valid
2303 * 0x04, Vaux5HwHPReq1Valid
2304 * 0x08, Vaux5SysClkReq1HPValid
2305 */
2306 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2307 /*
2308 * 0x01, Vaux6SwHPReqValid
2309 * 0x02, Vaux6HwHPReq2Valid
2310 * 0x04, Vaux6HwHPReq1Valid
2311 * 0x08, Vaux6SysClkReq1HPValid
2312 */
2313 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2314 /*
2315 * 0x01, VclkbSwHPReqValid
2316 * 0x02, VclkbHwHPReq2Valid
2317 * 0x04, VclkbHwHPReq1Valid
2318 * 0x08, VclkbSysClkReq1HPValid
2319 */
2320 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2321 /*
2322 * 0x01, Vrf1SwHPReqValid
2323 * 0x02, Vrf1HwHPReq2Valid
2324 * 0x04, Vrf1HwHPReq1Valid
2325 * 0x08, Vrf1SysClkReq1HPValid
2326 */
2327 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2328 /*
2329 * 0x02, VTVoutEna
2330 * 0x04, Vintcore12Ena
2331 * 0x38, Vintcore12Sel
2332 * 0x40, Vintcore12LP
2333 * 0x80, VTVoutLP
2334 */
2335 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2336 /*
2337 * 0x02, VaudioEna
2338 * 0x04, VdmicEna
2339 * 0x08, Vamic1Ena
2340 * 0x10, Vamic2Ena
2341 * 0x20, Vamic12LP
2342 * 0xC0, VdmicSel
2343 */
2344 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2345 /*
2346 * 0x01, Vamic1_dzout
2347 * 0x02, Vamic2_dzout
2348 */
2349 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2350 /*
2351 * 0x07, VHSICSel
2352 * 0x08, VHSICOffState
2353 * 0x10, VHSIEna
2354 * 0x20, VHSICLP
2355 */
2356 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2357 /*
2358 * 0x07, VSDIOSel
2359 * 0x08, VSDIOOffState
2360 * 0x10, VSDIOEna
2361 * 0x20, VSDIOLP
2362 */
2363 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2364 /*
2365 * 0x03, Vsmps1Regu
2366 * 0x0c, Vsmps1SelCtrl
2367 * 0x10, Vsmps1AutoMode
2368 * 0x20, Vsmps1PWMMode
2369 */
2370 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2371 /*
2372 * 0x03, Vsmps2Regu
2373 * 0x0c, Vsmps2SelCtrl
2374 * 0x10, Vsmps2AutoMode
2375 * 0x20, Vsmps2PWMMode
2376 */
2377 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2378 /*
2379 * 0x03, Vsmps3Regu
2380 * 0x0c, Vsmps3SelCtrl
2381 * 0x10, Vsmps3AutoMode
2382 * 0x20, Vsmps3PWMMode
2383 * NOTE! PRCMU register
2384 */
2385 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2386 /*
2387 * 0x03, VpllRegu
2388 * 0x0c, VanaRegu
2389 */
2390 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2391 /*
2392 * 0x03, VextSupply1Regu
2393 * 0x0c, VextSupply2Regu
2394 * 0x30, VextSupply3Regu
2395 * 0x40, ExtSupply2Bypass
2396 * 0x80, ExtSupply3Bypass
2397 */
2398 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2399 /*
2400 * 0x03, Vaux1Regu
2401 * 0x0c, Vaux2Regu
2402 */
2403 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2404 /*
2405 * 0x0c, VRF1Regu
2406 * 0x03, Vaux3Regu
2407 */
2408 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2409 /*
2410 * 0x3f, Vsmps1Sel1
2411 */
2412 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2413 /*
2414 * 0x3f, Vsmps1Sel2
2415 */
2416 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2417 /*
2418 * 0x3f, Vsmps1Sel3
2419 */
2420 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2421 /*
2422 * 0x3f, Vsmps2Sel1
2423 */
2424 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2425 /*
2426 * 0x3f, Vsmps2Sel2
2427 */
2428 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2429 /*
2430 * 0x3f, Vsmps2Sel3
2431 */
2432 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2433 /*
2434 * 0x7f, Vsmps3Sel1
2435 * NOTE! PRCMU register
2436 */
2437 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2438 /*
2439 * 0x7f, Vsmps3Sel2
2440 * NOTE! PRCMU register
2441 */
2442 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2443 /*
2444 * 0x0f, Vaux1Sel
2445 */
2446 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2447 /*
2448 * 0x0f, Vaux2Sel
2449 */
2450 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2451 /*
2452 * 0x07, Vaux3Sel
2453 * 0x70, Vrf1Sel
2454 */
2455 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2456 /*
2457 * 0x01, VextSupply12LP
2458 */
2459 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2460 /*
2461 * 0x07, Vanasel
2462 * 0x30, Vpllsel
2463 */
2464 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2465 /*
2466 * 0x03, Vaux4RequestCtrl
2467 */
2468 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2469 /*
2470 * 0x03, Vaux4Regu
2471 */
2472 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2473 /*
2474 * 0x0f, Vaux4Sel
2475 */
2476 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2477 /*
2478 * 0x03, Vaux5RequestCtrl
2479 */
2480 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2481 /*
2482 * 0x03, Vaux5Regu
2483 */
2484 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2485 /*
2486 * 0x3f, Vaux5Sel
2487 */
2488 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2489 /*
2490 * 0x03, Vaux6RequestCtrl
2491 */
2492 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2493 /*
2494 * 0x03, Vaux6Regu
2495 */
2496 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2497 /*
2498 * 0x3f, Vaux6Sel
2499 */
2500 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2501 /*
2502 * 0x03, VCLKBRequestCtrl
2503 */
2504 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2505 /*
2506 * 0x03, VCLKBRegu
2507 */
2508 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2509 /*
2510 * 0x07, VCLKBSel
2511 */
2512 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2513 /*
2514 * 0x03, Vrf1RequestCtrl
2515 */
2516 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2517 /*
2518 * 0x01, VpllDisch
2519 * 0x02, Vrf1Disch
2520 * 0x04, Vaux1Disch
2521 * 0x08, Vaux2Disch
2522 * 0x10, Vaux3Disch
2523 * 0x20, Vintcore12Disch
2524 * 0x40, VTVoutDisch
2525 * 0x80, VaudioDisch
2526 */
2527 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2528 /*
2529 * 0x02, VanaDisch
2530 * 0x04, VdmicPullDownEna
2531 * 0x08, VpllPullDownEna
2532 * 0x10, VdmicDisch
2533 */
2534 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2535 /*
2536 * 0x01, Vaux4Disch
2537 */
2538 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2539 /*
2540 * 0x01, Vaux5Disch
2541 * 0x02, Vaux6Disch
2542 * 0x04, VCLKBDisch
2543 */
2544 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2545};
2546
3c1b8438 2547static int ab8500_regulator_init_registers(struct platform_device *pdev,
b54969ac 2548 struct ab8500_reg_init *reg_init,
3c1b8438 2549 int id, int mask, int value)
a7ac1d9e
LJ		 2550{
2551 int err;
2552
3c1b8438 2553 BUG_ON(value & ~mask);
b54969ac 2554 BUG_ON(mask & ~reg_init[id].mask);
a7ac1d9e 2555
3c1b8438 2556 /* initialize register */
a7ac1d9e
LJ		 2557 err = abx500_mask_and_set_register_interruptible(
2558 &pdev->dev,
b54969ac
LJ		 2559 reg_init[id].bank,
2560 reg_init[id].addr,
3c1b8438 2561 mask, value);
a7ac1d9e
LJ		 2562 if (err < 0) {
2563 dev_err(&pdev->dev,
2564 "Failed to initialize 0x%02x, 0x%02x.\n",
b54969ac
LJ		 2565 reg_init[id].bank,
2566 reg_init[id].addr);
a7ac1d9e
LJ		 2567 return err;
2568 }
a7ac1d9e 2569 dev_vdbg(&pdev->dev,
3c1b8438 2570 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
b54969ac
LJ		 2571 reg_init[id].bank,
2572 reg_init[id].addr,
3c1b8438 2573 mask, value);
a7ac1d9e
LJ		 2574
2575 return 0;
2576}
2577
a5023574 2578static int ab8500_regulator_register(struct platform_device *pdev,
b54969ac
LJ		 2579 struct regulator_init_data *init_data,
2580 struct ab8500_regulator_info *regulator_info,
2581 int id, struct device_node *np)
a7ac1d9e 2582{
8e6a8d7d 2583 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
a7ac1d9e
LJ		 2584 struct ab8500_regulator_info *info = NULL;
2585 struct regulator_config config = { };
2586 int err;
2587
2588 /* assign per-regulator data */
b54969ac 2589 info = &regulator_info[id];
a7ac1d9e
LJ		 2590 info->dev = &pdev->dev;
2591
2592 config.dev = &pdev->dev;
2593 config.init_data = init_data;
2594 config.driver_data = info;
2595 config.of_node = np;
2596
2597 /* fix for hardware before ab8500v2.0 */
8e6a8d7d 2598 if (is_ab8500_1p1_or_earlier(ab8500)) {
a7ac1d9e
LJ		 2599 if (info->desc.id == AB8500_LDO_AUX3) {
2600 info->desc.n_voltages =
2601 ARRAY_SIZE(ldo_vauxn_voltages);
ec1cc4d9 2602 info->desc.volt_table = ldo_vauxn_voltages;
a7ac1d9e
LJ		 2603 info->voltage_mask = 0xf;
2604 }
2605 }
2606
2607 /* register regulator with framework */
2608 info->regulator = regulator_register(&info->desc, &config);
2609 if (IS_ERR(info->regulator)) {
2610 err = PTR_ERR(info->regulator);
2611 dev_err(&pdev->dev, "failed to register regulator %s\n",
2612 info->desc.name);
2613 /* when we fail, un-register all earlier regulators */
2614 while (--id >= 0) {
b54969ac 2615 info = &regulator_info[id];
a7ac1d9e
LJ		 2616 regulator_unregister(info->regulator);
2617 }
2618 return err;
2619 }
2620
2621 return 0;
2622}
2623
b54969ac 2624static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2625 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2626 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2627 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2628 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2629 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2630 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2631 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2632 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2633 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2634 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2635};
2636
547f384f
LJ		 2637static struct of_regulator_match ab8505_regulator_match[] = {
2638 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2639 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2640 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2641 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2642 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2643 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2644 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2645 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2646 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2647 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2648 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2649 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2650 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2651};
2652
ae0a9a3e
LJ		 2653static struct of_regulator_match ab8540_regulator_match[] = {
2654 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2655 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2656 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2657 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
2658 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2659 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2660 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2661 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2662 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2663 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2664 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2665 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2666};
2667
8e6a8d7d
LJ		 2668static struct of_regulator_match ab9540_regulator_match[] = {
2669 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2670 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2671 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2672 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2673 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2674 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2675 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2676 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2677 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2678 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2679 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2680};
2681
a5023574 2682static int
b54969ac
LJ		 2683ab8500_regulator_of_probe(struct platform_device *pdev,
2684 struct ab8500_regulator_info *regulator_info,
2685 int regulator_info_size,
2686 struct of_regulator_match *match,
2687 struct device_node *np)
3a8334b9
LJ		 2688{
2689 int err, i;
2690
b54969ac 2691 for (i = 0; i < regulator_info_size; i++) {
3a8334b9 2692 err = ab8500_regulator_register(
b54969ac
LJ		 2693 pdev, match[i].init_data, regulator_info,
2694 i, match[i].of_node);
3a8334b9
LJ		 2695 if (err)
2696 return err;
2697 }
2698
2699 return 0;
2700}
2701
a5023574 2702static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 2703{
2704 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 2705 struct device_node *np = pdev->dev.of_node;
b54969ac 2706 struct of_regulator_match *match;
732805a5
BJ		 2707 struct ab8500_platform_data *ppdata;
2708 struct ab8500_regulator_platform_data *pdata;
c789ca20 2709 int i, err;
b54969ac
LJ		 2710 struct ab8500_regulator_info *regulator_info;
2711 int regulator_info_size;
2712 struct ab8500_reg_init *reg_init;
2713 int reg_init_size;
2714
8e6a8d7d
LJ		 2715 if (is_ab9540(ab8500)) {
2716 regulator_info = ab9540_regulator_info;
2717 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
2718 reg_init = ab9540_reg_init;
2719 reg_init_size = AB9540_NUM_REGULATOR_REGISTERS;
2720 match = ab9540_regulator_match;
2721 match_size = ARRAY_SIZE(ab9540_regulator_match)
547f384f
LJ		 2722 } else if (is_ab8505(ab8500)) {
2723 regulator_info = ab8505_regulator_info;
2724 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
2725 reg_init = ab8505_reg_init;
2726 reg_init_size = AB8505_NUM_REGULATOR_REGISTERS;
ae0a9a3e
LJ		 2727 } else if (is_ab8540(ab8500)) {
2728 regulator_info = ab8540_regulator_info;
2729 regulator_info_size = ARRAY_SIZE(ab8540_regulator_info);
2730 reg_init = ab8540_reg_init;
2731 reg_init_size = AB8540_NUM_REGULATOR_REGISTERS;
8e6a8d7d
LJ		 2732 } else {
2733 regulator_info = ab8500_regulator_info;
2734 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
2735 reg_init = ab8500_reg_init;
2736 reg_init_size = AB8500_NUM_REGULATOR_REGISTERS;
2737 match = ab8500_regulator_match;
2738 match_size = ARRAY_SIZE(ab8500_regulator_match)
2739 }
c789ca20 2740
3a8334b9 2741 if (np) {
b54969ac 2742 err = of_regulator_match(&pdev->dev, np, match, match_size);
3a8334b9
LJ		 2743 if (err < 0) {
2744 dev_err(&pdev->dev,
2745 "Error parsing regulator init data: %d\n", err);
2746 return err;
2747 }
2748
b54969ac
LJ		 2749 err = ab8500_regulator_of_probe(pdev, regulator_info,
2750 regulator_info_size, match, np);
3a8334b9
LJ		 2751 return err;
2752 }
2753
c789ca20
SI		 2754 if (!ab8500) {
2755 dev_err(&pdev->dev, "null mfd parent\n");
2756 return -EINVAL;
2757 }
732805a5
BJ		 2758
2759 ppdata = dev_get_platdata(ab8500->dev);
2760 if (!ppdata) {
2761 dev_err(&pdev->dev, "null parent pdata\n");
2762 return -EINVAL;
2763 }
2764
2765 pdata = ppdata->regulator;
fc24b426
BJ		 2766 if (!pdata) {
2767 dev_err(&pdev->dev, "null pdata\n");
2768 return -EINVAL;
2769 }
c789ca20 2770
cb189b07 2771 /* make sure the platform data has the correct size */
b54969ac 2772 if (pdata->num_regulator != regulator_info_size) {
79568b94 2773 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 2774 return -EINVAL;
2775 }
2776
da0b0c47
LJ		 2777 /* initialize debug (initial state is recorded with this call) */
2778 err = ab8500_regulator_debug_init(pdev);
2779 if (err)
2780 return err;
2781
79568b94 2782 /* initialize registers */
732805a5 2783 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 2784 int id, mask, value;
79568b94 2785
732805a5
BJ		 2786 id = pdata->reg_init[i].id;
2787 mask = pdata->reg_init[i].mask;
2788 value = pdata->reg_init[i].value;
79568b94
BJ		 2789
2790 /* check for configuration errors */
3c1b8438 2791 BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
79568b94 2792
b54969ac 2793 err = ab8500_regulator_init_registers(pdev, reg_init, id, mask, value);
a7ac1d9e 2794 if (err < 0)
79568b94 2795 return err;
79568b94
BJ		 2796 }
2797
d1a82001
LJ		 2798 /* register external regulators (before Vaux1, 2 and 3) */
2799 err = ab8500_ext_regulator_init(pdev);
2800 if (err)
2801 return err;
2802
c789ca20 2803 /* register all regulators */
b54969ac
LJ		 2804 for (i = 0; i < regulator_info_size; i++) {
2805 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
2806 regulator_info, i, NULL);
a7ac1d9e 2807 if (err < 0)
c789ca20 2808 return err;
c789ca20
SI		 2809 }
2810
2811 return 0;
2812}
2813
8dc995f5 2814static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 2815{
d1a82001 2816 int i, err;
8e6a8d7d 2817 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac
LJ		 2818 struct ab8500_regulator_info *regulator_info;
2819 int regulator_info_size;
c789ca20 2820
8e6a8d7d
LJ		 2821
2822 if (is_ab9540(ab8500)) {
2823 regulator_info = ab9540_regulator_info;
2824 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
547f384f
LJ		 2825 } else if (is_ab8505(ab8500)) {
2826 regulator_info = ab8505_regulator_info;
2827 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
8e6a8d7d
LJ		 2828 } else {
2829 regulator_info = ab8500_regulator_info;
2830 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
2831 }
b54969ac
LJ		 2832
2833 for (i = 0; i < regulator_info_size; i++) {
c789ca20 2834 struct ab8500_regulator_info *info = NULL;
b54969ac 2835 info = &regulator_info[i];
09aefa12
BJ		 2836
2837 dev_vdbg(rdev_get_dev(info->regulator),
2838 "%s-remove\n", info->desc.name);
2839
c789ca20
SI		 2840 regulator_unregister(info->regulator);
2841 }
2842
d1a82001
LJ		 2843 /* remove external regulators (after Vaux1, 2 and 3) */
2844 err = ab8500_ext_regulator_exit(pdev);
2845 if (err)
2846 return err;
2847
da0b0c47
LJ		 2848 /* remove regulator debug */
2849 err = ab8500_regulator_debug_exit(pdev);
2850 if (err)
2851 return err;
2852
c789ca20
SI		 2853 return 0;
2854}
2855
2856static struct platform_driver ab8500_regulator_driver = {
2857 .probe = ab8500_regulator_probe,
5eb9f2b9 2858 .remove = ab8500_regulator_remove,
c789ca20
SI		 2859 .driver = {
2860 .name = "ab8500-regulator",
2861 .owner = THIS_MODULE,
2862 },
2863};
2864
2865static int __init ab8500_regulator_init(void)
2866{
2867 int ret;
2868
2869 ret = platform_driver_register(&ab8500_regulator_driver);
2870 if (ret != 0)
2871 pr_err("Failed to register ab8500 regulator: %d\n", ret);
2872
2873 return ret;
2874}
2875subsys_initcall(ab8500_regulator_init);
2876
2877static void __exit ab8500_regulator_exit(void)
2878{
2879 platform_driver_unregister(&ab8500_regulator_driver);
2880}
2881module_exit(ab8500_regulator_exit);
2882
2883MODULE_LICENSE("GPL v2");
2884MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 2885MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 2886MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 2887MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
2888MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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