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regulator: ab8500: Fix list_voltage for fixed voltage regulators
[deliverable/linux.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
bd28a157 49 * @is_enabled: status of regulator (on/off)
7ce4669c 50 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 51 * @update_bank: bank to control on/off
c789ca20 52 * @update_reg: register to control on/off
bd28a157
EV		 53 * @update_mask: mask to enable/disable and set mode of regulator
54 * @update_val: bits holding the regulator current mode
55 * @update_val_idle: bits to enable the regulator in idle (low power) mode
56 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 57 * @mode_bank: bank with location of mode register
58 * @mode_reg: mode register
59 * @mode_mask: mask for setting mode
60 * @mode_val_idle: mode setting for low power
61 * @mode_val_normal: mode setting for normal power
47c16975 62 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 63 * @voltage_reg: register to control regulator voltage
64 * @voltage_mask: mask to control regulator voltage
a0a7014c 65 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 66 */
67struct ab8500_regulator_info {
68 struct device *dev;
69 struct regulator_desc desc;
c789ca20 70 struct regulator_dev *regulator;
3fe52289 71 struct ab8500_shared_mode *shared_mode;
bd28a157 72 bool is_enabled;
7ce4669c 73 int load_lp_uA;
47c16975
MW		 74 u8 update_bank;
75 u8 update_reg;
e1159e6d 76 u8 update_mask;
bd28a157
EV		 77 u8 update_val;
78 u8 update_val_idle;
79 u8 update_val_normal;
3fe52289
LJ		 80 u8 mode_bank;
81 u8 mode_reg;
82 u8 mode_mask;
83 u8 mode_val_idle;
84 u8 mode_val_normal;
47c16975
MW		 85 u8 voltage_bank;
86 u8 voltage_reg;
87 u8 voltage_mask;
a0a7014c 88 u8 voltage_shift;
d7607baf
LJ		 89 struct {
90 u8 voltage_limit;
91 u8 voltage_bank;
92 u8 voltage_reg;
93 u8 voltage_mask;
94 u8 voltage_shift;
95 } expand_register;
c789ca20
SI		 96};
97
98/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 99static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 100 1100000,
101 1200000,
102 1300000,
103 1400000,
104 1500000,
105 1800000,
106 1850000,
107 1900000,
108 2500000,
109 2650000,
110 2700000,
111 2750000,
112 2800000,
113 2900000,
114 3000000,
115 3300000,
116};
117
ec1cc4d9 118static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 119 1200000,
120 1500000,
121 1800000,
122 2100000,
123 2500000,
124 2750000,
125 2790000,
126 2910000,
127};
128
62ab4111 129static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 130 1800000,
131 1050000,
132 1100000,
133 1200000,
134 1500000,
135 2200000,
136 2500000,
137 2790000,
138};
139
62ab4111 140static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 141 1200000,
142 1500000,
143 1800000,
144 2100000,
145 2500000,
146 2750000,
147 2790000,
148 2910000,
149 3050000,
150};
151
684d5ce4
ZH		 152static const unsigned int ldo_vaux56_ab8540_voltages[] = {
153 750000, 760000, 770000, 780000, 790000, 800000,
154 810000, 820000, 830000, 840000, 850000, 860000,
155 870000, 880000, 890000, 900000, 910000, 920000,
156 930000, 940000, 950000, 960000, 970000, 980000,
157 990000, 1000000, 1010000, 1020000, 1030000,
158 1040000, 1050000, 1060000, 1070000, 1080000,
159 1090000, 1100000, 1110000, 1120000, 1130000,
160 1140000, 1150000, 1160000, 1170000, 1180000,
161 1190000, 1200000, 1210000, 1220000, 1230000,
162 1240000, 1250000, 1260000, 1270000, 1280000,
163 1290000, 1300000, 1310000, 1320000, 1330000,
164 1340000, 1350000, 1360000, 1800000, 2790000,
165};
166
ec1cc4d9 167static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 168 1200000,
169 1225000,
170 1250000,
171 1275000,
172 1300000,
173 1325000,
174 1350000,
175};
176
62ab4111 177static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 178 1160000,
179 1050000,
180 1100000,
181 1500000,
182 1800000,
183 2200000,
184 2910000,
185 3050000,
186};
187
b080c78a
LJ		 188static const unsigned int fixed_1200000_voltage[] = {
189 1200000,
190};
191
192static const unsigned int fixed_1800000_voltage[] = {
193 1800000,
194};
195
196static const unsigned int fixed_2000000_voltage[] = {
197 2000000,
198};
199
200static const unsigned int fixed_2050000_voltage[] = {
201 2050000,
202};
203
204static const unsigned int fixed_3300000_voltage[] = {
205 3300000,
206};
207
8a3b1b87
LJ		 208static const unsigned int ldo_vana_voltages[] = {
209 1050000,
210 1075000,
211 1100000,
212 1125000,
213 1150000,
214 1175000,
215 1200000,
216 1225000,
217};
218
219static const unsigned int ldo_vaudio_voltages[] = {
220 2000000,
221 2100000,
222 2200000,
223 2300000,
224 2400000,
225 2500000,
226 2600000,
227 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
228};
229
4c84b4dd
LJ		 230static const unsigned int ldo_vdmic_voltages[] = {
231 1800000,
232 1900000,
233 2000000,
234 2850000,
235};
236
3fe52289
LJ		 237static DEFINE_MUTEX(shared_mode_mutex);
238static struct ab8500_shared_mode ldo_anamic1_shared;
239static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 240static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
241static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 242
c789ca20
SI		 243static int ab8500_regulator_enable(struct regulator_dev *rdev)
244{
fc24b426 245 int ret;
c789ca20
SI		 246 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
247
fc24b426
BJ		 248 if (info == NULL) {
249 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 250 return -EINVAL;
fc24b426 251 }
c789ca20 252
47c16975 253 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 254 info->update_bank, info->update_reg,
bd28a157 255 info->update_mask, info->update_val);
f71bf528 256 if (ret < 0) {
c789ca20
SI		 257 dev_err(rdev_get_dev(rdev),
258 "couldn't set enable bits for regulator\n");
f71bf528
AL		 259 return ret;
260 }
09aefa12 261
bd28a157
EV		 262 info->is_enabled = true;
263
09aefa12
BJ		 264 dev_vdbg(rdev_get_dev(rdev),
265 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
266 info->desc.name, info->update_bank, info->update_reg,
bd28a157 267 info->update_mask, info->update_val);
09aefa12 268
c789ca20
SI		 269 return ret;
270}
271
272static int ab8500_regulator_disable(struct regulator_dev *rdev)
273{
fc24b426 274 int ret;
c789ca20
SI		 275 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
276
fc24b426
BJ		 277 if (info == NULL) {
278 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 279 return -EINVAL;
fc24b426 280 }
c789ca20 281
47c16975 282 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 283 info->update_bank, info->update_reg,
284 info->update_mask, 0x0);
f71bf528 285 if (ret < 0) {
c789ca20
SI		 286 dev_err(rdev_get_dev(rdev),
287 "couldn't set disable bits for regulator\n");
f71bf528
AL		 288 return ret;
289 }
09aefa12 290
bd28a157
EV		 291 info->is_enabled = false;
292
09aefa12
BJ		 293 dev_vdbg(rdev_get_dev(rdev),
294 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
295 info->desc.name, info->update_bank, info->update_reg,
296 info->update_mask, 0x0);
297
c789ca20
SI		 298 return ret;
299}
300
7ce4669c
BJ		 301static unsigned int ab8500_regulator_get_optimum_mode(
302 struct regulator_dev *rdev, int input_uV,
303 int output_uV, int load_uA)
304{
305 unsigned int mode;
306
307 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
308
309 if (info == NULL) {
310 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
311 return -EINVAL;
312 }
313
314 if (load_uA <= info->load_lp_uA)
315 mode = REGULATOR_MODE_IDLE;
316 else
317 mode = REGULATOR_MODE_NORMAL;
318
319 return mode;
320}
321
bd28a157
EV		 322static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
323 unsigned int mode)
324{
3fe52289
LJ		 325 int ret = 0;
326 u8 bank;
327 u8 reg;
328 u8 mask;
329 u8 val;
330 bool dmr = false; /* Dedicated mode register */
bd28a157
EV		 331 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
332
333 if (info == NULL) {
334 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
335 return -EINVAL;
336 }
337
3fe52289
LJ		 338 if (info->shared_mode) {
339 /*
340 * Special case where mode is shared between two regulators.
341 */
342 struct ab8500_shared_mode *sm = info->shared_mode;
343 mutex_lock(&shared_mode_mutex);
344
345 if (mode == REGULATOR_MODE_IDLE) {
346 sm->lp_mode_req = true; /* Low power mode requested */
347 if (!((sm->shared_regulator)->
348 shared_mode->lp_mode_req)) {
349 mutex_unlock(&shared_mode_mutex);
350 return 0; /* Other regulator prevent LP mode */
351 }
352 } else {
353 sm->lp_mode_req = false;
354 }
355 }
356
357 if (info->mode_mask) {
358 /* Dedicated register for handling mode */
359
360 dmr = true;
361
362 switch (mode) {
363 case REGULATOR_MODE_NORMAL:
364 val = info->mode_val_normal;
365 break;
366 case REGULATOR_MODE_IDLE:
367 val = info->mode_val_idle;
368 break;
369 default:
370 if (info->shared_mode)
371 mutex_unlock(&shared_mode_mutex);
372 return -EINVAL;
373 }
374
375 bank = info->mode_bank;
376 reg = info->mode_reg;
377 mask = info->mode_mask;
378 } else {
379 /* Mode register same as enable register */
380
381 switch (mode) {
382 case REGULATOR_MODE_NORMAL:
383 info->update_val = info->update_val_normal;
384 val = info->update_val_normal;
385 break;
386 case REGULATOR_MODE_IDLE:
387 info->update_val = info->update_val_idle;
388 val = info->update_val_idle;
389 break;
390 default:
391 if (info->shared_mode)
392 mutex_unlock(&shared_mode_mutex);
393 return -EINVAL;
394 }
395
396 bank = info->update_bank;
397 reg = info->update_reg;
398 mask = info->update_mask;
bd28a157
EV		 399 }
400
3fe52289 401 if (info->is_enabled || dmr) {
bd28a157 402 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289
LJ		 403 bank, reg, mask, val);
404 if (ret < 0)
bd28a157
EV		 405 dev_err(rdev_get_dev(rdev),
406 "couldn't set regulator mode\n");
7ce4669c
BJ		 407
408 dev_vdbg(rdev_get_dev(rdev),
409 "%s-set_mode (bank, reg, mask, value): "
410 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 411 info->desc.name, bank, reg,
412 mask, val);
bd28a157
EV		 413 }
414
3fe52289
LJ		 415 if (info->shared_mode)
416 mutex_unlock(&shared_mode_mutex);
742a7325 417
3fe52289 418 return ret;
bd28a157
EV		 419}
420
421static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
422{
423 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
424 int ret;
3fe52289
LJ		 425 u8 val;
426 u8 val_normal;
427 u8 val_idle;
bd28a157
EV		 428
429 if (info == NULL) {
430 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
431 return -EINVAL;
432 }
433
3fe52289
LJ		 434 /* Need special handling for shared mode */
435 if (info->shared_mode) {
436 if (info->shared_mode->lp_mode_req)
437 return REGULATOR_MODE_IDLE;
438 else
439 return REGULATOR_MODE_NORMAL;
440 }
441
442 if (info->mode_mask) {
443 /* Dedicated register for handling mode */
444 ret = abx500_get_register_interruptible(info->dev,
445 info->mode_bank, info->mode_reg, &val);
446 val = val & info->mode_mask;
447
448 val_normal = info->mode_val_normal;
449 val_idle = info->mode_val_idle;
450 } else {
451 /* Mode register same as enable register */
452 val = info->update_val;
453 val_normal = info->update_val_normal;
454 val_idle = info->update_val_idle;
455 }
456
457 if (val == val_normal)
bd28a157 458 ret = REGULATOR_MODE_NORMAL;
3fe52289 459 else if (val == val_idle)
bd28a157
EV		 460 ret = REGULATOR_MODE_IDLE;
461 else
462 ret = -EINVAL;
463
464 return ret;
465}
466
c789ca20
SI		 467static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
468{
fc24b426 469 int ret;
c789ca20 470 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 471 u8 regval;
c789ca20 472
fc24b426
BJ		 473 if (info == NULL) {
474 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 475 return -EINVAL;
fc24b426 476 }
c789ca20 477
47c16975 478 ret = abx500_get_register_interruptible(info->dev,
09aefa12 479 info->update_bank, info->update_reg, &regval);
c789ca20
SI		 480 if (ret < 0) {
481 dev_err(rdev_get_dev(rdev),
482 "couldn't read 0x%x register\n", info->update_reg);
483 return ret;
484 }
485
09aefa12
BJ		 486 dev_vdbg(rdev_get_dev(rdev),
487 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
488 " 0x%x\n",
489 info->desc.name, info->update_bank, info->update_reg,
490 info->update_mask, regval);
491
492 if (regval & info->update_mask)
bd28a157 493 info->is_enabled = true;
c789ca20 494 else
bd28a157
EV		 495 info->is_enabled = false;
496
497 return info->is_enabled;
c789ca20
SI		 498}
499
3bf6e90e 500static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 501{
09aefa12 502 int ret, val;
c789ca20 503 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 504 u8 regval;
c789ca20 505
fc24b426
BJ		 506 if (info == NULL) {
507 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 508 return -EINVAL;
fc24b426 509 }
c789ca20 510
09aefa12
BJ		 511 ret = abx500_get_register_interruptible(info->dev,
512 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 513 if (ret < 0) {
514 dev_err(rdev_get_dev(rdev),
515 "couldn't read voltage reg for regulator\n");
516 return ret;
517 }
518
09aefa12 519 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 520 "%s-get_voltage (bank, reg, mask, shift, value): "
521 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
522 info->desc.name, info->voltage_bank,
523 info->voltage_reg, info->voltage_mask,
524 info->voltage_shift, regval);
09aefa12 525
09aefa12 526 val = regval & info->voltage_mask;
a0a7014c 527 return val >> info->voltage_shift;
c789ca20
SI		 528}
529
d7607baf
LJ		 530static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
531{
532 int ret, val;
533 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
534 u8 regval, regval_expand;
535
536 if (info == NULL) {
537 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
538 return -EINVAL;
539 }
540
541 ret = abx500_get_register_interruptible(info->dev,
542 info->voltage_bank, info->voltage_reg, &regval);
543
544 if (ret < 0) {
545 dev_err(rdev_get_dev(rdev),
546 "couldn't read voltage reg for regulator\n");
547 return ret;
548 }
549
550 ret = abx500_get_register_interruptible(info->dev,
551 info->expand_register.voltage_bank,
552 info->expand_register.voltage_reg, &regval_expand);
553
554 if (ret < 0) {
555 dev_err(rdev_get_dev(rdev),
556 "couldn't read voltage reg for regulator\n");
557 return ret;
558 }
559
560 dev_vdbg(rdev_get_dev(rdev),
561 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
562 " 0x%x\n",
563 info->desc.name, info->voltage_bank, info->voltage_reg,
564 info->voltage_mask, regval);
565 dev_vdbg(rdev_get_dev(rdev),
566 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
567 " 0x%x\n",
568 info->desc.name, info->expand_register.voltage_bank,
569 info->expand_register.voltage_reg,
570 info->expand_register.voltage_mask, regval_expand);
571
572 if (regval_expand&(info->expand_register.voltage_mask))
573 /* Vaux3 has a different layout */
574 val = info->expand_register.voltage_limit;
575 else
576 val = (regval & info->voltage_mask) >> info->voltage_shift;
577
578 return val;
579}
580
ae713d39
AL		 581static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
582 unsigned selector)
c789ca20 583{
fc24b426 584 int ret;
c789ca20 585 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 586 u8 regval;
c789ca20 587
fc24b426
BJ		 588 if (info == NULL) {
589 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 590 return -EINVAL;
fc24b426 591 }
c789ca20 592
c789ca20 593 /* set the registers for the request */
a0a7014c 594 regval = (u8)selector << info->voltage_shift;
47c16975 595 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 596 info->voltage_bank, info->voltage_reg,
597 info->voltage_mask, regval);
c789ca20
SI		 598 if (ret < 0)
599 dev_err(rdev_get_dev(rdev),
600 "couldn't set voltage reg for regulator\n");
601
09aefa12
BJ		 602 dev_vdbg(rdev_get_dev(rdev),
603 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
604 " 0x%x\n",
605 info->desc.name, info->voltage_bank, info->voltage_reg,
606 info->voltage_mask, regval);
607
c789ca20
SI		 608 return ret;
609}
610
d7607baf
LJ		 611static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
612 unsigned selector)
613{
614 int ret;
615 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
616 u8 regval;
617
618 if (info == NULL) {
619 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
620 return -EINVAL;
621 }
622
623 if (selector >= info->expand_register.voltage_limit) {
624 /* Vaux3 bit4 has different layout */
625 regval = (u8)selector << info->expand_register.voltage_shift;
626 ret = abx500_mask_and_set_register_interruptible(info->dev,
627 info->expand_register.voltage_bank,
628 info->expand_register.voltage_reg,
629 info->expand_register.voltage_mask,
630 regval);
631 } else {
632 /* set the registers for the request */
633 regval = (u8)selector << info->voltage_shift;
634 ret = abx500_mask_and_set_register_interruptible(info->dev,
635 info->voltage_bank, info->voltage_reg,
636 info->voltage_mask, regval);
637 }
638 if (ret < 0)
639 dev_err(rdev_get_dev(rdev),
640 "couldn't set voltage reg for regulator\n");
641
642 dev_vdbg(rdev_get_dev(rdev),
643 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
644 " 0x%x\n",
645 info->desc.name, info->voltage_bank, info->voltage_reg,
646 info->voltage_mask, regval);
647
648 return ret;
649}
650
651static int ab8500_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
652 unsigned int old_sel,
653 unsigned int new_sel)
654{
655 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
656
5fc9da6d 657 return info->desc.enable_time;
d7607baf
LJ		 658}
659
7ce4669c
BJ		 660static struct regulator_ops ab8500_regulator_volt_mode_ops = {
661 .enable = ab8500_regulator_enable,
662 .disable = ab8500_regulator_disable,
663 .is_enabled = ab8500_regulator_is_enabled,
664 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
665 .set_mode = ab8500_regulator_set_mode,
666 .get_mode = ab8500_regulator_get_mode,
667 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
668 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
669 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 670};
671
d7607baf
LJ		 672static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
673 .enable = ab8500_regulator_enable,
674 .disable = ab8500_regulator_disable,
675 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
676 .set_mode = ab8500_regulator_set_mode,
677 .get_mode = ab8500_regulator_get_mode,
678 .is_enabled = ab8500_regulator_is_enabled,
679 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
680 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
681 .list_voltage = regulator_list_voltage_table,
682 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
683};
684
8a3b1b87
LJ		 685static struct regulator_ops ab8500_regulator_volt_ops = {
686 .enable = ab8500_regulator_enable,
687 .disable = ab8500_regulator_disable,
688 .is_enabled = ab8500_regulator_is_enabled,
689 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
690 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
691 .list_voltage = regulator_list_voltage_table,
692 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
693};
694
7ce4669c
BJ		 695static struct regulator_ops ab8500_regulator_mode_ops = {
696 .enable = ab8500_regulator_enable,
697 .disable = ab8500_regulator_disable,
698 .is_enabled = ab8500_regulator_is_enabled,
699 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
700 .set_mode = ab8500_regulator_set_mode,
701 .get_mode = ab8500_regulator_get_mode,
d7816ab0 702 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 703};
704
705static struct regulator_ops ab8500_regulator_ops = {
706 .enable = ab8500_regulator_enable,
707 .disable = ab8500_regulator_disable,
708 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 709 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 710};
711
3fe52289
LJ		 712static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
713 .enable = ab8500_regulator_enable,
714 .disable = ab8500_regulator_disable,
715 .is_enabled = ab8500_regulator_is_enabled,
716 .set_mode = ab8500_regulator_set_mode,
717 .get_mode = ab8500_regulator_get_mode,
718 .list_voltage = regulator_list_voltage_table,
719};
720
8e6a8d7d 721/* AB8500 regulator information */
6909b452
BJ		 722static struct ab8500_regulator_info
723 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 724 /*
e1159e6d
BJ		 725 * Variable Voltage Regulators
726 * name, min mV, max mV,
727 * update bank, reg, mask, enable val
ec1cc4d9 728 * volt bank, reg, mask
c789ca20 729 */
6909b452
BJ		 730 [AB8500_LDO_AUX1] = {
731 .desc = {
732 .name = "LDO-AUX1",
7ce4669c 733 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 734 .type = REGULATOR_VOLTAGE,
735 .id = AB8500_LDO_AUX1,
736 .owner = THIS_MODULE,
737 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 738 .volt_table = ldo_vauxn_voltages,
530158b6 739 .enable_time = 200,
6909b452 740 },
7ce4669c 741 .load_lp_uA = 5000,
6909b452
BJ		 742 .update_bank = 0x04,
743 .update_reg = 0x09,
744 .update_mask = 0x03,
bd28a157
EV		 745 .update_val = 0x01,
746 .update_val_idle = 0x03,
747 .update_val_normal = 0x01,
6909b452
BJ		 748 .voltage_bank = 0x04,
749 .voltage_reg = 0x1f,
750 .voltage_mask = 0x0f,
6909b452
BJ		 751 },
752 [AB8500_LDO_AUX2] = {
753 .desc = {
754 .name = "LDO-AUX2",
7ce4669c 755 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 756 .type = REGULATOR_VOLTAGE,
757 .id = AB8500_LDO_AUX2,
758 .owner = THIS_MODULE,
759 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 760 .volt_table = ldo_vauxn_voltages,
530158b6 761 .enable_time = 200,
6909b452 762 },
7ce4669c 763 .load_lp_uA = 5000,
6909b452
BJ		 764 .update_bank = 0x04,
765 .update_reg = 0x09,
766 .update_mask = 0x0c,
bd28a157
EV		 767 .update_val = 0x04,
768 .update_val_idle = 0x0c,
769 .update_val_normal = 0x04,
6909b452
BJ		 770 .voltage_bank = 0x04,
771 .voltage_reg = 0x20,
772 .voltage_mask = 0x0f,
6909b452
BJ		 773 },
774 [AB8500_LDO_AUX3] = {
775 .desc = {
776 .name = "LDO-AUX3",
7ce4669c 777 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 778 .type = REGULATOR_VOLTAGE,
779 .id = AB8500_LDO_AUX3,
780 .owner = THIS_MODULE,
781 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 782 .volt_table = ldo_vaux3_voltages,
530158b6 783 .enable_time = 450,
6909b452 784 },
7ce4669c 785 .load_lp_uA = 5000,
6909b452
BJ		 786 .update_bank = 0x04,
787 .update_reg = 0x0a,
788 .update_mask = 0x03,
bd28a157
EV		 789 .update_val = 0x01,
790 .update_val_idle = 0x03,
791 .update_val_normal = 0x01,
6909b452
BJ		 792 .voltage_bank = 0x04,
793 .voltage_reg = 0x21,
794 .voltage_mask = 0x07,
6909b452
BJ		 795 },
796 [AB8500_LDO_INTCORE] = {
797 .desc = {
798 .name = "LDO-INTCORE",
7ce4669c 799 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 800 .type = REGULATOR_VOLTAGE,
801 .id = AB8500_LDO_INTCORE,
802 .owner = THIS_MODULE,
803 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 804 .volt_table = ldo_vintcore_voltages,
530158b6 805 .enable_time = 750,
6909b452 806 },
7ce4669c 807 .load_lp_uA = 5000,
6909b452
BJ		 808 .update_bank = 0x03,
809 .update_reg = 0x80,
810 .update_mask = 0x44,
cc40dc29 811 .update_val = 0x44,
bd28a157
EV		 812 .update_val_idle = 0x44,
813 .update_val_normal = 0x04,
6909b452
BJ		 814 .voltage_bank = 0x03,
815 .voltage_reg = 0x80,
816 .voltage_mask = 0x38,
a0a7014c 817 .voltage_shift = 3,
6909b452 818 },
c789ca20
SI		 819
820 /*
e1159e6d
BJ		 821 * Fixed Voltage Regulators
822 * name, fixed mV,
823 * update bank, reg, mask, enable val
c789ca20 824 */
6909b452
BJ		 825 [AB8500_LDO_TVOUT] = {
826 .desc = {
827 .name = "LDO-TVOUT",
7ce4669c 828 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 829 .type = REGULATOR_VOLTAGE,
830 .id = AB8500_LDO_TVOUT,
831 .owner = THIS_MODULE,
832 .n_voltages = 1,
b080c78a 833 .volt_table = fixed_2000000_voltage,
ed3c138e 834 .enable_time = 500,
6909b452 835 },
7ce4669c 836 .load_lp_uA = 1000,
6909b452
BJ		 837 .update_bank = 0x03,
838 .update_reg = 0x80,
839 .update_mask = 0x82,
bd28a157 840 .update_val = 0x02,
7ce4669c
BJ		 841 .update_val_idle = 0x82,
842 .update_val_normal = 0x02,
6909b452
BJ		 843 },
844 [AB8500_LDO_AUDIO] = {
845 .desc = {
846 .name = "LDO-AUDIO",
7ce4669c 847 .ops = &ab8500_regulator_ops,
6909b452
BJ		 848 .type = REGULATOR_VOLTAGE,
849 .id = AB8500_LDO_AUDIO,
850 .owner = THIS_MODULE,
851 .n_voltages = 1,
530158b6 852 .enable_time = 140,
b080c78a 853 .volt_table = fixed_2000000_voltage,
6909b452 854 },
6909b452
BJ		 855 .update_bank = 0x03,
856 .update_reg = 0x83,
857 .update_mask = 0x02,
bd28a157 858 .update_val = 0x02,
6909b452
BJ		 859 },
860 [AB8500_LDO_ANAMIC1] = {
861 .desc = {
862 .name = "LDO-ANAMIC1",
7ce4669c 863 .ops = &ab8500_regulator_ops,
6909b452
BJ		 864 .type = REGULATOR_VOLTAGE,
865 .id = AB8500_LDO_ANAMIC1,
866 .owner = THIS_MODULE,
867 .n_voltages = 1,
530158b6 868 .enable_time = 500,
b080c78a 869 .volt_table = fixed_2050000_voltage,
6909b452 870 },
6909b452
BJ		 871 .update_bank = 0x03,
872 .update_reg = 0x83,
873 .update_mask = 0x08,
bd28a157 874 .update_val = 0x08,
6909b452
BJ		 875 },
876 [AB8500_LDO_ANAMIC2] = {
877 .desc = {
878 .name = "LDO-ANAMIC2",
7ce4669c 879 .ops = &ab8500_regulator_ops,
6909b452
BJ		 880 .type = REGULATOR_VOLTAGE,
881 .id = AB8500_LDO_ANAMIC2,
882 .owner = THIS_MODULE,
883 .n_voltages = 1,
530158b6 884 .enable_time = 500,
b080c78a 885 .volt_table = fixed_2050000_voltage,
6909b452 886 },
6909b452
BJ		 887 .update_bank = 0x03,
888 .update_reg = 0x83,
889 .update_mask = 0x10,
bd28a157 890 .update_val = 0x10,
6909b452
BJ		 891 },
892 [AB8500_LDO_DMIC] = {
893 .desc = {
894 .name = "LDO-DMIC",
7ce4669c 895 .ops = &ab8500_regulator_ops,
6909b452
BJ		 896 .type = REGULATOR_VOLTAGE,
897 .id = AB8500_LDO_DMIC,
898 .owner = THIS_MODULE,
899 .n_voltages = 1,
530158b6 900 .enable_time = 420,
b080c78a 901 .volt_table = fixed_1800000_voltage,
6909b452 902 },
6909b452
BJ		 903 .update_bank = 0x03,
904 .update_reg = 0x83,
905 .update_mask = 0x04,
bd28a157 906 .update_val = 0x04,
6909b452 907 },
7ce4669c
BJ		 908
909 /*
910 * Regulators with fixed voltage and normal/idle modes
911 */
6909b452
BJ		 912 [AB8500_LDO_ANA] = {
913 .desc = {
914 .name = "LDO-ANA",
7ce4669c 915 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 916 .type = REGULATOR_VOLTAGE,
917 .id = AB8500_LDO_ANA,
918 .owner = THIS_MODULE,
919 .n_voltages = 1,
530158b6 920 .enable_time = 140,
b080c78a 921 .volt_table = fixed_1200000_voltage,
6909b452 922 },
7ce4669c 923 .load_lp_uA = 1000,
6909b452
BJ		 924 .update_bank = 0x04,
925 .update_reg = 0x06,
926 .update_mask = 0x0c,
bd28a157 927 .update_val = 0x04,
7ce4669c
BJ		 928 .update_val_idle = 0x0c,
929 .update_val_normal = 0x04,
6909b452 930 },
8e6a8d7d 931};
6909b452 932
547f384f
LJ		 933/* AB8505 regulator information */
934static struct ab8500_regulator_info
935 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
936 /*
937 * Variable Voltage Regulators
938 * name, min mV, max mV,
939 * update bank, reg, mask, enable val
d3193103 940 * volt bank, reg, mask
547f384f
LJ		 941 */
942 [AB8505_LDO_AUX1] = {
943 .desc = {
944 .name = "LDO-AUX1",
945 .ops = &ab8500_regulator_volt_mode_ops,
946 .type = REGULATOR_VOLTAGE,
0b946411 947 .id = AB8505_LDO_AUX1,
547f384f
LJ		 948 .owner = THIS_MODULE,
949 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 950 .volt_table = ldo_vauxn_voltages,
547f384f 951 },
547f384f
LJ		 952 .load_lp_uA = 5000,
953 .update_bank = 0x04,
954 .update_reg = 0x09,
955 .update_mask = 0x03,
956 .update_val = 0x01,
957 .update_val_idle = 0x03,
958 .update_val_normal = 0x01,
959 .voltage_bank = 0x04,
960 .voltage_reg = 0x1f,
961 .voltage_mask = 0x0f,
547f384f
LJ		 962 },
963 [AB8505_LDO_AUX2] = {
964 .desc = {
965 .name = "LDO-AUX2",
966 .ops = &ab8500_regulator_volt_mode_ops,
967 .type = REGULATOR_VOLTAGE,
0b946411 968 .id = AB8505_LDO_AUX2,
547f384f
LJ		 969 .owner = THIS_MODULE,
970 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 971 .volt_table = ldo_vauxn_voltages,
547f384f 972 },
547f384f
LJ		 973 .load_lp_uA = 5000,
974 .update_bank = 0x04,
975 .update_reg = 0x09,
976 .update_mask = 0x0c,
977 .update_val = 0x04,
978 .update_val_idle = 0x0c,
979 .update_val_normal = 0x04,
980 .voltage_bank = 0x04,
981 .voltage_reg = 0x20,
982 .voltage_mask = 0x0f,
547f384f
LJ		 983 },
984 [AB8505_LDO_AUX3] = {
985 .desc = {
986 .name = "LDO-AUX3",
987 .ops = &ab8500_regulator_volt_mode_ops,
988 .type = REGULATOR_VOLTAGE,
0b946411 989 .id = AB8505_LDO_AUX3,
547f384f
LJ		 990 .owner = THIS_MODULE,
991 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 992 .volt_table = ldo_vaux3_voltages,
547f384f 993 },
547f384f
LJ		 994 .load_lp_uA = 5000,
995 .update_bank = 0x04,
996 .update_reg = 0x0a,
997 .update_mask = 0x03,
998 .update_val = 0x01,
999 .update_val_idle = 0x03,
1000 .update_val_normal = 0x01,
1001 .voltage_bank = 0x04,
1002 .voltage_reg = 0x21,
1003 .voltage_mask = 0x07,
547f384f
LJ		 1004 },
1005 [AB8505_LDO_AUX4] = {
1006 .desc = {
1007 .name = "LDO-AUX4",
1008 .ops = &ab8500_regulator_volt_mode_ops,
1009 .type = REGULATOR_VOLTAGE,
0b946411 1010 .id = AB8505_LDO_AUX4,
547f384f
LJ		 1011 .owner = THIS_MODULE,
1012 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1013 .volt_table = ldo_vauxn_voltages,
547f384f 1014 },
547f384f
LJ		 1015 .load_lp_uA = 5000,
1016 /* values for Vaux4Regu register */
1017 .update_bank = 0x04,
1018 .update_reg = 0x2e,
1019 .update_mask = 0x03,
1020 .update_val = 0x01,
1021 .update_val_idle = 0x03,
1022 .update_val_normal = 0x01,
1023 /* values for Vaux4SEL register */
1024 .voltage_bank = 0x04,
1025 .voltage_reg = 0x2f,
1026 .voltage_mask = 0x0f,
547f384f
LJ		 1027 },
1028 [AB8505_LDO_AUX5] = {
1029 .desc = {
1030 .name = "LDO-AUX5",
1031 .ops = &ab8500_regulator_volt_mode_ops,
1032 .type = REGULATOR_VOLTAGE,
1033 .id = AB8505_LDO_AUX5,
1034 .owner = THIS_MODULE,
1035 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1036 .volt_table = ldo_vaux56_voltages,
547f384f 1037 },
547f384f
LJ		 1038 .load_lp_uA = 2000,
1039 /* values for CtrlVaux5 register */
1040 .update_bank = 0x01,
1041 .update_reg = 0x55,
ae0a9a3e
LJ		 1042 .update_mask = 0x18,
1043 .update_val = 0x10,
1044 .update_val_idle = 0x18,
1045 .update_val_normal = 0x10,
547f384f
LJ		 1046 .voltage_bank = 0x01,
1047 .voltage_reg = 0x55,
1048 .voltage_mask = 0x07,
547f384f
LJ		 1049 },
1050 [AB8505_LDO_AUX6] = {
1051 .desc = {
1052 .name = "LDO-AUX6",
1053 .ops = &ab8500_regulator_volt_mode_ops,
1054 .type = REGULATOR_VOLTAGE,
1055 .id = AB8505_LDO_AUX6,
1056 .owner = THIS_MODULE,
1057 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1058 .volt_table = ldo_vaux56_voltages,
547f384f 1059 },
547f384f
LJ		 1060 .load_lp_uA = 2000,
1061 /* values for CtrlVaux6 register */
1062 .update_bank = 0x01,
1063 .update_reg = 0x56,
ae0a9a3e
LJ		 1064 .update_mask = 0x18,
1065 .update_val = 0x10,
1066 .update_val_idle = 0x18,
1067 .update_val_normal = 0x10,
547f384f
LJ		 1068 .voltage_bank = 0x01,
1069 .voltage_reg = 0x56,
1070 .voltage_mask = 0x07,
547f384f
LJ		 1071 },
1072 [AB8505_LDO_INTCORE] = {
1073 .desc = {
1074 .name = "LDO-INTCORE",
1075 .ops = &ab8500_regulator_volt_mode_ops,
1076 .type = REGULATOR_VOLTAGE,
0b946411 1077 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1078 .owner = THIS_MODULE,
1079 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1080 .volt_table = ldo_vintcore_voltages,
547f384f 1081 },
547f384f
LJ		 1082 .load_lp_uA = 5000,
1083 .update_bank = 0x03,
1084 .update_reg = 0x80,
1085 .update_mask = 0x44,
1086 .update_val = 0x04,
1087 .update_val_idle = 0x44,
1088 .update_val_normal = 0x04,
1089 .voltage_bank = 0x03,
1090 .voltage_reg = 0x80,
1091 .voltage_mask = 0x38,
547f384f
LJ		 1092 .voltage_shift = 3,
1093 },
1094
1095 /*
1096 * Fixed Voltage Regulators
1097 * name, fixed mV,
1098 * update bank, reg, mask, enable val
1099 */
1100 [AB8505_LDO_ADC] = {
1101 .desc = {
1102 .name = "LDO-ADC",
1103 .ops = &ab8500_regulator_mode_ops,
1104 .type = REGULATOR_VOLTAGE,
1105 .id = AB8505_LDO_ADC,
1106 .owner = THIS_MODULE,
1107 .n_voltages = 1,
b080c78a 1108 .volt_table = fixed_2000000_voltage,
a4d68468 1109 .enable_time = 10000,
547f384f 1110 },
547f384f
LJ		 1111 .load_lp_uA = 1000,
1112 .update_bank = 0x03,
1113 .update_reg = 0x80,
1114 .update_mask = 0x82,
1115 .update_val = 0x02,
1116 .update_val_idle = 0x82,
1117 .update_val_normal = 0x02,
1118 },
1119 [AB8505_LDO_USB] = {
1120 .desc = {
1121 .name = "LDO-USB",
1122 .ops = &ab8500_regulator_mode_ops,
1123 .type = REGULATOR_VOLTAGE,
0b946411 1124 .id = AB8505_LDO_USB,
547f384f
LJ		 1125 .owner = THIS_MODULE,
1126 .n_voltages = 1,
b080c78a 1127 .volt_table = fixed_3300000_voltage,
547f384f 1128 },
547f384f
LJ		 1129 .update_bank = 0x03,
1130 .update_reg = 0x82,
1131 .update_mask = 0x03,
1132 .update_val = 0x01,
1133 .update_val_idle = 0x03,
1134 .update_val_normal = 0x01,
1135 },
1136 [AB8505_LDO_AUDIO] = {
1137 .desc = {
1138 .name = "LDO-AUDIO",
8a3b1b87 1139 .ops = &ab8500_regulator_volt_ops,
547f384f 1140 .type = REGULATOR_VOLTAGE,
0b946411 1141 .id = AB8505_LDO_AUDIO,
547f384f 1142 .owner = THIS_MODULE,
8a3b1b87
LJ		 1143 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1144 .volt_table = ldo_vaudio_voltages,
547f384f 1145 },
547f384f
LJ		 1146 .update_bank = 0x03,
1147 .update_reg = 0x83,
1148 .update_mask = 0x02,
1149 .update_val = 0x02,
8a3b1b87
LJ		 1150 .voltage_bank = 0x01,
1151 .voltage_reg = 0x57,
1152 .voltage_mask = 0x7,
1153 .voltage_shift = 4,
547f384f
LJ		 1154 },
1155 [AB8505_LDO_ANAMIC1] = {
1156 .desc = {
1157 .name = "LDO-ANAMIC1",
3fe52289 1158 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1159 .type = REGULATOR_VOLTAGE,
0b946411 1160 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1161 .owner = THIS_MODULE,
1162 .n_voltages = 1,
b080c78a 1163 .volt_table = fixed_2050000_voltage,
547f384f 1164 },
4c84b4dd 1165 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1166 .update_bank = 0x03,
1167 .update_reg = 0x83,
1168 .update_mask = 0x08,
1169 .update_val = 0x08,
3fe52289
LJ		 1170 .mode_bank = 0x01,
1171 .mode_reg = 0x54,
1172 .mode_mask = 0x04,
1173 .mode_val_idle = 0x04,
1174 .mode_val_normal = 0x00,
547f384f
LJ		 1175 },
1176 [AB8505_LDO_ANAMIC2] = {
1177 .desc = {
1178 .name = "LDO-ANAMIC2",
3fe52289 1179 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1180 .type = REGULATOR_VOLTAGE,
0b946411 1181 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1182 .owner = THIS_MODULE,
1183 .n_voltages = 1,
b080c78a 1184 .volt_table = fixed_2050000_voltage,
547f384f 1185 },
3fe52289 1186 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1187 .update_bank = 0x03,
1188 .update_reg = 0x83,
1189 .update_mask = 0x10,
1190 .update_val = 0x10,
3fe52289
LJ		 1191 .mode_bank = 0x01,
1192 .mode_reg = 0x54,
1193 .mode_mask = 0x04,
1194 .mode_val_idle = 0x04,
1195 .mode_val_normal = 0x00,
547f384f
LJ		 1196 },
1197 [AB8505_LDO_AUX8] = {
1198 .desc = {
1199 .name = "LDO-AUX8",
1200 .ops = &ab8500_regulator_ops,
1201 .type = REGULATOR_VOLTAGE,
1202 .id = AB8505_LDO_AUX8,
1203 .owner = THIS_MODULE,
1204 .n_voltages = 1,
b080c78a 1205 .volt_table = fixed_1800000_voltage,
547f384f 1206 },
547f384f
LJ		 1207 .update_bank = 0x03,
1208 .update_reg = 0x83,
1209 .update_mask = 0x04,
1210 .update_val = 0x04,
1211 },
1212 /*
1213 * Regulators with fixed voltage and normal/idle modes
1214 */
1215 [AB8505_LDO_ANA] = {
1216 .desc = {
1217 .name = "LDO-ANA",
8a3b1b87 1218 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1219 .type = REGULATOR_VOLTAGE,
0b946411 1220 .id = AB8505_LDO_ANA,
547f384f 1221 .owner = THIS_MODULE,
8a3b1b87
LJ		 1222 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1223 .volt_table = ldo_vana_voltages,
547f384f 1224 },
547f384f
LJ		 1225 .load_lp_uA = 1000,
1226 .update_bank = 0x04,
1227 .update_reg = 0x06,
1228 .update_mask = 0x0c,
1229 .update_val = 0x04,
1230 .update_val_idle = 0x0c,
1231 .update_val_normal = 0x04,
8a3b1b87
LJ		 1232 .voltage_bank = 0x04,
1233 .voltage_reg = 0x29,
1234 .voltage_mask = 0x7,
547f384f
LJ		 1235 },
1236};
1237
8e6a8d7d
LJ		 1238/* AB9540 regulator information */
1239static struct ab8500_regulator_info
1240 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1241 /*
1242 * Variable Voltage Regulators
1243 * name, min mV, max mV,
1244 * update bank, reg, mask, enable val
d3193103 1245 * volt bank, reg, mask
8e6a8d7d
LJ		 1246 */
1247 [AB9540_LDO_AUX1] = {
1248 .desc = {
1249 .name = "LDO-AUX1",
1250 .ops = &ab8500_regulator_volt_mode_ops,
1251 .type = REGULATOR_VOLTAGE,
0b946411 1252 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1253 .owner = THIS_MODULE,
1254 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1255 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1256 },
8e6a8d7d
LJ		 1257 .load_lp_uA = 5000,
1258 .update_bank = 0x04,
1259 .update_reg = 0x09,
1260 .update_mask = 0x03,
1261 .update_val = 0x01,
1262 .update_val_idle = 0x03,
1263 .update_val_normal = 0x01,
1264 .voltage_bank = 0x04,
1265 .voltage_reg = 0x1f,
1266 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1267 },
1268 [AB9540_LDO_AUX2] = {
1269 .desc = {
1270 .name = "LDO-AUX2",
1271 .ops = &ab8500_regulator_volt_mode_ops,
1272 .type = REGULATOR_VOLTAGE,
0b946411 1273 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1274 .owner = THIS_MODULE,
1275 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1276 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1277 },
8e6a8d7d
LJ		 1278 .load_lp_uA = 5000,
1279 .update_bank = 0x04,
1280 .update_reg = 0x09,
1281 .update_mask = 0x0c,
1282 .update_val = 0x04,
1283 .update_val_idle = 0x0c,
1284 .update_val_normal = 0x04,
1285 .voltage_bank = 0x04,
1286 .voltage_reg = 0x20,
1287 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1288 },
1289 [AB9540_LDO_AUX3] = {
1290 .desc = {
1291 .name = "LDO-AUX3",
1292 .ops = &ab8500_regulator_volt_mode_ops,
1293 .type = REGULATOR_VOLTAGE,
0b946411 1294 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1295 .owner = THIS_MODULE,
1296 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1297 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1298 },
8e6a8d7d
LJ		 1299 .load_lp_uA = 5000,
1300 .update_bank = 0x04,
1301 .update_reg = 0x0a,
1302 .update_mask = 0x03,
1303 .update_val = 0x01,
1304 .update_val_idle = 0x03,
1305 .update_val_normal = 0x01,
1306 .voltage_bank = 0x04,
1307 .voltage_reg = 0x21,
1308 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1309 },
1310 [AB9540_LDO_AUX4] = {
1311 .desc = {
1312 .name = "LDO-AUX4",
1313 .ops = &ab8500_regulator_volt_mode_ops,
1314 .type = REGULATOR_VOLTAGE,
1315 .id = AB9540_LDO_AUX4,
1316 .owner = THIS_MODULE,
1317 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1318 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1319 },
8e6a8d7d
LJ		 1320 .load_lp_uA = 5000,
1321 /* values for Vaux4Regu register */
1322 .update_bank = 0x04,
1323 .update_reg = 0x2e,
1324 .update_mask = 0x03,
1325 .update_val = 0x01,
1326 .update_val_idle = 0x03,
1327 .update_val_normal = 0x01,
1328 /* values for Vaux4SEL register */
1329 .voltage_bank = 0x04,
1330 .voltage_reg = 0x2f,
1331 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1332 },
1333 [AB9540_LDO_INTCORE] = {
1334 .desc = {
1335 .name = "LDO-INTCORE",
1336 .ops = &ab8500_regulator_volt_mode_ops,
1337 .type = REGULATOR_VOLTAGE,
0b946411 1338 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1339 .owner = THIS_MODULE,
1340 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1341 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1342 },
8e6a8d7d
LJ		 1343 .load_lp_uA = 5000,
1344 .update_bank = 0x03,
1345 .update_reg = 0x80,
1346 .update_mask = 0x44,
1347 .update_val = 0x44,
1348 .update_val_idle = 0x44,
1349 .update_val_normal = 0x04,
1350 .voltage_bank = 0x03,
1351 .voltage_reg = 0x80,
1352 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1353 .voltage_shift = 3,
1354 },
6909b452 1355
8e6a8d7d
LJ		 1356 /*
1357 * Fixed Voltage Regulators
1358 * name, fixed mV,
1359 * update bank, reg, mask, enable val
1360 */
1361 [AB9540_LDO_TVOUT] = {
1362 .desc = {
1363 .name = "LDO-TVOUT",
1364 .ops = &ab8500_regulator_mode_ops,
1365 .type = REGULATOR_VOLTAGE,
0b946411 1366 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1367 .owner = THIS_MODULE,
1368 .n_voltages = 1,
b080c78a 1369 .volt_table = fixed_2000000_voltage,
a4d68468 1370 .enable_time = 10000,
8e6a8d7d 1371 },
8e6a8d7d
LJ		 1372 .load_lp_uA = 1000,
1373 .update_bank = 0x03,
1374 .update_reg = 0x80,
1375 .update_mask = 0x82,
1376 .update_val = 0x02,
1377 .update_val_idle = 0x82,
1378 .update_val_normal = 0x02,
1379 },
1380 [AB9540_LDO_USB] = {
1381 .desc = {
1382 .name = "LDO-USB",
1383 .ops = &ab8500_regulator_ops,
1384 .type = REGULATOR_VOLTAGE,
1385 .id = AB9540_LDO_USB,
1386 .owner = THIS_MODULE,
1387 .n_voltages = 1,
b080c78a 1388 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1389 },
8e6a8d7d
LJ		 1390 .update_bank = 0x03,
1391 .update_reg = 0x82,
1392 .update_mask = 0x03,
1393 .update_val = 0x01,
1394 .update_val_idle = 0x03,
1395 .update_val_normal = 0x01,
1396 },
1397 [AB9540_LDO_AUDIO] = {
1398 .desc = {
1399 .name = "LDO-AUDIO",
1400 .ops = &ab8500_regulator_ops,
1401 .type = REGULATOR_VOLTAGE,
0b946411 1402 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1403 .owner = THIS_MODULE,
1404 .n_voltages = 1,
b080c78a 1405 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1406 },
8e6a8d7d
LJ		 1407 .update_bank = 0x03,
1408 .update_reg = 0x83,
1409 .update_mask = 0x02,
1410 .update_val = 0x02,
1411 },
1412 [AB9540_LDO_ANAMIC1] = {
1413 .desc = {
1414 .name = "LDO-ANAMIC1",
1415 .ops = &ab8500_regulator_ops,
1416 .type = REGULATOR_VOLTAGE,
0b946411 1417 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1418 .owner = THIS_MODULE,
1419 .n_voltages = 1,
b080c78a 1420 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1421 },
8e6a8d7d
LJ		 1422 .update_bank = 0x03,
1423 .update_reg = 0x83,
1424 .update_mask = 0x08,
1425 .update_val = 0x08,
1426 },
1427 [AB9540_LDO_ANAMIC2] = {
1428 .desc = {
1429 .name = "LDO-ANAMIC2",
1430 .ops = &ab8500_regulator_ops,
1431 .type = REGULATOR_VOLTAGE,
0b946411 1432 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1433 .owner = THIS_MODULE,
1434 .n_voltages = 1,
b080c78a 1435 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1436 },
8e6a8d7d
LJ		 1437 .update_bank = 0x03,
1438 .update_reg = 0x83,
1439 .update_mask = 0x10,
1440 .update_val = 0x10,
1441 },
1442 [AB9540_LDO_DMIC] = {
1443 .desc = {
1444 .name = "LDO-DMIC",
1445 .ops = &ab8500_regulator_ops,
1446 .type = REGULATOR_VOLTAGE,
0b946411 1447 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1448 .owner = THIS_MODULE,
1449 .n_voltages = 1,
b080c78a 1450 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1451 },
8e6a8d7d
LJ		 1452 .update_bank = 0x03,
1453 .update_reg = 0x83,
1454 .update_mask = 0x04,
1455 .update_val = 0x04,
1456 },
1457
1458 /*
1459 * Regulators with fixed voltage and normal/idle modes
1460 */
1461 [AB9540_LDO_ANA] = {
1462 .desc = {
1463 .name = "LDO-ANA",
1464 .ops = &ab8500_regulator_mode_ops,
1465 .type = REGULATOR_VOLTAGE,
0b946411 1466 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1467 .owner = THIS_MODULE,
1468 .n_voltages = 1,
b080c78a 1469 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1470 },
8e6a8d7d
LJ		 1471 .load_lp_uA = 1000,
1472 .update_bank = 0x04,
1473 .update_reg = 0x06,
1474 .update_mask = 0x0c,
1475 .update_val = 0x08,
1476 .update_val_idle = 0x0c,
1477 .update_val_normal = 0x08,
1478 },
c789ca20
SI		 1479};
1480
ae0a9a3e
LJ		 1481/* AB8540 regulator information */
1482static struct ab8500_regulator_info
1483 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1484 /*
1485 * Variable Voltage Regulators
1486 * name, min mV, max mV,
1487 * update bank, reg, mask, enable val
d3193103 1488 * volt bank, reg, mask
ae0a9a3e
LJ		 1489 */
1490 [AB8540_LDO_AUX1] = {
1491 .desc = {
1492 .name = "LDO-AUX1",
1493 .ops = &ab8500_regulator_volt_mode_ops,
1494 .type = REGULATOR_VOLTAGE,
0b946411 1495 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1496 .owner = THIS_MODULE,
1497 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1498 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1499 },
1500 .load_lp_uA = 5000,
1501 .update_bank = 0x04,
1502 .update_reg = 0x09,
1503 .update_mask = 0x03,
1504 .update_val = 0x01,
1505 .update_val_idle = 0x03,
1506 .update_val_normal = 0x01,
1507 .voltage_bank = 0x04,
1508 .voltage_reg = 0x1f,
1509 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1510 },
1511 [AB8540_LDO_AUX2] = {
1512 .desc = {
1513 .name = "LDO-AUX2",
1514 .ops = &ab8500_regulator_volt_mode_ops,
1515 .type = REGULATOR_VOLTAGE,
0b946411 1516 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1517 .owner = THIS_MODULE,
1518 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1519 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1520 },
1521 .load_lp_uA = 5000,
1522 .update_bank = 0x04,
1523 .update_reg = 0x09,
1524 .update_mask = 0x0c,
1525 .update_val = 0x04,
1526 .update_val_idle = 0x0c,
1527 .update_val_normal = 0x04,
1528 .voltage_bank = 0x04,
1529 .voltage_reg = 0x20,
1530 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1531 },
1532 [AB8540_LDO_AUX3] = {
1533 .desc = {
1534 .name = "LDO-AUX3",
d7607baf 1535 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1536 .type = REGULATOR_VOLTAGE,
0b946411 1537 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1538 .owner = THIS_MODULE,
1539 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1540 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1541 },
1542 .load_lp_uA = 5000,
1543 .update_bank = 0x04,
1544 .update_reg = 0x0a,
1545 .update_mask = 0x03,
1546 .update_val = 0x01,
1547 .update_val_idle = 0x03,
1548 .update_val_normal = 0x01,
1549 .voltage_bank = 0x04,
1550 .voltage_reg = 0x21,
1551 .voltage_mask = 0x07,
d7607baf
LJ		 1552 .expand_register = {
1553 .voltage_limit = 8,
1554 .voltage_bank = 0x04,
1555 .voltage_reg = 0x01,
1556 .voltage_mask = 0x10,
1557 .voltage_shift = 1,
1558 }
ae0a9a3e
LJ		 1559 },
1560 [AB8540_LDO_AUX4] = {
1561 .desc = {
1562 .name = "LDO-AUX4",
1563 .ops = &ab8500_regulator_volt_mode_ops,
1564 .type = REGULATOR_VOLTAGE,
0b946411 1565 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1566 .owner = THIS_MODULE,
1567 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1568 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1569 },
1570 .load_lp_uA = 5000,
1571 /* values for Vaux4Regu register */
1572 .update_bank = 0x04,
1573 .update_reg = 0x2e,
1574 .update_mask = 0x03,
1575 .update_val = 0x01,
1576 .update_val_idle = 0x03,
1577 .update_val_normal = 0x01,
1578 /* values for Vaux4SEL register */
1579 .voltage_bank = 0x04,
1580 .voltage_reg = 0x2f,
1581 .voltage_mask = 0x0f,
ae0a9a3e 1582 },
684d5ce4
ZH		 1583 [AB8540_LDO_AUX5] = {
1584 .desc = {
1585 .name = "LDO-AUX5",
1586 .ops = &ab8500_regulator_volt_mode_ops,
1587 .type = REGULATOR_VOLTAGE,
1588 .id = AB8540_LDO_AUX5,
1589 .owner = THIS_MODULE,
1590 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1591 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1592 },
1593 .load_lp_uA = 20000,
1594 /* values for Vaux5Regu register */
1595 .update_bank = 0x04,
1596 .update_reg = 0x32,
1597 .update_mask = 0x03,
1598 .update_val = 0x01,
1599 .update_val_idle = 0x03,
1600 .update_val_normal = 0x01,
1601 /* values for Vaux5SEL register */
1602 .voltage_bank = 0x04,
1603 .voltage_reg = 0x33,
1604 .voltage_mask = 0x3f,
684d5ce4
ZH		 1605 },
1606 [AB8540_LDO_AUX6] = {
1607 .desc = {
1608 .name = "LDO-AUX6",
1609 .ops = &ab8500_regulator_volt_mode_ops,
1610 .type = REGULATOR_VOLTAGE,
1611 .id = AB8540_LDO_AUX6,
1612 .owner = THIS_MODULE,
1613 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1614 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1615 },
1616 .load_lp_uA = 20000,
1617 /* values for Vaux6Regu register */
1618 .update_bank = 0x04,
1619 .update_reg = 0x35,
1620 .update_mask = 0x03,
1621 .update_val = 0x01,
1622 .update_val_idle = 0x03,
1623 .update_val_normal = 0x01,
1624 /* values for Vaux6SEL register */
1625 .voltage_bank = 0x04,
1626 .voltage_reg = 0x36,
1627 .voltage_mask = 0x3f,
684d5ce4 1628 },
ae0a9a3e
LJ		 1629 [AB8540_LDO_INTCORE] = {
1630 .desc = {
1631 .name = "LDO-INTCORE",
1632 .ops = &ab8500_regulator_volt_mode_ops,
1633 .type = REGULATOR_VOLTAGE,
0b946411 1634 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1635 .owner = THIS_MODULE,
1636 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1637 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1638 },
1639 .load_lp_uA = 5000,
1640 .update_bank = 0x03,
1641 .update_reg = 0x80,
1642 .update_mask = 0x44,
1643 .update_val = 0x44,
1644 .update_val_idle = 0x44,
1645 .update_val_normal = 0x04,
1646 .voltage_bank = 0x03,
1647 .voltage_reg = 0x80,
1648 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1649 .voltage_shift = 3,
1650 },
1651
1652 /*
1653 * Fixed Voltage Regulators
1654 * name, fixed mV,
1655 * update bank, reg, mask, enable val
1656 */
1657 [AB8540_LDO_TVOUT] = {
1658 .desc = {
1659 .name = "LDO-TVOUT",
1660 .ops = &ab8500_regulator_mode_ops,
1661 .type = REGULATOR_VOLTAGE,
0b946411 1662 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1663 .owner = THIS_MODULE,
1664 .n_voltages = 1,
a4d68468 1665 .enable_time = 10000,
ae0a9a3e 1666 },
ae0a9a3e
LJ		 1667 .load_lp_uA = 1000,
1668 .update_bank = 0x03,
1669 .update_reg = 0x80,
1670 .update_mask = 0x82,
1671 .update_val = 0x02,
1672 .update_val_idle = 0x82,
1673 .update_val_normal = 0x02,
1674 },
1675 [AB8540_LDO_AUDIO] = {
1676 .desc = {
1677 .name = "LDO-AUDIO",
1678 .ops = &ab8500_regulator_ops,
1679 .type = REGULATOR_VOLTAGE,
0b946411 1680 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1681 .owner = THIS_MODULE,
1682 .n_voltages = 1,
b080c78a 1683 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1684 },
1685 .update_bank = 0x03,
1686 .update_reg = 0x83,
1687 .update_mask = 0x02,
1688 .update_val = 0x02,
1689 },
1690 [AB8540_LDO_ANAMIC1] = {
1691 .desc = {
1692 .name = "LDO-ANAMIC1",
4c84b4dd 1693 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1694 .type = REGULATOR_VOLTAGE,
0b946411 1695 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1696 .owner = THIS_MODULE,
1697 .n_voltages = 1,
b080c78a 1698 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1699 },
4c84b4dd 1700 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1701 .update_bank = 0x03,
1702 .update_reg = 0x83,
1703 .update_mask = 0x08,
1704 .update_val = 0x08,
4c84b4dd
LJ		 1705 .mode_bank = 0x03,
1706 .mode_reg = 0x83,
1707 .mode_mask = 0x20,
1708 .mode_val_idle = 0x20,
1709 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1710 },
1711 [AB8540_LDO_ANAMIC2] = {
1712 .desc = {
1713 .name = "LDO-ANAMIC2",
4c84b4dd 1714 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1715 .type = REGULATOR_VOLTAGE,
0b946411 1716 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1717 .owner = THIS_MODULE,
1718 .n_voltages = 1,
b080c78a 1719 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1720 },
4c84b4dd 1721 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1722 .update_bank = 0x03,
1723 .update_reg = 0x83,
1724 .update_mask = 0x10,
1725 .update_val = 0x10,
4c84b4dd
LJ		 1726 .mode_bank = 0x03,
1727 .mode_reg = 0x83,
1728 .mode_mask = 0x20,
1729 .mode_val_idle = 0x20,
1730 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1731 },
1732 [AB8540_LDO_DMIC] = {
1733 .desc = {
1734 .name = "LDO-DMIC",
4c84b4dd 1735 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1736 .type = REGULATOR_VOLTAGE,
0b946411 1737 .id = AB8540_LDO_DMIC,
ae0a9a3e 1738 .owner = THIS_MODULE,
4c84b4dd 1739 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1740 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1741 },
4c84b4dd 1742 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1743 .update_bank = 0x03,
1744 .update_reg = 0x83,
1745 .update_mask = 0x04,
1746 .update_val = 0x04,
4c84b4dd
LJ		 1747 .voltage_bank = 0x03,
1748 .voltage_reg = 0x83,
1749 .voltage_mask = 0xc0,
ae0a9a3e
LJ		 1750 },
1751
1752 /*
1753 * Regulators with fixed voltage and normal/idle modes
1754 */
1755 [AB8540_LDO_ANA] = {
1756 .desc = {
1757 .name = "LDO-ANA",
1758 .ops = &ab8500_regulator_mode_ops,
1759 .type = REGULATOR_VOLTAGE,
0b946411 1760 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1761 .owner = THIS_MODULE,
1762 .n_voltages = 1,
b080c78a 1763 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1764 },
1765 .load_lp_uA = 1000,
1766 .update_bank = 0x04,
1767 .update_reg = 0x06,
1768 .update_mask = 0x0c,
1769 .update_val = 0x04,
1770 .update_val_idle = 0x0c,
1771 .update_val_normal = 0x04,
1772 },
1773 [AB8540_LDO_SDIO] = {
1774 .desc = {
1775 .name = "LDO-SDIO",
1776 .ops = &ab8500_regulator_volt_mode_ops,
1777 .type = REGULATOR_VOLTAGE,
1778 .id = AB8540_LDO_SDIO,
1779 .owner = THIS_MODULE,
62ab4111
LJ		 1780 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1781 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1782 },
ae0a9a3e
LJ		 1783 .load_lp_uA = 5000,
1784 .update_bank = 0x03,
1785 .update_reg = 0x88,
1786 .update_mask = 0x30,
1787 .update_val = 0x10,
1788 .update_val_idle = 0x30,
1789 .update_val_normal = 0x10,
1790 .voltage_bank = 0x03,
1791 .voltage_reg = 0x88,
1792 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1793 },
1794};
1795
3fe52289
LJ		 1796static struct ab8500_shared_mode ldo_anamic1_shared = {
1797 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1798};
1799
1800static struct ab8500_shared_mode ldo_anamic2_shared = {
1801 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1802};
1803
4c84b4dd
LJ		 1804static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1805 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1806};
1807
1808static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1809 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1810};
1811
79568b94
BJ		 1812struct ab8500_reg_init {
1813 u8 bank;
1814 u8 addr;
1815 u8 mask;
1816};
1817
1818#define REG_INIT(_id, _bank, _addr, _mask) \
1819 [_id] = { \
1820 .bank = _bank, \
1821 .addr = _addr, \
1822 .mask = _mask, \
1823 }
1824
8e6a8d7d 1825/* AB8500 register init */
79568b94
BJ		 1826static struct ab8500_reg_init ab8500_reg_init[] = {
1827 /*
33bc8f46 1828 * 0x30, VanaRequestCtrl
79568b94
BJ		 1829 * 0xc0, VextSupply1RequestCtrl
1830 */
43a5911b 1831 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1832 /*
1833 * 0x03, VextSupply2RequestCtrl
1834 * 0x0c, VextSupply3RequestCtrl
1835 * 0x30, Vaux1RequestCtrl
1836 * 0xc0, Vaux2RequestCtrl
1837 */
1838 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1839 /*
1840 * 0x03, Vaux3RequestCtrl
1841 * 0x04, SwHPReq
1842 */
1843 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1844 /*
1845 * 0x08, VanaSysClkReq1HPValid
1846 * 0x20, Vaux1SysClkReq1HPValid
1847 * 0x40, Vaux2SysClkReq1HPValid
1848 * 0x80, Vaux3SysClkReq1HPValid
1849 */
43a5911b 1850 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1851 /*
1852 * 0x10, VextSupply1SysClkReq1HPValid
1853 * 0x20, VextSupply2SysClkReq1HPValid
1854 * 0x40, VextSupply3SysClkReq1HPValid
1855 */
43a5911b 1856 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1857 /*
1858 * 0x08, VanaHwHPReq1Valid
1859 * 0x20, Vaux1HwHPReq1Valid
1860 * 0x40, Vaux2HwHPReq1Valid
1861 * 0x80, Vaux3HwHPReq1Valid
1862 */
43a5911b 1863 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1864 /*
1865 * 0x01, VextSupply1HwHPReq1Valid
1866 * 0x02, VextSupply2HwHPReq1Valid
1867 * 0x04, VextSupply3HwHPReq1Valid
1868 */
43a5911b 1869 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1870 /*
1871 * 0x08, VanaHwHPReq2Valid
1872 * 0x20, Vaux1HwHPReq2Valid
1873 * 0x40, Vaux2HwHPReq2Valid
1874 * 0x80, Vaux3HwHPReq2Valid
1875 */
43a5911b 1876 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1877 /*
1878 * 0x01, VextSupply1HwHPReq2Valid
1879 * 0x02, VextSupply2HwHPReq2Valid
1880 * 0x04, VextSupply3HwHPReq2Valid
1881 */
43a5911b 1882 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1883 /*
1884 * 0x20, VanaSwHPReqValid
1885 * 0x80, Vaux1SwHPReqValid
1886 */
43a5911b 1887 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1888 /*
1889 * 0x01, Vaux2SwHPReqValid
1890 * 0x02, Vaux3SwHPReqValid
1891 * 0x04, VextSupply1SwHPReqValid
1892 * 0x08, VextSupply2SwHPReqValid
1893 * 0x10, VextSupply3SwHPReqValid
1894 */
43a5911b 1895 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1896 /*
1897 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1898 * 0x04, SysClkReq3Valid1
1899 * 0x08, SysClkReq4Valid1
1900 * 0x10, SysClkReq5Valid1
1901 * 0x20, SysClkReq6Valid1
1902 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1903 * 0x80, SysClkReq8Valid1
1904 */
1905 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1906 /*
1907 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1908 * 0x04, SysClkReq3Valid2
1909 * 0x08, SysClkReq4Valid2
1910 * 0x10, SysClkReq5Valid2
1911 * 0x20, SysClkReq6Valid2
1912 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1913 * 0x80, SysClkReq8Valid2
1914 */
1915 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1916 /*
1917 * 0x02, VTVoutEna
1918 * 0x04, Vintcore12Ena
1919 * 0x38, Vintcore12Sel
1920 * 0x40, Vintcore12LP
1921 * 0x80, VTVoutLP
1922 */
1923 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1924 /*
1925 * 0x02, VaudioEna
1926 * 0x04, VdmicEna
1927 * 0x08, Vamic1Ena
1928 * 0x10, Vamic2Ena
1929 */
1930 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1931 /*
1932 * 0x01, Vamic1_dzout
1933 * 0x02, Vamic2_dzout
1934 */
1935 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1936 /*
43a5911b 1937 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1938 * 0x0c, VanaRegu
79568b94
BJ		 1939 */
1940 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1941 /*
1942 * 0x01, VrefDDREna
1943 * 0x02, VrefDDRSleepMode
1944 */
1945 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1946 /*
1947 * 0x03, VextSupply1Regu
1948 * 0x0c, VextSupply2Regu
1949 * 0x30, VextSupply3Regu
1950 * 0x40, ExtSupply2Bypass
1951 * 0x80, ExtSupply3Bypass
1952 */
1953 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1954 /*
1955 * 0x03, Vaux1Regu
1956 * 0x0c, Vaux2Regu
1957 */
1958 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1959 /*
1960 * 0x03, Vaux3Regu
1961 */
43a5911b 1962 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1963 /*
1964 * 0x0f, Vaux1Sel
1965 */
1966 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1967 /*
1968 * 0x0f, Vaux2Sel
1969 */
1970 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1971 /*
1972 * 0x07, Vaux3Sel
1973 */
43a5911b 1974 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1975 /*
1976 * 0x01, VextSupply12LP
1977 */
1978 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1979 /*
1980 * 0x04, Vaux1Disch
1981 * 0x08, Vaux2Disch
1982 * 0x10, Vaux3Disch
1983 * 0x20, Vintcore12Disch
1984 * 0x40, VTVoutDisch
1985 * 0x80, VaudioDisch
1986 */
43a5911b 1987 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1988 /*
1989 * 0x02, VanaDisch
1990 * 0x04, VdmicPullDownEna
1991 * 0x10, VdmicDisch
1992 */
43a5911b 1993 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1994};
1995
547f384f
LJ		 1996/* AB8505 register init */
1997static struct ab8500_reg_init ab8505_reg_init[] = {
1998 /*
1999 * 0x03, VarmRequestCtrl
2000 * 0x0c, VsmpsCRequestCtrl
2001 * 0x30, VsmpsARequestCtrl
2002 * 0xc0, VsmpsBRequestCtrl
2003 */
2004 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2005 /*
2006 * 0x03, VsafeRequestCtrl
2007 * 0x0c, VpllRequestCtrl
2008 * 0x30, VanaRequestCtrl
2009 */
2010 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
2011 /*
2012 * 0x30, Vaux1RequestCtrl
2013 * 0xc0, Vaux2RequestCtrl
2014 */
2015 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
2016 /*
2017 * 0x03, Vaux3RequestCtrl
2018 * 0x04, SwHPReq
2019 */
2020 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2021 /*
2022 * 0x01, VsmpsASysClkReq1HPValid
2023 * 0x02, VsmpsBSysClkReq1HPValid
2024 * 0x04, VsafeSysClkReq1HPValid
2025 * 0x08, VanaSysClkReq1HPValid
2026 * 0x10, VpllSysClkReq1HPValid
2027 * 0x20, Vaux1SysClkReq1HPValid
2028 * 0x40, Vaux2SysClkReq1HPValid
2029 * 0x80, Vaux3SysClkReq1HPValid
2030 */
2031 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2032 /*
2033 * 0x01, VsmpsCSysClkReq1HPValid
2034 * 0x02, VarmSysClkReq1HPValid
2035 * 0x04, VbbSysClkReq1HPValid
2036 * 0x08, VsmpsMSysClkReq1HPValid
2037 */
2038 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2039 /*
2040 * 0x01, VsmpsAHwHPReq1Valid
2041 * 0x02, VsmpsBHwHPReq1Valid
2042 * 0x04, VsafeHwHPReq1Valid
2043 * 0x08, VanaHwHPReq1Valid
2044 * 0x10, VpllHwHPReq1Valid
2045 * 0x20, Vaux1HwHPReq1Valid
2046 * 0x40, Vaux2HwHPReq1Valid
2047 * 0x80, Vaux3HwHPReq1Valid
2048 */
2049 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2050 /*
2051 * 0x08, VsmpsMHwHPReq1Valid
2052 */
2053 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2054 /*
2055 * 0x01, VsmpsAHwHPReq2Valid
2056 * 0x02, VsmpsBHwHPReq2Valid
2057 * 0x04, VsafeHwHPReq2Valid
2058 * 0x08, VanaHwHPReq2Valid
2059 * 0x10, VpllHwHPReq2Valid
2060 * 0x20, Vaux1HwHPReq2Valid
2061 * 0x40, Vaux2HwHPReq2Valid
2062 * 0x80, Vaux3HwHPReq2Valid
2063 */
2064 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2065 /*
2066 * 0x08, VsmpsMHwHPReq2Valid
2067 */
2068 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2069 /*
2070 * 0x01, VsmpsCSwHPReqValid
2071 * 0x02, VarmSwHPReqValid
2072 * 0x04, VsmpsASwHPReqValid
2073 * 0x08, VsmpsBSwHPReqValid
2074 * 0x10, VsafeSwHPReqValid
2075 * 0x20, VanaSwHPReqValid
2076 * 0x40, VpllSwHPReqValid
2077 * 0x80, Vaux1SwHPReqValid
2078 */
2079 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2080 /*
2081 * 0x01, Vaux2SwHPReqValid
2082 * 0x02, Vaux3SwHPReqValid
2083 * 0x20, VsmpsMSwHPReqValid
2084 */
2085 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2086 /*
2087 * 0x02, SysClkReq2Valid1
2088 * 0x04, SysClkReq3Valid1
2089 * 0x08, SysClkReq4Valid1
2090 */
2091 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2092 /*
2093 * 0x02, SysClkReq2Valid2
2094 * 0x04, SysClkReq3Valid2
2095 * 0x08, SysClkReq4Valid2
2096 */
2097 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2098 /*
2099 * 0x01, Vaux4SwHPReqValid
2100 * 0x02, Vaux4HwHPReq2Valid
2101 * 0x04, Vaux4HwHPReq1Valid
2102 * 0x08, Vaux4SysClkReq1HPValid
2103 */
2104 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2105 /*
2106 * 0x02, VadcEna
2107 * 0x04, VintCore12Ena
2108 * 0x38, VintCore12Sel
2109 * 0x40, VintCore12LP
2110 * 0x80, VadcLP
2111 */
2112 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2113 /*
2114 * 0x02, VaudioEna
2115 * 0x04, VdmicEna
2116 * 0x08, Vamic1Ena
2117 * 0x10, Vamic2Ena
2118 */
2119 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2120 /*
2121 * 0x01, Vamic1_dzout
2122 * 0x02, Vamic2_dzout
2123 */
2124 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2125 /*
2126 * 0x03, VsmpsARegu
2127 * 0x0c, VsmpsASelCtrl
2128 * 0x10, VsmpsAAutoMode
2129 * 0x20, VsmpsAPWMMode
2130 */
2131 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2132 /*
2133 * 0x03, VsmpsBRegu
2134 * 0x0c, VsmpsBSelCtrl
2135 * 0x10, VsmpsBAutoMode
2136 * 0x20, VsmpsBPWMMode
2137 */
2138 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2139 /*
2140 * 0x03, VsafeRegu
2141 * 0x0c, VsafeSelCtrl
2142 * 0x10, VsafeAutoMode
2143 * 0x20, VsafePWMMode
2144 */
2145 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2146 /*
2147 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2148 * 0x0c, VanaRegu
2149 */
2150 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2151 /*
2152 * 0x03, VextSupply1Regu
2153 * 0x0c, VextSupply2Regu
2154 * 0x30, VextSupply3Regu
2155 * 0x40, ExtSupply2Bypass
2156 * 0x80, ExtSupply3Bypass
2157 */
2158 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2159 /*
2160 * 0x03, Vaux1Regu
2161 * 0x0c, Vaux2Regu
2162 */
2163 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2164 /*
2165 * 0x0f, Vaux3Regu
2166 */
2167 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2168 /*
2169 * 0x3f, VsmpsASel1
2170 */
2171 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2172 /*
2173 * 0x3f, VsmpsASel2
2174 */
2175 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2176 /*
2177 * 0x3f, VsmpsASel3
2178 */
2179 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2180 /*
2181 * 0x3f, VsmpsBSel1
2182 */
2183 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2184 /*
2185 * 0x3f, VsmpsBSel2
2186 */
2187 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2188 /*
2189 * 0x3f, VsmpsBSel3
2190 */
2191 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2192 /*
2193 * 0x7f, VsafeSel1
2194 */
2195 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2196 /*
2197 * 0x3f, VsafeSel2
2198 */
2199 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2200 /*
2201 * 0x3f, VsafeSel3
2202 */
2203 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2204 /*
2205 * 0x0f, Vaux1Sel
2206 */
2207 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2208 /*
2209 * 0x0f, Vaux2Sel
2210 */
2211 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2212 /*
2213 * 0x07, Vaux3Sel
2214 * 0x30, VRF1Sel
2215 */
2216 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2217 /*
2218 * 0x03, Vaux4RequestCtrl
2219 */
2220 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2221 /*
2222 * 0x03, Vaux4Regu
2223 */
2224 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2225 /*
2226 * 0x0f, Vaux4Sel
2227 */
2228 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2229 /*
2230 * 0x04, Vaux1Disch
2231 * 0x08, Vaux2Disch
2232 * 0x10, Vaux3Disch
2233 * 0x20, Vintcore12Disch
2234 * 0x40, VTVoutDisch
2235 * 0x80, VaudioDisch
2236 */
2237 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2238 /*
2239 * 0x02, VanaDisch
2240 * 0x04, VdmicPullDownEna
2241 * 0x10, VdmicDisch
2242 */
2243 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2244 /*
2245 * 0x01, Vaux4Disch
2246 */
2247 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2248 /*
2249 * 0x07, Vaux5Sel
2250 * 0x08, Vaux5LP
2251 * 0x10, Vaux5Ena
2252 * 0x20, Vaux5Disch
2253 * 0x40, Vaux5DisSfst
2254 * 0x80, Vaux5DisPulld
2255 */
2256 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2257 /*
2258 * 0x07, Vaux6Sel
2259 * 0x08, Vaux6LP
2260 * 0x10, Vaux6Ena
2261 * 0x80, Vaux6DisPulld
2262 */
2263 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2264};
2265
8e6a8d7d
LJ		 2266/* AB9540 register init */
2267static struct ab8500_reg_init ab9540_reg_init[] = {
2268 /*
2269 * 0x03, VarmRequestCtrl
2270 * 0x0c, VapeRequestCtrl
2271 * 0x30, Vsmps1RequestCtrl
2272 * 0xc0, Vsmps2RequestCtrl
2273 */
2274 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2275 /*
2276 * 0x03, Vsmps3RequestCtrl
2277 * 0x0c, VpllRequestCtrl
2278 * 0x30, VanaRequestCtrl
2279 * 0xc0, VextSupply1RequestCtrl
2280 */
2281 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2282 /*
2283 * 0x03, VextSupply2RequestCtrl
2284 * 0x0c, VextSupply3RequestCtrl
2285 * 0x30, Vaux1RequestCtrl
2286 * 0xc0, Vaux2RequestCtrl
2287 */
2288 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2289 /*
2290 * 0x03, Vaux3RequestCtrl
2291 * 0x04, SwHPReq
2292 */
2293 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2294 /*
2295 * 0x01, Vsmps1SysClkReq1HPValid
2296 * 0x02, Vsmps2SysClkReq1HPValid
2297 * 0x04, Vsmps3SysClkReq1HPValid
2298 * 0x08, VanaSysClkReq1HPValid
2299 * 0x10, VpllSysClkReq1HPValid
2300 * 0x20, Vaux1SysClkReq1HPValid
2301 * 0x40, Vaux2SysClkReq1HPValid
2302 * 0x80, Vaux3SysClkReq1HPValid
2303 */
2304 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2305 /*
2306 * 0x01, VapeSysClkReq1HPValid
2307 * 0x02, VarmSysClkReq1HPValid
2308 * 0x04, VbbSysClkReq1HPValid
2309 * 0x08, VmodSysClkReq1HPValid
2310 * 0x10, VextSupply1SysClkReq1HPValid
2311 * 0x20, VextSupply2SysClkReq1HPValid
2312 * 0x40, VextSupply3SysClkReq1HPValid
2313 */
2314 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2315 /*
2316 * 0x01, Vsmps1HwHPReq1Valid
2317 * 0x02, Vsmps2HwHPReq1Valid
2318 * 0x04, Vsmps3HwHPReq1Valid
2319 * 0x08, VanaHwHPReq1Valid
2320 * 0x10, VpllHwHPReq1Valid
2321 * 0x20, Vaux1HwHPReq1Valid
2322 * 0x40, Vaux2HwHPReq1Valid
2323 * 0x80, Vaux3HwHPReq1Valid
2324 */
2325 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2326 /*
2327 * 0x01, VextSupply1HwHPReq1Valid
2328 * 0x02, VextSupply2HwHPReq1Valid
2329 * 0x04, VextSupply3HwHPReq1Valid
2330 * 0x08, VmodHwHPReq1Valid
2331 */
2332 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2333 /*
2334 * 0x01, Vsmps1HwHPReq2Valid
2335 * 0x02, Vsmps2HwHPReq2Valid
2336 * 0x03, Vsmps3HwHPReq2Valid
2337 * 0x08, VanaHwHPReq2Valid
2338 * 0x10, VpllHwHPReq2Valid
2339 * 0x20, Vaux1HwHPReq2Valid
2340 * 0x40, Vaux2HwHPReq2Valid
2341 * 0x80, Vaux3HwHPReq2Valid
2342 */
2343 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2344 /*
2345 * 0x01, VextSupply1HwHPReq2Valid
2346 * 0x02, VextSupply2HwHPReq2Valid
2347 * 0x04, VextSupply3HwHPReq2Valid
2348 * 0x08, VmodHwHPReq2Valid
2349 */
2350 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2351 /*
2352 * 0x01, VapeSwHPReqValid
2353 * 0x02, VarmSwHPReqValid
2354 * 0x04, Vsmps1SwHPReqValid
2355 * 0x08, Vsmps2SwHPReqValid
2356 * 0x10, Vsmps3SwHPReqValid
2357 * 0x20, VanaSwHPReqValid
2358 * 0x40, VpllSwHPReqValid
2359 * 0x80, Vaux1SwHPReqValid
2360 */
2361 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2362 /*
2363 * 0x01, Vaux2SwHPReqValid
2364 * 0x02, Vaux3SwHPReqValid
2365 * 0x04, VextSupply1SwHPReqValid
2366 * 0x08, VextSupply2SwHPReqValid
2367 * 0x10, VextSupply3SwHPReqValid
2368 * 0x20, VmodSwHPReqValid
2369 */
2370 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2371 /*
2372 * 0x02, SysClkReq2Valid1
2373 * ...
2374 * 0x80, SysClkReq8Valid1
2375 */
2376 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2377 /*
2378 * 0x02, SysClkReq2Valid2
2379 * ...
2380 * 0x80, SysClkReq8Valid2
2381 */
2382 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2383 /*
2384 * 0x01, Vaux4SwHPReqValid
2385 * 0x02, Vaux4HwHPReq2Valid
2386 * 0x04, Vaux4HwHPReq1Valid
2387 * 0x08, Vaux4SysClkReq1HPValid
2388 */
2389 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2390 /*
2391 * 0x02, VTVoutEna
2392 * 0x04, Vintcore12Ena
2393 * 0x38, Vintcore12Sel
2394 * 0x40, Vintcore12LP
2395 * 0x80, VTVoutLP
2396 */
2397 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2398 /*
2399 * 0x02, VaudioEna
2400 * 0x04, VdmicEna
2401 * 0x08, Vamic1Ena
2402 * 0x10, Vamic2Ena
2403 */
2404 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2405 /*
2406 * 0x01, Vamic1_dzout
2407 * 0x02, Vamic2_dzout
2408 */
2409 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2410 /*
2411 * 0x03, Vsmps1Regu
2412 * 0x0c, Vsmps1SelCtrl
2413 * 0x10, Vsmps1AutoMode
2414 * 0x20, Vsmps1PWMMode
2415 */
2416 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2417 /*
2418 * 0x03, Vsmps2Regu
2419 * 0x0c, Vsmps2SelCtrl
2420 * 0x10, Vsmps2AutoMode
2421 * 0x20, Vsmps2PWMMode
2422 */
2423 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2424 /*
2425 * 0x03, Vsmps3Regu
2426 * 0x0c, Vsmps3SelCtrl
2427 * NOTE! PRCMU register
2428 */
2429 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2430 /*
2431 * 0x03, VpllRegu
2432 * 0x0c, VanaRegu
2433 */
2434 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2435 /*
2436 * 0x03, VextSupply1Regu
2437 * 0x0c, VextSupply2Regu
2438 * 0x30, VextSupply3Regu
2439 * 0x40, ExtSupply2Bypass
2440 * 0x80, ExtSupply3Bypass
2441 */
2442 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2443 /*
2444 * 0x03, Vaux1Regu
2445 * 0x0c, Vaux2Regu
2446 */
2447 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2448 /*
2449 * 0x0c, Vrf1Regu
2450 * 0x03, Vaux3Regu
2451 */
2452 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2453 /*
2454 * 0x3f, Vsmps1Sel1
2455 */
2456 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2457 /*
2458 * 0x3f, Vsmps1Sel2
2459 */
2460 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2461 /*
2462 * 0x3f, Vsmps1Sel3
2463 */
2464 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2465 /*
2466 * 0x3f, Vsmps2Sel1
2467 */
2468 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2469 /*
2470 * 0x3f, Vsmps2Sel2
2471 */
2472 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2473 /*
2474 * 0x3f, Vsmps2Sel3
2475 */
2476 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2477 /*
2478 * 0x7f, Vsmps3Sel1
2479 * NOTE! PRCMU register
2480 */
2481 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2482 /*
2483 * 0x7f, Vsmps3Sel2
2484 * NOTE! PRCMU register
2485 */
2486 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2487 /*
2488 * 0x0f, Vaux1Sel
2489 */
2490 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2491 /*
2492 * 0x0f, Vaux2Sel
2493 */
2494 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2495 /*
2496 * 0x07, Vaux3Sel
2497 * 0x30, Vrf1Sel
2498 */
2499 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2500 /*
2501 * 0x01, VextSupply12LP
2502 */
2503 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2504 /*
2505 * 0x03, Vaux4RequestCtrl
2506 */
2507 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2508 /*
2509 * 0x03, Vaux4Regu
2510 */
2511 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2512 /*
2513 * 0x08, Vaux4Sel
2514 */
2515 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2516 /*
2517 * 0x01, VpllDisch
2518 * 0x02, Vrf1Disch
2519 * 0x04, Vaux1Disch
2520 * 0x08, Vaux2Disch
2521 * 0x10, Vaux3Disch
2522 * 0x20, Vintcore12Disch
2523 * 0x40, VTVoutDisch
2524 * 0x80, VaudioDisch
2525 */
2526 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2527 /*
2528 * 0x01, VsimDisch
2529 * 0x02, VanaDisch
2530 * 0x04, VdmicPullDownEna
2531 * 0x08, VpllPullDownEna
2532 * 0x10, VdmicDisch
2533 */
2534 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2535 /*
2536 * 0x01, Vaux4Disch
2537 */
2538 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2539};
2540
ae0a9a3e
LJ		 2541/* AB8540 register init */
2542static struct ab8500_reg_init ab8540_reg_init[] = {
2543 /*
2544 * 0x01, VSimSycClkReq1Valid
2545 * 0x02, VSimSycClkReq2Valid
2546 * 0x04, VSimSycClkReq3Valid
2547 * 0x08, VSimSycClkReq4Valid
2548 * 0x10, VSimSycClkReq5Valid
2549 * 0x20, VSimSycClkReq6Valid
2550 * 0x40, VSimSycClkReq7Valid
2551 * 0x80, VSimSycClkReq8Valid
2552 */
2553 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2554 /*
2555 * 0x03, VarmRequestCtrl
2556 * 0x0c, VapeRequestCtrl
2557 * 0x30, Vsmps1RequestCtrl
2558 * 0xc0, Vsmps2RequestCtrl
2559 */
2560 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2561 /*
2562 * 0x03, Vsmps3RequestCtrl
2563 * 0x0c, VpllRequestCtrl
2564 * 0x30, VanaRequestCtrl
2565 * 0xc0, VextSupply1RequestCtrl
2566 */
2567 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2568 /*
2569 * 0x03, VextSupply2RequestCtrl
2570 * 0x0c, VextSupply3RequestCtrl
2571 * 0x30, Vaux1RequestCtrl
2572 * 0xc0, Vaux2RequestCtrl
2573 */
2574 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2575 /*
2576 * 0x03, Vaux3RequestCtrl
2577 * 0x04, SwHPReq
2578 */
2579 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2580 /*
2581 * 0x01, Vsmps1SysClkReq1HPValid
2582 * 0x02, Vsmps2SysClkReq1HPValid
2583 * 0x04, Vsmps3SysClkReq1HPValid
2584 * 0x08, VanaSysClkReq1HPValid
2585 * 0x10, VpllSysClkReq1HPValid
2586 * 0x20, Vaux1SysClkReq1HPValid
2587 * 0x40, Vaux2SysClkReq1HPValid
2588 * 0x80, Vaux3SysClkReq1HPValid
2589 */
2590 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2591 /*
2592 * 0x01, VapeSysClkReq1HPValid
2593 * 0x02, VarmSysClkReq1HPValid
2594 * 0x04, VbbSysClkReq1HPValid
2595 * 0x10, VextSupply1SysClkReq1HPValid
2596 * 0x20, VextSupply2SysClkReq1HPValid
2597 * 0x40, VextSupply3SysClkReq1HPValid
2598 */
2599 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2600 /*
2601 * 0x01, Vsmps1HwHPReq1Valid
2602 * 0x02, Vsmps2HwHPReq1Valid
2603 * 0x04, Vsmps3HwHPReq1Valid
2604 * 0x08, VanaHwHPReq1Valid
2605 * 0x10, VpllHwHPReq1Valid
2606 * 0x20, Vaux1HwHPReq1Valid
2607 * 0x40, Vaux2HwHPReq1Valid
2608 * 0x80, Vaux3HwHPReq1Valid
2609 */
2610 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2611 /*
2612 * 0x01, VextSupply1HwHPReq1Valid
2613 * 0x02, VextSupply2HwHPReq1Valid
2614 * 0x04, VextSupply3HwHPReq1Valid
2615 */
2616 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2617 /*
2618 * 0x01, Vsmps1HwHPReq2Valid
2619 * 0x02, Vsmps2HwHPReq2Valid
2620 * 0x03, Vsmps3HwHPReq2Valid
2621 * 0x08, VanaHwHPReq2Valid
2622 * 0x10, VpllHwHPReq2Valid
2623 * 0x20, Vaux1HwHPReq2Valid
2624 * 0x40, Vaux2HwHPReq2Valid
2625 * 0x80, Vaux3HwHPReq2Valid
2626 */
2627 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2628 /*
2629 * 0x01, VextSupply1HwHPReq2Valid
2630 * 0x02, VextSupply2HwHPReq2Valid
2631 * 0x04, VextSupply3HwHPReq2Valid
2632 */
2633 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2634 /*
2635 * 0x01, VapeSwHPReqValid
2636 * 0x02, VarmSwHPReqValid
2637 * 0x04, Vsmps1SwHPReqValid
2638 * 0x08, Vsmps2SwHPReqValid
2639 * 0x10, Vsmps3SwHPReqValid
2640 * 0x20, VanaSwHPReqValid
2641 * 0x40, VpllSwHPReqValid
2642 * 0x80, Vaux1SwHPReqValid
2643 */
2644 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2645 /*
2646 * 0x01, Vaux2SwHPReqValid
2647 * 0x02, Vaux3SwHPReqValid
2648 * 0x04, VextSupply1SwHPReqValid
2649 * 0x08, VextSupply2SwHPReqValid
2650 * 0x10, VextSupply3SwHPReqValid
2651 */
2652 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2653 /*
2654 * 0x02, SysClkReq2Valid1
2655 * ...
2656 * 0x80, SysClkReq8Valid1
2657 */
2658 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2659 /*
2660 * 0x02, SysClkReq2Valid2
2661 * ...
2662 * 0x80, SysClkReq8Valid2
2663 */
2664 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2665 /*
2666 * 0x01, Vaux4SwHPReqValid
2667 * 0x02, Vaux4HwHPReq2Valid
2668 * 0x04, Vaux4HwHPReq1Valid
2669 * 0x08, Vaux4SysClkReq1HPValid
2670 */
2671 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2672 /*
2673 * 0x01, Vaux5SwHPReqValid
2674 * 0x02, Vaux5HwHPReq2Valid
2675 * 0x04, Vaux5HwHPReq1Valid
2676 * 0x08, Vaux5SysClkReq1HPValid
2677 */
2678 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2679 /*
2680 * 0x01, Vaux6SwHPReqValid
2681 * 0x02, Vaux6HwHPReq2Valid
2682 * 0x04, Vaux6HwHPReq1Valid
2683 * 0x08, Vaux6SysClkReq1HPValid
2684 */
2685 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2686 /*
2687 * 0x01, VclkbSwHPReqValid
2688 * 0x02, VclkbHwHPReq2Valid
2689 * 0x04, VclkbHwHPReq1Valid
2690 * 0x08, VclkbSysClkReq1HPValid
2691 */
2692 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2693 /*
2694 * 0x01, Vrf1SwHPReqValid
2695 * 0x02, Vrf1HwHPReq2Valid
2696 * 0x04, Vrf1HwHPReq1Valid
2697 * 0x08, Vrf1SysClkReq1HPValid
2698 */
2699 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2700 /*
2701 * 0x02, VTVoutEna
2702 * 0x04, Vintcore12Ena
2703 * 0x38, Vintcore12Sel
2704 * 0x40, Vintcore12LP
2705 * 0x80, VTVoutLP
2706 */
2707 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2708 /*
2709 * 0x02, VaudioEna
2710 * 0x04, VdmicEna
2711 * 0x08, Vamic1Ena
2712 * 0x10, Vamic2Ena
2713 * 0x20, Vamic12LP
2714 * 0xC0, VdmicSel
2715 */
2716 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2717 /*
2718 * 0x01, Vamic1_dzout
2719 * 0x02, Vamic2_dzout
2720 */
2721 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2722 /*
2723 * 0x07, VHSICSel
2724 * 0x08, VHSICOffState
2725 * 0x10, VHSIEna
2726 * 0x20, VHSICLP
2727 */
2728 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2729 /*
2730 * 0x07, VSDIOSel
2731 * 0x08, VSDIOOffState
2732 * 0x10, VSDIOEna
2733 * 0x20, VSDIOLP
2734 */
2735 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2736 /*
2737 * 0x03, Vsmps1Regu
2738 * 0x0c, Vsmps1SelCtrl
2739 * 0x10, Vsmps1AutoMode
2740 * 0x20, Vsmps1PWMMode
2741 */
2742 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2743 /*
2744 * 0x03, Vsmps2Regu
2745 * 0x0c, Vsmps2SelCtrl
2746 * 0x10, Vsmps2AutoMode
2747 * 0x20, Vsmps2PWMMode
2748 */
2749 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2750 /*
2751 * 0x03, Vsmps3Regu
2752 * 0x0c, Vsmps3SelCtrl
2753 * 0x10, Vsmps3AutoMode
2754 * 0x20, Vsmps3PWMMode
2755 * NOTE! PRCMU register
2756 */
2757 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2758 /*
2759 * 0x03, VpllRegu
2760 * 0x0c, VanaRegu
2761 */
2762 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2763 /*
2764 * 0x03, VextSupply1Regu
2765 * 0x0c, VextSupply2Regu
2766 * 0x30, VextSupply3Regu
2767 * 0x40, ExtSupply2Bypass
2768 * 0x80, ExtSupply3Bypass
2769 */
2770 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2771 /*
2772 * 0x03, Vaux1Regu
2773 * 0x0c, Vaux2Regu
2774 */
2775 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2776 /*
2777 * 0x0c, VRF1Regu
2778 * 0x03, Vaux3Regu
2779 */
2780 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2781 /*
2782 * 0x3f, Vsmps1Sel1
2783 */
2784 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2785 /*
2786 * 0x3f, Vsmps1Sel2
2787 */
2788 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2789 /*
2790 * 0x3f, Vsmps1Sel3
2791 */
2792 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2793 /*
2794 * 0x3f, Vsmps2Sel1
2795 */
2796 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2797 /*
2798 * 0x3f, Vsmps2Sel2
2799 */
2800 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2801 /*
2802 * 0x3f, Vsmps2Sel3
2803 */
2804 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2805 /*
2806 * 0x7f, Vsmps3Sel1
2807 * NOTE! PRCMU register
2808 */
2809 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2810 /*
2811 * 0x7f, Vsmps3Sel2
2812 * NOTE! PRCMU register
2813 */
2814 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2815 /*
2816 * 0x0f, Vaux1Sel
2817 */
2818 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2819 /*
2820 * 0x0f, Vaux2Sel
2821 */
2822 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2823 /*
2824 * 0x07, Vaux3Sel
2825 * 0x70, Vrf1Sel
2826 */
2827 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2828 /*
2829 * 0x01, VextSupply12LP
2830 */
2831 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2832 /*
2833 * 0x07, Vanasel
2834 * 0x30, Vpllsel
2835 */
2836 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2837 /*
2838 * 0x03, Vaux4RequestCtrl
2839 */
2840 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2841 /*
2842 * 0x03, Vaux4Regu
2843 */
2844 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2845 /*
2846 * 0x0f, Vaux4Sel
2847 */
2848 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2849 /*
2850 * 0x03, Vaux5RequestCtrl
2851 */
2852 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2853 /*
2854 * 0x03, Vaux5Regu
2855 */
2856 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2857 /*
2858 * 0x3f, Vaux5Sel
2859 */
2860 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2861 /*
2862 * 0x03, Vaux6RequestCtrl
2863 */
2864 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2865 /*
2866 * 0x03, Vaux6Regu
2867 */
2868 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2869 /*
2870 * 0x3f, Vaux6Sel
2871 */
2872 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2873 /*
2874 * 0x03, VCLKBRequestCtrl
2875 */
2876 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2877 /*
2878 * 0x03, VCLKBRegu
2879 */
2880 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2881 /*
2882 * 0x07, VCLKBSel
2883 */
2884 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2885 /*
2886 * 0x03, Vrf1RequestCtrl
2887 */
2888 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2889 /*
2890 * 0x01, VpllDisch
2891 * 0x02, Vrf1Disch
2892 * 0x04, Vaux1Disch
2893 * 0x08, Vaux2Disch
2894 * 0x10, Vaux3Disch
2895 * 0x20, Vintcore12Disch
2896 * 0x40, VTVoutDisch
2897 * 0x80, VaudioDisch
2898 */
2899 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2900 /*
2901 * 0x02, VanaDisch
2902 * 0x04, VdmicPullDownEna
2903 * 0x08, VpllPullDownEna
2904 * 0x10, VdmicDisch
2905 */
2906 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2907 /*
2908 * 0x01, Vaux4Disch
2909 */
2910 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2911 /*
2912 * 0x01, Vaux5Disch
2913 * 0x02, Vaux6Disch
2914 * 0x04, VCLKBDisch
2915 */
2916 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2917};
2918
b54969ac 2919static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2920 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2921 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2922 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2923 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2924 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2925 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2926 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2927 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2928 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2929 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2930};
2931
547f384f
LJ		 2932static struct of_regulator_match ab8505_regulator_match[] = {
2933 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2934 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2935 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2936 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2937 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2938 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2939 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2940 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2941 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2942 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2943 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2944 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2945 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2946};
2947
ae0a9a3e
LJ		 2948static struct of_regulator_match ab8540_regulator_match[] = {
2949 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2950 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2951 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2952 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2953 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2954 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2955 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2956 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2957 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2958 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2959 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2960 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2961 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2962 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2963};
2964
8e6a8d7d
LJ		 2965static struct of_regulator_match ab9540_regulator_match[] = {
2966 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2967 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2968 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2969 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2970 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2971 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2972 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2973 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2974 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2975 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2976 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2977};
2978
da45edc7
LJ		 2979static struct {
2980 struct ab8500_regulator_info *info;
2981 int info_size;
2982 struct ab8500_reg_init *init;
2983 int init_size;
2984 struct of_regulator_match *match;
2985 int match_size;
2986} abx500_regulator;
2987
33aeb49e
LJ		 2988static void abx500_get_regulator_info(struct ab8500 *ab8500)
2989{
2990 if (is_ab9540(ab8500)) {
2991 abx500_regulator.info = ab9540_regulator_info;
2992 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2993 abx500_regulator.init = ab9540_reg_init;
2994 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2995 abx500_regulator.match = ab9540_regulator_match;
2996 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2997 } else if (is_ab8505(ab8500)) {
2998 abx500_regulator.info = ab8505_regulator_info;
2999 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
3000 abx500_regulator.init = ab8505_reg_init;
3001 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
3002 abx500_regulator.match = ab8505_regulator_match;
3003 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
3004 } else if (is_ab8540(ab8500)) {
3005 abx500_regulator.info = ab8540_regulator_info;
3006 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
3007 abx500_regulator.init = ab8540_reg_init;
3008 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
3009 abx500_regulator.match = ab8540_regulator_match;
3010 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
3011 } else {
3012 abx500_regulator.info = ab8500_regulator_info;
3013 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
3014 abx500_regulator.init = ab8500_reg_init;
3015 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
3016 abx500_regulator.match = ab8500_regulator_match;
3017 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
3018 }
3019}
3020
da45edc7
LJ		 3021static int ab8500_regulator_init_registers(struct platform_device *pdev,
3022 int id, int mask, int value)
3023{
3024 struct ab8500_reg_init *reg_init = abx500_regulator.init;
3025 int err;
3026
3027 BUG_ON(value & ~mask);
3028 BUG_ON(mask & ~reg_init[id].mask);
3029
3030 /* initialize register */
3031 err = abx500_mask_and_set_register_interruptible(
3032 &pdev->dev,
3033 reg_init[id].bank,
3034 reg_init[id].addr,
3035 mask, value);
3036 if (err < 0) {
3037 dev_err(&pdev->dev,
3038 "Failed to initialize 0x%02x, 0x%02x.\n",
3039 reg_init[id].bank,
3040 reg_init[id].addr);
3041 return err;
3042 }
3043 dev_vdbg(&pdev->dev,
3044 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3045 reg_init[id].bank,
3046 reg_init[id].addr,
3047 mask, value);
3048
3049 return 0;
3050}
3051
3052static int ab8500_regulator_register(struct platform_device *pdev,
3053 struct regulator_init_data *init_data,
3054 int id, struct device_node *np)
3055{
3056 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3057 struct ab8500_regulator_info *info = NULL;
3058 struct regulator_config config = { };
3059 int err;
3060
3061 /* assign per-regulator data */
3062 info = &abx500_regulator.info[id];
3063 info->dev = &pdev->dev;
3064
3065 config.dev = &pdev->dev;
3066 config.init_data = init_data;
3067 config.driver_data = info;
3068 config.of_node = np;
3069
3070 /* fix for hardware before ab8500v2.0 */
3071 if (is_ab8500_1p1_or_earlier(ab8500)) {
3072 if (info->desc.id == AB8500_LDO_AUX3) {
3073 info->desc.n_voltages =
3074 ARRAY_SIZE(ldo_vauxn_voltages);
3075 info->desc.volt_table = ldo_vauxn_voltages;
3076 info->voltage_mask = 0xf;
3077 }
3078 }
3079
3080 /* register regulator with framework */
3081 info->regulator = regulator_register(&info->desc, &config);
3082 if (IS_ERR(info->regulator)) {
3083 err = PTR_ERR(info->regulator);
3084 dev_err(&pdev->dev, "failed to register regulator %s\n",
3085 info->desc.name);
3086 /* when we fail, un-register all earlier regulators */
3087 while (--id >= 0) {
3088 info = &abx500_regulator.info[id];
3089 regulator_unregister(info->regulator);
3090 }
3091 return err;
3092 }
3093
3094 return 0;
3095}
3096
a5023574 3097static int
b54969ac 3098ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3099 struct device_node *np)
3a8334b9 3100{
33aeb49e 3101 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3102 int err, i;
3103
33aeb49e 3104 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3105 err = ab8500_regulator_register(
33aeb49e 3106 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3107 if (err)
3108 return err;
3109 }
3110
3111 return 0;
3112}
3113
a5023574 3114static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3115{
3116 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3117 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3118 struct ab8500_platform_data *ppdata;
3119 struct ab8500_regulator_platform_data *pdata;
c789ca20 3120 int i, err;
b54969ac 3121
33aeb49e
LJ		 3122 if (!ab8500) {
3123 dev_err(&pdev->dev, "null mfd parent\n");
3124 return -EINVAL;
8e6a8d7d 3125 }
c789ca20 3126
33aeb49e
LJ		 3127 abx500_get_regulator_info(ab8500);
3128
3a8334b9 3129 if (np) {
33aeb49e
LJ		 3130 err = of_regulator_match(&pdev->dev, np,
3131 abx500_regulator.match,
3132 abx500_regulator.match_size);
3a8334b9
LJ		 3133 if (err < 0) {
3134 dev_err(&pdev->dev,
3135 "Error parsing regulator init data: %d\n", err);
3136 return err;
3137 }
3138
33aeb49e 3139 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3140 return err;
3141 }
3142
732805a5
BJ		 3143 ppdata = dev_get_platdata(ab8500->dev);
3144 if (!ppdata) {
3145 dev_err(&pdev->dev, "null parent pdata\n");
3146 return -EINVAL;
3147 }
3148
3149 pdata = ppdata->regulator;
fc24b426
BJ		 3150 if (!pdata) {
3151 dev_err(&pdev->dev, "null pdata\n");
3152 return -EINVAL;
3153 }
c789ca20 3154
cb189b07 3155 /* make sure the platform data has the correct size */
33aeb49e 3156 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3157 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3158 return -EINVAL;
3159 }
3160
da0b0c47
LJ		 3161 /* initialize debug (initial state is recorded with this call) */
3162 err = ab8500_regulator_debug_init(pdev);
3163 if (err)
3164 return err;
3165
79568b94 3166 /* initialize registers */
732805a5 3167 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3168 int id, mask, value;
79568b94 3169
732805a5
BJ		 3170 id = pdata->reg_init[i].id;
3171 mask = pdata->reg_init[i].mask;
3172 value = pdata->reg_init[i].value;
79568b94
BJ		 3173
3174 /* check for configuration errors */
33aeb49e 3175 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3176
33aeb49e 3177 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3178 if (err < 0)
79568b94 3179 return err;
79568b94
BJ		 3180 }
3181
f7eae37f
RV		 3182 if (!is_ab8505(ab8500)) {
3183 /* register external regulators (before Vaux1, 2 and 3) */
3184 err = ab8500_ext_regulator_init(pdev);
3185 if (err)
3186 return err;
3187 }
d1a82001 3188
c789ca20 3189 /* register all regulators */
33aeb49e 3190 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3191 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3192 i, NULL);
a7ac1d9e 3193 if (err < 0)
c789ca20 3194 return err;
c789ca20
SI		 3195 }
3196
3197 return 0;
3198}
3199
8dc995f5 3200static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3201{
d1a82001 3202 int i, err;
8e6a8d7d 3203 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3204
33aeb49e 3205 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3206 struct ab8500_regulator_info *info = NULL;
33aeb49e 3207 info = &abx500_regulator.info[i];
09aefa12
BJ		 3208
3209 dev_vdbg(rdev_get_dev(info->regulator),
3210 "%s-remove\n", info->desc.name);
3211
c789ca20
SI		 3212 regulator_unregister(info->regulator);
3213 }
3214
f7eae37f
RV		 3215 if (!is_ab8505(ab8500)) {
3216 /* remove external regulators (after Vaux1, 2 and 3) */
3217 err = ab8500_ext_regulator_exit(pdev);
3218 if (err)
3219 return err;
3220 }
d1a82001 3221
da0b0c47
LJ		 3222 /* remove regulator debug */
3223 err = ab8500_regulator_debug_exit(pdev);
3224 if (err)
3225 return err;
3226
c789ca20
SI		 3227 return 0;
3228}
3229
3230static struct platform_driver ab8500_regulator_driver = {
3231 .probe = ab8500_regulator_probe,
5eb9f2b9 3232 .remove = ab8500_regulator_remove,
c789ca20
SI		 3233 .driver = {
3234 .name = "ab8500-regulator",
3235 .owner = THIS_MODULE,
3236 },
3237};
3238
3239static int __init ab8500_regulator_init(void)
3240{
3241 int ret;
3242
3243 ret = platform_driver_register(&ab8500_regulator_driver);
3244 if (ret != 0)
3245 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3246
3247 return ret;
3248}
3249subsys_initcall(ab8500_regulator_init);
3250
3251static void __exit ab8500_regulator_exit(void)
3252{
3253 platform_driver_unregister(&ab8500_regulator_driver);
3254}
3255module_exit(ab8500_regulator_exit);
3256
3257MODULE_LICENSE("GPL v2");
3258MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3259MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3260MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3261MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3262MODULE_ALIAS("platform:ab8500-regulator");
Linux kernel - Deliverables
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